Electromagnetic radiation detector

Abstract

The invention relates to an electromagnetic radiation detector, comprising an absorber configured to absorb electromagnetic radiation, a MOS-FET type transistor thermally coupled to the absorber, and a control circuit. The transistor comprises a source and a drain doped with a first type of conductivity, a channel, and a gate electrically isolated from the channel by a gate dielectric layer of the transistor. The control circuit is electrically connected to the source, the drain, and the gate, and configured to apply an electrical potential difference between the gate and the source less than or equal to a threshold voltage of the transistor. The gate is made of silicon doped with a second type of conductivity opposite to the first type of conductivity, with a majority charge carrier concentration less than or equal to 10¹⁹ cm⁻³. The gate dielectric layer has a thickness less than or equal to 50 nm. (See Figure 1A for abbreviations.)

Description

Title of the invention: Electromagnetic radiation detector technical field

[0001] The field of the invention is that of the detection of electromagnetic radiation, in particular infrared or terahertz, more specifically that of bolometer-type thermal detectors employing a thermometer incorporating a field-effect transistor. The invention also relates to a method for manufacturing such a detector. PREVIOUS STATE OF THE ART

[0002] An electromagnetic radiation detector, also called a photodetector, may comprise an array of at least one pixel, each pixel comprising a bolometer-type thermal detector. Each bolometer comprises a micro-board suspended above a substrate by thermally insulated arms. The micro-board includes an absorber capable of converting electromagnetic radiation into thermal energy, and a thermometer thermally coupled to the absorber and adapted to provide an electrical signal representative of a temperature change in the absorber. The detector further comprises a control circuit integrated in and on the substrate. It is electrically connected to the thermometer via the thermally insulated arms and is configured to read the electrical signal provided by the thermometer.

[0003] The thermometer may comprise a sensitive material whose electrical resistivity varies with the material's temperature, such as vanadium oxide (VOx). Patent application WO201855276 proposes a solution in which the sensitive material is replaced by a field-effect transistor. The device described in this patent application improves the response time of prior art transistor bolometers. It is also suitable for pixel sizes smaller than 10 µm.

[0004] In this document, the thermometer includes a MOS-type transistor. The transistor has a mid-gap metal gate, allowing the operating gate voltage to be lowered to a range between 50 mV and 75 mV. Thus, a temperature change in the transistor channel results in a large change in the drain current, which is the electrical signal read by the control circuit. The thermometer is therefore particularly sensitive.

[0005] Patent application WO2021123616 proposes a technical improvement for increasing the signal-to-noise ratio of the electrical signal read by the control circuit. The thermometer of the device described in this document also includes A field-effect transistor (FET) comprises a front gate made of a middle-band gap metal. The transistor's drain current constitutes the electrical signal read by the control circuit. The transistor also includes a rear gate, located on one side of a transistor channel opposite the front gate.

[0006] In WO2021123616, it is proposed to generate a blocking layer at one of two opposite faces of the transistor channel, both extending parallel to the front gate. The blocking layer can be a charge carrier accumulation or inversion layer. It reduces the influence of a gate voltage variation on the drain current, and consequently increases the signal-to-noise ratio.

[0007] The blocking layer appears at sufficiently high specific gate bias voltages, up to 7 V, or even 12.5 V in absolute value, which are incompatible with a standard control circuit designed to generally deliver a bias voltage of 3 V or less. It is possible to lower these absolute values ​​either by superficially doping the channel or by forming a gate oxide of the particular transistor. More precisely, in the latter case, the gate oxide consists of two sublayers made of specific materials that generate an electrostatic dipole between the front gate and the channel. However, both of these methods have the disadvantage of being difficult to fabricate. Description of the invention

[0008] The invention aims to remedy at least in part the drawbacks of the prior art, and more particularly to offer a sensitive thermal detector, having an improved signal-to-noise ratio, compatible with a standard control circuit.

[0009] To this end, the object of the invention is an electromagnetic radiation detector, comprising an absorber configured to absorb electromagnetic radiation, and a MOS-FET type transistor thermally coupled to the absorber. The MOS-FET type transistor comprises a source doped with a first type of conductivity, a drain doped with the first type of conductivity, a channel extending from the source to the drain, and a gate electrically isolated from the channel by a gate dielectric layer of the transistor.

[0010] The detector further comprises a control circuit electrically connected to the source, drain, and gate; and configured to apply an electrical potential difference between the gate and the source less than or equal in absolute value to a threshold voltage of the transistor. The gate is made of silicon doped with a second type of conductivity opposite to the first type of conductivity, with a majority charge carrier concentration less than or equal to 10¹⁹ cm³. The dielectric layer the grid has a thickness less than or equal to 50 nm.

[0011] Some preferred but not limiting aspects of this detector are the following.

[0012] The detector may further comprise a substrate, a micro-board made of a dielectric material suspended above the substrate, and a semiconductor portion extending over an underside of the micro-board in which the drain, channel and source can be housed.

[0013] The absorber can extend over a part of the micro-board devoid of the semiconductor portion.

[0014] The transistor may further include a rear grid electrically connected to the control circuit and electrically isolated from the channel by the micro-board.

[0015] The rear grille can be part of the absorber.

[0016] The micro-board can have a thickness between 10 nm and 150 nm.

[0017] The drain and the grid can be connected to the control circuit by a first arm With thermal insulation, the source can be electrically connected to the control circuit by a second thermal insulation arm, and the micro-board can be suspended above the substrate by the first and second thermal insulation arms.

[0018] The rear grid can be electrically connected to the source by means of a rear-facing electrical contact passing through the micro-board, and the source can be electrically connected to the second thermal insulation arm by means of a source electrode opposite the rear-facing electrical contact.

[0019] The transistor may be a depletion-mode transistor.

[0020] The transistor may be an enhancement transistor.

[0021] The invention also relates to a method for manufacturing a detector according to any one of the preceding characteristics, comprising the following grid formation steps: formation of a sacrificial pad; formation of spacers on flanks of the sacrificial pad; conformal deposition of a first barrier layer on the spacers and the sacrificial pad; deposition of a planarizing semiconductor layer so as to completely cover the first barrier layer, polishing of the planarizing semiconductor layer with a stop on the first barrier layer to obtain a first sacrificial layer; etching of a grid opening through the first barrier layer via an upper surface of the first barrier layer opposite the sacrificial pad, the opening having dimensions strictly smaller than the dimensions of the sacrificial pad;removal of the sacrificial pad to obtain a cavity in its place; filling the cavity with silicon to seal the gate opening and thus obtain the gate.

[0022] The sacrificial pad can be formed on a semiconductor portion in which the drain, channel, and source can be housed, and the sacrificial pad can protect the channel during a stage of installing the source and the drain.

[0023] The sacrificial pad can be made of silicon.

[0024] The cavity filling step may include a deposition of a planarizing semiconductor layer doped in-situ, so as to totally fill a volume of the cavity in communication with the gate opening and to cover the first sacrificial layer and the first barrier layer; a polishing of the planarizing semiconductor layer with stopping on the first sacrificial layer.

[0025] The manufacturing process may further include a micro-board release etching during which the first sacrificial layer is selectively etched with respect to the first barrier layer and the grid. Brief description of the drawings

[0026] Other aspects, objects, advantages and features of the invention will become more apparent upon reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the accompanying drawings in which:

[0027] [Fig.1A] is a schematic view along a section plane AA of an example of a photodetector according to the invention;

[0028] [Fig.1B] is a schematic view along a section plane BB of the example photodetector;

[0029] [Fig.2] is a partial top view of the example photodetector on which the section planes AA and BB are shown;

[0030] [Fig.3] illustrates a biasing scheme of a transistor implemented in the photodetector example;

[0031] [Fig.4] shows simulation results using design assistance software;

[0032] Figures 5A to 5N illustrate intermediate steps in a manufacturing process for a first intermediate structure;

[0033] [Fig.6A] is a schematic cross-sectional view of the first intermediate structure;

[0034] Fig. 6B is a schematic cross-sectional view of a second intermediate structure to be assembled with the first intermediate structure to obtain the photodetector example.

[0035] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0036] In the figures and in the following description, the same reference numerals represent identical or similar elements. Furthermore, the various elements are not drawn to scale in order to enhance the clarity of the figures. Moreover, the different embodiments and variants are not mutually exclusive and may be combined. Unless otherwise indicated, the terms "Approximately", "about", "in the order of" mean within 10%, and preferably within 5%. Furthermore, the terms "between ... and ..." and equivalents mean that the limits are included, unless otherwise stated.

[0037] The invention relates to a detector of electromagnetic radiation, preferably in the infrared or terahertz range. The photodetector comprises an array of at least one pixel. The pixels may, for example, have a size between 5 pm and 12 pm, particularly when the electromagnetic radiation has a wavelength between 8 pm and 14 pm, that is to say, in the far-infrared range.

[0038] Each pixel includes an absorber configured to absorb electromagnetic radiation and a thermometer. The thermometer includes a MOS-FET type transistor thermally coupled to the absorber, such that the transistor's temperature increases as the power of the electromagnetic radiation absorbed by the absorber increases. The transistor is electrically connected to a control circuit. It has a source and a drain doped with a first type of conductivity, and a gate made of a semiconductor material doped with a second type of conductivity. The gate is electrically isolated from a channel of the transistor by a gate dielectric layer.

[0039] During operation, the control circuit applies an electrical potential difference between the gate and the source that is less than or equal in absolute value to a threshold voltage of the transistor, advantageously constant. Thus, the transistor operates in a so-called low inversion regime. In this regime, the drain current is sensitive to variations in transistor parameters, such as, for example, a fluctuation in the gate voltage or a variation in the channel temperature, here proportional to a variation in the power of the electromagnetic radiation absorbed by the absorber.

[0040] In the context of the invention, the second type of conductivity is contrasted with the first type of conductivity. The gate has a majority charge carrier concentration lower than a maximum concentration identified by the inventors, and the thickness of the gate dielectric layer is less than or equal to a maximum thickness also identified by the inventors. The inventors have observed that, during operation, the combination of these characteristics creates a depleted region in the gate near the gate dielectric layer. The inventors have further identified that the appearance of this depleted region, in combination with the gate conductivity type, results in an increase in the temperature coefficient of change (TCC) of the transistor, while reducing the sensitivity of the drain current to variations in transistor parameters other than temperature.Thus, the detector's sensitivity is increased along with the signal-to-noise ratio. The TCC value can be increased by up to 25% compared to transistors using a "mid-gap" type metal gate. of earlier art.

[0041]

[0042] A MOS-FET (or Metal-Oxide-Semiconductor Field Effect Transistor) is a field-effect transistor comprising a channel and an electrostatic control gate electrically isolated from the channel by a dielectric layer on the transistor's gate. The gate is not necessarily metallic, contrary to what a literal translation of the English name might suggest. It can be made of a semiconductor material, such as doped polycrystalline silicon. Applying a bias voltage to the gate modulates the channel's conductivity to control the electrical current flowing through the channel between a source and a drain of the transistor. This electrical current is called the drain current (ID). The temperature coefficient of current (TCC) is an important characteristic of a MOSFET transistor. It is given by the relation TCC = - ' °where Id is the dT transistor drain current and T the temperature.

[0043] A depleted region or zone of a semiconductor layer is defined as a region within which the concentration of mobile charge carriers is substantially reduced, for example, due to diffusion, an electric field, or recombination. The region has a mobile charge carrier concentration strictly lower than the concentration of doping species of the same type as the mobile charge carriers in the region. The region may be completely devoid of mobile or free charge carriers. A depleted region or zone can be identified from simulation results.

[0044] In the description, two elements are "thermally coupled" when a thermal conduction path links the two elements so that heat can be efficiently transferred from one to the other. The two elements may be in physical contact with each other. They may also be separated from each other by a medium of low thermal resistance, for example, less than or equal to 1E3 K / W. Alternatively or in addition, heat may be transferred from one to the other by convection and / or radiation.

[0045] For the purposes of this description, a layer is defined as an area consisting of one or more sub-layers of a material whose thickness along a z-axis is less than, for example, ten times or even twenty times, its longitudinal dimensions of width and length in an xy plane perpendicular to the z-axis. A layer may be structured. When it consists of several sub-layers, the sub-layers may be made of different materials. The sub-layer(s) extend in planes substantially parallel to the xy plane.

[0046] Specific embodiments relating to a detector will be described of electromagnetic radiation comprising an absorber configured to absorb electromagnetic radiation, thermally coupled to a MOS-FET transistor. However, these embodiments can be adapted to other optoelectronic devices, such as a fingerprint sensor exploiting a difference in thermal conductivity between the ridges and valleys of a fingerprint. In this case, heat can, for example, be transferred from the finger to the absorber by thermal conduction.

[0047] An example of a photodetector according to the invention will be described with reference to Figures IA, IB, and 2. A single pixel of the photodetector is shown in these figures, but the photodetector may comprise several pixels identical to the one shown, for example, arranged in a matrix. Figure 2 is a schematic top view of the pixel on which only certain features of the photodetector have been shown for clarity. Figures IA and IB are partial views along section planes AA and BB, respectively, shown in Figure 2. For clarity, only two extreme portions of the respective section planes are shown here.

[0048] In this example, the MOS-FET type transistor may be an enhancement-mode NMOS type transistor. Alternatively, the MOS-FET type transistor may be a depletion-mode NMOS type transistor, an enhancement-mode PMOS type transistor, or a depletion-mode PMOS type transistor, without departing from the scope of the invention.

[0049] The photodetector 1 comprises a substrate 100, a control circuit (not shown), and an array of at least one pixel. The array extends parallel to the substrate 100. The pixel includes a micro-board 160, an absorber 170, and a MOS-FET transistor. The micro-board 160 is suspended above the substrate 100. The substrate 100 includes a substantially flat upper face 100.1 on the same side as the micro-board 160 with respect to the substrate 100.

[0050] A three-dimensional orthogonal (X, Y, Z) direct coordinate system is defined herein and for the remainder of this description, where the X and Y axes form a plane parallel to the upper face 100.1 of the substrate 100, and where the Z axis is oriented orthogonally to the upper face 100.1, from the upper face 100.1 towards the micro-board 160. When the photodetector 1 comprises a multi-pixel matrix, the X axis and / or the Y axis are oriented along respective axes of the matrix. In the remainder of this description, the terms "vertical" and "vertically" refer to an orientation substantially parallel to the Z axis, and the terms "horizontally" and "horizontally" refer to an orientation substantially parallel to the (X, Y) plane. Furthermore, the terms "lower" and "upper" refer to an increasing positioning as one moves away from the substrate 100 along the +Z direction.

[0051] The substrate 100 may, for example, be at least partially derived from a wafer, for example made of silicon, and may optionally have undergone cutting and / or thinning steps. It may comprise a stack of interconnects having one or more levels of conductive lines extending parallel to the (X, Y) plane, optionally interconnected with each other by conductive vias. In this case, the upper face 100.1 of the substrate 100 is an upper face of the interconnect stack. The control circuit is integrated in and / or on the substrate 100 and may comprise conductive lines and / or vias of the interconnect stack.

[0052] The micro-board 160 is here made of one or more electrically insulating materials, advantageously dielectric, for example silicon dioxide (SiO₂). It may include on one or more of its faces an electrically insulating layer, for example a layer serving to protect the micro-board 160 during etching. It extends parallel to the upper face 100.1 of the substrate 100. It is, for example, rectangular or square in shape in a plane parallel to the (X, Y) plane.

[0053] The MOS-FET transistor comprises a drain 150.3, a source 150.1, and a channel 150.2 extending parallel to the (X, Y) plane from the drain 150.3 to the source 150.1. The drain 150.3, the source 150.1, and the channel 150.2 are housed in a semiconductor portion 150 made of a single-crystal semiconductor material, for example, silicon (Si) or silicon-germanium (SiGe). The semiconductor portion 150 extends over a lower face of the micro-board 160 so as to be in physical contact with it. For example, its thickness, measured parallel to the Z-axis, is between 5 nm and 100 nm, preferably between 15 nm and 50 nm. Drain 150.3 and source 150.1 are doped with a first type of conductivity and may contain regions with different concentrations of dopant atoms and / or dopant atoms of different types. In this particular example, drain 150.3 and source 150.1 are N-type doped; channel 150.2 is P-type or intrinsically doped.

[0054] The transistor comprises a gate 135 and a gate dielectric layer 140. The gate 135 is electrically isolated from the channel by the gate dielectric layer 140. The gate dielectric layer 140 comprises one or more sublayers, each made of a dielectric material. The dielectric material may, for example, be silicon dioxide (SiO₂) or hafnium dioxide (HfO₂). In this example, the gate dielectric layer 140 is a single layer of silicon dioxide (SiO₂).

[0055] The gate 135 is made of a semiconductor material doped with a second type of conductivity opposite to the first type of conductivity. In this example, the gate 135 is made of polycrystalline or amorphous silicon. It may be partially silicided, that is, the gate 135 may include a region of silicide located on one side of the gate 135 opposite the gate dielectric layer 140. Here, it is P-doped. since the drain 150.3 and the source 150.1 are N-type doped. For example, it has a thickness measured parallel to the Z axis between 10 nm and 200 nm, preferably between 25 nm and 100 nm.

[0056] The gate dielectric layer 140 is interposed between channel 150.2 and gate 135, in physical contact with both channel 150.2 and gate 135. Its thickness, measured parallel to the Z-axis, is less than a maximum thickness, and gate 135 has a majority charge carrier concentration less than a maximum concentration, so that during operation, a depleted region 135.1 appears in gate 135. The thickness of the gate dielectric layer 140 is sufficiently small that a Fermi level of gate 135 aligns with a Fermi level of channel 150.2, thereby curving gap energy bands of gate 135 in the vicinity of the gate dielectric layer 140. The depleted region 135.1 is represented by a dashed line in Figures IA and IB. It extends deep into the grid from the grid dielectric layer 140. For example, it has a thickness between 2 nm and 15 nm.It can, for example, be identified from simulation results.

[0057] In the case where the gate is made of polycrystalline or amorphous silicon, as in this example, the maximum thickness is 50 nm and the maximum concentration is 10¹⁹ cm³. The thickness of the gate dielectric layer 140 is, for example, between 3 nm and 50 nm, preferably between 4 nm and 20 nm, or even between 4 nm and 15 nm. The average concentration of majority charge carriers in the gate 135 is, for example, between 5 x 10¹⁵ cm³ and 10¹⁹ cm³, preferably between 10¹⁶ cm³ and 5 x 10¹⁸ cm³.

[0058] The absorber 170 extends over one face of the micro-board 160 opposite the semiconductor portion 150, so as to be in contact with the micro-board 160. This is the upper face of the micro-board 160, since the semiconductor portion 150 extends over the lower face. The absorber 170 is a metallic layer. Advantageously, it has a resistance substantially equal to the impedance of free space, namely 377 Ω / square. It may comprise one or more metallic sublayers of Ti, TiN, NiCr, Al, Au, W, Cu, AlCu, etc. The absorber 170 is here a titanium nitride (TiN) layer with a thickness between 3 nm and 50 nm, preferably between 3 nm and 10 nm. The absorber 170 may also include an antenna.

[0059] In this example, the absorber 170 has a portion opposite the channel 150.2. The micro-board 160 has a thickness measured parallel to the Z-axis at the channel that is sufficiently small to allow thermal coupling between the absorber 170 and the channel 150.2, and to allow the application of an electric field in the channel 150.2 when the absorber 170 is electrically polarized. The thickness of the micro-board 160 is sufficient to ensure good mechanical strength. In the case of a silicon dioxide (SiO₂) micro-board 160, as in this example, the micro-plate 160 has a thickness between 10 nm and 150 nm, preferably between 10 nm and 50 nm, for example equal to 25 nm.

[0060] The absorber 170 preferably extends over the entire upper surface of the micro-board 160, as shown here. Advantageously, it extends over a portion of the micro-board 160 that is not covered by the semiconductor portion 150, that is to say, it extends over a portion of the upper surface that is not opposite the semiconductor portion 150. Thus, the absorption of electromagnetic radiation by the absorber is maximized.

[0061] Here, the grid 135 has a closed ring shape in a plane parallel to the (X, Y) plane. The semiconductor portion 150 also has a closed ring shape in this plane. The grid 135 and the semiconductor portion 150 each have, for example, a substantially constant horizontal width along the ring. The grid 135 is centered at every point on the semiconductor portion 150.

[0062] Optional spacers 136 are in contact with opposite sides of the gate 135. The drain 150.3 and the source 150.1 extend into respective portions of the semiconductor portion 150 opposite the spacers 136. The boundaries between the drain 150.3, the channel 150.2, and the source 150.1 are schematically represented by dashed lines in Figures IA and IB. The spacers 136 may be flush with a lower face of the gate 135 opposite the gate dielectric layer 140. They are made of one or more electrically insulating materials, for example, one or more dielectric materials such as silicon dioxide (SiO₂) or silicon nitride (SiN). Here, they are made of silicon nitride (SiN).

[0063] The micro-board 160 is suspended above the substrate 100 by thermal insulation arms 120, two arms in the example shown. In other words, the micro-board 160 is held above the substrate 100 by the arms so as not to be in physical contact with the substrate 100.

[0064] The thermal insulation arms 120 are arranged between the microboard 160 and the substrate 100. They extend in a plane parallel to the (X, Y) plane. Each thermal insulation arm 120 has a proximal end attached to the microboard 160 by an electrode 121, 123, 125, and a distal end resting on an anchoring pillar 105, 115. Each thermal insulation arm 120 is electrically conductive. It has a cross-section and length sufficient to thermally insulate the microboard 160 and the transistor from the substrate 100 and the control circuit. The smaller the cross-sectional area and / or the longer the thermal insulation arm 120, the better the thermal insulation of the micro-board 160. To increase the length, it is possible, for example, to give each thermal insulation arm 120 a serpentine shape as shown in [Fig.2].Each 120 thermal insulation arm can have a conductive metallic core. of electricity, surrounded by an insulating sheath, for example made of an etch-resistant material used to remove a sacrificial material on which the micro-board 160 rests during an intermediate step in a manufacturing process. In this example, the core is made of titanium nitride (TiN) and the sheath is made of amorphous silicon, suitable for resisting etching with hydrofluoric acid in the vapor phase.

[0065] Here, a first thermal insulation arm 120 has its proximal end fixed to the micro-board 160 by a source electrode 121 in contact with the source 150.1 of the transistor. The source electrode 121 is made of an electrically conductive material. It is in contact with the core of the first thermal insulation arm 120. The distal end of the first thermal insulation arm 120 rests on an upper anchoring pillar 115, which itself rests on a lower anchoring pillar 105. The upper anchoring pillar 115 is in contact with the core of the first thermal insulation arm 120 and the lower anchoring pillar 105 is electrically connected to the control circuit, so that the source 150.1 is electrically connected to the control circuit by the source electrode 121, the first thermal insulation arm 120 and the lower and upper anchoring pillars 105, 115.

[0066] A second thermal insulation arm 120 has its proximal end fixed to the micro-board 160 by a grid electrode 125 in contact with the grid 135 and a drain electrode 123 in contact with the drain 150.3. The drain and grid electrodes 123, 125 are in contact with the core of the second thermal insulation arm 120, so that the grid 135 and the drain 150.3 are short-circuited. The distal end of the second thermal insulation arm 120 rests on an additional upper anchoring pillar 115, which itself rests on an additional lower anchoring pillar 105. The additional upper anchoring pillar 115 is in contact with the core of the second thermal insulation arm 120 and the additional lower anchoring pillar 105 is electrically connected to the control circuit, so that the grid 135 and the drain 150.3 are electrically connected to the control circuit by the second thermal insulation arm 120, the lower and upper anchoring pillars 105, 115, and, respectively, the grid electrode 125 and the drain electrode 123. .

[0067] The lower and upper anchoring pillars 105, 115 are made of metal, for example, the same metallic material. In the latter case, there may not be an interface between the lower anchoring pillar 105 and the upper anchoring pillar 115. The lower anchoring pillars 105 are, for example, all identical in shape and size. The upper anchoring pillars 115 are, for example, all identical in shape and size. The lower and upper anchoring pillars 105, 115 are here cylindrical in shape with the same diameter and a longitudinal axis parallel to the Z-axis. In this example, they are made of copper, possibly coated with a protective layer.

[0068] The source, drain and grid electrodes 121, 123, 125 are metallic. They For example, they have a tungsten (W) core surrounded by a first titanium nitride (TiN) coating, itself surrounded by a second titanium (Ti) coating. Here, they are cylindrical in shape with the same diameter, and their longitudinal axis is parallel to the Z-axis.

[0069] In this example, the pixel further comprises a rear-facing electrical contact 128 electrically connecting the absorber 170 to the source 150.1. More precisely, the rear-facing electrical contact 128 is a part of the absorber 170 conforming to a through-hole 161 extending from the upper face to the lower face of the micro-board 160. The through-hole 161 here has a cylindrical shape coaxial with the source electrode 121. In this case, the part of the absorber 170 opposite the channel 150.2 constitutes an optional rear gate of the transistor, at the same electrical potential as the source 150.1.

[0070] The photodetector 1 further comprises an optional lower barrier layer 110 and an optional upper barrier layer 130. The lower barrier layer 110 extends over the upper face of the substrate 100. The lower anchoring pillars 105 pass completely through the lower barrier layer 110, so as not to leave any space between the lower barrier layer 110 and the lower anchoring pillars 105. The upper barrier layer 130 extends over the lower face of the micro-board 160, over the grid 135, the spacers 136, over lateral sides of the grid dielectric layer 140 and over lateral sides of the micro-board 160. The source, drain and grid electrodes 121, 123, 125 pass completely through the upper barrier layer 130, so as not to leave any space between the lower barrier layer 110 and the source, drain and grid electrodes 121, 123, 125.The lower and upper barrier layers 110, 130 are made of a material suitable for resisting an engraving used to remove a sacrificial material on which the micro-plate 160 rests during an intermediate step of a manufacturing process.

[0071] The example of a photodetector 1 described in connection with Figures IA, IB, and 2 is advantageous because it allows the micro-board 160 to be suspended with only two thermal isolation arms 120, and thus provides optimal insulation for the micro-board 160 and the MOS-FET transistor. However, according to the biasing scheme in [Fig. 3], the electrical potentials VG, Vs, VD, and VBg applied respectively to the gate 135, the drain 150.3, the source 150.1, and the optional rear gate can be set independently of each other without departing from the scope of this invention. The gate 135, the source 150.1, the drain 150.3, and the rear gate can each be electrically connected to the control circuit with or without a thermal isolation arm. The 120 thermal insulation arms are therefore optional and can be any number less than or equal to 4 when present.

[0072] In [Fig.4], simulation results of the example photodetector are presented. Figures IA, IB, and 2 were generated using computer-aided design (CAD) software. The transistor is an N-MOS type. Channel 150.2 has a length L of 0.5 pm, meaning that the drain 150.3 is separated from the source 150.1 at every point by a minimum distance of 0.5 pm below the gate 135. The length L is commonly referred to as the gate length in technical terms. The gate width W is the length of a centerline separating the drain 150.3 from the source 150.1 and extending from one end of channel 150.2 to the other. When the canal has a closed ring shape, the midline also has a closed ring shape.

[0073] The thickness of the gate dielectric layer 140 is 9 nm. The gate dielectric layer 140 is made of silicon dioxide (SiO₂). The electrical potentials VBg and Vs, applied to the back gate and the source respectively, are 0 V. The electrical potential difference between the gate 135 and the source 150.1 varies so as to vary the drain current ID.

[0074] In [Fig. 4], the TCC value (ordinate axis in %K') is given as a function of IdW / L (abscissa axis in amperes) for three different concentrations of majority charge carriers in the gate 135 (curves C1, C2, and C3), here of the acceptor type, and for a prior art MOS-FET transistor having a "mid-gap" type metal gate (curve C0). The TCC curve for the "mid-gap" type metal gate is always lower than the other two curves. The TCC value increases as the concentration of majority charge carriers in the gate 135 decreases. The gain in TCC compared to a "mid-gap" type metal grid is thus equal to 6% for an acceptor type Na doping concentration equal to 1019 cm3 (C1 curve), equal to 14% for Na equal to 1018 cm3 (C2 curve), and equal to 25% for Na equal to 1016 cm3 (C3 curve).

[0075] The inventors have further verified that the TCC does not vary substantially with a variation in the thickness of the grid dielectric layer 140. The relative variation of the TCC is for example strictly less than 2% for a variation in the thickness of the grid dielectric layer 140 between 5 nm and 20 nm, a normalized drain current ID.W / L varying between 10 14 A and 5.10 4 A and a concentration of Na acceptor type dopant atoms in the grid 135 equal to 1017 cm3.

[0076] The inventors have also verified that the TCC does not vary substantially with a variation in the thickness of the grid 135. The variation of the TCC is for example substantially zero for a variation in the thickness of grid 135 between 25 nm and 150 nm, and a concentration of Na acceptor type dopant atoms in grid 135 equal to 1017 cm3.

[0077] An example of a method for manufacturing a photodetector 1 according to the invention will now be described with reference to Figures 5A to 5N, 6A and 6B. In this example, the Photodetector 1 comprises an enhancement-mode NMOS transistor. However, it is easy to modify the doping in the manufacturing process to obtain a photodetector 1 comprising an enhancement-mode NMOS transistor, or an enhancement-mode PMOS transistor, or a depletion-mode PMOS transistor. Figures 5A to 5N illustrate intermediate steps in the example manufacturing process aimed at obtaining a first intermediate structure 10 as illustrated in [Fig. 5A].

[0078] In [Fig. 5A], an assembly is provided comprising a temporary substrate 200, a buried dielectric layer 210, and an upper semiconductor layer. The buried dielectric layer 210 is intercalated and in contact with the temporary substrate 200 and the upper semiconductor layer. The temporary substrate 200 has an upper face located at the interface between the temporary substrate 200 and the buried dielectric layer 210. The upper semiconductor layer may be doped or intrinsic. The assembly may, for example, be a silicon-on-insulator (SOI) plate. The upper semiconductor layer and the temporary substrate 200 are then made of monocrystalline silicon, and the buried dielectric layer 210 is made of silicon dioxide (SiO₂). Here, the assembly is an SOI plate, for example 200 mm or 300 mm in diameter, and the top semiconductor layer is P-doped single-crystal silicon.

[0079] The buried dielectric layer 210 preferably has a thickness between 10 nm and 150 nm, preferably between 10 nm and 50 nm, for example equal to 25 nm. The upper semiconductor layer has, for example, a thickness between 5 nm and 100 nm, preferably between 15 nm and 40 nm.

[0080] The entire thickness of the upper semiconductor layer is then locally etched to obtain a semiconductor portion 150 intended to accommodate a source 150.1, a channel 150.2, and a drain 150.3 of a MOS-FET transistor. The semiconductor portion 150 can have any shape in a plane parallel to the upper face of the temporary substrate 200. It has a top face and sides. The top face of the semiconductor portion 150 joins the sides on one side of the semiconductor portion 150 opposite the buried dielectric layer 210. The semiconductor portion 150 can have a substantially constant width measured parallel to the top face. Here, it has a closed, substantially rectangular ring shape.

[0081] In [Fig. 5B], a conformal layer is formed on the sides and top face of the semiconductor portion 150. The conformal layer is intended to be a gate dielectric layer 140 of the transistor. It is made of a dielectric material. It can be obtained by deposition, or, when it is made of silicon dioxide (SiO₂), as in this example, by thermal oxidation.

[0082] The conformal layer typically has a thickness between 3 nm and 50 nm, at level of the upper face of the semiconductor portion 150.

[0083] In [Fig. 5C], a planarizing sacrificial layer 215 is formed. The planarizing sacrificial layer 215 is made of a material that can be selectively etched with respect to the gate dielectric layer 140. It can, for example, be made of amorphous or polycrystalline silicon, or a polymer. Here, it is made of polycrystalline silicon, deposited by low-pressure chemical vapor deposition, or LPCVD (Liquid Phase Chemical Vapor Deposition).

[0084] The planarizing sacrificial layer 215 has a substantially flat surface and is parallel to the upper face of the temporary substrate 200 opposite the semiconducting portion 150, preferably opposite a substantial part of the upper face of the temporary substrate 200.

[0085] In [Fig. 5D], a sacrificial pad 220 is formed. To do this, the planarizing sacrificial layer 215 is locally etched throughout to obtain the sacrificial pad 220. The sacrificial pad 220 has flanks substantially orthogonal to the upper face of the temporary substrate 200, joined by an upper face of the sacrificial pad 220 located on a side of the sacrificial pad 220 opposite the temporary substrate 200. It has a width equal to the minimum distance separating two opposite flanks of the sacrificial pad 220 in a plane parallel to the upper face of the temporary substrate 200, and a thickness measured perpendicular to the upper face. It rests entirely on a central region of the semiconductor portion 150, so as to separate two opposite regions of the semiconductor portion 150, located on either side of the central region. The width of the sacrificial pad 220 defines a gate length of the transistor.

[0086] In [Fig. 5E], a first ion implantation of first dopant ions is carried out over the entire structure obtained in the step of [Fig. 5D], followed by activation of the first dopant ions. During this step, the sacrificial pad 220 protects the part of the semiconductor portion 150 intended to be the channel 150.2 of the transistor and receives a quantity of first dopant ions to obtain a doped sacrificial pad 221, doped at least partially. The opposite regions of the semiconductor portion 150 become doped regions 231, doped of the same type as the doped sacrificial pad 221, in this example of type N. The energy of the first dopant ions is preferentially chosen to dope the entire thickness of the semiconductor portion 150 at the level of the opposite regions. The dose of first dopant ions is chosen for example to obtain a concentration of first dopant atoms in the 231 doped regions between 1017 at.cm3 ​​and 1020 at.cm3.The first dopant atoms are derived from the first dopant ions and are of a first type of conductivity.

[0087] In [Fig. 5F], spacers 136 are formed on the flanks of the doped sacrificial pad 221. For this purpose, a conformal dielectric layer can be deposited on the di-layer The buried electrical element 210, the grid dielectric layer 140, and the doped sacrificial pad 221 are all present. In this example, the dielectric layer is a silicon nitride (SiN) layer deposited by LPCVD. The dielectric layer is then anisotropically etched, perpendicular to the top face of the temporary substrate 200, across its entire thickness, leaving residues only at the flanks of the doped sacrificial pad 221. These residues are the spacers 136.

[0088] Once the spacers 136 are formed, a second ion implantation of second dopant ions is carried out. During this step, the doped sacrificial pad 221 protects the portion of the semiconductor area 150 intended to be the channel 150.2 of the transistor and receives a quantity of second dopant ions to obtain a doubly doped sacrificial pad 222. In addition, the spacers 136 protect a portion of the doped region 231 so that only a portion of each doped region 231 receives a quantity of second dopant ions to become a doubly doped region 232.

[0089] The energy of the second dopant ions is preferably chosen to dope the entire thickness of the semiconductor portion 150 at the level of the doubly doped regions 232 with second dopant atoms. The second dopant atoms are of the first type of conductivity. The dose of second dopant ions is, for example, chosen to obtain a total concentration of dopant atoms in the doubly doped regions 232 of between 10¹⁹ at.cm³ and 10²¹ at.cm³.

[0090] In this example of a manufacturing process, it is possible to omit the first or second implantation substep. It is also possible to omit the spacer 136 forming substep.

[0091] In [Fig. 5G], a first barrier layer 241 is conformally deposited on the doubly doped sacrificial pad 222, the spacers 136, the grid dielectric layer 140, and the buried dielectric layer 210. The first barrier layer 241 is intended to protect the elements it covers during a subsequent step of etching sacrificial layers, known as liberation etching. The first barrier layer 241 is, for example, made of alumina (Al₂O₃) or aluminum nitride (Al₂O₅), so as to resist etching with hydrofluoric acid (HF) in the vapor phase.

[0092] In [Fig. 5H], a planarizing layer 250 is deposited so as to completely cover the first barrier layer 241. The planarizing layer 250 is made of an electrically insulating material, for example a dielectric. It is suitable for etching during the release etching process. In this example, it is made of silicon dioxide (SiO₂).

[0093] In [Fig.51], a chemical-mechanical polishing (CMP) of the planarizing layer 250 is carried out with a stop on the first barrier layer 241 to obtain a first sacrificial layer 251. At the end of this step, the first barrier layer 241 has a top surface opposite the doped sacrificial pad 222 flush with the first sacrificial layer 251.

[0094] In [Fig. 5J], the first barrier layer 241 is locally etched through its upper surface to obtain a grid opening 225. The grid opening 225 has all its dimensions along directions in a plane parallel to the upper face of the temporary substrate 200 strictly smaller than the dimensions of the doped sacrificial pad 222 along the same directions. A difference in size between the doped sacrificial pad 222 and the grid opening 225 is, for example, sufficient to compensate for alignment errors during a photolithography substep implemented to define the grid opening 225 during the step in [Fig. 5J].

[0095] At the end of this step, the portions of the first barrier layer 241 in physical contact with the doubly doped sacrificial pad 222 each constitute a protective flap 241.1. Preferably, each protective flap 241.1 has all its dimensions in a plane parallel to the upper face of the temporary substrate 200 sufficient to protect the spacers 136 and the gate dielectric layer 140 during the release etching. For example, they are all greater than 50 nm, or even greater than 100 nm.

[0096] An attack on the spacers 136 during the release etching is likely to generate parasitic charges altering the operation of the photodetector 1. An attack on the gate dielectric layer 140 during the release etching is likely to induce a parasitic gate current of the transistor and / or a decrease in the TCC and / or a greater detection noise, when the photodetector 1 is in operation.

[0097] In [Fig. 5K], the doubly doped sacrificial pad 222 is removed. To do this, the entire doubly doped sacrificial pad 222 is selectively etched with respect to the first barrier layer 241 and the first sacrificial layer 251, preferably by wet etching. This creates a cavity 226 in place of the doubly doped sacrificial pad 222. When the planarizing sacrificial layer 215 is made of amorphous or polycrystalline silicon, the doubly doped sacrificial pad 222 can be etched with a 1% concentrated TMAH or HF solution. When the planarizing sacrificial layer 215 is made of a polymer, the doubly doped sacrificial pad 222 can be etched with an oxygen plasma.

[0098] The steps in Figures 5L and 5M are aimed at filling the cavity 226 with a semiconductor material to obtain a gate 135 of the transistor. In [Fig. 5L], a planarizing semiconductor layer 260 is conformally deposited so as to completely fill a volume of the cavity 226 in communication with the gate opening 225. The planarizing semiconductor layer 260 completely covers the gate dielectric layer 140 inside the cavity 226. Preferably, it fills substantially the entire cavity 226, as shown here. In this case, it covers more The first sacrificial layer 251 and the first barrier layer 241 are located at the level of the protective flaps 241.1, as shown in [Fig. 5L]. The planarizing semiconductor layer 260 is doped in situ with a second type of conductivity, opposite to the first type of conductivity. It is made of a semiconductor material resistant to liberation etching. In this example, it is made of polycrystalline or amorphous silicon, for liberation etching using hydrofluoric acid (HF) in the vapor phase.

[0099] In [Fig. 5M], when the planarizing semiconductor layer 260 covers the first sacrificial layer 251, a chemical-mechanical polishing (CMP) of the planarizing semiconductor layer 260 is performed, stopping at the first sacrificial layer 251, to obtain a residual portion of the planarizing semiconductor layer 260 located in the cavity 226. When the planarizing semiconductor layer 260 has not been doped in-situ, i.e., simultaneously with the deposition of the planarizing semiconductor layer 260, the residual portion is doped with the second type of conductivity following the planarization substep, for example, by implantation or diffusion of doping species. The residual portion is intended to be a gate 135 of the transistor. Since the first sacrificial layer 251 is flush with the first barrier layer 241 and the polishing stops on the first sacrificial layer 251, the grid 135 has a summit surface 135.2 flush with the first barrier layer 241 and blocking the grid opening 225. .

[0100] Since the planarizing semiconductor layer 260 is made of a semiconductor material resistant to release etching, the grid 135 is not damaged during release etching even though it is not covered by the first barrier layer 241 at its summit surface 135.2. The first barrier layer 241 and the summit surface 135.2 of the grid 135 together protect the spacers 136 during release etching.

[0101] In [Fig. 5N], a second sacrificial layer 252 is deposited, preferably of the same material as the first sacrificial layer 251. The second sacrificial layer 252 is made of an electrically insulating material, for example a dielectric, here silicon dioxide (SiO₂). A drain electrode 123, a gate electrode 125, and a source electrode 121 (not shown) are formed by substeps of photolithography, etching, deposition, and polishing. The source, drain, and gate electrodes 121, 123, and 125 pass completely through the second sacrificial layer 252. The source and drain electrodes extend through the first sacrificial layer 251, the first barrier layer 241, and the gate dielectric layer 140, to respective doubly doped regions 232. The grid electrode 125 is in physical contact with the apex surface 135.2 of the grid 135.The source, drain and grid electrodes 121, 123, 125 are flush with a top face of the . second sacrificial layer 252. Each source electrode 121 and each drain electrode 123 have a section in contact with the first barrier layer 241 over its entire periphery.

[0102] Following the step in [Fig. 5N], one or more thermal insulation arms 120 are formed by substeps of photolithography, etching, and deposition. A third sacrificial layer 253 is then deposited on the second sacrificial layer 252 and each thermal insulation arm 120, preferably in the same material as the first sacrificial layer 251 and / or the second sacrificial layer 252. The third sacrificial layer 253 is made of an electrically insulating material, for example a dielectric, here silicon dioxide (SiO₂). Next, upper anchoring pillars 115 are formed extending into the third sacrificial layer 253 from an upper face of the third sacrificial layer 253 located on one side of the third sacrificial layer 253 opposite the temporary substrate 200, until reaching a thermal insulation arm 120. This gives a first intermediate structure 10, represented schematically in [Fig. 0A].

[0103] The upper face of the third sacrificial layer 253 together with the ends of the upper anchoring pillars 115 constitutes a first bonding face 253.1 of the first intermediate structure 10. The first bonding face 253.1 has surface condition, roughness and flatness characteristics allowing hybrid direct bonding.

[0104] Fig. B is a schematic cross-sectional view of a second intermediate structure 20 to be assembled with the first intermediate structure 10 to obtain the photodetector 1. The second intermediate structure 20 comprises, superimposed, a substrate 100, a lower barrier layer 110 and a fourth sacrificial layer 254. The lower barrier layer 110 is intercalated and in contact with the substrate 100 and the fourth sacrificial layer 254.

[0105] The fourth sacrificial layer 254 is preferably made of the same material as the first sacrificial layer 251 and / or the second sacrificial layer 252 and / or the third sacrificial layer 253. The fourth sacrificial layer 254 is made of an electrically insulating material, for example a dielectric, here silicon oxide (SiO).

[0106] The substrate 100 includes a control circuit. The second intermediate structure 20 includes one or more lower anchoring pillars 105. Each lower anchoring pillar 105 passes completely through the fourth sacrificial layer 254 and the lower barrier layer 110, and extends to a connection pad of the control circuit. When the photodetector 1 has a multi-pixel array, the upper anchoring pillars 115 are repeated at the pixel pitch of the photodetector 1. The substrate 100 or the second intermediate structure 20 may be supplied by a foundry of electronic chips, at least in part.

[0107] The second intermediate structure 20 has a second bonding face 254.1 on a side opposite the substrate 100. The second bonding face 254.1 has ends of the upper anchoring pillars 115 and a surface of the fourth sacrificial layer 254. It has surface condition, roughness and flatness characteristics allowing hybrid direct bonding.

[0108] In a final step, the first bonding face 253.1 is brought into contact with the second bonding face 254.1 so as to bring a lower anchoring pillar 105 into contact with a respective upper anchoring pillar 115, and the third sacrificial layer 253 into contact with the fourth sacrificial layer 254. The first bonding face 253.1 and the second bonding face 254.1 together constitute a bonding interface. The bonding interface is optionally reinforced by heat treatment.

[0109] The temporary substrate 200 is then removed by substeps of lapping and / or polishing and / or wet or dry etching. The thickness of the buried dielectric layer 210 can optionally then be adjusted by one or more substeps of deposition and / or polishing and / or etching. This can, for example, be advantageous for obtaining a micro-board thickness 160 that gives the micro-board 160 specific mechanical and / or electrical properties from a set taken from standard SOI boards.

[0110] A metallic layer, for example titanium nitride (TiN), is deposited on the buried dielectric layer 210. Preferably, the metallic layer has a thickness that allows it to be adapted to the impedance of a vacuum. The metallic layer and the buried dielectric layer 210 are etched locally, through and through, until the first barrier layer 241 is reached, without exceeding it, so as to define a micro-plate 160 in the buried dielectric layer 210 in contact with the transistor. The residual part of the metallic layer constitutes an absorber 170 of the photodetector 1.

[0111] An additional barrier layer is deposited, completely covering the absorber 170, the micro-board 160, and the first barrier layer 241. A vent is made through the additional barrier layer and the first barrier layer 241 in a region where they are both in contact. The release etching is then performed. For this purpose, the first, second, third, and fourth sacrificial layers 251, 252, 253, 253 are selectively etched with respect to the first barrier layer 241, the lower barrier layer 110, and the grid 135, for example, by hydrofluoric acid in the vapor phase.

[0112] Specific embodiments have just been described. Various variants and modifications will be apparent to those skilled in the art.

Claims

Demands

1. Detector (1) of electromagnetic radiation, comprising: • an absorber (170) configured to absorb electromagnetic radiation, • a MOS-FET type transistor thermally coupled to the absorber (170), comprising • a source (150.1) doped with a first type of conductivity, • a drain (150.3) doped with the first type of conductivity, • a channel (150.2) extending from the source (150.1) to the drain (150.3), • a gate (135) electrically isolated from the channel (150.2) by a gate dielectric layer (140) of the transistor, • a control circuit electrically connected to the source (150.1), the drain (150.3) and the gate (135); and configured to apply an electrical potential difference between the gate (135) and the source (150.1).1) less than or equal in absolute value to a threshold voltage of the transistor, the detector (1) being characterized in that • the gate (135) is made of silicon doped with a second type of conductivity opposite to the first type of conductivity with a concentration of majority charge carriers less than or equal to 1019 cm3, and in that • the dielectric layer of gate (140) has a thickness less than or equal to 50 nm.

2. Detector (1) according to claim 1, further comprising a substrate (100), a micro-board (160) of a dielectric material suspended above the substrate (100), and a semiconducting portion (150) extending over a lower face of the micro-board (160) in which the drain (150.3), the channel (150.2) and source (150.1) are housed.

3. Detector (1) according to claim 2, wherein the absorber (170) extends over a portion of the micro-board (160) lacking the portion semiconductor (150).

4. Detector (1) according to any one of claims 2 or 3, wherein the transistor further comprises a rear gate electrically connected to the control circuit and electrically isolated from the channel (150.2) by the micro-board (160).

5. Detector (1) according to claim 4, wherein the rear grid is a part of the absorber (170).

6. Detector (1) according to claim 5, wherein the micro-board (160) has a thickness between 10 nm and 150 nm.

7. Detector (1) according to any one of claims 2 to 6, wherein the drain (150.3) and the grid (135) are connected to the control circuit by a first thermal insulation arm (120), the source (150.1) is electrically connected to the control circuit by a second thermal insulation arm (120), and the micro-board (160) is suspended above the substrate (100) by the first and second thermal insulation arms (120).

8. Detector (1) according to claims 4 and 7, wherein the rear grid is electrically connected to the source (150.1) by a rear-facing electrical contact (128) passing through the micro-board (160), and the source (150.1) is electrically connected to the second thermal insulation arm (120) by a source electrode (121) opposite the rear-facing electrical contact (128).

9. Detector (1) according to any one of the preceding claims, wherein the transistor is a depletion transistor.

10. Detector (1) according to any one of claims 1 to 8, wherein the transistor is an enhancement transistor.

11. A method for manufacturing a detector (1) according to any one of claims 1 to 10, comprising the following grid formation steps (135): • formation of a sacrificial pad (222), • formation of spacers (136) on flanks of the sacrificial pad (222), • conformal deposition of a first barrier layer (241) on the spacers (136) and the sacrificial pad (222), • deposition of a planarizing semiconductor layer (260) so as to completely cover the first barrier layer (241), • polishing of the planarizing semiconductor layer (260) with stopping on the first barrier layer (241) to obtain a first sacrificial layer (251), • etching of a gate opening (225) passing through the first barrier layer (241) through a top surface of the first barrier layer (241) opposite the sacrificial pad (222), the opening having dimensions strictly less than the dimensions of the sacrificial pad (222), • removal of the sacrificial pad (220) to obtain a cavity (226) in place of the sacrificial pad (222), • filling of the cavity (226) with silicon so as to close the gate opening (225) and thus obtain the gate (135).

12. A manufacturing method according to claim 11, wherein the sacrificial pad (222) is formed on a semiconductor portion (150) in which the drain (150.3), the channel (150.2) and the source (150.1) are housed, and the sacrificial pad (220) protects the channel (150.2) during a step of implanting the source (150.1) and the drain (150.3).

13. A manufacturing method according to any one of claims 11 or 12, wherein the sacrificial pad (220) is made of silicon.

14. A manufacturing method according to any one of claims 11 to 13, wherein the cavity filling step (226) comprises: • a deposition of a planarizing semiconductor layer (260) doped in-situ, so as to totally fill a volume of the cavity (226) in communication with the gate opening (225) and to cover the first sacrificial layer (251) and the first barrier layer (241), • a polishing of the planarizing semiconductor layer (260) with stopping on the first sacrificial layer (251).

15. A manufacturing method according to any one of claims 11 to 14, wherein the detector (1) is a detector according to any one of claims 2 to 8, further comprising a micro-plate release etching (160) during which the first sacrificial layer- ficielle (251) is selectively engraved with respect to the first barrier layer (241) and the grid (135).

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