silicon wafer

Abstract

silicon wafer (10) wherein the 50% threshold of a nanotopography within a 2 mm square spot having a size with a length in at least one direction of 2 mm and an area of ​​4 mm 2 exhibits 1.0 nm or less, and wherein the 50% nanotopography threshold is less than or equal to 0.4 times the 99.5% nanotopography threshold.

Description

TECHNICAL AREA

[0001] The present invention relates to a polished silicon wafer. A polishing process by which such a silicon wafer can be produced is described. BACKGROUND

[0002] Silicon wafers are widely used as a substrate material for semiconductor devices. Silicon wafers are produced by sequentially performing processes including external peripheral grinding, slicing into wafers, lapping, etching, double-sided polishing, single-sided polishing, and washing to create a silicon single-crystal ingot. Of these, the single-sided polishing process is necessary to remove any unevenness or waviness on the wafer surface and thus improve its flatness, achieving a high-gloss finish through CMP (chemical-mechanical polishing).

[0003] Typically, a single-wafer polishing (CMP) setup is used for the one-sided polishing process of a silicon wafer. The wafer polishing setup includes a rotating carrier plate to which a polishing pad is attached, and a polishing head for pressing the wafer onto the polishing pad and holding it in place. The setup rotates the carrier plate and polishing head while a slurry is fed in, thus polishing one surface of the wafer.

[0004] In recent years, silicon wafers have developed a problem with a minute surface irregularity known as "nanotopography." Nanotopography refers to a periodic ripple component present on the wafer surface with a wavelength shorter than that of "BOW" (bending) and "warp" (curvature) and longer than that of "surface roughness," ranging from 0.2 mm to 20 mm and exhibiting an amplitude (peak-to-valley value) of several tens of nm. If the nanotopography exceeds a certain threshold, the yield of shallow trench insulation (STI) in a device process deteriorates, leading to significant variation in device characteristics, such as the threshold voltage Vth. T , leads.

[0005] Regarding nanotopography, for example WO 2004 / 100 243 A1 describes a slurry composition for chemical-mechanical polishing which is capable of compensating for the nanotopography effect, and a method for planarizing the surface of a semiconductor device using the composition.

[0006] US patent 2019 / 0061095A1 discloses a method for chemically-mechanically polishing the surface of a wafer using a polishing pad.

[0007] US 2003 / 0 216 111 A1 discloses polishing pads with a surface roughness of 0.1 - 10µm and thickness variations of less than 30µm.

[0008] US 2011 / 0 256 812 A1 also concerns polishing using polishing pads.

[0009] JP 2003 - 257 908 A concerns a wafer with a low threshold of nanotopography.

[0010] DE 10 2014 106 290 A1 discloses a method for measuring the nanotopography of wafers. SUMMARY OF THE INVENTION [Problem to be solved by the invention]

[0011] The recent trend in precision tooling leads to a significant reduction in the spacing between adjacent elements, thus increasing the influence of nanotopography on tool dimensional accuracy. For example, the presence of nanotopography causes a variation in machining allowances for CMP machining, affecting the height dimension of the elements. Accordingly, it is necessary to ensure that nanotopographic characteristics fall within stricter specifications in the future, and improvements in nanotopographic characteristics within a very small area of ​​2 mm square (2 mm × 2 mm) are particularly in demand.

[0012] It is therefore an objective of the present invention to provide a silicon wafer polished by a wafer polishing process capable of improving nanotopography characteristics within a spot on the surface of a wafer with a 2mm square area. [Means of solving the problems]

[0013] As a result of intensive research into a mechanism for generating nanotopography, the present inventors have discovered that a polishing unevenness occurring in a one-sided polishing process, where the machining allowance is set to approximately 0.5 µm, causes a 2 mm² nanotopography, and that this polishing unevenness is caused by a non-uniform thickness of a polishing pad. It was assumed that a certain degree of thickness variation in the plane of the polishing pad is necessary to retain slurry between the polishing pad and the surface of the wafer being machined, thus improving polishing efficiency. However, considering a waviness component in a very small area of ​​2 mm², the present inventors have found that it is necessary to sufficiently reduce the thickness variation in the plane of the polishing pad.Furthermore, it was found that when assessing nanotopography within a 2mm square area, using a 50% threshold for nanotopography instead of the 99.95% and 99.5% thresholds is effective in reducing variation in device characteristics.

[0014] The present invention was based on such technical results and a wafer polishing method that can be used to produce a silicon wafer according to the invention is a method for chemical-mechanical polishing on a surface of a wafer by two or more polishing steps with different polishing rates, wherein a thickness variation in the plane (standard deviation) of a polishing pad used in a polishing step with a machining allowance of 0.3 µm or more is 2.0 µm or less.

[0015] According to the present invention, the 2 mm square nanotopography on the wafer surface, which is caused by the thickness variation of the polishing pad, can be improved. In particular, by reducing the 50% threshold for the 2 mm square nanotopography to 1.0 nm or less, it is possible to reduce the variation in device characteristics in the wafer plane and thereby produce semiconductor chips with uniform device characteristics.

[0016] In the present invention, the two or more polishing steps preferably include a first polishing step for polishing the surface of the wafer by 0.3 µm or more, and a second polishing step for polishing the surface of the wafer at a polishing rate lower than that of the first polishing step. The in-plane thickness variation (standard deviation) of a polishing pad used in the first polishing step is preferably 2.0 µm or less. In this case, the polishing rate of the wafer in the first polishing step is preferably 50 nm / min or more. Polishing a roughness that occurs in the first polishing step affects the nanotopography on the wafer surface; however, by reducing the thickness variation (standard deviation) of the polishing pad used in the first polishing step to 2.0 µm or less, it is possible to suppress a polishing roughness and thereby improve the 2 mm square nanotopography.

[0017] In the present invention, the 50% threshold for the nanotopography within a location defined on the surface of the wafer polished by the first and second polishing steps is a size with a length in at least one direction of 2 mm and an area of ​​2 mm². 2 or more and 4 mm 2or less, preferably 1.0 nm or less. The 50% nanotopography threshold refers to a maximum value below 50% of accumulated values ​​of a nanotopography value for each site on the wafer plane, obtained as a result of excluding the upper 50% of the accumulated values. The site size is preferably 2 mm square (2 mm × 2 mm). By reducing the 50% nanotopography threshold within a 2 mm square site on the wafer surface to 1.0 nm or less, nanotopography characteristics can be further improved. This makes it possible to reduce variation in device characteristics on the wafer plane and thereby fabricate semiconductor chips with uniform device characteristics.

[0018] In the present invention, the relative velocity of the wafer to the polishing pad in the first polishing step is preferably 0.3 m / s or less, and the in-plane thickness variation (standard deviation) of the polishing pad used in the first polishing step is preferably 1.6 µm or less. Furthermore, the ROA (roll-off amount) at a position 1 mm inward from an outermost periphery of the wafer polished by the first and second polishing steps is preferably 20 nm or less. This makes it possible not only to improve the 2 mm square nanotopography on the wafer surface due to a thickness variation of the polishing pad, but also the flatness of the wafer's outer periphery.

[0019] The wafer polishing method according to the present invention preferably further comprises a polishing pad thickness evaluation step for measuring an in-plane thickness variation of a polishing pad used in the chemical and mechanical polishing of a wafer, and checking whether the in-plane thickness variation (standard deviation) is 2.0 µm or less, and a polishing pad thickness adjustment step for adjusting the thickness distribution of the polishing pad if the in-plane thickness variation (standard deviation) of the polishing pad is not 2.0 µm or less, so that the thickness variation (standard deviation) is reduced to 2.0 µm or less, and the polishing pad with an in-plane thickness variation (standard deviation) of 2.0 µm or less is preferably used to polish the surface of the wafer by 0.3 µm or more.This allows the thickness variation (standard deviation) of a polishing pad used in the polishing step to polish the wafer surface by 0.3 µm to be 2.0 µm or less without failure, thus enabling reliable improvement of nanotopography characteristics within a 2mm square area on the silicon wafer.

[0020] Furthermore, a silicon wafer according to the present invention is a silicon wafer in which the 50% threshold of a nanotopography is present within a 2 mm square spot having a size with a length in at least one direction of 2 mm and an area of ​​4 mm². 2exhibits a nanotopography size of 1.0 nm or less, and wherein the 50% threshold of the nanotopography is less than or equal to 0.4 times the 99.5% threshold of the nanotopography. In this case, the ROA at a position 1 mm inward from an outermost periphery of the wafer is preferably 20 nm or less. According to the present invention, variation in device characteristics in the wafer plane can be reduced to enable the fabrication of semiconductor chips with uniform device characteristics. [Advantageous effects of the invention]

[0021] According to the present invention, a silicon wafer polished by the wafer polishing process described above can be provided. BRIEF DESCRIPTION OF THE DRAWINGS [ Fig. 1] Fig. Figure 1 is a schematic view to explain a silicon wafer polishing process which can be used to produce the claimed silicon wafer. [ Fig. 2] Fig. Figure 2 is a schematic view to explain the relationship between the polishing head and the polishing pad, which is shown in Fig. 1 are illustrated. [ Fig. 3] Fig. Figure 3 is a flowchart to explain the silicon wafer polishing process, which uses the process described in Fig. 1 illustrated single-sided polishing device is used. [ Fig. 4] Fig. Figure 4 is a graph showing the relationship between the thickness variation distribution (standard deviation) of the polishing pad and the 2mm square nanotopography value. [ Fig. 5] Fig. Figure 5 is a graph showing the relationship between the polishing allowance of the wafer and the nanotopography within the 2mm square spot. [ Fig. 6] Fig. Figure 6 is a graph showing the relationship between the relative velocity of the wafer to the pad and the nanotopography at the location of the 2mm square. [ Fig.7] Fig. Figure 7 is a graph showing the relationship between the relative velocity of the wafer to the pad and the ROA at the wafer outer peripheral part. WAYS TO EXECUTIVE THE INVENTION

[0022] A preferred embodiment of the present invention is described in detail below with reference to the accompanying drawings.

[0023] Fig. Figure 1 is a schematic view to explain a silicon wafer polishing process which can be used to produce the claimed silicon wafer.

[0024] As in Fig.As illustrated in Figure 1, a silicon wafer polishing process is a method for chemically-mechanically polishing one side of a silicon wafer using a single-sided, single-wafer-type polishing device 100. A machine-machinable silicon wafer 10 is cut from a single-crystal silicon ingot grown by a CZ process using a wire saw and is then subjected to lapping (double-sided grinding) and double-sided polishing.

[0025] The single-sided polishing device 100 comprises a polishing head 120 for clamping the silicon wafer 10 and a rotating carrier plate 140 to which a polishing pad 150 is attached. The single-sided polishing device 100 is further equipped with a rotation mechanism for rotating the polishing head 120 and a movement mechanism for moving the polishing head 120 inside and outside the rotating carrier plate 140.

[0026] The polishing pad 150 is not specifically limited in terms of structure and can be a polishing pad with a two-layer structure, in which a NAP layer (polyurethane foam layer) is formed on an underlying layer obtained by impregnating a non-woven fabric with polyurethane, or it can be a velour-type polishing pad with a two-layer structure, which includes a hard NAP layer and a soft NAP layer.

[0027] In the single-sided polishing device 100, in a state in which the silicon wafer 10 is held by the polishing head 120, a surface to be machined (i.e. a surface facing the rotary carrier plate 140) of the silicon wafer 10 is pressed against the polishing pad 150 on the rotary carrier plate 140 and the polishing head 120 and the rotary carrier plate 140 are rotated together.

[0028] Then a slurry 170 is provided by a slurry delivery device 160, while the polishing head 120 and the rotary carrier plate 140 are moved accordingly in order to chemically and mechanically polish the surface of the silicon wafer 10 to be polished.

[0029] Fig. Figure 2 is a schematic view to explain the relationship between the polishing head 120 and the polishing pad 150, which is shown in Fig. 1 are illustrated.

[0030] As in Fig.As illustrated in Figure 2, the polishing head 120 has a backplate 122 for clamping the silicon wafer 10, and a retaining ring 124 to prevent the silicon wafer 10 being polished from popping out is provided at the peripheral edge of the backplate 122. The silicon wafer 10 is subjected to one-sided polishing with its one surface (surface to be polished) protruding from a lower end surface 124A of the retaining ring 124, and the polishing pad 150, which is an elastic body, is forced downwards beneath the silicon wafer 10 by a pressing force from the polishing head 120.The slurry 170, which is supplied to the polishing head 150, flows from the centers of the rotary carrier plate 140 and the polishing pad 150 to the peripheral edges due to the centrifugal force caused by the rotation of the rotary carrier plate 140, and enters a small gap between the silicon wafer 10 and the polishing pad 150 and between the retaining ring 124 and the polishing pad 150.

[0031] Fig. Figure 3 is a flowchart to explain the silicon wafer polishing process, which uses the process described in Fig. 1 illustrated single-sided polishing device 100 is used.

[0032] As in Fig.As illustrated in Figure 3, the silicon wafer polishing process according to the present embodiment includes a polishing pad thickness assessment step S10 for measuring, in advance, a variation in the thickness of the polishing pad, a first polishing step S11 for polishing the surface of the silicon wafer by 0.3 µm or more using the polishing pad after assessment, a second polishing step S12 for further polishing the surface of the silicon wafer polished in the first polishing step S11 at a polishing rate lower than that of the first polishing step S11, and a 2 mm square nanotopography assessment step S13 for measuring the nanotopography within a 2 mm square area on the silicon wafer after polishing.

[0033] The first polishing step S11 is a so-called semi-final polishing step in which the silicon wafer is polished at a polishing rate higher than that of the second polishing step S12, using a slurry with a high etch rate. The polishing rate (first polishing rate) in the first polishing step S11 is 50 nm / min or more, and preferably 100 nm / min or more.

[0034] The in-plane thickness variation (standard deviation) of a polishing pad used in the first polishing step S11 is set to 2.0 µm or less. Accordingly, in the first polishing step S11, chemical-mechanical polishing is performed with the in-plane thickness variation (standard deviation) of a silicon wafer limited to 2.0 µm or less, thus making it possible not only to ensure a machining allowance of 0.3 µm or more, but also to reduce the nanotopography within a 2 mm² area to 1.0 nm or less.

[0035] When the relative velocity of the wafer to the polishing pad is set to a low speed of 0.3 m / s or less, the in-plane thickness variation (standard deviation) of the polishing pad used in the first polishing step S11 is preferentially set to 1.6 µm or less. Rotating the polishing head and rotary carrier plate at a low speed to reduce the relative velocity of the wafer to the polishing pad can improve the flatness of the wafer's outer periphery, while likely degrading nanotopographic characteristics. However, when the in-plane variation (standard deviation) of the polishing pad is set to 1.6 µm or less, the ROA at a position 1 mm inward from the outermost periphery of the wafer can be reduced to 20 nm or less, and the nanotopography within a 2 mm square area can be reduced to 1.0 nm or less.This means that the flatness of the wafer outer peripheral part and nanotopography characteristics can be improved.

[0036] The second polishing step, S12, is preferably a so-called final polishing step in which the surface of the silicon wafer is polished at a second polishing rate lower than the first, using a slurry with a low etch rate. The etch rate in the second polishing step, S12, is 10 nm / min or less, and preferably 5 nm / min or less. A velour leather polishing pad consisting of an upper NAP layer and a lower non-woven fabric layer is used in the second polishing step, S12. Furthermore, the low polishing rate allows the use of a polishing pad with a thickness variation (standard deviation) of 20 µm or less.

[0037] In the present embodiment, it is preferred to perform a polishing pad thickness assessment step S10 prior to the first polishing step S11. This step measures the thickness distribution in the plane of the polishing pad used in the first polishing step S11 and verifies whether the thickness variation in the plane (standard deviation) of the polishing pad is 2.0 µm or less. A polishing pad with a thickness variation (standard deviation) of 2.0 µm or less can be used as an acceptable product in the first polishing step S11. Conversely, a polishing pad with a thickness variation exceeding 2.0 µm must be adjusted with respect to its thickness distribution so that the thickness variation (standard deviation) is reduced to 2.0 µm or less.This allows a polishing pad with a thickness variation (standard deviation) of 2.0 µm or less to be used in the first polishing step S11 without failure, making it possible to improve nanotopography characteristics within a 2mm square area on the silicon wafer after polishing.

[0038] In the present embodiment, it is preferred to perform a 2 mm² nanotopography evaluation step S13 after the first polishing step S11 and the second polishing step S12 to evaluate the nanotopography within a 2 mm² area on the silicon wafer. If a 50% threshold value of a nanotopography within a 2 mm² area on the silicon wafer is 1.0 nm or less, the silicon wafer is determined to be acceptable with respect to nanotopography characteristics; conversely, if the 50% threshold value exceeds 1.0 nm, the silicon wafer is determined to be a failure. The 50% threshold value (50%Th) of a nanotopography refers to a nanotopography value whose cumulative probability is 50%, which is a maximum value when only a relatively small nanotopography is set as an evaluation target, excluding the upper 50% of the nanotopography.

[0039] When measuring nanotopography, a height map indicating the roughness of the wafer surface is generated and then flattened by filtering, removing curvature or waviness on the micrometer scale. The filtered height map of the wafer surface is then divided into spots of a desired size (in this example, a 2 mm square), and a peak-to-valley (PV) value is calculated for each spot. Then, as described above, a PV value with a 50% cumulative probability is selected from the PV values ​​of all spots to represent the nanotopography value of the wafer surface.

[0040] If the silicon wafer is identified as a failure with respect to nanotopographic characteristics after passing through the first polishing step S11 and the second polishing step S12, it is preferred to perform a polishing pad thickness adjustment step to adapt the thickness of the polishing pad used to polish the failed wafer in the first polishing step S11 and then perform additional polishing of the failed wafer. Alternatively, a new, different polishing pad with a smaller thickness variation than the polishing pad used in the first polishing step S11 is used to perform additional polishing of the failed wafer. Furthermore, as an alternative, a new polishing pad might not be used for the failed wafer, but rather when the first polishing step S11 is performed in the next batch.In this case, the 2 mm square nanotopography (50% threshold) can be reduced to 1.0 nm or less in the next batch, although the nanotopography of the failed wafer is not improved. If the nanotopography value is 0.1 nm or less, a ROA ≤ 20 nm can also be achieved while using a polishing pad with improved thickness distribution.

[0041] If the in-plane thickness variation (standard deviation) of the polishing pad used in the first polishing step S11 is set to 2.0 µm or less, the 50% threshold for nanotopography within a 2 mm square spot can be reduced to 1.0 nm or less; however, the suppression effect for, e.g., a 99.5% threshold is small. The nanotopography extracted based on a 99.5% threshold level includes a previously process-derived large waviness that cannot be corrected by CMP, so no change occurs even if CMP conditions are modified. However, waviness of the 50% threshold level can be controlled by CMP, thus enabling an improvement in nanotopography. The 50% threshold is the median value of the nanotopography distribution, around which many spots are distributed, thus allowing the nanotopography within many spots to be improved.

[0042] In general, when the threshold is changed from 0% to 100%, the change in nanotopography (threshold curve) differs significantly depending on the nanotopography spot size. That is, nanotopography within a 2 mm square spot will draw a threshold curve that is completely different from nanotopography within, for example, a 10 mm square spot.Although there may be a case, for example, where the 99.5% threshold for nanotopography within a 10 mm square is smaller than a 1% threshold for nanotopography within a 2 mm square, the probability that the 99.5% threshold for nanotopography within a 10 mm square is smaller than a 10% threshold for nanotopography within a 2 mm square is very low, and the probability that the 99.5% threshold for nanotopography within a 10 mm square is smaller than the 50% threshold for nanotopography within a 2 mm square is almost zero.

[0043] Furthermore, the 50% threshold, even for the same 2 mm² nanotopography, is sufficiently smaller than the 99.5% threshold and is typically 0.4 times smaller or less. That is, if the 50% threshold for nanotopography within a 2 mm² area is 1.0 nm, the 99.5% threshold for nanotopography within a 2 mm² area is 2.5 nm or more.

[0044] As described above, in the silicon wafer polishing process according to the present embodiment, the in-plane thickness variation (standard deviation) of the polishing pad used in the first polishing step S11 with a machining allowance of 0.3 µm or more is set to 2.0 µm or less, thus improving the nanotopography within a 2 mm² area on the wafer surface, which is caused by the thickness variation (standard deviation) of the polishing pad. In particular, the 50% threshold for nanotopography within a 2 mm² area can be reduced to 1.0 nm or less. This makes it possible to reduce variation in device characteristics in the wafer plane and thereby produce semiconductor chips with uniform device characteristics.

[0045] Although the preferred embodiment of the present invention has been described, the present invention is not limited to the above embodiment and various modifications can be made within the scope of protection of the present invention, and all such modifications are included in the present invention.

[0046] For example, the wafer polishing method according to the above embodiment includes a two-stage polishing step with different polishing rates; however, the number of stages is not limited to two, but the polishing step can have three or more stages. Although the polishing method in the above embodiment is applied to a silicon wafer, the present invention can be applied to wafers other than silicon. [Examples]

[0047] The influence of polishing pad thickness variation (standard deviation) on nanotopography was assessed. First, polishing pad samples #1 to #5 were prepared. Samples #1 to #3 were each a polishing pad with an underlying nonwoven fabric layer bonded with polyurethane and a NAP layer formed on top. The surface of the nonwoven fabric was smoothed to reduce thickness variation. The thicknesses of samples #1 to #3 were varied so that #1 > #2 > #3. Samples #4 and #5 were each a polishing pad consisting of only a single NAP layer. Sample #4 had a two-layer NAP structure obtained by laminating two NAP layers, and sample #5 had a single-layer NAP structure using only one NAP layer.

[0048] The thickness distribution of polishing pad samples #1 to #5 was then measured. A Schopper thickness gauge was used to measure the thickness at 2-cm intervals within an 80-cm² area, followed by mapping of the measurement results. The evaluation results of the thickness distributions of polishing pads #1 to #5 are shown in Table 1. [Table 1] sample type Average (mm) R (mm) σ (mm) 1 Nonwoven fabric + NAP 0,724 0,156 0,0254 #2 Nonwoven fabric + NAP 0,650 0,049 0,0160 #3 Nonwoven fabric + NAP 0,684 0,040 0,0059 #4 Two NAP layers 0,616 0,017 0,0016 #5 Single NAP layer 0,304 0,008 0,0011

[0049] As shown in Table 1, the mean values ​​(mm) of the thickness distributions of polishing pad samples #1 to #5 were such that #1 > #3 > #2 > #4 > #5. Conversely, the ranges R (mm) and standard deviations σ (mm) of the thickness distributions of polishing pad samples #1 to #5 were such that #1 > #2 > #3 > #4 > #5.

[0050] Polishing pad samples #1 to #5 were then used to perform one-sided polishing on silicon wafers W1 to W5, each with a diameter of 200 mm. Subsequently, the 2 mm square nanotopography of silicon wafers W1 to W5 was measured. The nanotopography measurement was performed using an optical interferometric flatness / nanotopography measurement device (KLA-Tencor Corporation: Wafer Sight 2). The spot size of each wafer was set to 2 mm square, and the nanotopography value within each spot was calculated and mapped. Furthermore, the 99.5% and 50% thresholds were calculated from the nanotopography distribution. The results are shown in Table 2.

[0051] The 99.5% nanotopography threshold refers to a nanotopography value with a cumulative probability of 99.5%. As described above, the 50% nanotopography threshold also refers to a nanotopography value with a cumulative probability of 50%. That is, the 99.5% nanotopography threshold is a maximum nanotopography value obtained after excluding the top 0.5% of values, which are very large abnormal values. The 50% nanotopography threshold refers to a maximum value obtained when only a relatively small nanotopography is used as an assessment target, excluding the top 50% of nanotopography values. [Table 2] Thickness variation of the polishing pad [µm] 99.5% threshold for nanotopography [nm] 50% threshold for nanotopography [nm] 25 3,9 2,8 16 3,8 1,9 5,9 3,6 1,3 1,6 3,5 0,9 1,1 3,6 0,7

[0052] Fig. Figure 4 is a graph showing the relationship between the thickness variation distribution (standard deviation) of the polishing pad shown in Table 2 and the 2mm square nanotopography value.

[0053] As in Fig. As illustrated in Figure 4, the 99.5% threshold for nanotopography shows a weak correlation with the thickness variation (standard deviation) of the polishing pad, and the thickness variation (standard deviation) of the polishing pad has a small influence on the 99.5% threshold. On the other hand, the 50% threshold shows a strong correlation with the thickness variation (standard deviation) of the polishing pad, and the 50% threshold for nanotopography is higher the greater the thickness variation (standard deviation) of the polishing pad. Accordingly, the 2 mm square nanotopography can be reduced by reducing the thickness variation (standard deviation) of the polishing pad. Furthermore, it can be seen from the graph from Fig.4. It can be seen that reducing the 50% threshold for 2mm square nanotopography to 1.0 nm or less requires reducing the thickness variation (standard deviation) of the polishing pad to 2.0 µm or less.

[0054] Then, the influence of the relative speed of the wafer to the polishing pad on the nanotopography was assessed.

[0055] First, the nanotopography (50% threshold (50%Th)) within the 2 mm square area of ​​the wafer was measured when the polishing allowance of a silicon wafer with a diameter of 300 mm and a thickness of 780 µm was sequentially increased from 0.1 µm in increments of 0.1 µm to 0.5 µm. The thickness variation (standard deviation) of the polishing pad used in polishing the silicon wafer was 1.6 µm. Consequently, it can be seen that, as in Fig.Figure 5 illustrates that the 2mm square nanotopography characteristics deteriorate the greater the polishing addition of the wafer.

[0056] The nanotopography (50% threshold (50%Th)) within the 2 mm square spot was then assessed when the relative velocity of the wafer was changed from 0.2 m / s to 1.1 m / s. The results are presented in Fig. 6 shown.

[0057] It can be made of Fig. 6. It can be seen that the nanotopography is smaller the higher the wafer polishing speed, and conversely, the nanotopography is larger the lower the wafer polishing speed. It can also be seen that the nanotopography is larger the greater the thickness variation (standard deviation) of the polishing pad.

[0058] The ROA (Reference Area of ​​Accuracy) was then assessed at the wafer's outer periphery when the wafer's relative velocity was changed from 0.2 m / s to 1.1 m / s. The ROA is a flatness index at the wafer's outer periphery and is defined as the amount of drop at a position 149 mm (1 mm inward from the outermost wafer periphery) from the wafer center when the least-squares plane of a rectangular area, obtained by peripherally dividing the section at 5° intervals from 120 mm to 148 mm from the wafer center, is set as a reference plane. The results are presented in Fig. 7 shown.

[0059] It can be made of Fig. 7. It can be seen that the ROA at the wafer's outer periphery deteriorates the higher the wafer polishing speed. It can also be seen that the thickness variation (standard deviation) of the polishing pad has no influence on the ROA at the wafer's outer periphery.

[0060] The results above show that reducing the 2 mm² nanotopography to 1.0 nm or less requires setting the thickness variation (standard deviation) of the polishing pad to 1.6 µm or less, and that when the thickness variation (standard deviation) of the polishing pad is 1.6 µm, it is necessary to set the relative velocity of the wafer to 0.5 m / s or more. The results further show that when the thickness variation (standard deviation) of the polishing pad is 1.6 µm or less, the 2 mm² nanotopography can be reduced to 1.0 nm or less over a wide range (0.2 m / s to 1.1 m / s) of relative velocity of the wafer. On the other hand, it can be seen that reducing the ROA at the wafer outer periphery to 20 nm or less requires adjusting the relative velocity of the wafer to less than 0.4 m / s.

[0061] Accordingly, to reduce the 2mm square nanotopography to 1.0 nm or less and to reduce the ROA at the wafer outer peripheral part to 20 nm or less, it is advantageous to set the thickness variation (standard deviation) of the polishing pad to 1.6 µm or less and to set the relative velocity of the wafer to 0.3 m / s or less. [Description of the reference numbers] 10 silicon wafers 100 Single-sided polishing device 120 polishing head 124 retaining ring 124A Lower end surface of the retaining ring 140 Rotary carrier plate 150 polishing pads 160 slurry dispensing devices 170 Slurry

Claims

Silicon wafer (10) wherein the 50% threshold of a nanotopography within a 2mm square spot having a size with a length in at least one direction of 2 mm and an area of ​​4 mm2 is 1.0 nm or less, and wherein the 50% threshold of the nanotopography is less than or equal to 0.4 times the 99.5% threshold of the nanotopography. Silicon wafer according to claim 1, wherein the ROA at a position 1 mm inward from an outermost periphery of the wafer is 20 nm or less.

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