SiC semiconductor component

Abstract

SiC semiconductor device, comprising: a SiC chip (2) with a main surface (3) having a first surface (6), a second surface (7) recessed in a thickness direction to a first depth (D1) outside the first surface (6), and a connecting surface (8A-8D) connecting the first surface (6) and the second surface (7), and in which a mesa (9) is defined by the first surface (6), the second surface (7) and the connecting surface (8A-8D); a transistor structure (30) formed on an inner section of the first surface (6), wherein the transistor structure (30) has a gate trench structure (31) having a second depth (D2) that is less than the first depth (D1), and a source trench structure (41) having a third depth (D3) that is greater than the second depth (D2), and which is adjacent to the gate trench structure (31) in a direction (Y); a dummy structure (60, 60A) formed at a circumferential boundary section of the first surface (6), wherein the dummy structure (60, 60A) has a plurality of dummy source trench structures (61), each of which has the third depth (D3) and which adjoin each other in one direction (Y); and an insulating film (110) covering the gate trench structure (31) and the source trench structure (41) over the main surface (3), wherein the insulating film (110) is in direct contact with both the first gate trench structure (31) and the source trench structure (41).

Description

[0001] The present invention relates to a SiC semiconductor device. TECHNICAL AREA

[0002] Patent literature 1 discloses a semiconductor device comprising a semiconductor substrate, a gate trench structure formed on the semiconductor substrate and a source trench structure formed such that it adjoins the gate trench structure. Background List of citations Patent literature Patent literature 1: US 2017 / 0 040 423 A1 Patent literature 2: DE 20 2019 005 382 U1 Patent literature 3: WO 2020 / 080 295 A1 Patent literature 4: US 2010 / 0 140 689 A1 Summary of the invention; Technical task

[0003] A preferred embodiment of the present invention is a SiC semiconductor device that can improve reliability. Solution to the task

[0004] According to one embodiment of the present invention, a SiC semiconductor device according to claim 1 is provided.

[0005] According to one embodiment of the present invention, a SiC semiconductor device is provided according to claim 21.

[0006] The aforementioned or further objects, features and effects of the present invention are clarified by the following description of preferred embodiments with reference to the accompanying drawings. Brief description of the drawings [ Fig. 1] Fig. Figure 1 is a top view of a SiC semiconductor device according to a first preferred embodiment of the present invention. [ Fig. 2] Fig. 2 is a cross-sectional view showing a cross-section along the in Fig. Line II-II shown in Figure 1 shows a structure within a SiC chip that is omitted. [ Fig. 3] Fig. 3 is a top view showing a first main surface of the in Fig. Figure 1 shows the SiC chips and in which the structure within the SiC chip is omitted. [ Fig. 4] Fig. 4 is a top view showing the Fig. Figure 3 shows the first main surface, which visually simplifies a structure built into the SiC chip. [ Fig. 5] Fig. 5 is an enlarged top view of a main section of the in Fig. 4 shown first main surface. [ Fig. 6] Fig. 6 is an enlarged top view of an end section of a Fig. 5 transistor area shown. [ Fig. 7] Fig. 7 is an enlarged top view of an inner part of the in Fig. 5 transistor area shown. [ Fig. 8] Fig. 8 is a cross-sectional view along the in Fig. 6 shown line VIII-VIII. [ Fig. 9] Fig. 9 is a cross-sectional view along the in Fig. 6 shown line IX-IX. [ Fig. 10] Fig. 10 is a cross-sectional view along the in Fig. Line XX shown in 6. [ Fig. 11] Fig. 11 is a cross-sectional view along the in Fig. Line XI-XI shown in 6. [ Fig. 12] Fig. 12 is a cross-sectional view along the in Fig. 7 shown line XII-XII. [ Fig. 13] Fig. 13 is an enlarged top view of a corner area of ​​a Fig. 5 first perimeter area shown. [ Fig. 14] Fig. 14 is a cross-sectional view along the in Fig. 13 shown line XIV-XIV. [ Fig. 15] Fig. 15 is a cross-sectional view along the in Fig. 13 shown line XV-XV. [ Fig. 16] Fig. 16 is an enlarged top view of an end section of the in Fig. 5 first perimeter area shown. [ Fig. 17] Fig. 17 is an enlarged top view of an internal section of the in Fig. 5 first perimeter area shown. [ Fig. 18] Fig. 18 is a cross-sectional view along the in Fig. 16 shown line XVIII-XVIII. [ Fig. 19] Fig. 19 is a cross-sectional view along the in Fig. 16 shown line XIX-XIX. [ Fig. 20] Fig. 20 is a cross-sectional view along the in Fig. Line XX-XX shown in 16. [ Fig. 21] Fig. 21 is a cross-sectional view along line XXI-XXI in Fig. 17. [ Fig. 22] Fig. 22 is a cross-sectional view along the in Fig. 1 shown line XXII-XXII. [ Fig. 23] Fig. 23 is a cross-sectional view along line XXIII-XXIII in Fig. 1. [ Fig. 24] Fig. 24 is a cross-sectional view along line XXIV-XXIV in Fig. 1. [ Fig. 25] Fig. 25 is a cross-sectional view along line XXV-XXV in Fig. 1. [ Fig. 26] Fig. 26 is a cross-sectional view along line XXVI-XXVI in Fig. 1. [ Fig. 27] Fig. Figure 27 is a top view describing the structure of a main surface electrode. [ Fig. 28] Fig. Figure 28 is a top view describing the structure of a second inorganic insulating layer. [ Fig. 29A] Fig. 29A is a cross-sectional view showing an example of a manufacturing process of the in Fig. 1 shows the SiC semiconductor device depicted. [ Fig. 29B] Fig. 29B is a cross-sectional view taken one step after the one from Fig. 29A is shown. [ Fig. 29C] Fig. 29C is a cross-sectional view taken one step after the one from Fig. 29B shows. [ Fig. 29D] Fig. 29D is a cross-sectional view, taken one step after the one from Fig. 29C is shown. [ Fig. 29E] Fig. 29E is a cross-sectional view taken one step after the one from Fig. 29D shows. [ Fig. 29F] Fig. 29F is a cross-sectional view, taken one step after the one from Fig. 29E is shown. [ Fig. 29G] Fig. 29G is a cross-sectional view, taken one step after the one from Fig. 29F shows. [ Fig. 29H] Fig. 29H is a cross-sectional view taken one step after the one from Fig. 29G is displayed. [ Fig. 29I] Fig. 29I is a cross-sectional view taken one step after the one from Fig. 29H is displayed. [ Fig. 29J] Fig. 29J is a cross-sectional view taken one step after the one from Fig. 29I shows. [ Fig. 29K] Fig. 29K is a cross-sectional view, taken one step after the one from Fig. 29J shows. [ Fig. 29L] Fig. 29L is a cross-sectional view, taken one step after the one from Fig. 29K is displayed. [ Fig. 29M] Fig. 29M is a cross-sectional view, taken one step after the one from Fig. 29L is displayed. [ Fig. 29N] Fig. 29N is a cross-sectional view taken one step after the one from Fig. 29M is shown. [ Fig. 29O] Fig. 29O is a cross-sectional view taken one step after the one from Fig. 29N is shown. [ Fig. 29P] Fig. 29P is a cross-sectional view taken one step after the one from Fig. 29O is shown. [ Fig. 29Q] Fig. 29Q is a cross-sectional view taken one step after the one from Fig. 29P is displayed. [ Fig. 29R] Fig. 29R is a cross-sectional view taken one step after the one from Fig. 29Q is shown. [ Fig. 29S] Fig. 29S is a cross-sectional view taken one step after the one from Fig. 29R is shown. [ Fig. 29T] Fig. 29T is a cross-sectional view, taken one step after the one from Fig. 29S shows. [ Fig. 29U] Fig. 29U is a cross-sectional view taken one step after the one from Fig. 29T is displayed. [ Fig. 29V] Fig. 29V is a cross-sectional view, taken one step after the one from Fig. 29U is shown. [ Fig. 30] Fig. 30 corresponds to Fig. Figure 5 is a top view showing a SiC semiconductor device according to a first preferred reference embodiment. [ Fig. 31A] Fig. 31A is a cross-sectional view showing an example of a manufacturing process of the in Fig. 30 SiC semiconductor devices are shown. [ Fig. 31B] Fig. 31B is a cross-sectional view showing a step that is based on the Fig. 31A follows. [ Fig. 31C] Fig. 31C is a cross-sectional view taken one step after the one from Fig. 31B shows. [ Fig. 31D] Fig. 31D is a cross-sectional view, taken one step after the one from Fig. 31C is shown. [ Fig. 32] Fig. 32 corresponds Fig. Figure 6 is a top view showing a SiC semiconductor device according to a second preferred reference embodiment. [ Fig. 33] Fig. 33 is a cross-sectional view along the in Fig. 32 shown line XXXIII-XXXIII. [ Fig. 34] Fig. 34 corresponds Fig. 6 and is a top view showing a SiC semiconductor device according to a second preferred embodiment of the present invention. [ Fig. 35] Fig. 35 is a cross-sectional view along the in Fig. 34 shown line XXXV-XXXV. [ Fig. 36] Fig. 36 is a cross-sectional view along the in Fig. 34 shown line XXXVI-XXXVI. [ Fig. 37] Fig. 37 is a cross-sectional view along the in Fig. 34 shown line XXXVII-XXXVII. [ Fig. 38] Fig. 38 corresponds Fig. 16 and is a top view of the in Fig. 34 SiC semiconductor devices shown. [ Fig. 39] Fig. 39 is a cross-sectional view along the in Fig. 38 shown line XXXIX-XXXIX. [ Fig. 40] Fig. 40 is a cross-sectional view along the in Fig. 38 lines shown XL-XL. [ Fig. 41] Fig. 41 is a cross-sectional view along the in Fig. 38 shown line XLI-XLI. Description of the embodiments

[0007] Fig. Figure 1 is a top view of a SiC semiconductor device 1 according to a first preferred embodiment of the present invention. Fig. 2 is a cross-sectional view showing a cross-section along the in Fig. 1 shows line II-II and in which a structure within a SiC chip 2 is omitted. Fig. 3 is a top view showing a first main surface 3 of the in Fig. Figure 1 shows the SiC chip 2 and in which the structure inside the SiC chip 2 is omitted.

[0008] Referring to Fig. 1 to Fig. 3. The SiC semiconductor device 1 is an electronic component which, in this preferred embodiment, comprises the SiC chip 2 formed from a hexagonal SiC (silicon carbide) single crystal. In this embodiment, the SiC semiconductor device 1 is also a semiconductor switching device containing a SiC MISFET (metal-insulator-semiconductor field-effect transistor). The hexagonal SiC single crystal has a variety of polytypes, including a 2H (hexagonal) SiC single crystal, a 4H SiC single crystal, a 6H SiC single crystal, etc. In the present embodiment, an example is shown in which the SiC chip 2 is a 4H SiC single crystal, although other polytypes are not excluded.

[0009] The SiC chip 2 has the shape of a rectangular parallelepiped. The SiC chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side faces 5A to 5D that connect the first main surface 3 and the second main surface 4. The first main surface 3 is a component surface in which a functional component is formed. The second main surface 4 is a component-free surface in which no functional component is formed. Viewed from their normal directions Z (hereinafter referred to simply as the "top view"), the first main surface 3 and the second main surface 4 are each quadrilateral. The first main surface 3 and the second main surface 4 can each have a square or rectangular shape in the top view.

[0010] The first principal surface 3 and the second principal surface 4 are formed by c-planes of the SiC single crystal. The c-planes comprise a silicon plane ((0001) plane) of the SiC single crystal and a carbon plane ((000-1) plane) of the SiC single crystal. Preferably, the first principal surface 3 is formed by the silicon plane and the second principal surface 4 by the carbon plane. The first principal surface 3 and the second principal surface 4 can have an off angle, where these surfaces are inclined at a predetermined angle in a predetermined off direction with respect to the c-planes. Preferably, the off direction is a direction of the a-axis ([11-20] direction) of the SiC single crystal. The off angle can be greater than 0° and less than or equal to 10°. Preferably, the off angle is equal to or less than 5°. Preferably, the off-angle is at least 2° and at most 4.5°.

[0011] The second main surface 4 can be a rough surface exhibiting either grinding marks or annealing marks (specifically: laser irradiation marks), or both. The annealing marks can be amorphous SiC and / or SiC silicided (alloyed) with a metal (specifically: Si). Preferably, the second main surface 4 is an ohmic surface exhibiting at least annealing marks.

[0012] The first face 5A and the second face 5B extend in a first direction X along the first principal surface 3 and point in a second direction Y that intersects the first direction X (specifically, that intersects the first direction X perpendicularly). The third face 5C and the fourth face 5D extend in the second direction Y and face each other in the first direction X. In this embodiment, the first direction X is a direction of the m-axis ([1-100] direction) of the SiC single crystal, and the second direction Y is a direction of the a-axis of the SiC single crystal. In other words, the first face 5A and the second face 5B are formed by an a-plane of the SiC single crystal, and the third face 5C and the fourth face 5D are formed by an m-plane of the SiC single crystal.The first to fourth side surfaces 5A to 5D each define a circumferential boundary of the first main surface 3 and a circumferential boundary of the second main surface 4.

[0013] The first four face surfaces, 5A to 5D, can be ground surfaces, each exhibiting grinding marks from cutting with a dicing edge, or cleavage surfaces, each containing a modified layer formed by laser irradiation. Specifically, the modified layer is a region where a portion of the crystal structure of the SiC chip 2 has been altered to exhibit a different property. In other words, the modified layer is a region where the density, refractive index, mechanical strength (crystal strength), or other physical properties have been altered to differ from those of the SiC chip 2. The modified layer can include at least one of the following: an amorphous layer, a molten / post-cured layer, a defect layer, a dielectric breakdown layer, or a layer with a modified refractive index.

[0014] If the first to fourth face surfaces 5A to 5D are cleavage surfaces, then the first face surface 5A and the second face surface 5B can form an inclined surface with an inclination angle due to the off angle. If the normal direction Z is set to 0°, the inclination angle due to the off angle is an angle with respect to this normal direction Z. The first face surface 5A and the second face surface 5B can form an inclined surface extending along the c-axis direction (

[0001] direction) of the SiC single crystal with respect to the normal direction Z.

[0015] The angle of inclination due to the off angle is essentially equal to the off angle. The angle of inclination resulting from the off angle can be greater than 0° and less than or equal to 10° (preferably not less than 2° and not greater than 4.5°). The third face 5C and the fourth face 5D extend in the off direction (direction of the a-axis) and therefore have no angle of inclination due to the off angle. The third face 5C and the fourth face 5D extend planarly in the second direction Y (direction of the a-axis) and in the normal direction Z. More precisely, the third face 5C and the fourth face 5D are configured such that they are essentially perpendicular to the first principal surface 3 and the second principal surface 4.

[0016] The first main surface 3 has an active surface 6, an outer surface 7, and first to fourth connecting surfaces 8A to 8D. The active surface 6, the outer surface 7, and the first to fourth connecting surfaces 8A to 8D form an active mesa 9 in the first main surface 3. The active surface 6 is also referred to as the first surface, the outer surface 7 as the second surface, and the active mesa 9 is also referred to as the mesa.

[0017] The active surface 6 is a surface in which a MISFET with an insulated gate trench is formed. The active surface 6 is located at an inward distance from the circumferential edge (first to fourth side faces 5A to 5D) of the first main surface 3. The active surface 6 has a flat surface extending in the first direction X and in the second direction Y. The active surface 6 has a quadrilateral shape with four sides that, in plan view, are parallel to the circumferential edge of the first main surface 3. In this embodiment, a corner section of the active surface 6 is chamfered (specifically, R-chamfered) towards the side of the outer surface 7. Therefore, in this embodiment, the active surface 6 is quadrilateral, with the four corners being curved (rounded) in plan view.

[0018] The outer surface 7 is located outside the active surface 6 and is recessed with a first depth D1 in the thickness direction of the SiC chip 2 (on the side of the second main surface 4) from the active surface 6. In other words, the outer surface 7 is located on the side of the second main surface 4 with respect to the active surface 6. The outer surface 7 is ribbon-shaped and extends along the active surface 6 in plan view. More precisely, the outer surface 7 is annular (specifically: quadrilateral) and surrounds the active surface 6 in plan view.

[0019] The outer surface 7 has a flat surface extending in the first direction X and the second direction Y, and is essentially parallel to the active surface 6. The outer surface 7 is connected to the first to fourth side surfaces 5A to 5D. The first depth D1 of the outer surface 7 is preferably not less than 0.5 µm and not more than 10 µm. Preferably, the first depth D1 is 5 µm or less. Particularly preferably, the first depth D1 is 2.5 µm or less.

[0020] The first to fourth connecting surfaces 8A to 8D extend in the normal direction Z and connect the active surface 6 and the outer surface 7. The first connecting surface 8A is located on the side of the first side surface 5A, the second connecting surface 8B is located on the side of the second side surface 5B, the third connecting surface 8C is located on the side of the third side surface 5C, and the fourth connecting surface 8D is located on the side of the fourth side surface 5D. The first connecting surface 8A and the second connecting surface 8B extend in the first direction X and face each other in the second direction Y. The third connecting surface 8C and the fourth connecting surface 8D extend in the second direction Y and face each other in the first direction X.The first compound surface 8A and the second compound surface 8B are facing the a-planes of the SiC single crystal, and the third compound surface 8C and the fourth compound surface 8D are facing the m-planes of the SiC single crystal.

[0021] The first to fourth interconnect surfaces 8A to 8D can be configured substantially perpendicular to the active surface 6 and the outer surface 7. In this case, a quadrilateral-prismatic active mesa 9 is formed in the first main surface 3. The first to fourth interconnect surfaces 8A to 8D can be inclined obliquely downwards from the active surface 6 towards the outer surface 7. In this case, a quadrilateral-pyramidal active mesa 9 is formed in the first main surface 3. The inclination angle of each of the first to fourth interconnect surfaces 8A to 8D is preferably not less than 90° and not more than 135°. The inclination angle of each of the first to fourth interconnect surfaces 8A to 8D is an angle formed between each of the first to fourth interconnect surfaces 8A to 8D and the active surface 6 of the SiC chip 2.Preferably, the inclination angle of each of the first to fourth connecting surfaces 8A to 8D is 95° or less.

[0022] The SiC semiconductor device 1 has a first n-type semiconductor region 10 (first conductivity type) formed on a surface layer section of the second main surface 4 of the SiC chip 2. The first semiconductor region 10 forms a drain of the MISFET. The first semiconductor region 10 can be referred to as the drain region. The first semiconductor region 10 has an n-type impurity concentration that is substantially uniform in the thickness direction. The n-type impurity concentration of the first semiconductor region 10 is preferably not less than 1 × 10⁻⁶. 18 cm -3 and no more than 1x10 21 cm -3 be.

[0023] The first semiconductor region 10 is formed on the surface layer section of the second main surface 4 at a distance from the outer surface 7 on the side of the second main surface 4. The first semiconductor region 10 is formed over the entire area of ​​the surface layer section of the second main surface 4 and is exposed to the second main surface 4 and to the first to fourth side surfaces 5A to 5D. In other words, the first semiconductor region 10 is the second main surface 4 and parts of the first to fourth side surfaces 5A to 5D.

[0024] The thickness of the first semiconductor region 10 is preferably not less than 5 µm and not more than 300 µm. Typically, the thickness of the first semiconductor region 10 is not less than 50 µm and not more than 250 µm. The thickness of the first semiconductor region 10 is adjusted by grinding the second main surface 4. In the present embodiment, the first semiconductor region 10 is an n-type semiconductor substrate (SiC substrate).

[0025] The SiC semiconductor device 1 has a second n-type semiconductor region 11 formed on a surface layer section of the first main surface 3 of the SiC chip 2. The second semiconductor region 11 is electrically connected to the first semiconductor region 10 and, together with the first semiconductor region 10, forms a drain of the MISFET. The second semiconductor region 11 is also referred to as a drift region. The second semiconductor region 11 has an n-type impurity concentration that is lower than the n-type impurity concentration of the first semiconductor region 10. The n-type impurity concentration of the second semiconductor region 11 is preferably not less than 1 × 10⁻⁶. 15 cm -3 and no more than 1x10 18 cm -3 be.

[0026] The second semiconductor region 11 is formed over the entire area of ​​the surface layer section of the first main surface 3 and is exposed from the first main surface 3 and from the first to fourth side surfaces 5A to 5D. More precisely, the second semiconductor region 11 is exposed from the active surface 6, the outer surface 7, and the first to fourth interconnect surfaces 8A to 8D. The second semiconductor region 11 comprises the first main surface 3 and portions of the first to fourth side surfaces 5A to 5D. The thickness of the second semiconductor region 11 is preferably not less than 5 µm and not more than 20 µm. The thickness of the second semiconductor region 11 is based on the thickness of the active surface 6. In the present embodiment, the second semiconductor region 11 is formed by an n-type epitaxial layer (SiC epitaxial layer).

[0027] Preferably, the second semiconductor region 11 has a concentration gradient in which the n-like impurity concentration increases (specifically: gradually increases) from the side of the first semiconductor region 10 towards the first main surface 3. In other words, the second semiconductor region 11 preferably has a first concentration region 12 (low concentration region) located on the side of the first semiconductor region 10 and having a comparatively low concentration, and a second concentration region 13 (high concentration region) located on the side of the first main surface 3 and having a higher concentration than the first concentration region 12.

[0028] The first concentration region 12 is located on the side of the first semiconductor region 10 with respect to the outer surface 7 and is exposed from the first to the fourth side surfaces 5A to 5D. The second concentration region 13 is located on the side of the first main surface 3 with respect to the first concentration region 12 and is exposed from the active surface 6, from the outer surface 7, and from the first to the fourth compound surfaces 8A to 8D. The n-like impurity concentration of the first concentration region 12 is preferably not less than 1 × 10 15 cm -3 and no more than 1x10 17 cm -3 The n-like impurity concentration of the second concentration range 13 may preferably be no less than 1×10 16 cm -3 and no more than 1x10 18 cm -3 be.

[0029] In the SiC chip 2, the SiC semiconductor device 1 has a third n-type semiconductor region 14 (concentration transition region) located between the first semiconductor region 10 and the second semiconductor region 11. The third semiconductor region 14 is electrically connected to the first semiconductor region 10 and the second semiconductor region 11 and, together with the first and second semiconductor regions 10 and 11, forms a drain of the MISFET. The third semiconductor region 14 can be described as a buffer region. The third semiconductor region 14 has a concentration gradient in which the n-type impurity concentration decreases from the n-type impurity concentration of the first semiconductor region 10 towards the n-type impurity concentration of the second semiconductor region 11 (specifically: it decreases gradually).

[0030] The third semiconductor region 14 is located in the entire area between the first semiconductor region 10 and the second semiconductor region 11 and is exposed from the first to the fourth face 5A to 5D. In other words, the third semiconductor region 14 comprises parts of the first to fourth face 5A to 5D. The thickness of the third semiconductor region 14 is preferably not less than 1 µm and not more than 10 µm. In the present embodiment, the third semiconductor region 14 is formed by an n-type epitaxial layer (SiC epitaxial layer).

[0031] Fig. 4 is a top view showing the Fig. Figure 3 shows the first main surface 3 and in which a structure built into the SiC chip 2 is visually simplified. Fig. 5 is an enlarged top view of a main section of the in Fig. 4 shown first main surface 3.

[0032] As in Fig. 4 and Fig. As shown in Figure 5, the SiC semiconductor device 1 contains a transistor region 20 embedded in the active area 6. The transistor region 20 can be referred to as the active area. In the present embodiment, only one transistor region 20 is embedded in the active area 6. In other words, in the present embodiment, the SiC semiconductor device 1 is a discrete device with the single transistor region 20. In the present embodiment, the transistor region 20 is located in a central section of the active area 6 at an inward distance from the first interconnection surface 8A and the second interconnection surface 8B. The transistor region 20 has a quadrilateral shape with four sides that run parallel to the first to fourth interconnection surfaces 8A to 8D.

[0033] In the active area 6, the SiC semiconductor device 1 has a plurality of circumferential regions 21 and 22, each of which lies in a region outside the transistor region 20. More precisely, the circumferential regions 21 and 22 have a first circumferential region 21 and a second circumferential region 22. The first circumferential region 21 is ribbon-shaped and extends in the first direction X between the third interconnection surface 8C and the fourth interconnection surface 8D in a region between the first interconnection surface 8A and the transistor region 20. The first circumferential region 21 faces the transistor region 20 in the second direction Y. The second circumferential region 22 is ribbon-shaped and extends in the first direction X between the third interconnection surface 8C and the fourth interconnection surface 8D in a region between the second interconnection surface 8B and the transistor region 20.The second circumferential region 22 faces the first circumferential region 21, with the transistor region 20 lying between the second circumferential region 22 and the first circumferential region 21 in the second direction Y.

[0034] Fig. 6 is an enlarged view of an end section of the in Fig. 5 of the transistor area shown 20. Fig. 7 is an enlarged top view of an inner part of the in Fig. 5 of the transistor area shown 20. Fig. Figure 8 is a cross-sectional view along line VIII-VIII in Fig. 6 shown. Fig. Figure 9 is a cross-sectional view along line IX-IX in Fig. 6 shown. Fig. Figure 10 is a cross-sectional view along line XX in Fig. 6. Fig. Figure 11 is a cross-sectional view along line XI-XI in Fig. 6. Fig. 12 is a cross-sectional view along line XII-XII in Fig. 7 shown.

[0035] With reference to Fig. 6 to Fig. 12 The SiC semiconductor device 1 contains a p-like body region 23 (second conductivity type) formed on a surface layer section of the active area 6. The body region 23 forms part of the body diode of the MISFET. The p-like impurity concentration of the body region 23 is preferably not less than 1 × 10 16 cm -3 and no more than 1x10 1e cm -3More precisely, the body region 23 is formed on a surface layer section of the second semiconductor region 11 over the entire area of ​​the active area 6. Even more precisely, the body region 23 is formed on the surface layer section of the second concentration region 13 and faces the first semiconductor region 10 (third semiconductor region 14), with part of the first concentration region 12 lying between the body region 23 and the first semiconductor region 10.

[0036] In the active area 6, the SiC semiconductor device 1 contains an n-type source region 24, which is formed in a surface layer section of the body region 23. The source region 24 forms a source of the MISFET. The source region 24 has an n-type impurity concentration that exceeds the n-type impurity concentration of the second semiconductor region 11 (second concentration region 13). The n-type impurity concentration of the source region 24 is preferably not less than 1 × 10⁻⁶ 18 cm -3 and no more than 1x10 21 cm -3 be.

[0037] In the present embodiment, the source region 24 is formed in the surface layer section of the body region 23 over the entire area of ​​the active area 6. The source region 24 is formed at a distance from a lower part of the body region 23 in the direction of the side of the active area 6. The source region 24 forms a channel of the MISFET with the second semiconductor region 11 (second concentration region 13) in the body region 23. The source region 24 does not necessarily have to be formed over the entire area of ​​the active area 6, and within the active area 6 the source region 24 can also be formed only in a region (e.g., in Tran20) in which a channel is to be formed.

[0038] The SiC semiconductor device 1 has a transistor structure 30 formed on the active area 6 in the transistor region 20 (in an inner section of the active area 6). The transistor structure 30 has several gate-trench structures 31 formed on the active area 6. The gate-trench structures 31 form a gate of the MISFET. A gate potential is applied to the gate-trench structure 31. The gate-trench structures 31 control the switching on and off of the channel in the body region 23.

[0039] The gate-trench structures 31 are formed on the inner section of the active surface 6 at a distance from the first to fourth connection surfaces 8A to 8D in the plan view. The gate-trench structures 31 are each formed in a band-like (rectangular) shape, extending in the first direction X in the plan view, and are formed with gaps between them in the second direction Y. The gate-trench structures 31 are formed in a strip-like shape and extend in the first direction X in the plan view. Preferably, the gate-trench structures 31 intersect a line in the first direction X that runs through the central section of the active surface 6 in the second direction Y in the plan view.

[0040] Each of the gate-trench structures 31 has a first width W1. The first width W1 is a width in a direction perpendicular to a direction in which each of the gate-trench structures 31 extends. The first width W1 is preferably not less than 0.1 µm and not more than 3 µm. Preferably, the first width W1 is not less than 0.5 µm and not greater than 1.5 µm.

[0041] The gate-trench structures 31 are arranged in the second direction Y with first distances P1 to each other. The first distance P1 is the distance between two trench-gate structures 31 that are adjacent in the second direction Y. Preferably, the first distance P1 is greater than the first width W1 (W1 < P1). The first distance P1 is preferably not less than 0.4 µm and not greater than 5 µm. Preferably, the first distance P1 is not less than 0.8 µm and not more than 3 µm.

[0042] Each of the gate-trench structures 31 has a second depth D2. The second depth D2 is less than the first depth D1 of the outer surface 7 (D2 < D1). The second depth D2 is preferably not less than 0.1 µm and not more than 3 µm. Preferably, the second depth D2 is not less than 0.5 µm and not more than 2 µm. Preferably, the aspect ratio D2 / W1 of each gate-trench structure 31 is not less than 1 and not more than 5. The aspect ratio D2 / W1 is a ratio between the second depth D2 and the first width W1. Particularly preferably, the aspect ratio D2 / W1 is 1.5 or more.

[0043] Each of the gate-trench structures 31 has a side wall and a bottom wall. A portion of the gate-trench structures 31 forming a long side is formed by the a-plane of the SiC single crystal. A portion forming a short side of the side wall of each gate-trench structure 31 is formed by the m-plane of the SiC single crystal. The bottom wall of each gate-trench structure 31 is formed by the c-plane of the SiC single crystal.

[0044] Each of the gate-trough structures 31 can be configured vertically with a substantially uniform opening width. Each of the gate-trough structures 31 can have a conical (tapering) shape, the opening width of which tapers (becomes narrower) towards the bottom wall. Preferably, the bottom wall of each gate-trough structure 31 is curved in the direction of the second surface 4. Naturally, the bottom wall of each gate-trough structure 31 can have a flat surface parallel to the active surface 6.

[0045] Each of the gate trench structures 31 is formed on the active area 6 such that it traverses the body region 23 and the source region 24 and reaches the second semiconductor region 11. More precisely, each of the gate trench structures 31 is formed at a distance from the bottom section of the second semiconductor region 11 in the direction of the side of the active area 6 and faces the first semiconductor region 10 (third semiconductor region 14), with a portion of the second semiconductor region 11 lying between the first semiconductor region 10 and each of the gate trench structures 31. In the present embodiment, each of the gate trench structures 31 is formed in the second concentration region 13 and faces the first concentration region 12, with a portion of the second concentration region 13 lying between the first concentration region 12 and each of the gate trench structures 31.The side wall of each of the gate-trough structures 31 is in contact with the second semiconductor region 11, the body region 23 and the source region 24. The bottom wall of each gate-trough structure 31 is in contact with the second semiconductor region 11.

[0046] Each of the gate-trough structures 31 comprises a gate-trough 32, a gate-insulating layer 33, and a gate-electrode 34. The individual gate-trough structure 31 is described below. The gate-trough 32 forms the side wall and the bottom wall of the gate-trough structure 31. The side wall and the bottom wall form a surface (inner wall and outer wall) of the gate-trough 32.

[0047] An opening edge section of the gate trench 32 is inclined obliquely downwards from the active surface 6 towards the gate trench 32. The opening edge section is a connecting section between the active surface 6 and the side wall of the gate trench 32. In the present embodiment, the opening edge section is formed in a curved shape, recessed towards the SiC chip 2. The opening edge section can be bent towards the inside of the gate trench 32.

[0048] The gate insulating film 33 is formed as a film on the inner wall of the gate groove 32 and defines a recessed space in the gate groove 32. The gate insulating film 33 covers the second semiconductor region 11, the body region 23, and the source region 24 on the inner wall of the gate groove 32. The gate insulating film 33 comprises at least one silicon oxide film, one silicon nitride film, or one silicon oxynitride film. In the present embodiment, the gate insulating film 33 has a single-layer structure, which is a silicon oxide film.

[0049] The gate insulating film 33 has a first section 33a, a second section 33b, and a third section 33c. The first section 33a covers the side wall of the gate trench 32. The second section 33b covers the bottom wall of the gate trench 32. The third section 33c covers the opening edge section. In the present embodiment, the third section 33c curves in a bent shape towards the inside of the gate trench 32 in the opening edge region.

[0050] The thickness of the first section 33a is preferably not less than 10 nm and not more than 100 nm. The second section 33b may have a thickness that exceeds the thickness of the first section 33a. The thickness of the second section 33b is preferably not less than 50 nm and not more than 200 nm. The third section 33c has a thickness that is greater than the thickness of the first section 33a. The thickness of the third section 33c is preferably not less than 50 nm and not more than 200 nm. Of course, a gate insulating layer 33 with a uniform thickness can also be formed.

[0051] The gate electrode 34 is embedded in the gate groove 32, with the gate insulating layer 33 located between the gate electrode 34 and the gate groove 32. The gate electrode 34 faces the second semiconductor region 11, the body region 23, and the source region 24, with the gate insulating layer 33 located between these regions and the gate electrode 34. The gate electrode 34 has an electrode surface that is exposed by the gate groove 32. The electrode surface of the gate electrode 34 has a curved shape that is recessed towards the bottom wall of the gate groove 32 and is tapered by the third section 33c of the gate insulating layer 33.

[0052] The gate potential is applied to the gate electrode 34. The gate electrode 34 controls the switching on and off of the channel in the body region 23 via the gate insulating film 33. Preferably, the gate electrode 34 is made of conductive polysilicon. The gate electrode 34 can contain n-type polysilicon doped with an n-type impurity and / or p-type polysilicon doped with a p-type impurity.

[0053] The transistor structure 30 has a plurality of first source-trenches 41 formed on the active surface 6. A source potential is supplied to the first source-trenches 41. This source potential can be a reference potential serving as an operating standard. The first source-trenches 41 are each formed on the active surface 6 such that they adjoin the gate-trenches 31 in the second direction Y. More precisely, the first source-trenches 41 are each formed in a region between two gate-trenches 31 that adjoin each other on the active surface 6, at a distance from each of the gate-trenches 31.

[0054] The first source trench structures 41 are each ribbon-shaped, extending in the first direction X in plan view, and are spaced apart in the second direction Y such that the individual gate trench structure 31 is arranged between them. The first source trench structures 41 are strip-shaped and extend in the first direction X in plan view.

[0055] Preferably, the first source trench structures 41 intersect the line passing through the central section of the active area 6 in the second direction Y in the plan view in the first direction X. In the present embodiment, each of the first trench trench structures 41 has a length greater than the length of each of the gate trench structures 31 with respect to the first direction X. The first trench trench structures 41 intersect an end section of each of the gate trench structures 31 from the side of the second direction Y in the first direction X in the plan view.

[0056] Each of the first source trench structures 41 has a region facing the second direction and is located in a region between the circumferential edge of the active surface 6 (third and fourth connection surfaces 8C and 8D) and the end section of each of the gate trench structures 31 in the top view. The first source trench structures 41 are exposed from at least one of the third and fourth connection surfaces 8C and 8D. In the present embodiment, the source trench structures 41 are exposed from both the third and fourth connection surfaces 8C and 8D. In other words, the first source trench structures 41 extend through the third and fourth connection surfaces 8C and 8D.

[0057] Each of the first source trench structures 41 has a second width W2. The second width W2 is a width in a direction (i.e., the second direction Y) that is perpendicular to a direction in which each of the first source trench structures 41 extends. The second width W2 is preferably not less than 0.1 µm and not more than 3 µm. Preferably, the second width W2 is not less than 0.5 µm and not greater than 1.5 µm. The second width W2 can be greater than the first width W1 (W1 < W2) or equal to or less than the first width W1 (W1 ≥ W2). In the present embodiment, the second width W2 is substantially equal to the first width W1 (W1 ≈ W2). Preferably, the second width W2 has a value that is within ±10% of the value of the first width W1.

[0058] Each of the first source trench structures 41 has a third depth D3. The third depth D3 is greater than the second depth D2 of the gate trench structure 31 (D2 < D3). Preferably, the third depth D3 is not less than 1.5 times and not more than 3 times the second depth D2. In the present embodiment, the third depth D3 is essentially equal to the first depth D1 of the outer surface 7 (D1 ≈ D3). In other words, each of the first source trench structures 41 is connected to the outer surface 7 and to the third and fourth connecting surfaces 8C and 8D. Preferably, the third depth D3 has a value within ±10% of the value of the first depth D1.

[0059] The third depth D3 is preferably not less than 0.5 µm and not more than 10 µm. Preferably, the third depth D3 is 5 µm or less. Particularly preferably, the third depth D3 is 2.5 µm or less. Preferably, the aspect ratio D3 / W2 of each of the first source trench structures 41 is not less than 1 and not more than 5. The aspect ratio D3 / W2 is a ratio between the third depth D3 and the second width W2. Particularly preferably, the aspect ratio D3 / W2 is 2 or more.

[0060] The first source trench structures 41 are arranged with second distances P2 between the gate trench structures 31 and the first source trench structures 41 in the second direction Y. The second distance P2 is a distance between the individual gate trench structure 31 and the individual first source trench structure 41 that adjoin each other in the second direction Y. Preferably, the second distance P2 is not less than 1 / 4 and not more than 1 / 2 of the first distance P1 (1 / 4 × P1 ≤ P2 ≤ 1 / 2 × P1).

[0061] The second spacing P2 is preferably not less than 0.1 µm and not more than 2.5 µm. Preferably, the second spacing P2 is not less than 0.5 µm and not more than 1.5 µm. Preferably, the second spacing P2 is smaller than the first width W1 of the gate trench structure 31 (P2 < W1). Preferably, the second spacing P2 is smaller than the second width W2 of the first trench structure 41 (P2 < W2). Of course, the second spacing P2 can be equal to or greater than the first width W1 and the second width W2.

[0062] Each of the first source trench structures 41 has a side wall and a bottom wall. The side wall of each of the first source trench structures 41 is formed by the a-plane of the SiC single crystal. The side wall of each of the first source trench structures 41 is in contact with the third and fourth connection surfaces 8C and 8D. The bottom wall of each of the first source trench structures 41 is formed by the c-plane of the SiC single crystal. The bottom wall of each of the first source trench structures 41 is in contact with the outer surface 7.

[0063] Each of the first source trench structures 41 can be configured vertically with a substantially uniform opening width. Each of the first source trench structures 41 can have a conical shape, the opening width of which tapers towards the bottom wall. Preferably, the bottom wall of each of the first source trench structures 41 is curved in the direction of the second surface 4. Naturally, the bottom wall of each of the first source trench structures 41 can have a flat surface parallel to the active surface 6.

[0064] Each of the first source trench structures 41 is formed on the active area 6 such that it traverses the body region 23 and the source region 24 and reaches the second semiconductor region 11. More precisely, each of the first source trench structures 41 is formed at a distance from the bottom section of the second semiconductor region 11 in the direction of the side of the active area 6 and faces the first semiconductor region 10 (third semiconductor region 14), with a portion of the second semiconductor region 11 lying between the first semiconductor region 10 and each of the first source trench structures 41. In the present embodiment, each of the first source trench structures 41 is formed in the second concentration region 13 and faces the first concentration region 12, with a portion of the second concentration region 13 lying between the first concentration region 12 and each of the first source trench structures 41.

[0065] The side wall of each of the first source trench structures 41 is in contact with the second semiconductor region 11, the body region 23, and the source region 24. The bottom wall of each of the first source trench structures 41 is in contact with the second semiconductor region 11. In the present embodiment, each of the first source trench structures 41 is deeper than each of the gate trench structures 31. In other words, the bottom wall of each of the first source trench structures 41 is located on the side of the bottom section of the second semiconductor region 11 (second concentration region 13) with respect to the bottom wall of each of the gate trench structures 31.

[0066] Each of the first source trench structures 41 has a source trench 42, a source insulating film 43, and a source electrode 44. The source trench 42, the source insulating film 43, and the source electrode 44 of each of the first source trench structures 41 can also be referred to as the "first source trench," "first source insulating film," and "first source electrode," respectively. The individual first source trench structure 41 is described below.

[0067] The source trench 42 forms the side wall and the bottom wall of the first source trench structure 41. The side wall and the bottom wall form a surface (inner wall and outer wall) of the source trench 42. An opening edge section of the source trench 42 is inclined obliquely downwards from the active surface 6 towards the source trench 42. The opening edge section is a connecting section between the active surface 6 and the side wall of the source trench 42. In the present embodiment, the opening edge section is formed in a curved shape, recessed towards the SiC chip 2. The opening edge section can be bent towards the inside of the source trench 42.

[0068] The source insulating film 43 is formed as a film on the inner wall of the source trench 42 and defines a recessed space within the source trench 42. The source insulating film 43 covers the second semiconductor region 11, the body region 23, and the source region 24 on the inner wall of the source trench 42. The source insulating film 43 comprises at least one silicon oxide film, one silicon nitride film, or one silicon oxynitride film. In the present embodiment, the source insulating film 43 has a single-layer structure, which is a silicon oxide film.

[0069] The source insulating film 43 has a first section 43a, a second section 43b, and a third section 43c. The first section 43a covers the side wall of the source trench 42. More precisely, the first section 43a covers the side wall of the source trench 42 and exposes the surface layer section of the first main surface 3 from the side wall of the source trench 42 at a distance from an opening end of the source trench 42 towards the side of the bottom wall in an arbitrary area (specifically, an area in which a contact area 70, described later, is formed) of the source trench 42.

[0070] The first section 43a covers the entire area of ​​the side wall of the source trench 42 on the side of the circumferential edge section of the active area 6. The second section 43b covers the bottom wall of the source trench 42. The third section 33c covers the opening edge section of the source trench 42 outside of an area in which the first section 43a is formed. In the present embodiment, the third section 43c curves in a bent shape towards the inside of the source trench 42 in the opening edge section.

[0071] The thickness of the first section 43a is preferably not less than 10 nm and not more than 100 nm. The second section 43b may have a thickness that exceeds the thickness of the first section 43a. The thickness of the second section 43b must be not less than 50 nm and not more than 200 nm. The third section 43c has a greater thickness than the first section 43a. The thickness of the third section 43c is preferably not less than 50 nm and not more than 200 nm. Naturally, a source insulating film 43 with a uniform thickness can be formed.

[0072] The source electrode 44 is embedded in the source trench 42, with the source insulating film 43 located between the source electrode 44 and the source trench 42. The source electrode 44 faces the second semiconductor region 11, the body region 23, and the source region 24, with the source insulating film 43 located between these regions and the source electrode 44. The source electrode 44 has an upper end section that is exposed by the source insulating film 43 in a section where the first section 43a of the source insulating film 43 has been formed. The upper section of the source electrode 44 defines a recess, deepened in the thickness direction of the SiC chip 2, between the source trench 42 and the source insulating film 43.

[0073] The source electrode 44 has an electrode surface that is exposed by the source trench 42. The electrode surface of the source electrode 44 is recessed in a curved shape towards the bottom wall of the source trench 42. The electrode surface of the source electrode 44 is tapered by the third section 43c of the insulating film at the side of the circumferential edge section of the active area 6.

[0074] The source potential is applied to the source electrode 44. Preferably, the source electrode 44 is made of conductive polysilicon. The source electrode 44 can comprise n-type polysilicon doped with an n-type impurity and / or p-type polysilicon doped with a p-type impurity. Preferably, the source electrode 44 comprises the same conductive material as the gate electrode 34.

[0075] The transistor structure 30 has a plurality of second source trench structures 51. The second source trench structure 51 is also referred to as the intermediate source trench structure. The source potential is supplied to the second source trench structures 51.

[0076] The second source trench structures 51 are each formed in a region between the perimeter of the active area 6 and the gate trench structures 31. More precisely, the second source trench structures 51 are each formed in a region between the third connection surface 8C and the gate trench structures 31, as well as in a region between the fourth connection surface 8D and the gate trench structures 31 in the active area 6. The second source trench structures 51 are each formed at a distance from the gate trench structure 31 and from two first source trench structures 41 in a region between these two first source trench structures 41, which are adjacent in the active area 6.

[0077] More precisely, the second source trench structures 51 are arranged with intervals between them in the second direction Y such that the single first gate trench structure 41 lies between them, and are each directly opposite the gate trench structures 31 in the first direction X. In other words, each of the second source trench structures 51 faces the gate trench structure 31 in the first direction X and the second source trench structure 51 in the second direction Y.

[0078] Furthermore, the second source trench structures 51 are each arranged in a region on the side of the third connection surface 8C and in a region on the side of the fourth connection surface 8D such that they enclose a corresponding gate trench structure 31 from both sides in the first direction X. The second source trench structures 51 are each ribbon-shaped and extend in the first direction X in the plan view. The second source trench structures 51 are strip-shaped and extend in the first direction X in the plan view.

[0079] The second source trench structures 51, positioned on the side of the third connection surface 8C, are free from the third connection surface 8C, and the second source trench structures 51, positioned on the side of the fourth connection surface 8D, are free from the fourth connection surface 8D. In other words, the second source trench structures 51 are shaped such that, according to their arrangement, they pass through one of the third and fourth connection surfaces 8C and 8D.

[0080] The second source trench structures 51 have a shorter length than the gate trench structures 31 with respect to the first direction X. Considering the single gate trench structure 31 and the two second source trench structures 51 arranged in the first direction X, the total length of the two second source trench structures 51 is less than the length of the single gate trench structure 31. The structure formed in this way ensures the channel length.

[0081] Each of the second source trench structures 51 has the second width W2 and the third depth D3 (aspect ratio D3 / W2) in the same way as the first source trench structure 41. The second source trench structures 51 are also arranged with the second spacings P2 in the second direction Y in the same way as the first source trench structure 41.

[0082] The second source trench structures 51 are arranged with third distances P3 between the gate trench structures 31 and the second source trench structures 51 in the first direction X. The third distance P3 is a distance between the individual gate trench structure 31 and the individual second source trench structures 51 that are adjacent to each other in the first direction X. Preferably, the third distance P3 is not less than 1 / 4 of the first distance P1 and not greater than the first distance P1 of the gate trench structures 31 (1 / 4 × P1 ≤ P3 < P1). Preferably, the third interval P3 is equal to or less than 1 / 2 of the first interval P1 (P3 ≤ 1 / 2 × P1).

[0083] The third distance P3 is preferably not less than 0.1 µm and not more than 2.5 µm. Preferably, the third distance P3 is not less than 0.5 µm and not more than 1.5 µm. Preferably, the third distance P3 is substantially equal to the second distance P2 between the gate trench structure 31 and the first source trench structure 41 (P2 ≈ P3). Preferably, the third interval P3 has a value that lies within ±10% of the value of the second interval P2.

[0084] Each of the second source trench structures 51 has a side wall and a bottom wall. The side wall forming the long side of each of the second source trench structures 51 is formed by the a-plane of the SiC single crystal. The side wall forming the short side of each of the second source trench structures 51 is formed by the m-plane of the SiC single crystal. The side wall of each of the second source trench structures 51 is in contact with one of the third and fourth connection surfaces 8C and 8D, respectively. The bottom wall of each of the second source trench structures 51 is formed by the c-plane of the SiC single crystal. The bottom wall of each of the second source trench structures 51 is in contact with the outer surface 7.

[0085] Each of the second source trench structures 51 can be configured vertically with a substantially uniform opening width. Each of the second source trench structures 51 can have a conical shape, the opening width of which tapers towards the bottom wall. Preferably, the bottom wall of each of the second source trench structures 51 is curved in the direction of the second main surface 4. Naturally, the bottom wall of each of the second source trench structures 51 can have a flat surface parallel to the active area 6.

[0086] Each of the second source trench structures 51 is formed on the active area 6 such that it traverses the body region 23 and the source region 24 and reaches the second semiconductor region 11. More precisely, each of the second source trench structures 51 is formed at a distance from the bottom section of the second semiconductor region 11 in the direction of the side of the active area 6 and faces the first semiconductor region 10 (third semiconductor region 14), with a portion of the second semiconductor region 11 lying between the first semiconductor region 10 and each of the second source trench structures 51. In the present embodiment, each of the second source trench structures 51 is formed in the second concentration region 13 and faces the first concentration region 12, with a portion of the second concentration region 13 lying between the first concentration region 12 and each of the second source trench structures 51.

[0087] The side wall of each of the second source trench structures 51 is in contact with the second semiconductor region 11, the body region 23, and the source region 24. The bottom wall of each of the second source trench structures 51 is in contact with the second semiconductor region 11. In the present embodiment, each of the second source trench structures 51 is deeper than each of the gate trench structures 31. In other words, the bottom wall of each of the second source trench structures 51 is located on the side of the bottom section of the second semiconductor region 11 (second concentration region 13) with respect to the bottom wall of each of the gate trench structures 31.

[0088] Each of the second source trench structures 51 features the source trench 42, the source insulating film 43, and the source electrode 44 in the same way as the first source trench structure 41. The source trench 42, the source insulating film 43, and the source electrode 44 of each of the second source trench structures 51 can also be referred to as the "second source trench", "second source insulating film", and "second source electrode", respectively.

[0089] In each of the second source trench structures 51, the third section 43c of the source insulating film 43 is formed over the entire area of ​​the opening edge section of the source trench 42. Furthermore, a description of the source trench 42, the source insulating film 43, and the source electrode 44 of the first source trench structure 41 is applicable to a description of the source trench 42, the source insulating film 43, and the source electrode 44 of the second source trench structure 51.

[0090] Fig. 13 is an enlarged top view of a corner section of the in Fig. 5 first perimeter area shown. Fig. 14 is a cross-sectional view along line XIV-XIV in Fig. 13. Fig. 15 is a cross-sectional view along line XV-XV in Fig. 13. Fig. 16 is an enlarged top view of an end section of the in Fig. 5 first perimeter area shown 21. Fig. 17 is an enlarged top view of an internal section of the in Fig. 5 first perimeter area shown 21. Fig. 18 is a cross-sectional view along the line XVIII-XVIII in Fig. 16.

[0091] Fig. 19 is a cross-sectional view along the XIX-XIX line in Fig. 16. Fig. 20 is a cross-sectional view along the line XX-XX in Fig. 16. Fig. 21 is a cross-sectional view along line XXI-XXI in Fig. 17. A structure on the side of the second circumferential region 22 (side of the second connecting surface 8B) is the same as a structure on the side of the first circumferential region 21 (side of the first connecting surface 8A), and therefore the structure on the side of the first (side of the first connecting surface 8A) is described below as an example.

[0092] Referring to Fig. 5 and Fig. In the SiC semiconductor device 1, 13 to 21, a dummy structure 60 is formed in the first circumferential region 21 (circumferential edge section of the active area 6) within the active area 6. The dummy structure 60 is a transistor region that does not operate as a MISFET and can also be referred to as a dummy transistor structure. In the present embodiment, the dummy structure 60 comprises a first dummy structure 60A and a second dummy structure 60B.

[0093] The first dummy structure 60A is formed in a region between the circumferential edge (first interconnection surface 8A) of the active area 6 and the transistor structure 30 in the first circumferential region 21. The first dummy structure 60A is formed on the circumferential edge section (region adjacent to the first interconnection surface 8A) of the active area 6 in the first circumferential region 21. The second dummy structure 60B is formed in a region between the transistor structure 30 and the first dummy structure 60A in the first circumferential region 21.

[0094] The first dummy structure 60A has a first dummy width WD1 with respect to the second direction Y. The second dummy structure 60B has a second dummy width WD2 with respect to the second direction Y. Preferably, the second dummy width WD2 is greater than the first dummy width WD1 (WD1 < WD2), although the second dummy width WD2 is arbitrary. Preferably, the second dummy width WD2 is equal to or less than five times as long as the first dummy width WD1 (WD2 < 5 × WD1). Particularly preferably, the second dummy width WD2 is equal to or less than three times as long as the first dummy width WD1 (WD2 < 3 × WD1).

[0095] It is sufficient if the dummy structure 60 comprises at least one of the first dummy structure 60A and one of the second dummy structure 60B, and it is not necessary that it simultaneously comprises both the first dummy structure 60A and the second dummy structure 60B. The dummy structure 60 may comprise a single dummy structure formed from either the first dummy structure 60A or the second dummy structure 60B. Preferably, the dummy structure 60 comprises at least the first dummy structure 60A. Preferably, the dummy structure 60 comprises both the first dummy structure 60A and the second dummy structure 60B.

[0096] The first dummy structure 60A has at least one first dummy source trench structure 61 formed on the active area 6. In the present embodiment, the first dummy structure 60A has a plurality of first dummy source trench structures 61. Preferably, the number of first dummy source trench structures 61 is not less than 10 and not more than 50, and the number of first dummy source trench structures 61 is arbitrary. The first dummy width WD1 is adjusted by the number of first dummy source trench structures 61. Particularly preferably, the number of first dummy source trench structures 61 is 25 or less. In this case, it is possible to prevent a reduction in the area of ​​the transistor region 20 by the first circumferential region 21.

[0097] The source potential is fed to the first dummy source trench structures 61. The first dummy source trench structures 61 are each formed in plan view as a band in the first direction X and arranged one behind the other at intervals in the second direction Y, so that they are adjacent to each other. The first dummy source trench structures 61 are formed in strip form and extend in plan view in the first direction X.

[0098] Preferably, the first dummy source trench structures 61 intersect the line that runs through the central part of the active area 6 in the second direction Y in the plan view, in the first direction X. In the present embodiment, each of the first dummy trench structures 61 has a length greater than the length of each of the gate trench structures 31 with respect to the first direction X. The first dummy source trench structures 61 intersect the end section of each of the gate trench structures 31 from the side of the second direction Y in the first direction X in the plan view.

[0099] Each of the first dummy source trench structures 61 has a section in a plan view between the perimeter of the active surface 6 (third and fourth connection surfaces 8C and 8D) and the end section of each of the gate trench structures 31 that faces the second direction Y. The first dummy source trench structures 61 face the gate trench structures 31, the first source trench structures 41, and the second source trench structures 51 in the second direction Y.

[0100] The first dummy source trench structures 61 are each exposed from at least one of the third and fourth connection surfaces 8C and 8D. In the present embodiment, the first dummy source trench structures 61 are each exposed from the third and fourth connection surfaces 8C and 8D. In other words, the first dummy source trench structures 61 traverse the third and fourth connection surfaces 8C and 8D in the same way as the first source trench structure 41.

[0101] Each of the first dummy source trench structures 61 has the second width W2 and the third depth D3 (aspect ratio D3 / W2) in the same way as the first source trench structure 41. In other words, each of the first dummy source trench structures 61 is connected to the outer surface 7 and the third and fourth connecting surfaces 8C and 8D.

[0102] The first dummy source trench structures 61 are arranged with fourth distances P4 between them in the second direction Y. The fourth distance P4 is a distance between two first dummy source trench structures 61 that are adjacent to each other in the second direction Y. Preferably, the fourth distance P4 is not less than 1 / 4 of the first distance P1 and not more than 1 / 2 of the first distance P1 (1 / 4 × P1 ≤ P4 ≤ 1 / 2 × P1).

[0103] The fourth distance P4 is preferably not less than 0.1 µm and not more than 2.5 µm. Preferably, the fourth distance P4 is not less than 0.5 µm and not more than 1.5 µm. Preferably, the fourth distance P4 is smaller than the first width W1 of the gate trench structure 31 (P4 < W1). Preferably, the fourth distance P4 is smaller than the second width W2 of the first dummy source trench structures 61 (P4 < W2). Of course, the fourth distance P4 can be equal to or greater than the first width W1 and the second width W2.

[0104] Preferably, the fourth distance P4 is substantially equal to the second distance P2 between the gate trench structure 31 and the first source trench structure 41 (P2 ≈ P4). Preferably, the fourth distance P4 has a value that lies within ±10% of the value of the second interval P2. Preferably, the fourth distance P4 is substantially equal to the third distance P3 between the gate trench structure 31 and the second source trench structure 51 (P3 ≈ P4). Preferably, the fourth distance P4 has a value that lies within ±10% of the value of the third interval P3.

[0105] Each of the first dummy-source trench structures 61 has a side wall and a bottom wall. The side wall of each of the first dummy-source trench structures 61 is formed by the a-plane of the SiC single crystal. The side wall of each of the first dummy-source trench structures 61 is in contact with the third and fourth connection surfaces 8C and 8D. The bottom wall of each of the first dummy-source trench structures 61 is formed by the c-plane of the SiC single crystal. The bottom wall of each of the first dummy-source trench structures 61 is in contact with the outer surface 7.

[0106] Each of the first dummy source trench structures 61 can be configured vertically with a substantially uniform opening width. Each of the first dummy structures of the source trench structures 61 can have a conical shape, the opening width of which tapers towards the bottom wall. Preferably, the bottom wall of each of the first dummy source trench structures 61 is curved in the direction of the second main surface 4. Naturally, the bottom wall of each of the first dummy source trench structures 61 can have a flat surface parallel to the active surface 6.

[0107] Each of the first dummy-source trench structures 61 is formed on the active surface 6 such that it traverses the body region 23 and the source region 24 and reaches the second semiconductor region 11. More precisely, each of the first dummy-source trench structures 61 is formed at a distance from the bottom section of the second semiconductor region 11 in the direction of the side of the active surface 6 and faces the first semiconductor region 10 (third semiconductor region 14), with a portion of the second semiconductor region 11 lying between the first semiconductor region 10 and each of the first dummy-source trench structures 61. In the present embodiment, each of the first dummy-source trench structures 61 is formed in the second concentration region 13 and faces the first concentration region 12, with a portion of the second concentration region 13 lying between the first concentration region 12 and each of the first dummy-source trench structures 61.

[0108] The side wall of each of the first dummy-source trench structures 61 is in contact with the second semiconductor region 11, the body region 23, and the source region 24. The bottom wall of each of the first dummy-source trench structures 61 is in contact with the second semiconductor region 11. In the present embodiment, each of the first dummy-source trench structures 61 is deeper than each of the gate trench structures 31. In other words, the bottom wall of each of the first dummy-source trench structures 61 is located on the side of the bottom section of the second semiconductor region 11 (second concentration region 13) with respect to the bottom wall of each of the gate trench structures 31.

[0109] Each of the first dummy source trench structures 61 has the source trench 42, the source insulating film 43, and the source electrode 44 in the same way as the first source trench structure 41. The source trench 42, the source insulating film 43, and the source electrode 44 of each of the first dummy source trench structures 61 can be referred to as the "first dummy source trench", "first dummy source insulating film", and "first dummy source electrode", respectively.

[0110] In each of the first dummy source trench structures 61, the third section 43c of the dummy source insulating film 43 is formed over the entire area of ​​the opening edge section of the source trench 42. Furthermore, a description of the source trench 42, the source insulating film 43, and the source electrode 44 of the first source trench structure 41 is applicable to a description of the source trench 42, the source insulating film 43, and the source electrode 44 of the first dummy source trench structure 61.

[0111] The second dummy structure 60B has at least one dummy gate trench structure 62 formed on the active surface 6, and at least one second dummy source trench structure 63 formed on the active surface 6 such that it adjoins the dummy gate trench structure 62. In the present embodiment, the second dummy structure 60B has a plurality of dummy gate trench structures 62 and a plurality of second dummy source trench structures 63.

[0112] The dummy gate trench structures 62 and the second dummy source trench structures 63 are arranged alternately with intervals between the dummy gate trench structures 62 and the second dummy source trench structures 63 in the second direction Y in a state in which two dummy gate trench structures 62 are defined as an arrangement start point and an arrangement end point, respectively. In the present embodiment, the second dummy structure 60B is defined by a trench structure group in which two dummy gate trench structures 62 are defined as an arrangement start point and an arrangement end point, respectively. The second dummy structure 60B is formed with the second distance P2 between the first source trench structure 41 of the transistor structure 30 and the second dummy structure 60B and with the fourth distance P4 (the second distance P2) between the first dummy source trench structure 61 of the first dummy structure 60A and the second dummy structure 60B.

[0113] Preferably, the number of dummy gate trench structures 62 is less than the number of gate trench structures 31, wherein the number of dummy gate trench structures 62 is freely selectable. The number of dummy gate trench structures 62 is preferably not less than 10 and not more than 50. Preferably, the number of dummy gate trench structures 62 is 25 or less. Preferably, the number of second dummy source trench structures 63 is less than the number of first source trench structures 41, wherein the number of second dummy source trench structures 63 is freely selectable. The number of second dummy source trench structures 63 is preferably not less than 10 and not more than 50. Preferably, the number of second dummy source trench structures 63 is 25 or less.

[0114] Preferably, the total number of dummy gate trench structures 62 and the second dummy source trench structures 63 is greater than the total number of first dummy source trench structures 61 of the first dummy structure 60A. Preferably, the total number of dummy gate trench structures 62 and the second dummy source trench structures 63 is 50 or less. In this case, it is possible to prevent a reduction in the area of ​​the transistor region 20 by the first circumferential region 21.

[0115] Unlike the gate trench structure 31, the dummy gate trench structures 62 do not form the gate of the MISFET. The source potential is supplied to the dummy gate trench structures 62. Therefore, channel formation is inhibited by the dummy gate trench structures 62. The dummy gate trench structures 62 are each ribbon-shaped, extending in the first direction X in plan view, and are arranged with intervals between them in the second direction Y. The dummy gate trench structures 62 are strip-shaped and extend in the first direction X in plan view.

[0116] Preferably, the dummy gate trench structures 62 intersect the line that runs through the central part of the active area 6 in the second direction Y in the plan view, in the first direction X. In the present embodiment, each of the dummy gate trench structures 62 has a length that is greater than the length of each of the gate trench structures 31 with respect to the first direction X. The dummy gate trench structures 62 intersect the end section of each of the gate trench structures 31 from the side of the second direction Y in the first direction X in the plan view.

[0117] The dummy gate trench structures 62 have a section in the top view between the perimeter of the active surface 6 (third and fourth connection surfaces 8C and 8D) and the end section of each of the gate trench structures 31, which faces the second direction Y. The dummy gate trench structures 62 face the gate trench structures 31, the first source trench structures 41, the second source trench structures 51, and the first dummy source trench structures 61 in the second direction Y.

[0118] The dummy gate trench structures 62 are exposed from at least one of the third and fourth connection surfaces 8C and 8D. In the present embodiment, the dummy gate trench structures 62 are exposed from both the third and fourth connection surfaces 8C and 8D. In other words, the dummy gate trench structures 62 traverse the third and fourth connection surfaces 8C and 8D in the same way as the first source trench structure 41.

[0119] Each of the dummy gate trench structures 62 has the first width W1 and the second depth D2 (aspect ratio D2 / W1) in the same way as gate trench structure 31. In other words, each of the first dummy source trench structures 61 is connected to the third and fourth connecting surfaces 8C and 8D at a distance from the outer surface 7 to the side of the active surface 6. The dummy gate trench structures 62 are also arranged with the first distances P1 in the second direction Y in the same way as gate trench structure 31.

[0120] Each of the dummy gate trench structures 62 has a side wall and a bottom wall. The side wall of each dummy gate trench structure 62 is formed by the a-plane of the SiC single crystal. The side wall of each dummy gate trench structure 62 is in contact with the third and fourth connection surfaces 8C and 8D. The bottom wall of each dummy gate trench structure 62 is formed by the c-plane of the SiC single crystal. The bottom wall of each dummy gate trench structure 62 is in contact with the third and fourth connection surfaces 8C and 8D.

[0121] Each of the dummy gate trench structures 62 can be configured in a vertical shape with a substantially uniform opening width. Each of the dummy gate trench structures 62 can have a conical shape, the opening width of which tapers towards the bottom wall. Preferably, the bottom wall of each dummy gate trench structure 62 is curved in the direction of the second surface 4. Naturally, the bottom wall of each dummy gate trench structure 62 can have a flat surface parallel to the active surface 6.

[0122] Each of the dummy gate trench structures 62 is formed at the active surface 6 such that it traverses the body region 23 and the source region 24 and reaches the second semiconductor region 11. More precisely, each of the dummy gate trench structures 62 is formed at a distance from the bottom section of the second semiconductor region 11 in the direction of the side of the active surface 6 and faces the first semiconductor region 10 (third semiconductor region 14), with a portion of the second semiconductor region 11 lying between the first semiconductor region 10 and each of the dummy gate trench structures 62.

[0123] In the present embodiment, each of the dummy gate trench structures 62 is formed in the second concentration region 13 and faces the first concentration region 12, with a portion of the second concentration region 13 lying between the first concentration region 12 and each of the dummy gate trench structures 62. The side wall of each of the dummy gate trench structures 62 is in contact with the second semiconductor region 11, the body region 23, and the source region 24. The bottom wall of each of the dummy gate trench structures 62 is in contact with the second semiconductor region 11.

[0124] Each of the dummy gate trench structures 62 has the gate trench 32, the gate insulating film 33, and the gate electrode 34 in the same way as the gate trench structure 31. The gate trench 32, the gate insulating film 33, and the gate electrode 34 of each of the dummy gate trench structures 62 can also be referred to as the "dummy gate trench," "dummy gate insulating film," and "dummy gate electrode," respectively. The description of the gate trench 32, the gate insulating film 33, and the gate electrode 34 of the gate trench structure 31 is applicable to the description of the gate trench 32, the gate insulating film 33, and the gate electrode 34 of the dummy gate trench structure 62.

[0125] The source potential is supplied to the second dummy source trench structures 63. The second dummy trench structures 63 are configured on the active surface 6 such that they each border the dummy gate trench structures 62 in the second direction Y. More precisely, the second dummy source trench structures 63 are each configured in a region between two adjacent dummy gate trench structures 62 in the active surface 6, at a distance from each of the dummy gate trench structures 62.

[0126] More precisely, the second dummy source trench structures 63 are each ribbon-shaped and extend in the first direction X in the plan view, and are arranged with intervals between them in the second direction Y such that the single dummy gate trench structure 62 is positioned between them. The second dummy source trench structures 63 are strip-shaped and extend in the first direction X in the plan view. Preferably, the second dummy source trench structures 63 intersect the line that runs through the central section of the active area 6 in the second direction Y in the plan view in the first direction X.

[0127] In the present embodiment, the second dummy source trench structures 63 have a length greater than the length of each of the gate trench structures 31 with respect to the first direction X. The second dummy source trench structures 63 intersect the end section of each of the gate trench structures 31 from the side of the second direction Y in the first direction X in the top view. The second dummy source trench structures 63 have a section facing the second direction Y in a region between the circumferential edge of the active surface 6 (third and fourth connection surfaces 8C and 8D) and an end section of each of the dummy gate trench structures 62 in the top view. The second dummy source trench structure 63 is oriented towards the gate trench structures 31, the first source trench structures 41, the second source trench structures 51, the first dummy source trench structures 61 and the dummy gate trench structures 62 in the second direction Y.

[0128] The second dummy source trench structures 63 are exposed from at least one of the third and fourth connection surfaces 8C and 8D. In the present embodiment, the second dummy source trench structures 63 are exposed from both the third and fourth connection surfaces 8C and 8D. In other words, the second dummy source trench structures 63 extend through the third and fourth connection surfaces 8C and 8D.

[0129] Each of the second dummy source trench structures 63 has the second width W2 and the third depth D3 (aspect ratio D3 / W2) in the same way as the first source trench structure 41. In other words, each of the second dummy source trench structures 63 is connected to the outer surface 7 and the third and fourth connecting surfaces 8C and 8D in the same way as the first source trench structure 41. The second dummy source trench structures 63 are also arranged with the second distances P2 in the second direction Y in the same way as the first source trench structure 41.

[0130] Each of the second dummy-source trench structures 63 has a side wall and a bottom wall. The side wall of each of the second dummy-source trench structures 63 is formed by the a-plane of the SiC single crystal. The side wall of each of the second dummy-source trench structures 63 is in contact with the third and fourth connection surfaces 8C and 8D. The bottom wall of each of the second dummy-source trench structures 63 is formed by the c-plane of the SiC single crystal. The bottom wall of each of the second dummy-source trench structures 63 is in contact with the outer face 7.

[0131] Each of the second dummy-source trench structures 63 can be configured vertically with a substantially uniform opening width. Each of the second dummy-source trench structures 63 can have a conical shape, the opening width of which tapers towards the bottom wall. Preferably, the bottom wall of each of the second dummy-source trench structures 63 is curved in the direction of the second surface 4. Naturally, the bottom wall of each of the second dummy-source trench structures 63 can have a flat surface parallel to the active surface 6.

[0132] Each of the second dummy-source trench structures 63 is formed on the active surface 6 such that it traverses the body region 23 and the source region 24 and reaches the second semiconductor region 11. More precisely, each of the second dummy-source trench structures 63 is formed at a distance from the bottom section of the second semiconductor region 11 in the direction of the side of the active surface 6 and faces the first semiconductor region 10 (third semiconductor region 14), with a portion of the second semiconductor region 11 lying between the first semiconductor region 10 and each of the second dummy-source trench structures 63. In the present embodiment, each of the second dummy-source trench structures 63 is formed in the second concentration region 13 and faces the first concentration region 12, with a portion of the second concentration region 13 lying between the first concentration region 12 and each of the second dummy-source trench structures 63.

[0133] The side wall of each of the second dummy-source trench structures 63 is in contact with the second semiconductor region 11, the body region 23, and the source region 24. The bottom wall of each of the second dummy-source trench structures 63 is in contact with the second semiconductor region 11. In the present embodiment, each of the second dummy-source trench structures 63 is deeper than each of the dummy-gate trench structures 62. In other words, the bottom wall of each of the second dummy-source trench structures 63 is located on the side of the bottom section of the second semiconductor region 11 (second concentration region 13) with respect to the bottom wall of each of the dummy-gate trench structures 62.

[0134] Each of the second dummy source trench structures 63 features the source trench 42, the source insulating film 43, and the source electrode 44. The source trench 42, the source insulating film 43, and the source electrode 44 of each of the second dummy source trench structures 63 can be referred to as the "second dummy source trench," "second dummy source insulating layer," and "second dummy source electrode," respectively.

[0135] In each of the second dummy source trench structures 63, the third section 43c of the source insulating film 43 is formed over the entire area of ​​the opening edge section of the source trench 42. Furthermore, a description of the source trench 42, the source insulating film 43, and the source electrode 44 of the first trench structure 41 is applicable to a description of the source trench 42, the source insulating film 43, and the source electrode 44 of the second dummy source trench structure 63.

[0136] Referring again to Fig. 6 to Fig. 12 The SiC semiconductor device 1 has a plurality of p-like contact areas 70 formed on the surface layer portion of the active area 6 of the transistor region 20. The contact areas 70 are each formed in a region along the first source trench structures 41 and not in a region along the second source trench structures 51. Each of the contact areas 70 has a p-like impurity that exceeds the p-like impurity concentration of the body region 23. The p-like impurity concentration of the contact area 70 is preferably not less than 1 × 10 18 cm -3 and no more than 1x10 21 cm -3 be.

[0137] The contact areas 70 are configured in plan view as a one-to-many correspondence to each of the first source trench structures 41. The contact areas 70 are arranged with intervals between them along each of the first source trench structures 41 in plan view and partially expose each of the first source trench structures 41. In the present embodiment, the contact areas 70 are each ribbon-shaped and extend in plan view in the first direction X. Preferably, each of the contact areas 70 has a length that is greater than the distance between two adjacent contact areas 70 in the first direction X.

[0138] In the present embodiment, the contact areas 70 covering the individual source trench structure 41 are aligned one-to-one with the contact areas 70 covering another, adjacent source trench structure 41 in the second direction Y. In other words, in this embodiment, the contact areas 70 are arranged as a whole with intervals between them in the first directions X and the second directions Y when viewed from above.

[0139] The contact areas 70 covering the single first source trench structure 41 can be offset by half a division (pitch) in the first direction X relative to the contact areas 70 covering another, adjacent first source trench structure 41. In other words, the contact areas 70 can be arranged in a staggered manner in plan view, offset by intervals in the first directions X and the second directions Y as a whole.

[0140] In the present embodiment, the contact areas 70 are formed at a distance from the circumferential edge of the active surface 6 (third and fourth connection surfaces 8C and 8D) in the direction of the inner section of the first source trench structure 41 in the top view. More precisely, the contact areas 70 on the inner section of the active surface 6 are formed such that the distance between an end section of the first trench structure 41 and an outermost contact area 70 is greater than the distance between two adjacent contact areas 70 in the first direction X.

[0141] In the present embodiment, the contact areas 70 are not formed in a section facing the second source trench structures 51 in the first source trench structures 41. Furthermore, the contact areas 70 are not formed in a section facing the end section of the gate trench structures 31 in the first source trench structures 41.

[0142] The contact areas 70 are exposed from the active area 6. The contact areas 70 are located at a distance from the gate trench structure 31 towards the side of the first source trench structure 41. Each of the contact areas 70 is located at a distance from the bottom section of the second semiconductor region 11 (second concentration region 13) towards the side of the active area 6 and faces the first semiconductor region 10 (third semiconductor region 14), with a portion of the second semiconductor region 11 lying between the first semiconductor region 10 and each of the contact areas 70. Each of the contact areas 70 covers the side wall and the bottom wall of each of the first source trench structures 41 in the second semiconductor region 11 (second concentration region 13). The contact areas 70 are electrically connected to the body region 23 in the side wall of each of the first source trench structures 41.

[0143] The SiC semiconductor device 1 has a plurality of p-like well regions 71 formed in the surface layer portion of the active area 6 of the transistor region 20. Each of the well regions 71 is formed in a region along each of the first source trench structures 41. Each of the well regions 71 has a p-like impurity concentration that exceeds the p-like impurity concentration of each of the contact regions 70. Preferably, the p-like impurity concentration of the well regions 71 exceeds the p-like impurity concentration of the body region 23. The p-like impurity concentration in the well regions 71 is preferably not less than 1 × 10⁻⁶ 16 cm -3 and no more than 1x10 18 cm -3 be.

[0144] The basin areas 71 are each formed in a one-to-one correspondence to the first source trench structures 41. Each basin area 71 is ribbon-shaped and extends in plan view along each of the first source trench structures 41 and is exposed by the third and fourth connecting surfaces 8C and 8D. Each basin area 71 is formed at a distance from the gate trench structure 31 to the side of the first gate trench structure 41 and exposes the gate trench structure 31.

[0145] Each of the basin areas 71 covers the side wall and the bottom wall of each of the first source trench structures 41. Each of the basin areas 71 covers each of the first source trench structures 41 with the contact areas 70 between each of the first source trench structures 41 and each of the basin areas 71. In other words, each of the basin areas 71 has a section that directly covers each of the first source trench structures 41 with the contact areas 70 between each of the first source trench structures 41 and this section of each of the basin areas 71, and a section that covers each of the first source trench structures 41 with the contact areas 70 between each of the first source trench structures 41 and this section of each of the basin areas 71. Each of the basin areas 71 is electrically connected to the body area 23 in the side wall of each of the first source trench structures 41.

[0146] Preferably, the thickness of a portion covering the bottom wall of each of the first source trench structures 41 in each of the basin areas 71 exceeds the thickness of a portion covering the side wall of each of the first source trench structures 41 in each of the basin areas 71. The thickness of the portion covering the side wall of each of the first source trench structures 41 in each of the basin areas 71 is the thickness in the normal direction to the side wall of each of the first source trench structures 41. The thickness of the portion covering the bottom wall of each of the first source trench structures 41 in each of the basin areas 71 is the thickness in the normal direction to the bottom wall of each of the first source trench structures 41.

[0147] In the present embodiment, each of the basin areas 71 is also formed in a region along each of the second source trench structures 51. Each of the basin areas 71 is formed as a one-to-one correspondence to each of the second source trench structures 51. Each of the basin areas 71 is ribbon-shaped and extends in plan view along each of the second source trench structures 51. Each of the basin areas 71 along each of the second source trench structures 51 on the side of the third connection surface 8C is exposed from the third connection surface 8C. Each of the basin areas 71 along each of the second source trench structures 51 on the side of the fourth connection surface 8D is exposed from the fourth connection surface 8D.

[0148] Each of the basin areas 71 is formed at a distance from the gate trench structure 31 to the side of the second gate trench structure 51 and exposes the gate trench structure 31. Each of the basin areas 71 covers the side wall and the bottom wall of each of the second source trench structures 51. Each of the basin areas 71 directly covers each of the second source trench structures 51. Each of the basin areas 71 is electrically connected to the body area 23 in the side wall of each of the second source trench structures 51.

[0149] Preferably, the thickness of a portion covering the bottom wall of each of the second source trench structures 51 of each of the basin areas 71 exceeds the thickness of a portion covering the side wall of each of the second source trench structures 51 of each of the basin areas 71. The thickness of the portion covering the side wall of each of the second source trench structures 51 of each basin area 71 is the thickness in the normal direction to the side wall of each of the second source trench structures 51. The thickness of the portion covering the bottom wall of each of the second source trench structures 51 of each of the basin areas 71 is the thickness in the normal direction to the bottom wall of each of the second source trench structures 51.

[0150] Each of the well areas 71 is formed at a distance from the bottom section of the second semiconductor area 11 (second concentration area 13) towards the side of the active area 6 and faces the first semiconductor area 10 (third semiconductor area 14), with a part of the second semiconductor area 11 lying between the first semiconductor area 10 and each of the well areas 71. In other words, each of the well areas 71 is electrically connected to the second semiconductor area 11 (second concentration area 13).

[0151] Preferably, the bottom section of the trough areas 71 is formed at a substantially uniform depth with respect to the bottom wall of the first source trench structures 41 and with respect to the bottom wall of the second source trench structures 51. The trough areas 71 form a pn junction to the second semiconductor region 11 (second concentration region 13) and extend a depletion layer in the width and depth direction of the SiC chip 2. The trough areas 71 bring the MISFET with an insulated gate into close proximity to the structure of a pn junction diode and relieve (dissipate) an electric field in the SiC chip 2.

[0152] Preferably, the well regions 71 are configured such that the depletion layer overlaps the bottom wall of the gate trench structure 31. The second concentration region 13, located between the well regions 71, reduces the JFET (Junction Field Effect Transistor) resistance. The second concentration region 13, located below the well regions 71, reduces the current propagation resistance. In the structure thus formed, the first concentration region 12 increases the dielectric strength of the SiC chip 2.

[0153] The SiC semiconductor device 1 has a plurality of p-like gate well regions 72, each formed in a section along the gate trench structures 31 in the surface layer section of the active area 6. The gate well regions 72 have a p-like impurity concentration that is lower than the p-like impurity concentration of the contact regions 70. Preferably, the p-like impurity concentration of each of the gate well regions 72 exceeds the p-like impurity concentration of the body region 23. The p-like impurity concentration in each of the gate well regions 72 is preferably not less than 1 × 10⁻⁶ 16 cm -3 and no more than 1x10 18 cm -3 Preferably, the p-like impurity concentration in each of the gate well areas 72 is substantially equal to the p-like impurity concentration in each of the well areas 71.

[0154] The gate basin areas 72 are each configured as a one-to-one correspondence with respect to the gate trench structures 31. Each of the gate basin areas 72 is ribbon-shaped and extends along the gate trench structures 31 in plan view. Each of the gate basin areas 72 is positioned at a distance from the first source trench structure 41 to the side of the gate trench structure 31. Each gate basin area 72 covers the side wall and the bottom wall of each gate trench structure 31. Each gate basin area 72 is electrically connected to the body area 23 in the side wall of each gate trench structure 31.

[0155] Each of the gate well regions 72 is formed at a distance from the bottom section of the second semiconductor region 11 (second concentration region 13) in the direction of the side of the first main surface 3 and faces the first semiconductor region 10 (third semiconductor region 14), with a portion of the second semiconductor region 11 lying between the first semiconductor region 10 and each of the gate well regions 72. In the present embodiment, each of the gate well regions 72 is formed in the second concentration region 13 and faces the first concentration region 12, with a portion of the second concentration region 13 lying between the first concentration region 12 and each of the gate well regions 72.

[0156] Preferably, the thickness of a portion covering the bottom wall of each of the gate-trough structures 31 of each gate-trough area 72 exceeds the thickness of a portion covering the side wall of each of the gate-trough structures 31 of each gate-trough area 72. The thickness of the portion covering the side wall of each of the gate-trough structures 31 of each gate-trough area 72 is the thickness normal to the side wall of each of the gate-trough structures 31. The thickness of the portion covering the bottom wall of each of the gate-trough structures 31 of each gate-trough area 72 is the thickness normal to the bottom wall of the gate-trough structure 31.

[0157] The bottom section of the gate well regions 72 is located on the bottom wall side of the gate trench structure 31 with respect to the bottom section of the well regions 71. Preferably, the bottom section of the gate well regions 72 is formed at a substantially uniform depth with respect to the bottom wall of the gate trench structures 31. The gate well regions 72 form a pn junction with the second semiconductor region 11 (second concentration region 13) and extend a depletion layer in the width and depth direction of the SiC chip 2. The gate well regions 72 bring the MISFET with an insulated gate into close proximity to the structure of a pn junction diode and relieve (dissolve) an electric field in the SiC chip 2.

[0158] Referring again to Fig. 13 to Fig. 21 The SiC semiconductor device 1 has a plurality of p-shaped dummy contact regions 73 formed on the surface layer section of the active area 6 of the first circumferential region 21. The dummy contact regions 73 are each formed in a region along the second dummy source trench structures 63 of the second dummy structure 60B and not in a region along the first dummy source trench structures 61 of the first dummy structure 60A.

[0159] The dummy contact areas 73 have a phosphorus-like impurity concentration that exceeds the phosphorus-like impurity concentration of the body area 23. The phosphorus-like impurity concentration of the contact areas 73 is preferably not less than 1 × 10 18 cm -3 and no more than 1x10 21 cm -3The concentration of phosphorus-like impurities in the contact areas 73 preferably exceeds the concentration of phosphorus-like impurities in the trough areas 71. Preferably, the concentration of phosphorus-like impurities in the dummy contact areas 73 is substantially equal to the concentration of phosphorus-like impurities in the contact areas 70.

[0160] The dummy contact areas 73 are configured in a top view as a one-to-many correspondence to each of the second dummy source trench structures 63. The dummy contact areas 73 are arranged with intervals between them along each of the second dummy source trench structures 63 in the top view and partially expose each of the second dummy source trench structures 63. In the present embodiment, the dummy contact areas 73 are each ribbon-shaped and extend in the first direction X in the top view. Preferably, the dummy contact areas 73 have a length that is greater than the distance between two adjacent dummy contact areas 73 in the first direction X.

[0161] In the present embodiment, the dummy contact areas 73 covering the individual second dummy-source trench structure 63 are oriented one-to-one in the second direction Y to the dummy contact areas 73 covering another, adjacent second dummy-source trench structure 63. In other words, in this embodiment, the dummy contact areas 73 are arranged in a matrix-like manner with gaps between them in the first directions X and the second directions Y, as viewed from above. In the present embodiment, the dummy contact areas 73 face the contact areas 70 in the second direction Y in the view from above.

[0162] The dummy contact areas 73 covering the single second dummy-source trench structure 63 can be offset by half a division (pitch) in the first direction X with respect to the dummy contact areas 73 covering another adjacent second dummy-source trench structure 63. In other words, the dummy contact areas 73 can be staggered in plan view in the first direction X and the second direction Y, with gaps between them. In this case, the dummy contact areas 73 can face the contact areas 70 in the second direction Y in plan view.

[0163] In the present embodiment, the dummy contact areas 73 are formed at a distance from the circumferential edge of the active surface 6 (third and fourth connection surfaces 8C and 8D) to the inner section of the second dummy-source trench structures 63 in the top view. More precisely, the dummy contact areas 73 on the inner section of the active surface 6 are formed such that the distance between an end section of the second dummy-source trench structure 63 and an outermost dummy contact area 73 is greater than the distance between two adjacent dummy contact areas 73 in the first direction X.

[0164] In the present embodiment, the dummy contact areas 73 are not formed in a section facing the second source trench structures 51 in the second dummy source trench structures 63. Furthermore, the dummy contact areas 73 are not formed in a section facing the end section of the gate trench structures 31 in the second dummy source trench structures 63. In other words, the dummy contact areas 73 are formed along the second dummy source trench structure 63 in the same way as the contact areas 70.

[0165] The dummy contact areas 73 are exposed from the active area 6. The dummy contact areas 73 are formed at a distance from the dummy gate trench structure 62 to the side of the second dummy gate trench structure 63. Each of the dummy contact areas 73 is formed at a distance from the bottom section of the second semiconductor region 11 (second concentration region 13) to the side of the active area 6 and faces the first semiconductor region 10 (third semiconductor region 14), with a portion of the second semiconductor region 11 lying between the first semiconductor region 10 and each of the dummy contact areas 73. Each of the dummy contact areas 73 covers the side wall and the bottom wall of each of the second dummy source trench structures 63 in the second semiconductor region 11 (second concentration region 13). The dummy contact areas 73 are electrically connected to the body area 23 in the side wall of the second dummy source trench structures 63.

[0166] The SiC semiconductor device 1 has a plurality of p-like dummy well regions 74 formed in the surface layer section of the active area 6 of the first circumferential region 21. The dummy well regions 74 have a p-like impurity concentration that is lower than the p-like impurity concentration of the dummy contact regions 73. Preferably, the p-like impurity concentration in the dummy well regions 74 exceeds the p-like impurity concentration of the body region 23. The p-like impurity concentration of the dummy well regions 74 is preferably not less than 1 × 10⁻⁶ 16 cm -3 and no more than 1x10 18 cm -3 The concentration of p-like impurities in the dummy trough areas 74 is preferably essentially equal to the concentration of p-like impurities in the trough areas 71.

[0167] The dummy trough areas 74 are formed in an area along the first dummy source trench structures 61 in the first dummy structure 60A. The dummy trough areas 74 are each formed as a one-to-one correspondence to the first dummy source trench structures 61. More precisely, each of the dummy trough areas 74 covers a corresponding first dummy source trench structure 61 at a distance from an adjacent first dummy source trench structure 61.

[0168] Each of the dummy trough areas 74 is ribbon-shaped and extends in plan view along each of the first dummy source trench structures 61 and is exposed from the third and fourth connection surfaces 8C and 8D. Each of the dummy trough areas 74 covers the side wall and the bottom wall of each of the first dummy source trench structures 61. Each of the dummy trough areas 74 directly covers each of the first dummy source trench structures 61. Each of the dummy trough areas 74 is electrically connected to the body area 23 in the side wall of each of the first dummy source trench structures 61.

[0169] Preferably, the thickness of a portion covering the bottom wall of each of the first dummy source trench structures 61 of each dummy basin area 74 exceeds the thickness of a portion covering the side wall of each of the first dummy source trench structures 61 of each dummy basin area 74. The thickness of the portion of each dummy basin area 74 covering the side wall of each of the first dummy source trench structures 61 is the thickness normal to the side wall of each of the first dummy source trench structures 61. The thickness of the portion of each dummy basin area 74 covering the bottom wall of each of the first dummy source trench structures 61 is the thickness normal to the bottom wall of each of the first dummy source trench structures 61.

[0170] In the present embodiment, each of the dummy trough areas 74 is also formed in a region along each of the second dummy source trench structures 63 in the second dummy structure 60B. The dummy trough areas 74 are each formed in a one-to-one correspondence to the second dummy source trench structures 63. Each of the dummy trough areas 74 covers a corresponding second dummy source trench structure 63 at a distance from the dummy gate trench structure 62 to the side of the second dummy source trench structure 63.

[0171] Each of the dummy trough areas 74 is ribbon-shaped and extends in plan view along each of the second dummy source trench structures 63 and is exposed by the third and fourth connection surfaces 8C and 8D. Each of the trough areas 74 covers the side wall and the bottom wall of each of the second dummy source trench structures 63. Each of the dummy trough areas 74 covers each of the second dummy source trench structures 63 with the dummy contact areas 73 between each of the second dummy source trench structures 63 and each of the dummy trough areas 74.

[0172] In other words, each of the dummy trough areas 74 has a section that directly covers each of the second dummy source trench structures 63 with the dummy contact areas 73 between each of the second dummy source trench structures 63 and this section of each dummy trough area 74, and a section that covers each of the second dummy source trench structures 63 with the dummy contact areas 73 between each of the second dummy source trench structures 63 and this section of each dummy trough area 74. Each of the dummy trough areas 74 is electrically connected to the body area 23 in the side wall of each of the second dummy source trench structures 63.

[0173] Preferably, the thickness of a portion covering the bottom wall of each of the second dummy-source trench structures 63 of each of the trough areas 74 exceeds the thickness of a portion covering the side wall of each of the second dummy-source trench structures 63 of each of the trough areas 74. The thickness of the portion covering the side wall of each of the second dummy-source trench structures 63 of each trough area 74 is the thickness normal to the side wall of each of the second dummy-source trench structures 63. The thickness of the portion covering the bottom wall of each of the second dummy-source trench structures 63 of each of the dummy trough areas 74 is the thickness normal to the bottom wall of each of the second dummy-source trench structures 63.

[0174] Each of the trough areas 74 is formed at a distance from the bottom section of the second semiconductor region 11 (second concentration region 13) towards the side of the active area 6 and faces the first semiconductor region 10 (third semiconductor region 14), with a portion of the second semiconductor region 11 located between the first semiconductor region 10 and each of the trough areas 74. In other words, each of the trough areas 74 is electrically connected to the second semiconductor region 11 (second concentration region 13). Preferably, the bottom section of the dummy trough areas 74 is formed at a substantially uniform depth with respect to the bottom wall of the first dummy source trench structures 61 and the bottom wall of the second dummy source trench structures 63.

[0175] Preferably, the bottom section of the dummy well regions 74 is formed at substantially the same depth as the bottom section of the well regions 71. The dummy well regions 74 form a pn junction with the second semiconductor region 11 (second concentration region 13) and extend a depletion layer in the width and depth direction of the SiC chip 2. The dummy well regions 74 bring the MISFET with insulated gate into close proximity to the structure of a pn junction diode and relieve an electric field in the SiC chip 2. Preferably, the dummy well regions 74 are configured such that the depletion layer overlaps the bottom wall of the dummy gate trench structures 62.

[0176] The SiC semiconductor device 1 has a plurality of p-like dummy gate well regions 75, each formed in a section along the dummy gate trench structures 62 in the surface layer section of the active area 6. The dummy gate well regions 75 have a p-like impurity concentration that exceeds the p-like impurity concentration of the body region 23. Preferably, the p-like impurity concentration in each dummy gate well region 75 is lower than the p-like impurity concentration in the dummy contact regions 73. The p-like impurity concentration in each dummy gate well region 75 is preferably not less than 1 × 10⁻⁶ 16 cm -3 and no more than 1x10 18 cm -3Preferably, the p-like impurity concentration in each of the dummy gate well areas 75 is substantially equal to the p-like impurity concentration in each of the gate well areas 72.

[0177] The dummy gate trough areas 75 are each configured as a one-to-one correspondence with respect to the dummy gate trench structures 62. Each dummy gate trough area 75 is ribbon-shaped and extends along each dummy gate trench structure 62 in plan view. Each dummy gate trough area 75 is positioned at a distance from the second dummy source trench structure 63 to the side of the dummy gate trench structure 62. Each dummy gate trough area 75 covers the side wall and the bottom wall of each dummy gate trench structure 62. Each dummy gate trough area 75 is electrically connected to the body area 23 in the side wall of each dummy gate trench structure 62.

[0178] Each of the dummy gate basin regions 75 is formed at a distance from the bottom section of the second semiconductor region 11 (second concentration region 13) in the direction of the side of the first main surface 3 and faces the first semiconductor region 10 (third semiconductor region 14), with a portion of the second semiconductor region 11 lying between the first semiconductor region 10 and each of the dummy gate basin regions 75. In the present embodiment, each of the dummy gate basin regions 75 is formed in the second concentration region 13 and faces the first concentration region 12, with a portion of the second concentration region 13 lying between the first concentration region 12 and each of the dummy gate basin regions 75.

[0179] Preferably, the thickness of a portion of each of the dummy gate trough areas 75 that covers the bottom wall of each of the dummy gate trench structures 62 exceeds the thickness of a portion that covers the side wall of each of the dummy gate trench structures 62 of each of the dummy gate trough areas 75. The thickness of the portion of each dummy gate trough area 75 that covers the side wall of each of the dummy gate trench structures 62 is the thickness in the normal direction to the side wall of each of the dummy gate trench structures 62. The thickness of the portion of each of the dummy gate trough areas 75 that covers the bottom wall of each of the dummy gate trench structures 62 is the thickness in the normal direction to the bottom wall of the dummy gate trench structure 62.

[0180] The bottom section of the dummy gate basin areas 75 is located on the side of the bottom wall of the dummy gate trench structure 62 with respect to the bottom section of the dummy gate basin areas 74. Preferably, the bottom section of the dummy gate basin areas 75 is formed at a substantially uniform depth with respect to the bottom wall of the dummy gate trench structures 62. Preferably, the bottom section of the dummy gate basin areas 75 is formed at substantially the same depth as the bottom section of the gate basin areas 72.

[0181] The dummy gate well regions 75 form a pn junction with the second semiconductor region 11 (second concentration region 13) and extend a depletion layer in the width and depth direction of the SiC chip 2. The dummy gate well regions 75 bring the MISFET with insulated gate close to the structure of a pn junction diode and relieve an electric field in the SiC chip 2.

[0182] Fig. 22 is a cross-sectional view along line XXII-XXII in Fig. 1 shown. Fig. 23 is a cross-sectional view along line XXIII-XXIII in Fig. 1. Fig. 24 is a cross-sectional view along line XXIV-XXIV in Fig. 1. Fig. 25 is a cross-sectional view along line XXV-XXV in Fig. 1. Fig. 26 is a cross-sectional view along line XXVI-XXVI in Fig. 1. Fig. Figure 27 is a top view describing the structure of a main surface electrode 120. Fig. Figure 28 is a top view describing the structure of a second inorganic insulating film 150.

[0183] The SiC semiconductor device 1 has a p-like outer contact area 80 formed on the surface layer section of the outer surface 7. The outer contact area 80 can harbor a p-like impurity concentration of at least 1 × 10⁻⁶ 18cm -3 and at most 1×10 21 cm -3 The outer contact area 80 exhibits a phosphorus-like impurity concentration that exceeds the phosphorus-like impurity concentration of the body area 23. Preferably, the phosphorus-like impurity concentration of the outer contact area 80 is substantially equal to the phosphorus-like impurity concentration of the contact area 70 (dummy contact area 73).

[0184] The outer contact area 80 is formed in a region between the circumferential edge of the active surface 6 and the circumferential edge of the outer surface 7, at a distance from the circumferential edge of the active surface 6 (first to fourth connection surfaces 8A to 8D) and from the circumferential edge of the outer surface 7 (first to fourth side surfaces 5A to 5D) in the top view. In the top view, the outer contact area 80 extends in a band-like shape along the active surface 6 (first to fourth connection surfaces 8A to 8D). In the present embodiment, the outer contact area 80 is annular and surrounds the active surface 6 in the top view. More precisely, the outer contact area 80 has a quadrilateral ring shape, the four sides of which run parallel to the active surface 6 in the top view.

[0185] The outer contact area 80 is located at a distance from the bottom section of the second semiconductor region 11 to the outer surface 7. More precisely, the outer contact area 80 is located at a distance from the bottom section of the second concentration region 13 to the outer surface 7. The entirety of the outer contact area 80 is located on the side of the bottom section of the second semiconductor region 11 with respect to the bottom wall of the gate trench structures 31 and with respect to the bottom wall of the dummy gate trench structures 62. The bottom section of the outer contact area 80 is located on the side of the bottom section of the second semiconductor region 11 with respect to the bottom wall of the first source trench structure 41, the bottom wall of the second source trench structure 51, the bottom wall of the first dummy source trench structures 61, and the bottom wall of the second dummy source trench structures 63.

[0186] Preferably, the base section of the outer contact region 80 is formed at essentially the same depth as the base section of the contact regions 70 and the dummy contact regions 73. The outer contact region 80, together with the second semiconductor region 11, forms a pn junction (specifically: the second concentration region 13). This creates a pn junction diode in which the outer contact region 80 serves as the anode and the second semiconductor region 11 as the cathode. The outer contact region 80 can also be referred to as the anode region.

[0187] The SiC semiconductor device 1 has a p-like outer well region 81 formed on the surface layer section of the outer surface 7. The p-like impurity concentration in the outer well region 81 is preferably not less than 1 × 10 16 cm -3 and no more than 1x10 18 cm -3The outer basin area 81 has a p-like impurity concentration that is lower than the p-like impurity concentration of the outer contact area 80. Preferably, the p-like impurity concentration of the outer basin area 81 is substantially equal to the p-like impurity concentration of the basin area 71 (dummy basin area 74). Preferably, the p-like impurity concentration of the outer basin area 81 is substantially equal to the p-like impurity concentration of the gate basin area 72 (dummy gate basin area 75).

[0188] The outer basin area 81 is formed in a region between the circumferential edge of the active surface 6 (first to fourth connection surfaces 8A to 8D) and the outer contact area 80 in the top view. In the top view, the outer basin area 81 extends in a band-like shape along the active surface 6 (first to fourth connection surfaces 8A to 8D). In the present embodiment, the outer basin area 81 is annular (in this embodiment, rectangular) and surrounds the active surface 6 (first to fourth connection surfaces 8A to 8D) in the top view.

[0189] In the present embodiment, the outer basin area 81 is formed over the entire area of ​​a region between the first to fourth connection surfaces 8A to 8D and the outer contact area 80. Furthermore, the outer basin area 81 extends from the outer surface 7 towards the first to fourth connection surfaces 8A to 8D and covers the first to fourth connection surfaces 8A to 8D in the SiC chip 2. The outer basin area 81 is electrically connected to the basin area 71, the dummy basin area 74, and the dummy gate basin area 75 in the surface layer section of the first to fourth connection surfaces 8A to 8D. A portion of the outer basin area 81 that covers the first to fourth connection surfaces 8A to 8D can be considered an integral (one-piece) basin area comprising the basin area 71, the dummy basin area 74, and the dummy gate basin area 75.

[0190] The outer basin area 81 is connected to basin area 71 in a section where the bottom wall of the first source trench structure 41 connects with the outer surface 7. In other words, the outer basin area 81 extends superficially and continuously from a portion of basin area 71 that covers the bottom wall of the first trench structure 41 to the outer surface 7. The outer basin area 81 is connected to basin area 71 in a section where the bottom wall of the second source trench structure 51 connects with the outer surface 7. In other words, the outer basin area 81 extends superficially and continuously from a portion of basin area 71 that covers the bottom wall of the second trench structure 51 towards the outer surface 7.

[0191] The outer trough area 81 is connected to the dummy trough area 74 in a section where the bottom wall of the first dummy-source trench structures 61 is connected to the outer surface 7. In other words, the outer trough area 81 extends superficially and continuously from a portion of the dummy trough area 74, which covers the bottom wall of the first dummy-source trench structure 61, towards the outer surface 7. The outer trough area 81 is also connected to the dummy trough area 74 in a section where the bottom wall of the second dummy-source trench structures 63 is connected to the outer surface 7. In other words, the outer trough area 81 extends superficially and continuously from a portion of the dummy trough area 74, which covers the bottom wall of the second dummy-source trench structure 63, towards the outer surface 7.

[0192] The outer basin area 81 is formed at a distance from the bottom section of the second semiconductor region 11 in the direction of the outer surface 7. More precisely, the outer basin area 81 is formed at a distance from the bottom section of the second concentration region 13 towards the outer surface 7. The entirety of the outer basin area 81 is located on the side of the bottom section of the second semiconductor region 11 with respect to the bottom wall of the gate trench structures 31 and with respect to the bottom wall of the dummy gate trench structures 62.

[0193] The outer basin area 81 is electrically connected to the outer contact area 80 in the outer surface 7. The outer basin area 81 is deeper than the outer contact area 80. The bottom section of the outer basin area 81 is located on the bottom side of the second semiconductor area 11 with respect to the bottom wall of the first source trench structure 41, the bottom wall of the second source trench structure 51, the bottom wall of the first dummy source trench structures 61, and the bottom wall of the second dummy source trench structures 63. Preferably, the bottom section of the outer basin area 81 is located at substantially the same depth as the bottom section of the basin area 71 and the bottom section of the dummy basin area 74.

[0194] The outer well region 81, together with the outer contact region 80, forms a pn junction with the second semiconductor region 11 (specifically, the second concentration region 13). Furthermore, the outer well region 81 forms a pn junction with the second semiconductor region 11 in a section along the first to fourth interconnect surfaces 8A to 8D. In other words, a pn junction is formed in the section along the first to fourth interconnect surfaces 8A to 8D in the SiC chip 2.

[0195] The SiC semiconductor device 1 has at least one (preferably not fewer than two and not more than twenty) p-shaped field region(s) 82A to 82E, which is / are formed in a region between the outer contact region 80 and the circumferential edge of the outer surface 7 (first to fourth side faces 5A to 5D) in the surface layer section of the outer surface 7. In the present embodiment, the SiC semiconductor device 1 has five field regions 82A to 82E. The five field regions 82A to 82E comprise a first field region 82A, a second field region 82B, a third field region 82C, a fourth field region 82D, and a fifth field region 82E. The first to fifth field regions 82A to 82E are formed in this order at a distance from the side of the outer contact region 80 to the circumferential side of the outer surface 7.

[0196] Field areas 82A to 82E relieve (dissolve) an electric field on the outer surface 7. The number, width, depth, p-type impurity concentration, etc., of field areas 82A to 82E can have different values ​​depending on the electric field to be relieved. The p-type impurity in field areas 82A to 82E should preferably be no less than 1 × 10 15 cm -3 and no more than 1x10 18 cm -3 be.

[0197] Each of the field areas 82A to 82E is ribbon-shaped and extends along the active surface 6 in plan view. Each of the field areas 82A to 82E is ring-shaped and surrounds the active surface 6 in plan view. More precisely, each of the field areas 82A to 82E has a quadrilateral ring shape with four sides that run parallel to the active surface 6 in plan view (first to fourth connection surfaces 8A to 8D). Each of the field areas 82A to 82E can be referred to as an FLR (Field Limiting Ring) area.

[0198] In the present embodiment, the innermost first field region 82A is connected to the outer contact region 80. The innermost first field region 82A, together with the outer contact region 80, forms a pn junction with the second semiconductor region 11 (specifically: the second concentration region 13). The second to fifth field regions 82B to 82E, on the other hand, are in an electrically floating state at a distance from the outer contact region 80. Each of the field regions 82A to 82E is deeper than the outer contact region 80. Each of the field regions 82A to 82E is located at a distance from the bottom section of the second semiconductor region 11 towards the outer surface 7. More precisely, each of the field regions 82A to 82E is located at a distance from the bottom section of the second concentration region 13 towards the outer surface 7.

[0199] The entirety of field areas 82A to 82E is located on the side of the bottom section of the second semiconductor area 11 with respect to the gate trench structure 31 and with respect to the bottom wall of the dummy gate trench structures 62. The bottom section of each of field areas 82A to 82E is located on the side of the bottom section of the second semiconductor area 11 with respect to the bottom wall of the first source trench structure 41, the bottom wall of the second source trench structures 51, the bottom wall of the first dummy source trench structures 61, and the bottom wall of the second dummy source trench structures 63.

[0200] Referring to the cross-sectional views of Fig. In the embodiment 6 to 21, the SiC semiconductor device 1 has a main surface insulating film 90 covering the first main surface 3. More precisely, the main surface insulating film 90 covers the active area 6, the outer surface 7, and the first to fourth interconnect surfaces 8A to 8D in a film-like manner. The main surface insulating film 90 comprises at least one silicon oxide film, one silicon nitride film, or one silicon oxynitride film. In the present embodiment, the main surface insulating film 90 has a single-layer structure, which is a silicon oxide film. More precisely, the main surface insulating film 90 comprises a silicon oxide film formed from an oxide of the SiC chip 2. The thickness of the main surface insulating film 90 is preferably not less than 50 nm and not more than 500 nm.

[0201] The main surface insulating film 90 covers the active area 6 in such a way that it is connected to the gate insulating film 33 of the gate trench structures 31, the source insulating film 43 of the first source trench structures 41, the source insulating film 43 of the second source trench structures 51, the source insulating film 43 of the first dummy source trench structures 61, the gate insulating film 33 of the dummy gate trench structures 62 and the source insulating film 43 of the second dummy source trench structures 63.

[0202] In other words, the main surface insulating film 90 exposes the gate electrode 34 of the gate trench structures 31, the source electrode 44 of the first source trench structures 41, the source electrode 44 of the second source trench structures 51, the source electrode 44 of the first dummy source trench structures 61, the gate electrode 34 of the dummy gate trench structures 62 and the source electrode 44 of the second dummy source trench structures 63 on the active area 6.

[0203] The main surface insulating film 90 covers the first to fourth connection surfaces 8A to 8D in such a way that it is connected to the gate insulating film 33 of the gate trench structures 31, the source insulating film 43 of the first source trench structures 41, the source insulating film 43 of the second source trench structures 51, the source insulating film 43 of the first dummy source trench structure 61, the gate insulating film 33 of the dummy gate trench structures 62 and the source insulating film 43 of the second dummy source trench structures 63.

[0204] In other words, the main surface insulating film 90 exposes the gate electrode 34 of the gate trench structures 31, the source electrode 44 of the first source trench structures 41, the source electrode 44 of the second source trench structures 51, the source electrode 44 of the first dummy source trench structures 61, the gate electrode 34 of the dummy gate trench structures 62, and the source electrode 44 of the second dummy source trench structures 63 in the first to fourth connection surfaces 8A to 8D. The main surface insulating film 90 is formed at an inward distance from the circumferential edge of the outer surface 7 (first to fourth inner surface 5A to 5D) and has a circumferential end wall that exposes the circumferential edge portion of the outer surface 7.

[0205] Referring to Fig. 6 and Fig. 8 The SiC semiconductor device 1 has a plurality of gate contact electrodes that cover the gate electrode 34 of the gate trench structure 31 above the first surface 3 (specifically: active area 6) in the transistor region 20. Fig. Figure 6 shows the gate contact electrodes 91, each represented by a thick dashed line. In the present embodiment, the gate contact electrodes 91 are not formed in the first circumferential region 21 and the second circumferential region 22. In other words, the gate contact electrodes 91 are not formed on the gate electrode 34 of the dummy gate trench structures 62.

[0206] The gate contact electrodes 91 each cover the gate trench structures 31 and are electrically connected to the corresponding gate electrodes 34. More precisely, the gate contact electrodes 91 are located at a distance from the inner section of the gate trench structures 31 at both end sections. In other words, the gate contact electrodes 91 are electrically connected to the corresponding gate electrodes 34 in a region adjacent to both end sections of the gate trench structure 31, with respect to the inner section of the gate trench structure 31.

[0207] The gate contact electrodes 91 extend from above the gate trench structures 31 onto the main surface insulating film 90. In the second direction Y, the gate contact electrodes 91 are positioned at a distance from the first source trench structures 41 in the top view. In the first direction X, the gate contact electrodes 91 are also positioned at a distance from the second source trench structures 51 in the top view.

[0208] The gate contact electrodes 91 are arranged alternately with the first source trench structures 41 in the second direction Y such that, in a top view, the individual first source trench structure 41 lies between them. In the present embodiment, the gate contact electrodes 91 are each formed in a band shape extending in the first direction X. The gate contact electrodes 91 do not face the second source trench structures 51 in the second direction Y in a top view.

[0209] The gate contact electrodes 91 have an electrode width WE that is greater than the first width W1 of the gate trench structure 31 (W1 < WE) with respect to the first direction X. The electrode width WE is a width in a direction (second direction Y) perpendicular to a direction (first direction X) in which the gate contact electrode 91 extends. The gate contact electrodes 91 have a shorter length than the length of the gate trench structure 31 in the second direction Y.

[0210] Each of the gate contact electrodes 91 has an electrode surface 91a extending along the active area 6. In the present embodiment, the gate contact electrodes 91 are formed in a conical shape (truncated square-cone), with the electrode width WE becoming narrower from the active area 6 to the electrode surface 91a. Preferably, the electrode surface 91a is wider than the electrode surface of the gate electrode 34 with respect to the second direction Y. In other words, the electrode surface 91a preferably has a section facing the gate electrode 34 in the normal direction Z and a section facing an area (i.e., the main surface insulating film 90) outside the gate trench structure 31 in the normal direction Z.

[0211] Preferably, each of the gate contact electrodes 91 is made of conductive polysilicon. Each of the gate contact electrodes 91 can comprise n-type polysilicon doped with an n-type impurity and / or p-type polysilicon doped with a p-type impurity. Preferably, each of the gate contact electrodes 91 is made of the same conductive material as each of the gate electrodes 34. In the present embodiment, each of the gate contact electrodes 91 is formed on a lead-out section that extends from each of the gate electrodes 34 into a space above the active area 6. In other words, the gate contact electrodes 91 are led out from the gate electrode 34 through the third section 33c of the gate insulating film 33 onto the main surface insulating film 90.

[0212] Referring to the top view and the cross-sectional view, which defines the perimeter of the active area 6 of the Fig. As shown in Figures 5 to 21, the SiC semiconductor device 1 has a sidewall wiring 100 which is formed above the outer surface 7 such that it covers at least one of the first to fourth interconnect surfaces 8A to 8D. The sidewall wiring 100 (lateral wiring) is designed as a sidewall structure (height-difference compensation structure) that compensates for a level difference (height difference) formed between the active surface 6 and the outer surface 7. More precisely, the sidewall wiring 100 is formed on the main surface insulating film 90.

[0213] Preferably, the sidewall wiring 100 covers at least one of the third and fourth connection surfaces 8C and 8D. In the present embodiment, the sidewall wiring 100 is ribbon-shaped and extends along the first to fourth connection surfaces 8A to 8D in plan view. More precisely, the sidewall wiring 100 is ring-shaped (specifically: rectangular) around the active surface 6 and extends over the entire surface of the first to fourth connection surfaces 8A to 8D.

[0214] In other words, the side wall wiring 100 extends in one direction (first direction X) along the gate trench structure 31, the first source trench structure 41, the second source trench structure 51, the first dummy source trench structure 61, the dummy gate trench structure 62 and the second dummy source trench structure 63 on the side of the first connection surface 8A and the second connection surface 8B. The side wall wiring 100 extends in one direction (second direction Y) which intersects the gate trench structure 31, the first source trench structure 41, the second source trench structure 51, the first dummy source trench structure 61, the dummy gate trench structure 62 and the second dummy source trench structure 63 on the side of the third connection surface 8C and the fourth connection surface 8D.

[0215] A portion covering the four corners (corner sections of the first to fourth connection surfaces 8A to 8D) of the active surface 6 of the sidewall wiring 100 is curved towards the side of the outer surface 7. In the present embodiment, the sidewall wiring 100 is therefore formed in a square ring shape, the four corners of which are curved as a whole in the top view.

[0216] The sidewall wiring 100 has a section that extends film-like along the outer surface 7 and a section that extends film-like along the first to fourth connection surfaces 8A to 8D. A portion of the sidewall wiring 100 located above the outer surface 7 may cover the outer surface 7 in an area on the side of the outer surface 7 with respect to the active surface 6. The portion of the sidewall wiring 100 located above the outer surface 7 may have a lesser thickness than the thickness (first depth D1) of the active mesa 9.

[0217] A portion of the sidewall wiring 100, located at the first to fourth connection surfaces 8A to 8D, is formed as a film along these surfaces. This portion of the sidewall wiring 100 may have an outer surface inclined obliquely downwards from the active surface 6 towards the outer surface 7. In this case, the outer surface of the sidewall wiring 100 may be curved and projecting away from the first to fourth connection surfaces 8A to 8D, or it may be curved and recessed towards the side of the first to fourth connection surfaces 8A to 8D.

[0218] The sidewall wiring 100 faces a portion of the outer basin area 81, with the main surface insulating film 90 located between this portion of the outer basin area 81 and the sidewall wiring 100 above the outer surface 7. Furthermore, the sidewall wiring 100 faces the outer contact area 80, with the main surface insulating film 90 located between the outer contact area 80 and the sidewall wiring 100 above the outer surface 7. In the present embodiment, the sidewall wiring 100 is formed at a distance from the field areas 82A to 82E in the direction of the side of the active surface 6 in the top view and does not face the field areas 82A to 82E with the main surface insulating film 90 located between the field areas 82A to 82E and the sidewall wiring 100.

[0219] The sidewall wiring 100 faces the SiC chip 2 at the first to fourth interconnect surfaces 8A to 8D, with the main surface insulating film 90 located between the SiC chip 2 and the sidewall wiring 100. In other words, the sidewall wiring 100 faces a pn junction (pn junction between the outer well region 81 and the second semiconductor region 11) along the first to fourth interconnect surfaces 8A to 8D, with the main surface insulating film 90 located between the pn junction and the sidewall wiring 100.

[0220] Furthermore, the sidewall wiring 100 covers the exposed section of the first source trench structure 41, the exposed section of the second source trench structure 51, the exposed section of the first dummy source trench structure 61, the exposed section of the dummy gate trench structure 62, and the exposed section of the second dummy source trench structure 63 on the first to fourth connection surfaces 8A to 8D. The sidewall wiring 100 is therefore electrically connected to the first source trench structure 41, the second source trench structure 51, the first dummy source trench structure 61, the dummy gate trench structure 62, and the second dummy source trench structure 63 on the first to fourth connection surfaces 8A to 8D.

[0221] More precisely, the sidewall wiring 100 is electrically connected to the source electrode 44 of the first source trench structure 41, the source electrode 44 of the second source trench structure 51, the source electrode 44 of the first dummy source trench structure 61, the gate electrode 34 of the dummy gate trench structure 62, and the source electrode 44 of the second dummy source trench structure 63 at the first to fourth connection surfaces 8A to 8D. In other words, the sidewall wiring 100 is configured as source potential-providing wiring above the outer surface 7.

[0222] In the present embodiment, the side wall wiring 100 is formed integrally with the source electrode 44 of the first source trench structure 41, the source electrode 44 of the second source trench structure 51, the source electrode 44 of the first dummy source trench structure 61, the gate electrode 34 of the dummy gate trench structure 62 and the source electrode 44 of the second dummy source trench structure 63 at the first to fourth connection surfaces 8A to 8D.

[0223] The sidewall wiring 100 has an overlap section 101 that runs along the edge section of the active surface 6 of at least one of the first to fourth connection surfaces 8A to 8D. The overlap section 101 is ribbon-shaped and extends along the edge section of the active surface 6 in plan view. In the present embodiment, the overlap section 101 extends along the edge section of the active surface 6 of all first to fourth connection surfaces 8A to 8D. In other words, the overlap section 101 extends along the edge section of the active surface 6 in plan view and is annular in shape to surround the inner section of the active surface 6.

[0224] The overlap section 101 has a pair of first overlap sections 101A and a pair of second overlap sections 101B. The pair of first overlap sections 101A is a portion of the overlap section 101 that extends along the first and second connection surfaces 8A and 8B, respectively, and the pair of second overlap sections 101B is a portion of the overlap section 101 that extends along the third and fourth connection surfaces 8C and 8D. The pair of first overlap sections 101A and the pair of second overlap sections 101B have the same structure. The structure of the first overlap section 101A on the side of the first connection surface 8A and the structure of the second overlap section 101B on the side of the third connection surface 8C are described below.

[0225] The first overlap section 101A faces the active surface 6, with the main surface insulating film 90 located between the active surface 6 and the first overlap section 101A, and covers at least one first dummy source trench structure 61 located at the outermost side. In the present embodiment, the first overlap section 101A covers the entire area of ​​the individual first dummy source trench structure 61 located at the outermost side. The first overlap section 101A is electrically connected to the source electrode 44 of the outermost first dummy source trench structure 61 above the active surface 6.

[0226] More precisely, the first overlap section 101A is formed integrally with the source electrode 44 of the outermost first dummy-source trench structure 61 above the active area 6. The first overlap section 101A can cover the first dummy-source trench structures 61. In this case, preferably the number of first dummy-source trench structures 61 covered by the first overlap section 101A is less than the number of first dummy-source trench structures 61 exposed by the first overlap section 101A.

[0227] The second overlap section 101B faces the active surface 6, with the main surface insulating film 90 located between the active surface 6 and the second overlap section 101B, and covers the end section of the first source trench structure 41, the end section of the second source trench structure 51, the end section of the first dummy source trench structure 61, the end section of the dummy gate trench structure 62, and the end section of the second dummy source trench structure 63. The second overlap section 101B is connected to the source electrode 44 of the first source trench structure 41, the source electrode 44 of the second source trench structure 51, the source electrode 44 of the first dummy source trench structure 61, the gate electrode 34 of the dummy gate trench structure 62, and the source electrode 44 of the The second dummy source trench structure 63 is electrically connected above the active area 6.

[0228] More precisely, the second overlap section 101B is formed integrally with the source electrode 44 of the first trench-trench structure 41, the source electrode 44 of the second source trench structure 51, the source electrode 44 of the first dummy source trench structure 61, the gate electrode 34 of the dummy gate trench structure 62 and the source electrode 44 of the second dummy source trench structure 63 over the active area 6.

[0229] The overlap section 101 has an overlap width WO. The overlap width WO is a width in a direction perpendicular to the direction in which the overlap section 101 extends based on the first to fourth connecting surfaces 8A to 8D. Preferably, the overlap width WO is less than the first depth D1 of the outer surface 7 (WO < D1). Preferably, the overlap width WO is less than the third depth of the first source trench structure 41 (WO < D3). The overlap width WO can be equal to or greater than the second depth D2 of the gate trench structure 31 (WO ≥ D2), or it can be less than the second depth D2 (WO < D2).

[0230] Preferably, the sidewall wiring 100 is made of conductive polysilicon. The sidewall wiring 100 can comprise n-type polysilicon doped with an n-type impurity and / or p-type polysilicon doped with a p-type impurity. Preferably, the sidewall wiring 100 is made of the same conductive material as the gate electrode 34. Furthermore, the sidewall wiring 100 is preferably made of the same conductive material as the source electrode 44.

[0231] The SiC semiconductor device 1 has a first inorganic insulating film 110 formed on the main surface insulating film 90. The first inorganic insulating film 110 can be referred to as an "intermediate insulating film," "intermediate insulating film," "top insulating film," or "covering object." The first inorganic insulating film 110 can have a layered structure comprising a plurality of insulating films or a single-layer structure formed from a single insulating film. Preferably, the first inorganic insulating film 110 comprises at least one silicon oxide film, one silicon nitride film, or one silicon oxynitride film.

[0232] The first inorganic insulating film 110 can have a layered structure in which at least two of the following films, silicon oxide film, silicon nitride film, or silicon oxynitride film, are layered in any order. The first inorganic insulating film 110 can have a single-layer structure formed from a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In the present embodiment, the first inorganic insulating film 110 has a layered structure in which a plurality of silicon oxide films are layered.

[0233] More precisely, the first inorganic insulating film 110 has a layered structure comprising an NSG film (undoped silicate glass) and a PSG film (phosphosilicate glass), layered in that order from the side of the main surface insulating film 90. The NSG film is a silicon oxide film undoped with impurities. The PSG film is a silicon oxide film doped with phosphorus. The thickness of the NSG film is preferably not less than 10 nm and not more than 300 nm. The thickness of the PSG film is preferably not less than 50 nm and not more than 500 nm. Preferably, the thickness of the first inorganic insulating film 110 is greater than the thickness of the main surface insulating film 90.

[0234] The first inorganic insulating film 110 covers the transistor region 20, the first circumferential region 21, and the second circumferential region 22 as a film above the active area 6. The first inorganic insulating film 110 selectively covers the gate trench structures 31, the first source trench structures 41, and the second source trench structures 51 in the transistor region 20. The first inorganic insulating film 110 covers the entire area of ​​the first dummy structure 60A and the entire area of ​​the second dummy structure 60B in the first and second circumferential regions 21 and 22. In other words, the first inorganic insulating film 110 covers the first dummy source trench structures 61, the dummy gate trench structures 62, and the second dummy source trench structure 63.

[0235] The first inorganic insulating film 110 covers the sidewall wiring 100 in an area between the active surface 6 and the outer surface 7 and extends through the first to fourth connection surfaces 8A to 8D from above the active surface 6 and is brought out onto the outer surface 7. The first inorganic insulating film 110 covers the sidewall wiring 100 in film form. The first inorganic insulating film 110 covers the main surface insulating film 90 in film form above the outer surface 7. The first inorganic insulating film 110 is formed at an inward distance from the circumferential edge of the outer surface 7 (first to fourth side surfaces 5A to 5D) and has a circumferential end wall that exposes the circumferential edge section of the outer surface 7. The circumferential end wall of the first inorganic insulating film 110 defines a notch opening 111 that exposes the circumferential edge section of the outer surface 7 together with the circumferential end wall of the main surface insulating film 90.

[0236] Referring to Fig. 6 and Fig. 14 The first inorganic insulating film 110 has a plurality of gate openings 112 on the side of the active area 6. The gate openings 112 are located on the side of the transistor region 20 and each exposes both end sections of the gate trench structures 31. The gate openings 112 are not formed on the side of the first circumferential region 21 and on the side of the second circumferential region 22 and do not expose the dummy gate trench structures 62.

[0237] In the present embodiment, the gate openings 112 expose the gate contact electrodes 91 in a one-to-one correspondence. Of course, the gate openings 112 can also expose individual gate contact electrodes 91 in a one-to-many correspondence. In the present embodiment, each of the gate openings 112 exposes the electrode surface 91a of a corresponding gate contact electrode 91 at a distance from the circumferential edge of a corresponding gate contact electrode 91 in the top view.

[0238] In other words, each of the gate openings 112 exposes only the electrode surface 91a of a corresponding gate contact electrode 91. In the present embodiment, the gate openings 112 are each ribbon-shaped and extend in a direction (first direction X) corresponding to the direction of the gate contact electrode 91. Viewed from above, the gate openings 112 appear as strips. The planar shape of the gate openings 112 is arbitrary and can be circular.

[0239] Referring to Fig. In section 11, the first inorganic insulating film 110 has a plurality of source openings 113 on the side of the active area 6. The source openings 113 are located on the side of the transistor area 20 and each exposes the first source trench structures 41. The source openings 113 do not expose the second source trench structures 51. In other words, the second source trench structures 51 are covered by the first inorganic insulating film 110. Furthermore, the source openings 113 are not formed on the side of the first circumferential area 21 and on the side of the second circumferential area 22 and do not expose the first dummy source trench structures 61 and the second dummy trench structures 63.

[0240] In the present embodiment, the source openings 113 are each configured to correspond one-to-one with the contact areas 70 and expose corresponding first source trench structures 41 at several locations. In other words, the source openings 113 are arranged in a matrix pattern or a staggered pattern with intervals between them, according to the arrangement of the contact areas 70 in the top view in the first directions X and the second directions Y.

[0241] In the present embodiment, the source openings 113 are each formed in a band shape, extending in the first direction X according to the planar shape of the contact areas 70. The planar shape of the source openings 113 is arbitrary and can be circular. Each of the source openings 113 exposes a corresponding source area 24 and a corresponding contact area 70 in addition to the source electrode 44 of a corresponding first source trench structure 41. Naturally, the source openings 113 can expose the first source trench structure 41 in a one-to-one correspondence. Preferably, in this case, the first source trench structure 41 is formed in a band shape, extending along the corresponding first source trench structure 41.

[0242] Referring to Fig. 10, Fig. 13 and Fig. In the present embodiment, the first inorganic insulating film 110 has at least one side wall opening 114 on the side of the outer surface 7. In the present embodiment, the first inorganic insulating film 110 has a single side wall opening 114. The side wall opening 114 is ribbon-shaped and extends along the side wall wiring 100 in plan view. In the present embodiment, the side wall opening 114 is annular (specifically, rectangular) and extends along the side wall wiring 100 in plan view. The side wall opening 114 exposes a portion of the side wall wiring 100 that covers the outer surface 7 over its entire circumference. In the present embodiment, the side wall opening 114 also exposes the outer contact area 80 over its entire circumference.

[0243] Referring to Fig. 22 to Fig. In the SiC semiconductor device 1, a first main surface electrode 120 is formed on the first inorganic insulating film 110. In the present embodiment, the first main surface electrode 120 is arranged only above the active area 6 and not above the outer surface 7. The first main surface electrode 120 has a gate main surface electrode 121. The gate main surface electrode 121 can be referred to as a gate pad electrode. The gate main surface electrode 121 is electrically connected to the gate trench structure 31 (gate electrode 34) and transmits the gate potential (gate signal) from the outside to the gate trench structure 31 (gate electrode 34).

[0244] The gate main surface electrode 121 is arranged in a top view at a distance from the first to fourth interconnection surfaces 8A to 8D above the circumferential edge section of the active surface 6. In the present embodiment, the gate main surface electrode 121 is arranged in a region facing the central section of the first interconnection surface 8A in the circumferential region of the active surface 6. The gate main surface electrode 121 is spaced at least from the outermost first dummy source trench structure 61 (sidewall wiring 100) in the direction of the inner surface of the active surface 6. The gate main surface electrode 121 has a quadrilateral shape with four sides that are parallel to the active surface 6 in a top view.

[0245] The gate main surface electrode 121 faces a portion of the first circumferential region 21 (part of the first dummy structure 60A), with the first inorganic insulating film 110 located between this portion of the first circumferential region 21 and the gate main surface electrode 121. Preferably, the gate main surface electrode 121 faces at least one of the first dummy source trench structures 61, with the first inorganic insulating film 110 located between the first dummy source trench structure 61 and the gate main surface electrode 121. In the present embodiment, the gate main surface electrode 121 crosses the first dummy source trench structures 61. The gate main surface electrode 121 is electrically separated from the first dummy source trench structures 61 by the first inorganic insulating film 110.

[0246] The gate main surface electrode 121 extends from the side of the first dummy structure 60A to the side of the second dummy structure 60B and faces a portion of the second dummy structure 60B, with the first inorganic insulating film 110 located between this portion of the second dummy structure 60B and the gate main surface electrode 121. The gate main surface electrode 121 faces either the dummy gate trench structure 62 or the second dummy source trench structure 63, with the first inorganic insulating film 110 located between the structure 62 (63) and the gate main surface electrode 121. In the present embodiment, the gate main surface electrode 121 crosses all dummy gate trench structures 62 and the second dummy source trench structure 63.The gate main surface electrode 121 is electrically separated from the dummy gate trench structures 62 and from the second dummy source trench structures 63 by the first inorganic insulating film 110.

[0247] The gate main surface electrode 121 extends from the side of the first circumferential region 21 to the side of the transistor region 20 and faces a portion of the transistor structure 30, with the first inorganic insulating film 110 located between this portion of the transistor structure 30 and the gate main surface electrode 121. The gate main surface electrode 121 faces either the gate trench structure 31 or the first source trench structure 41, or both. In the present embodiment, the gate main surface electrode 121 intersects the gate trench structures 31 and the first source trench structures 41. The gate main surface electrode 121 is electrically isolated from the gate trench structures 31 and the first source trench structures 41 by the first inorganic insulating film 110.The gate main surface electrode 121 is arranged at a distance from the second source trench structures 51 and is also electrically separated from the second trench structures 51.

[0248] The main gate surface electrode 121 has a gate electrode sidewall 121a (electrode sidewall) arranged on the first inorganic insulating film 110. The gate electrode sidewall 121a has a conical shape that slopes obliquely downwards from the surface of the main gate surface electrode 121. The gate electrode sidewall 121a can be formed in a curved, conical shape that curves towards the first inorganic insulating film 110.

[0249] The first main surface electrode 120 has a source main surface electrode 122. The source main surface electrode 122 is arranged on the active area 6 at a distance from the gate main surface electrode 121. The source main surface electrode 122 can also be referred to as the source pad electrode. The source main surface electrode 122 is electrically connected to the first source trench structures 41 (of the source electrode 44) and supplies the source potential to the first source trench structures 41 (source electrode 44) from the outside.

[0250] The source main surface electrode 122 is formed on the active surface 6 at a distance from the first to fourth interconnection surfaces 8A to 8D in the top view. In the present embodiment, the source main surface electrode 122 has a quadrilateral shape with four sides parallel to the active surface 6 (first to fourth interconnection surfaces 8A to 8D) in the top view. More precisely, the source main surface electrode 122 is polygonal and has a concave section that is recessed towards the inside of the active surface 6, so that in the top view it coincides with the gate main surface electrode 121 on one side along the first interconnection surface 8A.

[0251] The source main surface electrode 122 has a flat surface that is larger than the flat surface of the gate main surface electrode 121. The source main surface electrode 122 is arranged at a distance of at least one outermost first dummy source trench structures 61 (sidewall wiring 100) from the inside of the active surface 6. In the present embodiment, the source main surface electrode 122 is arranged at a distance from the first dummy structure 60A to the inside of the active surface 6 in the top view.

[0252] The source main surface electrode 122 has a main section 123, a first extension section 124, a second extension section 125, and a third extension section 126. The main section 123 is located above the transistor area 20 and faces the gate main surface electrode 121 in the second direction Y. In the present embodiment, the main section 123 faces all gate trench structures 31 and all first source trench structures 41. The main section 123 enters the source openings 113 from above the first inorganic insulating film 110 and is electrically connected to the source areas 24, the source electrodes 44, and the contact areas 70. The source potential applied to the source main surface electrode 122 is thus transferred to the source electrodes 44, the source areas 24, and the contact areas 70.

[0253] The first lead-out section 124 extends from above the transistor area 20 to one side (side of the third interconnect surface 8C) of the first circumferential area 21 and faces the gate main surface electrode 121 in the first direction X. The second lead-out section 125 extends from above the transistor area 20 to the other side (side of the fourth interconnect surface 8D) of the first circumferential area 21 and faces the first lead-out section 124, with the gate main surface electrode 121 located between the first lead-out section 124 and the second lead-out section 125 in the first direction X.

[0254] The first and second exit sections 124 and 125 face a portion of the second dummy structure 60B, with the first inorganic insulating film 110 located between this portion of the second dummy structure 60B and the first and second sections 124 and 125. The first and second exit sections 124 and 125 face either the dummy gate trench structure 62 or the second dummy source trench structure 63. In the present embodiment, the first and second sections 124 and 125 face both the dummy gate trench structure 62 and the second dummy source trench structure 63.

[0255] The first and second exit sections 124 and 125 can be oriented towards the dummy gate trench structures 62 and the second dummy source trench structures 63, respectively. The first and second trench sections 124 and 125 are electrically separated from the dummy gate trench structures 62 and the second dummy source trench structures 63, respectively, by means of the first inorganic insulating film 110.

[0256] In the present embodiment, the first and second output sections 124 and 125 are arranged at a distance from the side of the first dummy structure 60A to the side of the second dummy structure 60B. Therefore, the first and second output sections 124 and 125 do not face the first dummy source trench structures 61, with the first inorganic insulating film 110 located between the first dummy source trench structures 61 and the first and second output sections 124 and 125. The first and second output sections 124 and 125 are electrically isolated from the first dummy source trench structures 61 by the first inorganic insulating film 110.

[0257] Naturally, the first and second delivery sections 124 and 125 can extend from the side of the second dummy structure 60B to the side of the first dummy structure 60A and face a portion of the first dummy structure 60A, with the first inorganic insulating film 110 located between that portion of the first dummy structure 60A and the first and second delivery sections 124 and 125. In this case, the first and second delivery sections 124 and 125 can face at least one first dummy source trench structure 61, with the first inorganic insulating film 110 located between the first dummy source trench structure 61 and the first and second delivery sections 124 and 125.

[0258] The third lead-out section 126 extends from above the transistor region 20 to a space above the second circumferential region 22 and faces a portion of the second dummy structure 60B, with the first inorganic insulating film 110 located between this portion of the second dummy structure 60B and the third lead-out section 126. The third lead-out section 126 faces either the dummy gate trench 62, the second dummy source trench 63, or both.

[0259] In the present embodiment, the third exit section 126 faces both the dummy gate trench structure 62 and the second dummy source trench structures 63. The third exit section 126 can be oriented towards both the dummy gate trench structures 62 and the second dummy source trench structures 63. The third exit section 126 is electrically separated from both the dummy gate trench structures 62 and the second dummy source trench structures 63 by the first inorganic insulating film 110.

[0260] The third exit section 126 extends from the side of the second dummy structure 60B to the side of the first dummy structure 60A and faces a portion of the first dummy structure 60A, with the first inorganic insulating film 110 located between this portion of the first dummy structure 60A and the third exit section 126. In the present embodiment, the third exit section 126 faces the first dummy source trench structures 61 (in this embodiment, all first dummy source trench structures 61), with the first inorganic insulating film 110 located between the first dummy source trench structures 61 and the third exit section 126. The third exit section 126 is electrically separated from the first dummy source trench structures 61 by the first inorganic insulating film 110.

[0261] The source main surface electrode 122 has a source electrode sidewall 122a (electrode sidewall) arranged on the first inorganic insulating film 110. The source electrode sidewall 122a is conically shaped and inclined obliquely downwards from the main surface of the source main surface electrode 122. The source electrode sidewall 122a can be formed in a curved, tapered (conical) shape that is curved towards the first inorganic insulating film 110.

[0262] The SiC semiconductor device 1 has a wiring electrode 130 formed on the first inorganic insulating film 110. The wiring electrode 130 is guided around an arbitrary region that has a region covering the active area 6 and a region covering the outer area 7 on the first inorganic insulating film 110.

[0263] The wiring electrode 130 has a gate wiring electrode 131 (gate wiring). The gate wiring electrode 131 can also be referred to as a gate finger electrode. The gate wiring electrode 131 extends from the main gate surface electrode 121 to a portion of the first inorganic insulating film 110 covering the active area 6. The gate wiring electrode 131 is located above the active area 6 and not above the outer surface 7. The gate wiring electrode 131 transmits the gate potential applied to the main gate surface electrode 121 to another area.

[0264] The gate wiring electrode 131 extends from the gate main surface electrode 121 to a region between the first to fourth connection surfaces 8A to 8D and the source main surface electrode 122 at a distance from the first to fourth connection surfaces 8A to 8D and from the source main surface electrode 122. The gate wiring electrode 131 is ribbon-shaped and extends along the first to fourth connection surfaces 8A to 8D. More precisely, the gate wiring electrode 131 preferably extends in a ribbon shape along at least two of the first to fourth connection surfaces 8A to 8D, such that it faces the source main surface electrode 122 from several directions in a top view.

[0265] In the present embodiment, the gate wiring electrode 131 faces the source main surface electrode 122 from four directions in a top view. A portion of the gate wiring electrode 131, extending along the four corners of the active surface 6, is bent towards the outer surface 7. Therefore, in this embodiment, the gate wiring electrode 131 extends in a ribbon-like shape, with its four corners bent as a whole in a top view. The gate wiring 131 has an open section on the side of the second connection surface 8B. The position and size of the open section are freely selectable.

[0266] The gate wiring electrode 131 extends from the gate main surface electrode 121 onto the first circumferential region 21 and runs along the first and third connection surfaces 8A and 8C. The gate wiring electrode 131 faces a portion of the first dummy structure 60A and a portion of the second dummy structure 60B on the side of the first circumferential region 21, with the first inorganic insulating film 110 located between these portions and the gate wiring electrode 131.

[0267] More precisely, the gate wiring electrode 131 faces the first dummy source trench structures 61, the dummy gate trench structures 62, and the second dummy source trench structures 63, with the first inorganic insulating film 110 located between these structures and the gate wiring electrode 131. The gate wiring electrode 131 is electrically separated from the first dummy source trench structures 61, the dummy gate trench structures 62, and the second dummy source trench structures 63 by means of the first inorganic insulating film 110.

[0268] The gate wiring electrode 131 extends from the side of the first circumferential region 21 to the side of the transistor region 20 and runs along the third and fourth junction surfaces 8C and 8D. The gate wiring electrode 131 faces a portion of the transistor structure 30 on the side of the transistor region 20, with the first inorganic insulating film 110 located between this portion of the transistor structure 30 and the gate wiring electrode 131. The gate wiring electrode 131 intersects (particularly perpendicularly) the gate trench structures 31 and the first source trench structures 41 in the top view of the transistor region 20.

[0269] More precisely, the gate wiring electrode 131 extends in a direction (second direction Y) that intersects a direction (first direction X) in which the gate trench structures 31 and the first source trench structures 41 extend. In other words, the gate wiring electrode 131 extends in a direction (second direction Y) that intersects (specifically perpendicularly) the mutually facing directions (first direction X) of the gate trench structures 31 and the second source trench structures 51.

[0270] The gate wiring electrode 131 extends such that, in plan view, it traverses an area between the gate trench structure 31 and the second source trench structure 51, intersecting the end section of the gate trench structures 31, the inner section of the first source trench structures 41, and the end section of the second source trench structures 51 (particularly perpendicularly). The gate wiring electrode 131 enters the gate openings 112 from above the first inorganic insulating film 110 and is electrically connected to the gate contact electrodes 91. The gate potential applied to the main gate surface electrode 121 is thus transmitted to the gate trench structures 31 via the gate wiring electrode 131.

[0271] The gate wiring electrode 131 extends from the transistor region 20 into a space above the second circumferential region 22 and runs along the third surface 8C and the second surface 8B. The gate wiring electrode 131 faces a portion of the first dummy structure 60A and a portion of the second dummy structure 60B, with the first inorganic insulating film 110 located between these portions and the gate wiring electrode 131 on the side of the second circumferential region 22.

[0272] More precisely, the gate wiring electrode 131 faces the first dummy source trench structures 61, the dummy gate trench structures 62, and the second dummy source trench structures 63, with the first inorganic insulating film 110 located between these structures and the gate wiring electrode 131. The gate wiring electrode 131 is electrically separated from the first dummy source trench structures 61, the dummy gate trench structures 62, and the second dummy source trench structures 63 by means of the first inorganic insulating film 110.

[0273] The gate wiring electrode 131 has a gate wiring sidewall 131a (wiring sidewall) located on the first inorganic insulating film 110. The gate wiring sidewall 131a has a conical shape that slopes obliquely downwards from the main surface of the gate wiring electrode 131. The gate wiring sidewall 131a can be formed in a curved, tapered (conical) shape that curves towards the first inorganic insulating film 110.

[0274] The wiring electrode 130 has a source wiring electrode 132 (source wiring). The source wiring electrode 132 can be referred to as a source finger electrode. The source wiring electrode 132 transfers the source potential applied to the source main surface electrode 122 to another area. The source wiring electrode 132 extends from the source main surface electrode 122 through the open section of the gate wiring electrode 131 and is brought out onto a portion of the first inorganic insulating film 110 that covers the sidewall wiring 100. The source wiring electrode 132 is ribbon-shaped and extends along the sidewall wiring 100 at a distance from the gate wiring electrode 131 in the top view.

[0275] The source wiring electrode 132 is ribbon-shaped and extends along the first to fourth connection surfaces 8A to 8D. More precisely, the source wiring electrode 132 preferably extends ribbon-shaped along at least two of the first to fourth connection surfaces 8A to 8D, so that it faces the source main surface electrode 122 from several directions in a top view. In the present embodiment, the source wiring electrode 132 is ring-shaped (in particular, rectangular) and extends along the sidewall wiring 100, so that it faces the source main surface electrode 122 from four directions in a top view. In other words, the source wiring electrode 132 surrounds the gate main surface electrode 121, the source main surface electrode 122, and the gate wiring electrode 131 in a top view.

[0276] A portion of the source wiring electrode 132, extending along the four corners of the active surface 6, is curved towards the side of the outer surface 7. In the present embodiment, the source wiring electrode 132 is therefore ring-shaped, with its four corners curved as a whole in plan view. In the present embodiment, the source wiring electrode 132 covers the entire area of ​​the sidewall wiring 100 with the first inorganic insulating film 110 between the sidewall wiring 100 and the source wiring electrode 132.

[0277] Furthermore, the source wiring electrode 132 extends from above the sidewall wiring 100 onto a portion of the outer surface 7 of the first inorganic insulating film 110. More precisely, the source wiring electrode 132 extends onto the outer contact area 80 and, in plan view, forms a band along the outer contact area 80. In the present embodiment, the source wiring electrode 132 is annular (in particular, rectangular) and extends along the outer contact area 80 in plan view. In other words, the source wiring electrode 132 covers the outer contact area 80 and the sidewall wiring 100 over its entire circumference.

[0278] The source wiring electrode 132 enters the side wall opening 114 from above the first inorganic insulating film 110 and is electrically connected to the side wall wiring 100 and the outer contact area 80. In the present embodiment, the source wiring electrode 132 is electrically connected to the side wall wiring 100 and the outer contact area 80 over its entire circumference. The source potential applied to the source main surface electrode 122 is thus transferred to the side wall wiring 100 and the outer contact area 80 via the source wiring electrode 132.

[0279] The source potential of the sidewall wiring 100 is supplied to the first source trench structures 41, the second source trench structures 51, the first dummy source trench structures 61, the dummy gate trench structures 62, and the second dummy source trench structures 63. In other words, the use of the sidewall wiring 100 allows the source wiring electrode 132 to electrically connect the first source trench structure 41 to the source main surface electrode 122 at a different position than the position of the source main surface electrode 122.

[0280] Furthermore, the use of the sidewall wiring 100 makes it possible to electrically connect the source wiring electrode 132 to the second source trench structures 51, the first dummy source trench structures 61, the dummy gate trench structures 62, and the second dummy source trench structures 63, which are electrically isolated from the source main surface electrode 122 in the active area 6, from the side of the first to fourth connection surfaces 8A to 8D to the source main surface electrode 122. In other words, according to the sidewall wiring 100, any trench structure that is electrically isolated from the first main surface electrode 120 in the active area 6 is electrically connected to the first main surface electrode 120 in an area (first to fourth connection surfaces 8A to 8D) outside the active area 6.

[0281] The source wiring electrode 132 has a source wiring sidewall 132a (wiring sidewall) arranged on the first inorganic insulating film 110. The source wiring sidewall 132a is conically shaped and inclined obliquely downwards from the main surface of the source main surface electrode 122. The source wiring sidewall 132a can be formed in a curved, tapered (conical) shape that is curved towards the first inorganic insulating film 110.

[0282] The first main surface electrode 120 and the wiring electrode 130 each have a layered structure comprising a first electrode film 141 and a second electrode film 142, which are layered in that order from the side of the first inorganic insulating film 110. The first electrode film 141 is formed as a film along the first inorganic insulating film 110. The first electrode layer 141 is a metallic barrier film. In the present embodiment, the first electrode film 141 is a titanium-based metal film.

[0283] The first electrode film 141 comprises at least one titanium film or one titanium nitride film. The first electrode film 141 can have a single-layer structure formed from either a titanium film or a titanium nitride film. In the present embodiment, the first electrode film 141 has a layered structure comprising a titanium film and a titanium nitride film, layered in that order from the side of the first main surface 3. The thickness of the first electrode film 141 is preferably not less than 10 nm and not more than 500 nm.

[0284] The second electrode film 142 is formed in a film-like form along the first electrode film 141. The first electrode film 141 is a copper-based metal film or an aluminum-based metal film. The first electrode film 141 can comprise at least one of the following: a pure copper film (a copper film with a purity of 99% or more), a pure aluminum film (an aluminum film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In the present embodiment, the first electrode film 141 has a single-layer structure, which is an AlCu alloy film. The thickness of the second electrode film 142 is preferably not less than 0.5 µm and not more than 10 µm. Preferably, the thickness of the second electrode film 142 is not less than 2.5 µm and not more than 7.5 µm.

[0285] The SiC semiconductor device 1 has a second inorganic insulating film 150. The second inorganic insulating film 150 is made of an inorganic insulator with a comparatively high density and has a barrier property (shielding capacity) against water (moisture). In the present embodiment, for example, an oxide of the first main surface electrode 120 (in this case, aluminum oxide) degrades the electrical properties of the first main surface electrode 120. Furthermore, the oxide of the first main surface electrode 120 becomes a factor that, due to thermal expansion, leads to partial detachment, cracking, etc., of the first main surface electrode 120 or other structures.

[0286] The second inorganic insulating film 150 shields against external water (moisture) and protects the SiC chip 2 or the first main surface electrode 120 from oxidation by covering either the first inorganic insulating film 110 or the first main surface electrode 120, or both. The second inorganic insulating film 150 can also be referred to as a passivation film.

[0287] The second inorganic insulating film 150 can have a layered structure with multiple insulating layers or a single-layer structure formed from a single insulating layer. Preferably, the second inorganic insulating film 150 has at least one silicon oxide film, one silicon nitride film, or one silicon oxynitride film. The second inorganic insulating film 150 can have a layered structure comprising a plurality of silicon oxide films, a layered structure comprising a plurality of silicon nitride films, or a layered structure comprising a plurality of silicon oxynitride films.

[0288] The second inorganic insulating film 150 can have a layered structure in which at least two of the following films, silicon oxide film, silicon nitride film, and silicon oxynitride film, are layered in any order. The second inorganic insulating film 150 can have a single-layer structure formed from a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In the present embodiment, the second inorganic insulating film 150 has a single-layer structure formed from a silicon nitride film. In other words, the second inorganic insulating film 150 is an insulator that differs from that of the first inorganic insulating film 110.

[0289] Preferably, the thickness of the second inorganic insulating film 150 is less than the thickness of the first inorganic insulating film 110. The thickness of the second inorganic insulating film 150 can be equal to or greater than the thickness of the first inorganic insulating film 110. Preferably, the thickness of the second inorganic insulating film 150 is greater than the thickness of the first electrode film 141. Preferably, the thickness of the second inorganic insulating film 150 is equal to or less than the thickness of the second electrode film 142. Particularly preferably, the thickness of the second inorganic insulating film 150 is less than the thickness of the second electrode film 142. The thickness of the second inorganic insulating film 150 is preferably not less than 0.05 µm and not more than 5 µm. Preferably, the thickness of the second inorganic insulating film 150 is not less than 0.1 µm and not more than 2 µm.

[0290] Referring to Fig. 23, in the present embodiment, the second inorganic insulating film 150 has several inner cover sections 151 (electrode cover sections), an outer cover section 152 (insulation cover section), and a remote section 153. Each of the inner cover sections 151 covers the first main surface electrode 120 such that the electrode sidewall of the first main surface electrode 120 is exposed. More precisely, the inner cover sections 151 have an inner gate cover section 154, which covers the gate main surface electrode 121, and an inner source cover section 155, which covers the source main surface electrode 122.

[0291] The second inorganic insulating film 150 may comprise only the inner gate cover section 154 and / or the inner source cover section 155 and need not necessarily comprise both the inner gate cover section 154 and the inner source cover section 155 simultaneously. Preferably, the second inorganic insulating film 150 comprises at least the inner source cover section 155, which covers the source main surface electrode 122, the area of ​​which is larger than that of the gate main surface electrode 121.

[0292] The second inorganic insulating film 150 preferably has both the inner gate cover section 154 and the inner source cover section 155. It is also sufficient if the second inorganic insulating film 150 has at least one of the inner sections 151 and the outer section 152; it is not necessary for it to have both the inner sections 151 and the outer section 152. Preferably, the second inorganic insulating film 150 has at least the inner sections 151. Preferably, the second inorganic insulating film 150 has both the inner cover sections 151 and the outer cover section 152.

[0293] The inner gate cover section 154 of the second inorganic insulating film 150 covers the main gate surface electrode 121 such that the gate electrode sidewall 121a is exposed above the active area 6. More precisely, the inner gate cover section 154 covers the main gate surface electrode 121 at a distance from the gate electrode sidewall 121a such that the circumferential edge section of the main gate surface electrode 121 is exposed. The inner section of the main gate surface electrode 121 is also exposed by the inner cover section 154.

[0294] The inner gate cover section 154 is ribbon-shaped and extends along the gate electrode sidewall 121a in plan view. In the present embodiment, the inner gate cover section 154 is ring-shaped and surrounds the inner section of the main gate surface electrode 121 in plan view. More precisely, the inner gate cover section 154 is ring-shaped (in detail: quadrilateral) with four sides that run parallel to the gate electrode sidewall 121a in plan view.

[0295] The inner gate cover section 154 has a first inner wall section 154a on the side of the inner section of the gate main surface electrode 121 and a first outer wall section 154b on the side of the gate electrode side wall 121a. In the present embodiment, the first inner wall section 154a has a quadrilateral shape with four sides that are parallel to the gate electrode side wall 121a in plan view. The first inner wall section 154a has a conical shape that slopes obliquely downwards from the first surface of the second inorganic insulating film 150 towards the inner section of the gate main surface electrode 121. The first inner wall section 154a defines a first gate opening 156 that exposes the inner section of the gate main surface electrode 121.

[0296] The first outer wall section 154b is formed on the gate main surface electrode 121 at a distance from the gate electrode side wall 121a such that the circumferential edge section of the gate main surface electrode 121 is exposed. In the present embodiment, the first outer wall section 154b has a quadrilateral shape with four sides that run parallel to the gate electrode side wall 121a in plan view. The first outer wall section 154b has a conical shape that is inclined obliquely downwards from the surface of the second inorganic insulating film 150 towards the gate electrode side wall 121a of the gate main surface electrode 121.

[0297] The inner source covering section 155 of the second inorganic insulating film 150 covers the source main surface electrode 122 such that the source electrode sidewall 122a is exposed above the active area 6. More precisely, the inner source covering section 155 covers the source main surface electrode 122 at a distance from the source electrode sidewall 122a such that the circumferential edge section of the source main surface electrode 122 is exposed. The inner source covering section 155 also exposes the inner section of the source main surface electrode 122.

[0298] The inner source cover section 155 is ribbon-shaped and extends along the source electrode sidewall 122a in plan view. In the present embodiment, the inner source cover section 155 is annular, surrounding the inner section of the source main surface electrode 122 in plan view. The inner source cover section 155 has a section that is concavely recessed towards the inside of the source main surface electrode 122, so that it coincides with a section that forms the concave portion of the source electrode sidewall 122a in plan view. The inner source cover section 155 is therefore annular (more precisely: polygonal) and has sides parallel to the source electrode sidewall 122a in plan view.

[0299] The inner source cover section 155 has a second inner wall section 155a on the inside of the source main surface electrode 122 and a second outer wall section 155b on the side of the source electrode side wall 122a of the source main surface electrode 122. In the present embodiment, the second inner wall section 155a has a polygonal shape with sides that are parallel to the source electrode side wall 122a in plan view. The second inner wall section 155a has a tapered (conical) shape that slopes obliquely downwards from the main surface of the second inorganic insulating film 150 towards the inner section of the source main surface electrode 122. The second inner wall section 155a defines a first source opening 157 that exposes the inner section of the source main surface electrode 122.

[0300] The second outer wall section 155b is formed on the source main surface electrode 122 at a distance from the source electrode side wall 122a such that the circumferential edge section of the source main surface electrode 122 is exposed. In the present embodiment, the second outer wall section 155b has a polygonal shape with sides that run parallel to the source electrode side wall 122a in plan view. The second outer wall section 155b has a conical shape that is inclined obliquely downwards from the main surface of the second inorganic insulating film 150 towards the source electrode side wall 122a of the source main surface electrode 122.

[0301] The outer covering section 152 of the second inorganic insulating film 150 covers the first inorganic insulating film 110 at a distance from the gate main surface electrode 121 and from the source main surface electrode 122 towards the circumferential side of the first main surface 3, so that the gate electrode sidewall 121a and the source electrode sidewall 122a are exposed. The outer covering section 152 is also formed at a distance from the gate wiring electrode 131 towards the circumferential edge of the first surface 3, such that the gate wiring sidewall 131a is exposed. The outer covering section 152 is also formed at a distance from the source wiring electrode 132 towards the circumferential edge of the first surface 3, such that the source wiring sidewall 132a is exposed.The outer cover section 152 is formed at a distance from the side wall wiring 100 in the direction of the circumferential edge of the first main surface 3.

[0302] The outer cover section 152 is ribbon-shaped and extends along the active surface 6 (first to fourth connection surfaces 8A to 8D) in plan view. In plan view, the outer cover section 152 is ring-shaped around the active surface 6. More precisely, the outer cover section 152 has a quadrilateral, ring-shaped form with four sides that run parallel to the active surface 6 in plan view. In plan view, the outer cover section 152 surrounds the sidewall wiring 100, the gate main surface electrode 121, the source main surface electrode 122, the gate wiring electrode 131, and the source wiring electrode 132.

[0303] The outer cover section 152 faces at least one field area 82A to 82E, with the first inorganic insulating film 110 located between the field area and the outer cover section 152. In the present embodiment, the outer cover section 152 is formed at a distance from the innermost first field area 82A in the direction of the circumferential side of the first main surface 3 in plan view and faces the second to fifth field areas 82B to 82E, with the first inorganic insulating film 110 located between the second to fifth field areas 82B to 82E and the outer cover section 152. Of course, the outer cover section 152 can face all first to fifth field areas 82A to 82E, with the first inorganic insulating film 110 located between the first to fifth field areas 82A to 82E and the outer cover section 152.

[0304] In the present embodiment, the outer cover section 152 extends from above the first inorganic insulating film 110 onto the circumferential edge section of the outer surface 7, which is exposed by the notch opening 111. The first inorganic insulating film 110 (outer cover section 152) defines a dicing street 158 ​​in which the circumferential edge section of the outer surface 7 is exposed between the first inorganic insulating film 110 and the circumferential edge of the first main surface 3. The dicing street 158 ​​has a rectangular, annular shape that extends along the circumferential edge of the first surface 3. The width of the dicing street 158 ​​is preferably not less than 5 µm and not more than 25 µm. The width of the dicing street 158 ​​is a width in a direction perpendicular to the direction in which the dicing street 158 ​​extends.

[0305] The outer cover section 152 has a third inner wall section 152a on the side of the active surface 6 and a third outer wall section 152b on the circumferential side of the first main surface 3. The third inner wall section 152a is formed on the first inorganic insulating film 110 at a distance from the side wall opening 114 such that the first inorganic insulating film 110 is exposed above the outer surface 7. More precisely, the third inner wall section 152a is formed on the first inorganic insulating film 110 at a distance from the source wiring side wall 132a of the source wiring electrode 132 such that the first inorganic insulating film 110 is exposed.

[0306] In the present embodiment, the third inner wall section 152a has a rectangular shape with four sections parallel to the source wiring electrode 132 (source wiring side wall 132a) in the top view. The third inner wall section 152a jointly surrounds the side wall wiring 100, the gate main surface electrode 121, the source main surface electrode 122, the gate wiring electrode 131, and the source wiring electrode 132. The third inner wall section 152a has a conical shape that slopes obliquely downwards from the surface of the second inorganic insulating film 150 towards the first inorganic insulating film 110.

[0307] The third outer wall section 152b is formed in a plan view between the notch opening 111 and the circumferential edge of the outer surface 7, exposing the circumferential edge section of the outer surface 7. The third outer wall section 152b has a conical shape, inclined obliquely downwards from the surface of the second inorganic insulating film 150 towards the outer surface 7. The third outer wall section 152b defines the cutting line 158 between the third outer wall section 152b and the circumferential edge of the outer surface 7.

[0308] The removed section 153 of the second inorganic insulating film 150 is defined between the inner gate cover section 154 (first outer wall section 154b) and the 152 (third inner wall section 152a), between the inner source cover section 155 (second outer wall section 155b) and the outer cover section 152 (third inner wall section 152a) and between the inner gate cover section 154 (first outer wall section 154b) and the inner source cover section 155 (second outer wall section 155b).

[0309] In the present embodiment, the removed section 153 is ribbon-shaped and extends along the first to fourth connection surfaces 8A to 8D, along the first outer wall section 154b, and along the second outer wall section 155b in plan view. In the present embodiment, the removed section 153 has, in plan view, an annular section extending along the first outer wall section 154b and an annular section extending along the second outer wall section 155b (first to fourth connection surfaces 8A to 8D).

[0310] The removed section 153 exposes a height difference section (i.e., first to fourth junction surfaces 8A to 8D) between the active surface 6 and the outer surface 7 over its entire perimeter, and simultaneously exposes the gate electrode sidewall 121a, the source electrode sidewall 122a, the gate wiring sidewall 131a, and the source wiring sidewall 132a over their entire perimeter. In other words, the removed section 153 exposes the entire area of ​​the gate electrode 131, the entire area of ​​the source wiring electrode 132, and the entire area of ​​the sidewall wiring 100 located between the gate wiring electrode 131 and the source wiring electrode 132.

[0311] In the second inorganic insulating film 150, the inner gate cover section 154 is formed on the flat gate main surface electrode 121, and the inner source cover section 155 is formed on the flat source main surface electrode 122. The outer cover section 152 is formed on the flat first inorganic insulating film 110. Therefore, height differences in the second inorganic insulating film 150 caused by the sidewall wiring 100, the gate main surface electrode 121, the source main surface electrode 122, the gate wiring electrode 131, and the source wiring electrode 132 are eliminated by the remote section 153.

[0312] The SiC semiconductor device 1 has an organic insulating film 160 that selectively covers the first inorganic insulating film 110, the second inorganic insulating film 150, and the first main surface electrode 120. The organic insulating film 160 has a lower hardness than the second inorganic insulating film 150. In other words, the organic insulating film 160 has a lower modulus of elasticity than the second inorganic insulating film 150 and acts as a damping material (protective film) against external forces. The organic insulating film 160 protects the SiC chip 2, the first main surface electrode 120, the second inorganic insulating film 150, and so on, from external forces.

[0313] Preferably, the organic insulating film 160 comprises a photosensitive resin. The photosensitive resin can be of a negative or a positive type. The organic insulating film 160 can comprise at least one of the following films: a polyimide film, a polyamide film, or a polybenzoxazole film. In the present embodiment, the organic insulating film 160 comprises a polyimide film.

[0314] The thickness of the organic insulating film 160 is preferably not less than 1 µm and not more than 50 µm. Preferably, the thickness of the organic insulating film 160 is not less than 5 µm and not more than 20 µm. Preferably, the thickness of the organic insulating film 160 is greater than the thickness of the second inorganic insulating film 150. Particularly preferably, the thickness of the organic insulating film 160 is greater than the thickness of the first main surface electrode 120.

[0315] The organic insulating film 160 covers the gate electrode sidewall 121a of the main gate surface electrode 121 above the active area 6. More precisely, the organic insulating film 160 covers the gate electrode sidewall 121a over the entire circumference of the main gate surface electrode 121. The organic insulating film 160 covers the first electrode film 141 and the second electrode film 142 in the gate electrode sidewall 121a. The organic insulating film 160 covers the edge region of the main gate surface electrode 121.

[0316] In other words, the organic insulating film 160 extends from the gate electrode sidewall 121a towards the inner gate cover section 154 and covers the circumferential edge section of the gate main surface electrode 121 that is exposed between the gate electrode sidewall 121a and the inner gate cover section 154. Furthermore, the organic insulating film 160 extends from the circumferential edge section of the gate main surface electrode 121 onto the inner gate cover section 154 and covers the inner gate cover section 154.

[0317] The organic insulating film 160 covers the inner cover section 154 of the gate such that the inner section of the gate's main surface electrode 121 is exposed. More precisely, the organic insulating film 160 covers the inner gate cover section 154 such that the first inner wall section 154a of the inner gate cover section 154 is exposed. More precisely, the organic insulating film 160 covers the inner gate cover section 154 at a distance from the first inner wall section 154a to the side of the first outer wall section 154b, thus exposing the inner section of the gate's main surface electrode 121 and the edge section of the inner gate cover section 154.

[0318] The organic insulating film 160 covers the source electrode sidewall 122a of the source main surface electrode 122 above the active area 6. More precisely, the organic insulating film 160 covers the source electrode sidewall 122a over the entire circumference of the source main surface electrode 122. The organic insulating film 160 covers the first electrode film 141 and the second electrode film 142 at the source electrode sidewall 122a. The organic insulating film 160 covers the edge region of the source main surface electrode 122.

[0319] In other words, the organic insulating film 160 extends from the source electrode sidewall 122a towards the side of the inner source cover section 155 and covers the circumferential edge section of the source main surface electrode 122 that is exposed between the source electrode sidewall 122a and the inner source cover section 155. Furthermore, the organic insulating film 160 extends from the circumferential edge section of the source main surface electrode 122 onto the inner source cover section 155 and covers the inner source cover section 155.

[0320] The organic insulating film 160 covers the inner source cover section 155 such that the inner section of the source main surface electrode 122 is exposed. More precisely, the organic insulating film 160 covers the inner source cover section 155 such that the second inner wall section 155a of the inner source cover section 155 is exposed. More precisely, the organic insulating film 160 covers the inner source cover section 155 at a distance from the second inner wall section 155a to the side of the second outer wall section 155b, thus exposing the inner section of the source main surface electrode 122 and the edge section of the inner source cover section 155.

[0321] The organic insulating film 160 covers the gate wiring sidewall 131a of the gate wiring electrode 131 above the active area 6. More precisely, the organic insulating film 160 covers the gate wiring sidewall 131a over the entire circumference of the gate wiring electrode 131. The organic insulating film 160 covers the first electrode film 141 and the second electrode film 142 in the gate wiring sidewall 131a. The organic insulating film 160 extends from the gate wiring sidewall 131a onto the gate wiring electrode 131 and covers the entire surface of the gate wiring electrode 131.

[0322] The organic insulating film 160 covers the sidewall wiring 100 in an area between the active surface 6 and the outer surface 7, including the source wiring electrode 132 and the first inorganic insulating film 110 between the sidewall wiring 100 and the organic insulating film 160. The organic insulating film 160 covers the source wiring sidewall 132a over the entire circumference of the source wiring electrode 132. The organic insulating film 160 covers the first electrode film 141 and the second electrode film 142 at the source wiring sidewall 132a. The organic insulating film 160 extends from the source wiring sidewall 132a onto the source wiring electrode 132 and covers the entire surface of the source wiring electrode 132.In other words, the organic insulating film 160 covers the entire area of ​​the side wall wiring 100 with the source wiring electrode 132 and the first inorganic insulating film 110 between the side wall wiring 100 and the organic insulating film 160.

[0323] The organic insulating film 160 extends from above the source wiring electrode 132 onto the outer cover section 152 of the second inorganic insulating film 150 and covers the outer cover section 152. The organic insulating film 160 covers the outer cover section 152 in such a way that the circumferential edge section of the outer surface 7 is exposed. More precisely, the organic insulating film 160 covers the outer cover section 152 in such a way that the third outer wall section 152b of the outer cover section 152 is exposed. More precisely, the organic insulating film 160 covers the outer cover section 152 at a distance from the third outer wall section 152b in the direction of the side of the third inner wall section 152a and exposes the circumferential edge section of the outer surface 7 and the circumferential edge section of the outer cover section 152 in plan view.

[0324] The organic insulating film 160 has a fourth inner wall section 160a on the side of the gate main surface electrode 121. The fourth inner wall section 160a extends along the first inner wall section 154a (first gate opening 156) of the inner gate cover section 154. In the present embodiment, the fourth inner wall section 160a has a quadrilateral shape with four sides that run parallel to the first inner wall section 154a in plan view.

[0325] More precisely, the fourth inner wall section 160a is formed on the inner gate cover section 154 at a distance from the first inner wall section 154a towards the side of the first outer wall section 154b and exposes the inner section of the gate main surface electrode 121 and the edge section of the inner gate cover section 154. In other words, a second gate opening 161 exposes the inner section of the gate main surface electrode 121 and the inner gate cover section 154. The fourth inner wall section 160a defines the second gate opening 161, which exposes the inner section of the gate main surface electrode 121.

[0326] The fourth inner wall section 160a (second gate opening 161) is connected to the first inner wall section 154a (first gate opening 156) and together they form a single gate opening 162. The fourth inner wall section 160a (second gate opening 161) has a conical shape, inclined obliquely downwards from the surface of the organic insulating film 160 towards the first inner wall section 154a. In the present embodiment, the fourth inner wall section 160a is formed in a curved, tapered shape, curved towards the inner gate cover section 154.

[0327] The organic insulating film 160 has a fifth inner wall section 160b on the side of the source main surface electrode 122. The fifth inner wall section 160b extends along the second inner wall section 155a of the inner source cover section 155 (first source opening 157). In the present embodiment, the fifth inner wall section 160b has a polygonal shape with sides that, in plan view, run parallel to the second inner wall section 155a of the inner source cover section 155.

[0328] More precisely, the fifth inner wall section 160b is formed on the inner source cover section 155 at a distance from the second inner wall section 155a of the inner source cover section 155 in the direction of the side of the second outer wall section 155b and exposes the inner section of the source main surface electrode 122 and the edge section of the inner source cover section 155. In other words, a second source opening 163 exposes the inner section of the source main surface electrode 122 and the edge section of the inner source cover section 155. The fifth inner wall section 160b defines the second source opening 163, which exposes the inner section of the source main surface electrode 122.

[0329] The fifth inner wall section 160b (second source opening 163) is connected to the second inner wall section 155a of the inner source cover section 155 (first source opening 157) and forms a single source pad opening 164 with the second inner wall section 155a (first source opening 157). The fifth inner wall section 160b (second source opening 163) has a conical shape that is inclined obliquely downwards from the surface of the organic insulating film 160 towards the second inner wall section 155a. In the present embodiment, the fifth inner wall section 160b is formed in a curved, tapered shape that is bent towards the inner source cover section 155.

[0330] The organic insulating film 160 has a fourth outer wall section 160c. The fourth outer wall section 160c is formed at a distance from the circumferential edge section of the outer surface 7 (first to fourth side surfaces 5A to 5D) in the direction of the side of the outer cover section 152, so that the circumferential edge section of the outer surface 7 is exposed. More precisely, the fourth outer wall section 160c is formed on the third outer wall section 152b in such a way that it exposes the third outer wall section 152b of the outer cover section 152.

[0331] In the present embodiment, the fourth outer wall section 160c has a quadrilateral shape with four sides that run parallel to the active surface 6 in plan view. The fourth outer wall section 160c has a tapered shape that slopes obliquely downwards from the main surface of the organic insulating film 160 towards the third outer wall section 152b of the outer cover section 152. In the present embodiment, the fourth outer wall section 160c is formed in a curved, tapered shape that curves towards the outer cover section 152. The fourth outer wall section 160c, together with the third outer wall section 152b, defines the cutting line 158.

[0332] The organic insulating film 160 thus covers the edge section of the gate main surface electrode 121, the edge section of the source main surface electrode 122, the entire area of ​​the gate wiring electrode 131, and the inner covering sections 151 of the second inorganic insulating film 150 over the active area 6. The organic insulating film 160 covers parts that are exposed by the gate main surface electrode 121, the gate wiring electrode 131, the source main surface electrode 122, and the source wiring electrode 132 of the first inorganic insulating film 110 on the active area 6.

[0333] The organic insulating film 160 covers the entire surface of the source wiring electrode 132 (sidewall wiring 100) between the active surface 6 and the outer surface 7. The organic insulating film 160 covers the outer cover section 152 of the second inorganic insulating film 150. The organic insulating film 160 covers the parts of the first inorganic insulating film 110 on the outer surface 7 that are exposed by the source wiring electrode 132 and the second inorganic insulating film 150.

[0334] Furthermore, the organic insulating film 160 is shaped such that it spans the inner cover sections 151 and the outer cover section 152 of the second inorganic insulating film 150 and covers the entire area of ​​the source wiring electrode 132 (sidewall wiring 100), the entire area of ​​the gate wiring electrode 131, the edge section of the gate main surface electrode 121 and the edge section of the source main surface electrode 122 in the remote section 153 between the inner cover sections 151 and the outer cover section 152.

[0335] In other words, the organic insulating film 160 fills a gap formed by the first inorganic insulating film 110, the source wiring electrode 132 (sidewall wiring 100), the second inorganic insulating film 150, the gate main surface electrode 121, the source main surface electrode 122, the gate wiring electrode 131, and the source wiring electrode 132 in the remote section 153. The sidewall wiring 100 reduces the height difference of a portion of the organic insulating film 160 located in the remote section 153.

[0336] The SiC semiconductor device 1 has a second main surface electrode 170 that covers the second surface 4. The second main surface electrode 170 can be referred to as the drain electrode. The second main surface electrode 170 covers the entire area of ​​the second main surface 4 and is connected to the circumferential edge of the first main surface 3 (first to fourth side faces 5A to 5D). The second main surface electrode 170 is electrically connected to the first semiconductor area 10 (second main surface 4). More precisely, the second main surface electrode 170 forms an ohmic contact with the first semiconductor area 10 (second main surface 4).

[0337] In the present embodiment, the second main surface electrode 170 has at least one of the following films: a titanium film, a nickel film, a palladium film, an aubergine film, and an argentine film. The second main surface electrode 170 may have at least one titanium film, and the presence or absence of a nickel film, a palladium film, an aubergine film, and an argentine film is arbitrary, as is the order in which these films are layered. For example, the second main surface electrode 170 may have a titanium film, a nickel film, a palladium film, and an aubergine film layered in that order from the side of the second main surface 4. In another example, the second main surface electrode 170 may have a layered structure containing a titanium film, a nickel film, and an aubergine film.

[0338] Fig. 29A to Fig. 29V are cross-sectional views that illustrate an example of a manufacturing process of the in Fig. 1 shows the SiC semiconductor device 1. Referring to Fig. In step 29A, a SiC wafer 201 (wafer / semiconductor wafer) is prepared, which serves as the basis of the first semiconductor region 10. Next, crystal growth of the semiconductor crystal (SiC in the present embodiment) is carried out on a surface of the SiC wafer 201 by an epitaxial growth process. Therefore, the third semiconductor region 14 with a predetermined n-like impurity concentration and the second semiconductor region 11 with a predetermined n-like impurity concentration are formed on the SiC wafer 201 in that order. In the present embodiment, the third semiconductor region 14 and the second semiconductor region 11 each consist of a SiC epitaxial layer.

[0339] A wafer structure comprising the first semiconductor region 10 (SiC wafer 201), the third semiconductor region 14 (SiC epitaxial layer), and the second semiconductor region 11 (SiC epitaxial layer) is hereinafter referred to as SiC epi-wafer 202. SiC epi-wafer 202 has a first surface 203 on one side and a second surface 204 on the other. The first wafer main surface 203 and the second wafer main surface 204 correspond to the first main surface 3 and the second main surface 4, respectively, of SiC chip 2.

[0340] Subsequently, a multitude of component areas 205 and the designated cutting lines 206, which define the component areas 205, are embedded in the first main wafer surface 203. The component areas 205 are arranged in a matrix, e.g., with gaps between them in the first directions X and the second directions Y in the top view. The designated cutting lines 206 are formed in a grid-like manner according to the arrangement of the component areas 205 in the top view. Fig. 29A shows part of the component area 205, and the intended cutting line 206 is shown by an alternating long and short dashed line (the same applies to Fig. 29B to Fig. 29V).

[0341] Next, with reference to Fig. Figure 29B shows the p-type body region 23 and the n-type source region 24 (not shown) being formed on the surface layer section of the first wafer main surface 203. The body region 23 is formed over the entire area of ​​the surface layer section of the first wafer main surface 203 in this step. The body region 23 is formed by introducing a p-type impurity into the first wafer main surface 203. The source region 24 is formed over the entire area of ​​the surface layer section of the first wafer main surface 203 in this step. The source region 24 is formed by introducing an n-type impurity into the first wafer main surface 203. The source region 24 can be formed before the body region 23 formation step, although it is preferable to perform the source region 24 after the body region 23 formation step.

[0342] Next, as in Fig. As shown in Figure 29C, a hard mask 207 is formed on the first main wafer surface 203. The hard mask 207 can contain silicon oxide. The hard mask 207 can be produced by a CVD (chemical vapor deposition) process or a thermal oxidation process. In this step, the hard mask 207 is formed by the thermal oxidation process.

[0343] Next, as in Fig. As shown in Figure 29D, a first resist mask 208 with a predefined pattern is formed on the hard mask 207. The first resist mask 208 exposes areas where a plurality of gate trenches 209, a plurality of source trenches 210, and the outer surface 7 are to be formed, and covers areas other than these. Gate trench 32 of the gate trench structures 31 and gate trench 32 of the dummy gate trench structures 62 are contained within the gate trenches 209 (the same applies hereafter). Source trench 42 of the first source trench structures 41, source trench 42 of the second source trench structures 51, source trench 42 of the first dummy source trench structures 61 and source trench 42 of the second dummy source trench structures 63 are contained in source trenches 210 (hereinafter: the same applies).

[0344] Subsequently, unnecessary sections of the hard mask 207 are removed through the first resist mask 208 by an etching process (e.g., dry etching). This creates exposure patterns on the hard mask 207 corresponding to the gate trenches 209, the source trenches 210, and the outer surface 7. The first resist mask 208 is then removed.

[0345] Next, as in Fig. As shown in Figure 29E, unnecessary sections of the SiC epi-wafer 202 are removed by the etching process (e.g., dry etching) through the hard mask 207. In this step, the unneeded sections of the second semiconductor region 11 are removed. The gate grooves 209, the source grooves 210, and the outer surface 7 are thus formed on the first main wafer surface 203. The active mesa 9 is also formed on the first main wafer surface 203. The active mesa 9 comprises the active surface 6, the outer surface 7, and the first to fourth interconnect surfaces 8A to 8D.

[0346] Next, as in Fig. As shown in Figure 29F, a second resist mask 211 with a predefined pattern is formed on the hard mask 207. The second resist mask 211 covers each of the gate trenches 209 in such a way that it fills the gate trenches 209 and exposes the source trenches 210 and the outer surface 7.

[0347] In other words, the second resist mask 211 exposes all source trenches 42 of the first dummy source trench structures 61 (i.e., the entire area of ​​the first dummy structure 60A) and all second dummy source trench structures 63 (i.e., a portion of the second dummy structure 60B). The first dummy structure 60A and the second dummy structure 60B (especially the first dummy structure 60A) restrain the inclination of the second resist mask 211 caused by a height difference between the active surface 6 and the outer surface 7 in the circumferential boundary section of the active surface 6, and protect the transistor structure 30 from a defect in shape caused by the inclination of the second resist mask 211.

[0348] Next, as in Fig. As shown in Figure 29G, unnecessary sections of the SiC epi-wafer 202 are removed by the etching process through the second resist mask 211. Preferably, the etching process is an anisotropic dry etching process (e.g., the RIE (Reactive Ion Etching) process). In this step, the unneeded sections of the second semiconductor region 11 are removed. Therefore, the source trenches 210 and the outer surface 7 are further excavated downwards in the thickness direction (towards the side of the second wafer main surface (204)) of the SiC epi-wafer 202. The second resist mask 211 is then removed.

[0349] Next, as in Fig. Figure 29H shows the hard mask 207 removed by the etching process. The etching process can be a wet etching process and / or a dry etching process.

[0350] Next, as in Fig. As shown in Figure 29I, a third resist mask 212 with a predetermined pattern is formed on the first wafer main surface 203. The third resist mask 212 exposes areas where a multitude of trough regions 213 are to be formed and covers other areas. The trough regions 213 comprise trough region 71, gate trough region 72, dummy trough region 74, dummy gate trough region 75, and outer trough region 81. Subsequently, a p-like impurity is introduced into the surface layer portion of the first wafer main surface 203 through the third resist mask 212. Thus, the trough regions 213 are formed in the surface layer portion of the first wafer main surface 203. Afterward, the third resist mask 212 is removed.

[0351] Next, as in Fig. As shown in Figure 29J, a fourth resist mask 214 with a predetermined pattern is formed on the first wafer main surface 203. The fourth resist mask 214 exposes areas where field regions 82A to 82E are to be formed and covers other areas. Subsequently, a p-type impurity is introduced into the surface layer section of the first wafer main surface 203 through the fourth resist mask 214. Thus, field regions 82A to 82E are formed on the surface layer section of the first wafer main surface 203. Afterward, the fourth resist mask 214 is removed.

[0352] Next, as in Fig. As shown in Figure 29K, a fifth resist mask 215 with a predetermined pattern is formed on the first wafer main surface 203. The fifth resist mask 215 exposes areas where contact areas 216 are to be formed and covers other areas. The contact areas 216 include contact areas 70, dummy contact areas 73, and the outer contact area 80.

[0353] More precisely, the fifth resist mask 215 covers the gate trenches 209 in such a way that it fills the gate trenches 209. Furthermore, the fifth resist mask 215 covers the first dummy source trench structures 61 in such a way that it fills the source trenches 42 of the first dummy source trench structures 61. Additionally, the fifth resist mask 215 exposes the source trenches 42 of the first source trench structures 41, the source trenches 42 of the second source trench structures 51, the source trenches 42 of the second dummy source trench structures 63, and a portion of the outer area 7.

[0354] The fifth resist mask 215 covers all (the entire area of ​​the first dummy structure 60A) of the first dummy source trench structures 61. The first dummy structure 60A and the second dummy structure 60B (especially the second dummy structure 60B) restrain the inclination of the fifth resist mask 215 caused by a height difference between the active surface 6 and the outer surface 7 in the circumferential boundary section of the active surface 6, and protect the transistor structure 30 from a defect upon introduction of a p-type impurity caused by the inclination of the fifth resist mask 215.

[0355] Subsequently, a p-type impurity is introduced into the surface layer section of the first wafer main surface 203 through the fifth resist mask 215. The contact areas 216 are thus formed on the surface layer section of the first wafer main surface 203. The fifth resist mask 215 is then removed.

[0356] Next, with reference to Fig. In step 29L, a base insulating film 217 is formed, covering the first main surface of the wafer 203. The base insulating film 217 serves as the base of the gate insulating film 33, the source insulating film 43, and the main surface insulating film 90. The base insulating film 217 can be produced by the CVD (chemical vapor deposition) process or by thermal oxidation. In this step, the base insulating film 217 is formed by the thermal oxidation process. In other words, the base insulating film 217 has an oxide film formed from an oxide of the SiC epi-wafer 202.

[0357] In this step, a portion of the base insulating film 217 covering the side wall of the gate trench 209 and a portion of the base insulating film 217 covering the side wall of the source insulating film 210 are formed thinner than the other portions. Additionally, in this step, a portion of the base insulating film 217 covering the opening edge section of the gate trench 209 and a portion of the base insulating film 217 covering the opening edge section of the source trench 210 are formed thicker than the other portions.

[0358] Next, as in Fig. Figure 29M shows a first base electrode film 218 being formed on the first wafer main surface 203. The first base electrode film 218 serves as the base for the gate electrodes 34, the source electrodes 44, the gate contact electrodes 91, and the sidewall wiring 100. The first base electrode film 218 fills the gate grooves 209 and the source grooves 210 and covers the first wafer main surface 203 (active area 6, outer surface 7, and first to fourth interconnect surfaces 8A to 8D). In this step, the first base electrode film 218 has a polysilicon film. The first base electrode film 218 can be produced by CVD. Preferably, the CVD process is a low-pressure CVD (LP) process.

[0359] Next, with reference to Fig. 29N A sixth resist mask 219 with a predetermined pattern is formed on the first base electrode film 218. The sixth resist mask 219 covers the areas where the gate contact electrodes 91 and the sidewall wiring 100 are to be formed and exposes areas other than these. Subsequently, superfluous sections of the first base electrode film 218 are removed by the etching process through the sixth resist mask 219. The etching process can be a wet etching process and / or a dry etching process. The superfluous sections of the first base electrode film 218 are removed until the base insulating film 217 is exposed.

[0360] This process creates the gate electrodes 34, the source electrodes 44, the gate contact electrodes 91, and the sidewall wiring 100. Additionally, the gate trench structures 31, the first source trench structures 41, the second source trench structures 51, the first dummy source trench structures 61, the dummy gate trench structures 62, and the second dummy source trench structures 63 are formed. Then, the sixth resist mask 219 is removed.

[0361] Next, the first inorganic insulating film 110 is formed on the first main wafer surface 203 (see figure). Fig. 29O). The first inorganic insulating film 110 covers the gate trench structures 31, the first source trench structures 41, the second source trench structures 51, the first dummy source trench structures 61, the dummy gate trench structures 62, the second dummy source trench structures 63, and the sidewall wiring 100 on the first wafer main surface 203. In the present embodiment, the first inorganic insulating film 110 is formed from a silicon oxide film. The first inorganic insulating film 110 can be produced by the CVD process.

[0362] Next, with reference to Fig. 29P forms a seventh resist mask 220 with a predefined pattern on the first inorganic insulating film 110. The seventh resist mask 220 exposes areas where the notch opening 111, the gate openings 112, the source openings 113 and the sidewall opening 114 are to be formed, and covers other areas.

[0363] Subsequently, unnecessary sections of the first inorganic insulating film 110 and unnecessary sections of the base insulating film 217 are removed by the etching process through the sixth resist mask 219. The etching process can be wet etching and / or dry etching. This forms the notch opening 111, the gate openings 112, the source openings 113, and the sidewall opening 114 in the first inorganic insulating film 110.

[0364] Referring to Fig. 29Q next forms a second base electrode film 221, which serves as the base of the first main surface electrode 120, on the first wafer main surface 203. The second base electrode film 221 covers the entire area of ​​the first inorganic insulating film 110 on the first wafer main surface 203. The second base electrode film 221 has a layered structure, comprising the first electrode film 141 and the second electrode film 142, which are layered in that order from the side of the first wafer main surface 203.

[0365] In the present embodiment, the first electrode film 141 is made of a titanium-based metal film. In the present embodiment, the second electrode film 142 is made of an aluminum-based metal film. The first electrode film 141 and the second electrode film 142 can be produced by at least one of the processes of sputtering, vapor deposition, and plating. In the present embodiment, the first electrode film 141 and the second electrode film 142 are each produced by the sputtering process.

[0366] Next, with regard to Fig. 29R, an eighth resist mask 222 with a predefined pattern is formed on the second base electrode film 221. The eighth resist mask 222 covers areas where the first main surface electrode 120 (gate main surface electrode 121 and source main surface electrode 122) and the wiring electrode 130 (gate wiring electrode 131 and source wiring electrode 132) are located in the second base electrode film 221, and has an opening that exposes areas other than these.

[0367] Subsequently, superfluous sections of the second base electrode film 221 are removed by etching through the eighth resist mask 222. The etching process can be wet etching and / or dry etching. In this way, the first main surface electrode 120 and the wiring electrode 130 are formed. The eighth resist mask 222 is then removed.

[0368] Next, the second inorganic insulating film 150 is formed on the first wafer main surface 203 such that it covers the first inorganic insulating film 110 and the first main surface electrode 120 (see Fig. 29S). In the present embodiment, the second inorganic insulating film 150 is formed from a silicon nitride film. The second inorganic insulating film 150 is produced by the CVD process.

[0369] Next, with reference to Fig. 29T a ninth resist mask 223 with a predefined pattern is formed on the second inorganic insulating film 150. The ninth resist mask 223 covers a part of the second inorganic insulating film 150, which serves as inner cover section 151 and outer cover section 152, and exposes a part of the second inorganic insulating film 150, which serves as remote section 153 and cutting section 158.

[0370] Subsequently, superfluous sections of the second inorganic insulating film 150 are removed by the etching process through the ninth resist mask 223. The etching process can be wet etching and / or dry etching. In this way, the second inorganic insulating film 150 is created with the inner cover sections 151, the outer cover section 152, and the removed section 153. The outer cover section 152 of the second inorganic insulating film 150 defines the cutting path 158, which exposes the intended cutting lines 206 on the first wafer surface 203. The ninth resist mask 223 is then removed.

[0371] Referring to Fig. In the next step, the organic insulating film 160 is formed on the first main surface electrode 203 such that it covers the first main surface electrode 120, the first inorganic insulating film 110, and the second inorganic insulating film 150. The organic insulating film 160 is formed by applying a photosensitive resin to the first wafer main surface 203. In the present embodiment, the organic insulating film 160 is a polyimide film.

[0372] Next, the organic insulating film 160 will be applied according to… Fig. The 29V is exposed with a pattern corresponding to the second gate aperture 161, the second source aperture 163, and the cutting line 158, and then developed. This forms the second gate aperture 161, the second source aperture 163, and the cutting line 158 in the organic insulating film 160.

[0373] The SiC epi-wafer 202 is then brought to the desired thickness by grinding the second surface 204. This grinding step can be performed using a CMP (Chemical Mechanical Polishing) process. This creates grinding marks on the second main wafer surface 204. The grinding step of the second main wafer surface 204 is not strictly necessary and can be omitted if required.

[0374] However, the thinning of the first semiconductor area 10 leads to a reduction in the resistance value of the SiC chip 2. The second wafer main surface 204 can be subjected to an annealing treatment after grinding. The annealing treatment can be carried out using a laser irradiation process. This transforms the second wafer main surface 204 (second main surface 4) into an ohmic surface with grinding marks and laser irradiation marks.

[0375] The second main surface electrode 170 is then formed on the second wafer main surface 204. The second main surface electrode 170 forms an ohmic contact with the second wafer main surface 204. The second main surface electrode 170 can have at least one of the following films: a Ti film, a Ni film, a Pd film, an Au film, and an Ag film. The Ti film, the Ni film, the Pd film, the Au film, and the Ag film can be formed by at least one of the methods of sputtering, evaporation, and coating (sputtering in the present embodiment).

[0376] The SiC epi-wafer 202 is then cut along the designated cutting lines 206. The cutting step of the SiC epi-wafer 202 can include a cutting step using a dicing blade. In this case, the SiC epi-wafer 202 is cut along the designated cutting lines 206, which are defined by the cutting paths 158. Preferably, the dicing blade has a blade width that is less than the width of the cutting path 158. The first inorganic insulating film 110, the second inorganic insulating film 150, and the organic insulating film 160 are not positioned at the designated cutting lines 206 and thus escape being cut by the cutting blade.

[0377] The cutting step of the SiC epi-wafer 202 can include a slitting step using a laser beam method. In this case, a laser beam from a laser beam device (not shown) is directed onto the cutting path 158 at the SiC epi-wafer 202. Preferably, the laser beam is directed onto the SiC epi-wafer 202 in pulses from the side of the first main wafer surface 203 that does not have the second main surface electrode 170. A converging section (focal point) of the laser beam is directed onto the interior of the SiC epi-wafer 202 (half the section in the thickness direction), and the radiation position of the laser beam is moved along the cutting path 158 (more precisely, along the intended cutting lines 206).

[0378] Thus, a modified layer is formed within (inside) the SiC epi-wafer 202, which extends in a lattice-like pattern along the cutting line 158 in a top view. Preferably, the modified layer is formed at a distance from the first main wafer surface 203 within the SiC epi-wafer 202. Preferably, the modified layer is formed on a portion within the SiC epi-wafer that is formed from the first semiconductor region 10 (SiC wafer 201). Particularly preferably, the modified layer is formed in the first semiconductor region 10 (SiC wafer 201) at a distance from the second semiconductor region 11 (SiC epitaxial layer). Preferably, the modified layer is not formed in the second semiconductor region 11 (SiC epitaxial layer).

[0379] After the modified layer is formed, an external force is applied to the SiC epi-wafer 202, and the SiC epi-wafer 202 is cleaved, with the modified layer serving as the starting point. Preferably, the external force is applied to the SiC epi-wafer 202 from the side of the second main wafer surface 204. The second main surface electrode 170 is cleaved simultaneously with the cleavage of the SiC epi-wafer 202. The first inorganic insulating film 110, the second inorganic insulating film 150, and the organic insulating film 160 are not positioned at the designated cutting lines 206 and thus escape cleavage. The SiC semiconductor device 1 is fabricated in a process comprising the steps described above.

[0380] Fig. 30 corresponds to Fig. Figure 5 is a top view showing a SiC semiconductor device 301 according to a first preferred reference embodiment. Referring to Fig. 30 The SiC semiconductor device 301 according to the first preferred reference embodiment has the transistor structure 30 over the entire area of ​​the active area 6 and does not have the first dummy structure 60A and the second dummy structure 60B.

[0381] In other words, in the SiC semiconductor device 301, the transistor structure 30 with the gate trench structures 31, the first source trench structures 41, and the second source trench structures 51 is also formed at the circumferential edge of the active area 6 (first and second circumferential regions 21 and 22). Other structures of the SiC semiconductor device 301 according to the first preferred reference embodiment are essentially the same as those of the SiC semiconductor device 1. Therefore, a description of the other structures of the SiC semiconductor device 301 is omitted.

[0382] Fig. 31A to Fig. Figure 31D are cross-sectional views showing an example of a fabrication process for the SiC semiconductor device 301 according to the first preferred reference embodiment. Fig. 31A to Fig. Figure 31D shows a cross-section of the circumferential edge section of the active area 6 (first circumferential area 21).

[0383] Referring to Fig. 31A, according to the manufacturing process of the SiC semiconductor device 301, the second resist mask 211 with a predetermined pattern on the hard mask 207 (see also Fig. 29F) is formed in a step in which the source trenches 210 and the outer surface 7 are excavated. The second resist mask 211 covers each of the gate trenches 209 in such a way that it fills the gate trenches 209 and exposes the source trenches 210 and the outer surface 7. In this step, there is a case in which a portion of the second resist mask 211 filling the gate trenches 209 formed in the perimeter boundary section of the active surface 6 is inclined due to height differences between the active surface 6 and the outer surface 7.

[0384] Next, as in Fig. Figure 31B shows that unnecessary sections of the SiC epi-wafer 202 have been removed by the etching process using the second resist mask 211 (see also Fig. 29G). Preferably, the etching process is an anisotropic dry etching process (e.g., RIE process). In this step, the unnecessary sections of the second semiconductor region 11 are removed. Therefore, the source trenches 210 and the outer surface 7 are further excavated downwards in the thickness direction (towards the side of the second wafer main surface 204) of the SiC epi-wafer 202.

[0385] Next, as in Fig. Figure 31C shows the removal of the second resist mask 211. At this point, the removal of the second resist mask 211 in the circumferential boundary section of the active surface 6 is no longer sufficient due to the inclination of the second resist mask 211. Consequently, a portion of the second resist mask 211 remains as a residue in the gate trench 209.

[0386] Next, as in Fig. Figure 31D shows the hard mask 207 removed by the etching process. The etching process can be wet etching and / or dry etching. The inner wall of the gate trench 209 is partially removed by the remnants of the second resist mask 211 in the circumferential edge section of the active area 6. Therefore, a portion of the inner wall of the gate trench 209 exposed by the remnant of the second resist mask 211 is further eroded relative to a portion covered by this remnant. The SiC semiconductor device 301 is fabricated using the same process as the SiC semiconductor device 1.

[0387] The gate trench 32, with its inner wall exhibiting a shape defect in the circumferential edge section of the active area 6, is formed in the SiC semiconductor device 301 according to the first preferred reference embodiment. The gate trench 32, which is defective in shape, degrades the electrical properties of the SiC semiconductor device 301. For example, the incorrectly shaped gate trench 32 reduces the withstand voltage (voltage rating) of the SiC semiconductor device 1 or alters the gate threshold voltage.

[0388] Therefore, the SiC semiconductor device 1, comprising the SiC chip 2, the transistor structure 30, and the first dummy structure 60A (dummy structure 60), was used in the first preferred embodiment. The SiC chip 2 has the first main surface 3. The first main surface 3 has the active area 6 (first surface), the outer surface 7 (second surface), and the first to fourth interconnection surfaces 8A to 8D. The outer surface 7 is recessed to a depth D1 in the thickness direction outside the active area 6. The first to fourth interconnection surfaces 8A to 8D connect the active area 6 and the outer surface 7. The active area 6, the outer surface 7, and the first to fourth interconnection surfaces 8A to 8D define the active mesa 9 (mesa) in the first main surface 3.

[0389] The transistor structure 30 is formed on the inner section of the active area 6. The transistor structure 30 has the gate trench structure 31 and the first source trench structure 41. The gate trench structure 31 has a second depth D2, which is less than the first depth D1 (D2 < D1). The first source trench structure 41 has a third depth D3, which is greater than the second depth D2 (D2 < D3), and adjoins the gate trench structure 31 in one direction (second direction Y). The first dummy structure 60A is formed on the circumferential edge section of the active area 6. The first dummy structure 60A has the first dummy source trench structures 61, each of which has a third depth D3 (D2 < D3) and adjoins each other in one direction (second direction Y).

[0390] According to this structure, the transistor structure 30 is formed on the inner section of the active area 6, and the first dummy structure 60A, which does not function as a transistor structure 30, is formed on the circumferential edge section of the active area 6. Therefore, it is possible to prevent a change in the electrical properties of the transistor structure 30 caused by a defect in the shape of the circumferential edge section of the active area 6. Thus, it is possible to provide a SiC semiconductor device 1 that improves reliability.

[0391] More precisely, the first dummy source trench structures 61 are arranged one after the other at intervals, so that they are adjacent to each other. The first dummy source trench structures 61 are also arranged with intervals between them, without any trench structure having a depth less than the third depth between them. The gate potential is supplied to the gate trench structure 31. The source potential is supplied to the first trench structure 41. Preferably, the source potential is supplied to the first dummy source trench structures 61.

[0392] Preferably, the source trench structures 41 are exposed by one or both of the third and fourth connection surfaces 8C and 8D. Preferably, the first dummy source trench structures 61 are exposed by one or both of the third and fourth connection surfaces 8C and 8D.

[0393] Preferably, the gate trench structure 31 is formed at a distance from the third and fourth interconnect surfaces 8C and 8D to the inside of the active area 6. In this case, the transistor structure 30 preferably has at least one second source trench structure 51, which has the third depth D3 (D2 < D3) and is oriented towards the gate trench structure 31 in a direction (first direction X) that is perpendicular to the mutually facing directions (second direction Y) of both the gate trench structure 31 and the first source trench structure 41.

[0394] Preferably, at least one second source trench structure 51 is formed in a region between the circumferential edge of the active surface 6 and the gate trench structure 31. The second source trench structure 51 can be formed in a region between the third connection surface 8C and the gate trench structure 31 or in a region between the fourth connection surface 8D and the gate trench structure 31. Preferably, the second source trench structure 51 is exposed from the third connection surface 8C or the fourth connection surface 8D.

[0395] Preferably, the SiC semiconductor device 1 has a second dummy structure 60B, which is formed in a region between the transistor structure 30 and the first dummy structure 60A in the circumferential boundary section of the active area 6. The second dummy structure 60B has the dummy gate trench structure 62 with a second depth D2 (D2 < D3) and the second dummy source trench structure 63 with a third depth D3 (D2 < D3), and which adjoins the dummy gate trench structure 62 in one direction (second direction Y).

[0396] According to this structure, the second dummy structure 60B, which has the same configuration as transistor structure 30 but does not function like transistor structure 30, is formed in a region between transistor structure 30 and the first dummy structure 60A in the circumferential boundary section of the active area 6. In other words, a stepped structure is used in the active area 6, in which the first dummy structure 60A, the second dummy structure 60B, and transistor structure 30 are arranged in that order from the perimeter of the active area 6 inwards.

[0397] According to this structure, it is possible to appropriately limit a change in the electrical properties of the transistor structure 30 caused by a defect in the shape in the circumferential edge section of the active area 6. Therefore, it is possible to provide a SiC semiconductor device 1 that improves reliability. Preferably, the source potential is supplied to the dummy gate trench structures 62. Furthermore, the source potential is preferably also supplied to the second dummy source trench structure 63.

[0398] Preferably, the SiC semiconductor device 1 has the sidewall wiring 100 (sidewall structure) which is formed above the outer surface 7 such that it covers at least one of the first to fourth interconnection surfaces 8A to 8D. According to this structure, it is possible to reduce the height difference between the active surface 6 and the outer surface 7.

[0399] Preferably, the SiC semiconductor device 1 has a first inorganic insulating film 110 covering the transistor structure 30 and the first dummy structure 60A above the active area 6. Preferably, the SiC semiconductor device 1 has a gate main surface electrode 121 formed on the first inorganic insulating film 110. Preferably, the SiC semiconductor device 1 has a gate wiring electrode 131 extending from the gate main surface electrode 121 onto the first inorganic insulating film 110. Preferably, the gate wiring electrode 131 is electrically connected through the first inorganic insulating film 110 to the gate trench structure 31 and faces the first source trench structure 41, with the first inorganic insulating film 110 being located between the first source trench structure 41 and the gate wiring electrode 131.

[0400] Preferably, the SiC semiconductor device 1 has the source main surface electrode 122, which is formed on the first inorganic insulating film 110 at a distance from the gate main surface electrode 121 and from the gate wiring electrode 131. Preferably, the source main surface electrode 122 is electrically connected to the first source trench structure 41 via the first inorganic insulating film 110 and faces the gate trench structure 31 with the first inorganic insulating film 110 between the gate trench structure 31 and the source main surface electrode 122. Preferably, the source main surface electrode 122 is formed on the first inorganic insulating film 110 at a distance from the first dummy structure 60A, as seen in the top view.

[0401] Preferably, the SiC semiconductor device 1 has a source wiring electrode 132 that extends from the source main surface electrode 122 onto the first inorganic insulating film 110. Preferably, the source wiring electrode 132 penetrates the first inorganic insulating film 110 at a location different from that of the source main surface electrode 122 and is electrically connected to the first source trench structure 41. Preferably, the source wiring electrode 132 extends through the first inorganic insulating film 110 and is electrically connected to the first dummy source trench structure 61.

[0402] The SiC semiconductor device 1, which includes the SiC chip 2, the transistor structure 30 and the second dummy structure 60B (dummy structure 60), can be used to solve a problem in Fig. 31A to Fig. The problem depicted in Figure 31D is used. The SiC chip 2 has the first main surface 3. The first main surface 3 has the active area 6 (first surface), the outer surface 7 (second surface), and the first to fourth interconnection surfaces 8A to 8D. The outer surface 7 is recessed to a depth of D1 in the thickness direction outside the active area 6. The first to fourth interconnection surfaces 8A to 8D connect the active area 6 and the outer surface 7. The active area 6, the outer surface 7, and the first to fourth interconnection surfaces 8A to 8D define the active mesa 9 (mesa) in the first main surface 3.

[0403] The transistor structure 30 is formed on the inner section of the active area 6. The transistor structure 30 has the gate trench structure 31 and the first source trench structure 41. The gate trench structure 31 has a second depth D2, which is less than the first depth D1 (D2 < D1). The first source trench structure 41 has a third depth D3, which is greater than the second depth D2 (D2 < D3), and connects to the gate trench structure 31 in one direction (second direction Y). The first dummy structure 60A is formed on the circumferential edge section of the active area 6. The second dummy structure 60B has the dummy gate trench structure 62 with the second depth D2 (D2 < D1) and the dummy source trench structures 63 with the third depth D3 (D2 < D3), which connect to the dummy gate trench structure 62 in one direction (second direction Y).

[0404] According to this structure, the transistor structure 30 is formed on the inner section of the active area 6, and the second dummy structure 60B, which does not function as a transistor structure 30, is formed on the circumferential edge section of the active area 6. Therefore, it is possible to prevent a change in the electrical properties of the transistor structure 30 caused by a defect in the shape of the circumferential edge section of the active area 6. Thus, it is possible to provide a SiC semiconductor device 1 that improves reliability.

[0405] According to the first preferred embodiment, it is also possible to provide a SiC semiconductor device 1 with a wiring structure in which the design rules are flexible for a structure with the trench structure formed at the active mesa 9. In other words, the SiC semiconductor device 1 comprises the SiC chip 2, the first source trench structure 41 (trench structure), and the sidewall wiring 100.

[0406] The SiC chip 2 has a first main surface 3. The first main surface 3 has the active area 6 (first surface), the outer surface 7 (second surface), and the first to fourth interconnection surfaces 8A to 8D. The outer surface 7 is recessed to a depth D1 in the thickness direction outside the active surface 6. The first to fourth interconnection surfaces 8A to 8D connect the active surface 6 and the outer surface 7. The active surface 6, the outer surface 7, and the first to fourth interconnection surfaces 8A to 8D define the active mesa 9 (mesa) in the first main surface 3.

[0407] The first source trench structure 41 is configured at the active surface 6 such that it is exposed to at least one of the first to fourth interconnection surfaces 8A to 8D. The sidewall wiring 100 covers at least one of the first to fourth interconnection surfaces 8A to 8D above the outer surface 7, thus electrically connecting it to the first source trench structure 41. According to this structure, it is possible to electrically connect the first source trench structure 41 and the sidewall wiring 100 at the first to fourth interconnection surfaces 8A to 8D. Therefore, it is possible to provide a SiC semiconductor device 1 with a novel wiring structure in which the design rules can be flexibly implemented by the sidewall wiring 100.

[0408] Preferably, in this structure, the first source trench structures 41 are formed with intervals between them on the active surface 6. Preferably, in this case, the side wall wiring 100 is electrically connected to the first source trench structures 41 in at least one of the first to fourth connection surfaces 8A to 8D.

[0409] Preferably, the first source trench structure 41 comprises the source trench 42 formed at the active surface 6, the source insulating film 43 covering the inner wall of the source trench 42, and the source electrode 44 embedded in the source trench 42, wherein the source insulating film 43 lies between the source trench 42 and the source electrode 44. Preferably, in this case, the side wall wiring 100 is electrically connected to the source electrode 44.

[0410] Preferably, the SiC semiconductor device 1 has the main surface insulating film 90, which covers the outer surface 7 and the first to fourth interconnect surfaces 8A to 8D and is connected to the source insulating film 43. In this case, the sidewall wiring 100 is preferably formed on the main surface insulating film 90.

[0411] Preferably, the SiC semiconductor device 1 has a pn junction (well area 71 and / or outer well area 81) formed in a region along the first to fourth interconnection surfaces 8A to 8D within the SiC chip 2. Preferably, in this case, the sidewall wiring 100 faces the pn junction in the first to fourth interconnection surfaces 8A to 8D, with the main surface insulating film 90 located between the pn junction and the sidewall wiring 100.

[0412] Preferably, the sidewall wiring 100 is formed integrally with the source electrode 44. Preferably, the bottom wall of the source trench 42 is in contact with the outer surface 7. Preferably, the sidewall wiring 100 has the overlap section 101, which covers the circumferential edge section of the active surface 6. Preferably, the first source trench structure 41 extends in one direction (first direction X) in the plan view. Preferably, in this case, the sidewall wiring 100 runs in a cutting direction (second direction Y) that intersects one direction (first direction X) in the plan view.

[0413] Preferably, the SiC semiconductor device 1 has a first inorganic insulating film 110 covering the sidewall wiring 100. According to this structure, it is possible to protect the sidewall wiring 100 with the aid of the first inorganic insulating film 110. Preferably, in this structure, the first inorganic insulating film 110 extends through the sidewall wiring 100 and covers the active area 6 and the outer surface 7.

[0414] Viewed from another perspective, the SiC semiconductor device 1 comprises the SiC chip 2, the gate trench structure 31, the first source trench structure 41, and the sidewall wiring 100. The SiC chip 2 has the first main surface 3. The first main surface 3 includes the active area 6 (first surface), the outer surface 7 (second surface), and the first to fourth interconnect surfaces 8A to 8D. The outer surface 7 is recessed to a depth D1 in the thickness direction outside the active area 6. The first to fourth interconnect surfaces 8A to 8D connect the active area 6 and the outer surface 7. The active area 6, the outer surface 7, and the first to fourth interconnect surfaces 8A to 8D define the active mesa 9 (mesa) in the first main surface 3.

[0415] The gate trench structure 31 is formed on the active surface 6 at a distance from the first to fourth connection surfaces 8A to 8D. The first source trench structure 41 is formed on the active surface 6 such that it is exposed to at least one of the first to fourth connection surfaces 8A to 8D. The sidewall wiring 100 covers at least one of the first to fourth connection surfaces 8A to 8D, so that it is electrically connected to the first trench structure 41, and is formed above the outer surface 7.

[0416] According to this structure, it is possible to electrically connect the first source trench structures 41 and the sidewall wiring 100 at the first to fourth connection surfaces 8A to 8D. Therefore, it is possible to provide a SiC semiconductor device 1 with a novel wiring structure in which the design rules can be flexibly configured by the sidewall wiring 100.

[0417] Preferably, the first source trench structure 41 is deeper than the gate trench structure 31. Preferably, the gate trench structures 31 are formed on the active surface 6. Preferably, in this case, the first source trench structures 41 are formed on the active surface 6 alternating with the gate trench structures 31. Preferably, in this case, the sidewall wiring 100 is also electrically connected to the first source trench structures 41 and electrically isolated from the gate trench structures 31.

[0418] Preferably, the SiC semiconductor device 1 has the second source trench structure 51, which is formed in a region between the first to fourth interconnection surfaces 8A to 8D, and the source trench structure 31 in the active area 6. Preferably, in this structure, the second source trench structure 51 is exposed by at least one of the first to fourth interconnection surfaces 8A to 8D. In this structure, the sidewall wiring 100 is preferably electrically connected to the first source trench structure 41 and the second source trench structure 51.

[0419] Preferably, the SiC semiconductor device 1 has a first inorganic insulating film 110 covering the gate trench structure 31, the first source trench structure 41, and the sidewall wiring 100 above the first surface 3. According to this structure, it is possible to protect the gate trench structure 31, the first source trench structure 41, and the sidewall wiring 100 by means of the first inorganic insulating film 110.

[0420] Preferably, the SiC semiconductor device 1 has the gate main surface electrode 121, which is formed on the first inorganic insulating film 110. Preferably, the SiC semiconductor device 1 has the gate wiring electrode 131, which extends from the gate main surface electrode 121 onto the first inorganic insulating film 110, is electrically connected to the gate trench structure 31 via the first inorganic insulating film 110, and faces the first source trench structure 41, wherein the first inorganic insulating film 110 lies between the first source trench structure 41 and the gate wiring electrode 131.

[0421] Preferably, the SiC semiconductor device 1 has the source main surface electrode 122, which is formed on the first inorganic insulating film 110 and is electrically connected to the first source trench structure 41 via the first inorganic insulating film 110 and faces the gate trench structure 31, wherein the first inorganic insulating film 110 is located between the gate trench structure 31 and the source main surface electrode 122. Preferably, the SiC semiconductor device 1 has the source wiring electrode 132, which extends from the source main surface electrode 122 onto the first inorganic insulating film 110 and is electrically connected to the sidewall wiring 100 via the first inorganic insulating film 110.Preferably, the source wiring electrode 132 is electrically connected to the first source trench structure 41 at a different location than the source main surface electrode 122 through the first inorganic insulating film 110.

[0422] Fig. 32 corresponds Fig. Figure 6 is a top view showing a SiC semiconductor device 311 according to a second preferred reference embodiment. Fig. Figure 33 is a cross-sectional view along line XXXIII-XXIII in Fig. 32. The same reference numeral is used below to denote a structure corresponding to the structure described for the SiC semiconductor device 1, and a description of this structure is omitted.

[0423] In the SiC semiconductor device 311 according to the second preferred reference embodiment, the first source trench structures 41 are formed at a distance from the first to fourth interconnect surfaces 8A to 8D on the inner portion of the active area 6 in plan view. The first source trench structures 41 do not intersect the end portion of each of the gate trench structures 31 from the side of the second direction Y in the first direction X in plan view. In the present embodiment, each of the first source trench structures 41 has a length that substantially corresponds to the length of each of the gate trench structures 31 with respect to the first direction X.

[0424] The transistor structure 30 according to the SiC semiconductor device 311 has a plurality of second gate trench structures 321 formed on the active area 6. The gate potential is supplied to the second gate trench structures 321.

[0425] The second gate-trench structures 321 are each formed in the active area 6 at a distance from the first to fourth connection surfaces 8A to 8D such that they border the first source-trench structures 41 in the first direction X and the gate-trench structures 31 in the second direction Y. More precisely, the second gate-trench structures 321 are each formed at a distance from each of the gate-trench structures 31 in an area between two adjacent gate-trench structures 31 in the active area 6 and each border the first source-trench structures 41 in the first direction X.

[0426] More precisely, the second gate-trench structures 321 are each ribbon-shaped, extending in the first direction X in plan view and arranged with intervals in the second direction Y such that the individual gate-trench structure 31 is positioned between them. The second gate-trench structures 321 are strip-shaped and extend in the first direction X in plan view.

[0427] Each of the second gate-trench structures 321 has a third width W3. The third width W3 is a width in a direction (i.e., second direction Y) that is perpendicular to a direction in which each of the second gate-trench structures 321 extends (i.e., second direction Y). The third width W3 is preferably not less than 0.1 µm and not more than 3 µm. Preferably, the third width W3 is not less than 0.5 µm and not greater than 1.5 µm. The third width W3 can be greater than the first width W1 (W1 < W3) or equal to or less than the first width W1 (W1 ≥ W3). In the present embodiment, the third width W3 is substantially equal to the first width W1 (W1 ≈ W3). Preferably, the third width W3 has a value within ±10% of the value of the first width W1.

[0428] Each of the second gate trench structures 321 has a fourth depth D4. The fourth depth D4 is greater than the second depth D2 of the gate trench structure 31 (D2 < D4). Preferably, the fourth depth D4 is not less than 1.5 times and not more than 3 times the second depth D2. In the present embodiment, the fourth depth D4 is essentially equal to the first depth D1 of the outer surface 7 (D1 ≈ D4). Furthermore, the fourth depth D4 is essentially equal to the third depth D3 of the first source trench structure 41 (D3 ≈ D4). Preferably, the fourth depth D4 has a value that lies within ±10% of the value of the third depth D3.

[0429] The fourth depth D4 is preferably not less than 0.5 µm and not more than 10 µm. Preferably, the fourth depth D4 is 5 µm or less. Particularly preferably, the fourth depth D4 is 2.5 µm or less. Preferably, the aspect ratio D4 / W3 of each of the second gate-trench structures 321 is not less than 1 and not greater than 5. The aspect ratio D4 / W3 is a ratio between the fourth depth D4 and the third width W3. Particularly preferably, the aspect ratio D4 / W3 is 2 or more.

[0430] The second gate-trench structures 321 are arranged with fifth spacings P5 between the gate-trench structures 31 and the second gate-trench structures 321 in the second direction Y. The fifth spacing P5 is a distance between the individual gate-trench structure 31 and the individual second gate-trench structure 321 that are adjacent to each other in the second direction Y. Preferably, the fifth spacing P5 is not less than 1 / 4 of the first spacing P1 of the gate-trench structures 31 and not greater than the first spacing P1 (1 / 4 × P1 ≤ P5 < P1). Preferably, the fifth spacing P5 is equal to or less than 1 / 2 of the first spacing P1 (P5 ≤ 1 / 2 × P1).

[0431] The fifth distance P5 preferably has a value of no less than 0.1 µm and no more than 2.5 µm. Preferably, the fifth distance P5 is no less than 0.5 µm and no greater than 1.5 µm. Preferably, the fifth distance P5 is substantially equal to the second distance P2 between the gate trench structure 31 and the first source trench structure 41 (P2 ≈ P5). Preferably, the fifth distance P5 has a value that lies within ±10% of the value of the second distance P2.

[0432] The second gate-trench structures 321 are arranged with sixth spacings P6 between the first source-trench structures 41 and the second gate-trench structures 321 in the first direction X. The sixth spacing P6 is a distance between the individual first source-trench structure 41 and the individual second gate-trench structures 321 that are adjacent to each other in the first direction X. Preferably, the sixth spacing P6 is not less than 1 / 4 of the first spacing P1 of the gate-trench structures 31 and not greater than the first spacing P1 (1 / 4 × P1 ≤ P6 < P1). Preferably, the sixth spacing P6 is equal to or less than 1 / 2 of the first spacing P1 (P6 ≤ 1 / 2 × P1).

[0433] The sixth distance P6 is preferably not less than 0.1 µm and not greater than 2.5 µm. Preferably, the sixth distance P6 is not less than 0.5 µm and not greater than 1.5 µm. Preferably, the sixth distance P6 is substantially equal to the second distance P2 between the gate trench structure 31 and the first source trench structure 41 (P2 ≈ P6). Preferably, the sixth distance P6 has a value that lies within ±10% of the value of the second distance P2.

[0434] Each of the second gate-trench structures 321 has a side wall and a bottom wall. The side wall forming one long side of each of the second gate-trench structures 321 is formed by the a-plane of the SiC single crystal. The side wall forming one short side of each of the second gate-trench structures 321 is formed by the m-plane of the SiC single crystal. The bottom wall of each of the second gate-trench structures 321 is formed by the c-plane of the SiC single crystal.

[0435] Each of the second gate-trench structures 321 can be configured vertically with a substantially uniform opening width. Each of the second gate-trench structures 321 can have a conical shape, the opening width of which tapers towards the bottom wall. Preferably, the bottom wall of each of the second gate-trench structures 321 is curved in the direction of the second surface 4. Naturally, the bottom wall of each of the second gate-trench structures 321 can have a flat surface parallel to the active surface 6.

[0436] Each of the second gate trench structures 321 is formed on the active area 6 such that it traverses the body region 23 and the source region 24 and reaches the second semiconductor region 11. More precisely, each of the second gate trench structures 321 is formed at a distance from the bottom section of the second semiconductor region 11 in the direction of the side of the active area 6 and faces the first semiconductor region 10 (third semiconductor region 14), with a portion of the second semiconductor region 11 lying between the first semiconductor region 10 and each of the second gate trench structures 321. In the present embodiment, each of the second gate trench structures 321 is formed in the second concentration region 13 and faces the first concentration region 12, with a portion of the second concentration region 13 lying between the first concentration region 12 and each of the second gate trench structures 321.

[0437] The side wall of each of the second gate-trench structures 321 is in contact with the second semiconductor region 11, the body region 23, and the source region 24. The bottom wall of each of the second gate-trench structures 321 is in contact with the second semiconductor region 11. In the present embodiment, each of the second gate-trench structures 321 is deeper than each of the gate-trench structures 31. In other words, the bottom wall of each of the second gate-trench structures 321 is located on the side of the bottom section of the second semiconductor region 11 (second concentration region 13) with respect to the bottom wall of each of the gate-trench structures 31.

[0438] Each of the second gate trench structures 321 has a second gate trench 322, a second gate insulating film 323, and a second gate electrode 324. The second gate trench 322 forms the side wall and the bottom wall of the second gate trench structure 321. The side wall and the bottom wall form a surface of the second gate trench 322 (inner wall and outer wall).

[0439] An opening edge section of the second gate groove 322 is inclined obliquely downwards from the active surface 6 towards the second gate groove 322. The opening edge section is a connecting section between the active surface 6 and the side wall of the second gate groove 322. In the present embodiment, the opening edge section is formed in a curved shape, recessed towards the SiC chip 2. The opening edge section can be formed in a curved shape towards the inside of the second gate groove 322.

[0440] The second gate insulating film 323 is formed as a film on the inner wall of the second gate groove 322 and defines a recessed space in the second gate groove 322. The second gate insulating film 323 covers the second semiconductor region 11, the body region 23, and the source region 24 on the inner wall of the second gate groove 322. The second gate insulating film 323 comprises at least one silicon oxide film, one silicon nitride film, or one silicon oxynitride film. In the present embodiment, the second gate insulating film 323 has a single-layer structure formed from a silicon oxide film.

[0441] The second gate insulating film 323 has a first section 323a, a second section 323b, and a third section 323c. The first section 323a covers the side wall of the second gate trench 322. More precisely, the first section 323a covers the side wall of the second gate trench 322 and exposes the surface layer section of the first main surface 3 from an opening end of the second gate trench 322 at a distance from the opening end of the second gate trench 322 towards the side of the bottom wall in the active area 6. The first section 323a covers the entire surface of the side wall of the second gate trench 322 on the side of the perimeter edge section of the active area 6.

[0442] The second section 323b covers the bottom wall of the second gate trench 322. The third section 323c is formed on the side of the circumferential edge section of the active surface 6 at a distance from the inner section of the active surface 6 and covers the opening edge section of the second gate trench 322. In the present embodiment, the third section 323c curves in a curved shape towards the inside of the second gate trench 322 in the opening edge section.

[0443] The thickness of the first section 323a is preferably not less than 10 nm and not more than 100 nm. The second section 323b may have a thickness greater than that of the first section 323a. The thickness of the second section 323b is preferably not less than 50 nm and not more than 200 nm. The third section 43c has a greater thickness than the first section 43a. The thickness of the third section 323c is preferably not less than 50 nm and not more than 200 nm. Of course, a gate insulating layer 323 with a uniform thickness can also be formed.

[0444] The second gate electrode 324 is embedded in the second gate groove 322, with the second gate insulating film 323 located between the second gate groove 322 and the second gate electrode 324. The second gate electrode 324 faces the second semiconductor region 11, the body region 23, and the source region 24, with the second gate insulating film 323 located between these regions and the second gate electrode 324. The electrode surface of the second gate electrode 324 is exposed by the second gate groove 322. The electrode surface of the second gate electrode 324 is curved and recessed towards the bottom wall of the second gate groove 322.

[0445] The electrode surface of the second gate electrode 324 is tapered by the third section 323c of the insulating film at the side of the circumferential edge section of the active area 6. The gate potential is applied to the second gate electrode 324. Preferably, the second gate electrode 324 is made of conductive polysilicon. The second gate electrode 324 can comprise n-type polysilicon doped with an n-type impurity and / or p-type polysilicon doped with a p-type impurity. Preferably, the second gate electrode 324 comprises the same conductive material as the gate electrode 34.

[0446] As described, the second gate trench structure 321 is formed at the active area 6 of the SiC semiconductor device 311, corresponding to a structure of the first source trench structure 41. The second gate trench structure 321 can also be considered a section separate from the first source trench structure 41.

[0447] In the SiC semiconductor device 311, the second source trench structures 51 with the third spacing P3 between them are configured in the second direction Y such that they correspond one-to-one with the gate trench structures 31 and the second gate trench structures 321 in the first direction X. In other words, the second source trench structures 51 surround the single gate trench structure 31 from both sides in the first direction X. Furthermore, the second source trench structures 51 surround the second gate trench structures 321 with the source trench structures 41 from both sides in the first direction X. The other structures of the second source trench structures 51 are the same as those of the second source trench structures 51 according to the SiC semiconductor device 1.

[0448] The contact areas 70 are not formed in a region along the second gate trench structures 321 in the surface layer section of the first main surface 3. In the present embodiment, the gate basin regions 72 are formed in addition to the gate trench structures 31 also in a region along the second gate trench structures 321. The gate basin regions 72 are each formed in a one-to-one correspondence with the second gate trench structures 321.

[0449] Each of the gate trough areas 72 is ribbon-shaped and extends in plan view along each of the second gate trench structures 321. Each of the gate trough areas 72 is positioned at a distance from the gate trench structure 31 and the first source trench structure 41 towards the side of the second gate trench structure 321, exposing the gate trench structure 31 and the first source trench structure 41. Each of the gate trough areas 72 covers the bottom wall and the entire surface of the side wall of each of the second gate trench structures 321. Each of the gate trough areas 72 is electrically connected to the body area 23 in the side wall of each of the second gate trench structures 321.

[0450] The bottom section of each of the gate basin regions 72 covering each of the second gate trench structures 321 is located in a region on the side of the bottom section of the second semiconductor region 11 (second concentration region 13) with respect to the bottom section of each of the gate basin regions 72 covering each of the gate trench structures 31. The bottom section of each gate basin region 72 covering each of the second gate trench structures 321 is formed at a depth that is substantially the same as that of the bottom section of each gate basin region 71 covering each of the first source trench structures 41.

[0451] Each of the gate well regions 72, covering each of the second gate trench structures 321, is located at a distance from the bottom section of the second semiconductor region 11 (second concentration region 13) towards the side of the active area 6 and faces the first semiconductor region 10 (third semiconductor region 14), with a portion of the second semiconductor region 11 situated between the first semiconductor region 10 and each of the gate well regions 72. In other words, each of the gate well regions 72, covering each of the second gate trench structures 321, is electrically connected to the second semiconductor region 11 (second concentration region 13).

[0452] Preferably, the thickness of a portion of each gate trough area 72 covering the bottom wall of each of the second gate trench structures 321 is greater than the thickness of a portion of each gate trough area 72 covering the side wall of each of the second gate trench structures 321. The thickness of the portion of each gate trough area 72 covering the side wall of each of the second gate trench structures 321 is the thickness normal to the side wall of each of the second gate trench structures 321. The thickness of the portion of each gate trough area 72 covering the bottom wall of each of the second gate trench structures 321 is the thickness normal to the bottom wall of each of the second gate trench structures 321.

[0453] Preferably, the bottom section of the gate well regions 72 is formed at a substantially uniform depth with respect to the bottom wall of the second gate trench structures 321. The gate well regions 72 form a pn junction with the second semiconductor region 11 (second concentration region 13) and extend a depletion layer in the width and depth direction of the SiC chip 2. The gate well regions 72 bring the MISFET with an insulated gate into close proximity to the structure of a pn junction diode and relieve (dissipate) an electric field in the SiC chip 2.

[0454] The SiC semiconductor device 311 has gate contact electrodes 91. There are two gate contact electrodes 91: one on the side of the third interconnection surface 8C and one on the side of the fourth interconnection surface 8D. The gate contact electrode 91 on the side of the third interconnection surface 8C is described below. The gate contact electrode 91 covers the gate trench structure 31 and the second gate trench structure 321 at a distance from the first source trench structures 41 and the second source trench structures 51.

[0455] The gate contact electrode 91 is connected to the gate electrode 34 of the gate trench structures 31 and to the second gate electrode 324 of the second gate trench structures 321. The gate contact electrode 91 is ribbon-shaped and extends in the second direction Y such that it intersects the end section of the gate trench structures 31 and an inner section of the second gate trench structures 321 in the top view.

[0456] The gate contact electrode 91 has the electrode surface 91a, which extends along the active area 6. In the present embodiment, the gate contact electrode 91 has a conical shape (truncated cone shape) whose width tapers from the active area 6 to the electrode surface 91a. The electrode surface 91a has a section facing the gate electrode 34 in the normal direction Z and a section facing an area (i.e., the main surface insulating film 90) outside the gate trench structure 31 in the normal direction Z.

[0457] Preferably, the gate contact electrode 91 is made of conductive polysilicon. The gate contact electrode 91 can comprise n-type polysilicon doped with an n-type impurity and / or p-type polysilicon doped with a p-type impurity. Preferably, the gate contact electrode 91 is made of the same conductive material as each of the gate electrodes 34.

[0458] In the present embodiment, each of the gate contact electrodes 91 is formed from a lead-out section that extends from the gate electrode 34 and from the second gate electrode 324 to a space above the active area 6. In other words, the gate contact electrodes 91 are led from the gate electrode 34 through the third section 33c of the gate insulating film 33 to the main surface insulating film 90, and from the second gate electrode 324 through the third section 323c of the second gate insulating film 323 to the main surface insulating film 90.

[0459] In the present embodiment, the gate openings 112 are ribbon-shaped and extend along the gate contact electrodes 91, so that the gate contact electrodes 91 are each exposed. The gate wiring electrode 131 enters the gate openings 112 from above the first inorganic insulating film 110 and is electrically connected to the gate contact electrodes 91. The gate potential applied to the gate wiring electrode 131 is thus transmitted via the gate wiring electrode 131 to the gate trench structures 31 and to the second gate trench structures 321.

[0460] The SiC semiconductor element 311 according to the second preferred reference embodiment comprises the SiC chip 2, the gate trench structure 31, the second gate trench structure 321, the first inorganic insulating film 110, the main gate surface electrode 121, and the gate wiring electrode 131. The gate trench structure 31 is formed on the first surface 3 to a second depth D2. The second gate trench structure 321 has a fourth depth D4, which is greater than the second depth D2, and is formed on the first surface 3 such that it adjoins the gate trench structure 31.

[0461] The first inorganic insulating film 110 covers the gate trench structure 31 and the second gate trench structure 321 above the first main surface 3. The gate main surface electrode 121 is formed on the first inorganic insulating film 110. The gate wiring electrode 131 extends from the gate main surface electrode 121 onto the first inorganic insulating film 110 and is electrically connected through the first inorganic insulating film 110 to the gate trench structure 31 and the second gate trench structure 321. According to this structure, it is possible to supply the gate potential to the gate trench structure 31 while simultaneously preventing a decrease in the withstand voltage (dielectric strength).

[0462] Preferably, the SiC semiconductor device 311, according to the second preferred reference embodiment, has a gate well region 72 formed in a region along the gate trench structure 31 in the surface layer section of the SiC chip 2. This structure makes it possible to appropriately limit a reduction in the withstand voltage (voltage withstand capability). Preferably, the SiC semiconductor device 311 further has a second gate well region 72 formed in a region along the second gate trench structure 321 in the surface layer section of the SiC chip 2. This structure makes it possible to more appropriately limit a reduction in the withstand voltage (voltage withstand capability).

[0463] Preferably, the SiC semiconductor device 311, according to the second preferred reference embodiment, further comprises the gate contact electrode 91, which covers the gate electrode 34 and the second gate electrode 324 above the first surface 3. Preferably, in this case, the first inorganic insulating film 110 covers the gate contact electrode 91, and the gate wiring electrode 131 is electrically connected to the gate contact electrode 91 through the first inorganic insulating film 110.

[0464] According to this structure, it is possible to electrically connect the gate wiring electrode 131 to both the gate electrode 34 and the second gate electrode 324 simultaneously via the gate contact electrode 91. This structure also allows for the reduction of any alignment play of the gate wiring electrode 131 relative to the gate electrode 34 and the second gate electrode 324 using the gate contact electrode 91. In other words, any positional deviation of the gate wiring electrode 131 relative to the gate electrode 34 and the second gate electrode 324 can be compensated for by means of the gate contact electrode 91.

[0465] Thus, it is possible to electrically connect the gate wiring electrode 131 to the gate electrode 34 and the second gate electrode 324 in a suitable manner. Preferably, in this structure, the gate contact electrode 91 partially covers the gate electrode 34 and the second gate electrode 324. Preferably, the main gate surface electrode 121 is also formed on the first inorganic insulating film 110 at a distance from the gate contact electrode 91 in the top view.

[0466] In the SiC semiconductor device 311 according to the second preferred reference embodiment, the second gate trench structure 321, with a fourth depth D4 that exceeds the second depth D2 of the gate wiring electrode 31, is formed in a region below the gate wiring electrode 131. Therefore, the thickness of the second gate insulating film 323 of the second gate trench structure 321 may differ from the thickness of the gate insulating film 33 of the gate trench structure 31 due to a process defect. In this case, the withstand voltage may decrease due to the concentration of the electric field on the second gate trench structure 321 when the gate potential is applied to the second gate trench structure 321.

[0467] In the present embodiment, which relates to Fig. 1 to Fig. Referring to section 28, the SiC semiconductor device 1 is used, which comprises the SiC chip 2, the gate trench structure 31, the first source trench structure 41, the first inorganic insulating film 110, the gate main surface electrode 121, and the gate wiring electrode 131. The gate trench structure 31 is formed on the first surface 3. The first source trench structure 41 is arranged on the first main surface 3 in one direction (second direction Y) away from the gate trench structure 31.

[0468] The first inorganic insulating film 110 covers the gate trench structure 31 and the first source trench structure 41 above the first main surface 3. The gate main surface electrode 121 is formed on the first inorganic insulating film 110. The gate wiring electrode 131 extends from the gate main surface electrode 121 on the first inorganic insulating film 110 such that it crosses the gate trench structure 31 and the first source trench structure 41 in one direction (second direction Y), and is electrically connected to the gate trench structure 31 through the first inorganic insulating film 110 and faces the source trench structure, with the first inorganic insulating film 110 lying between the first source trench structure 41 and the gate wiring electrode 131.

[0469] According to this structure, it is possible to avoid a reduction in the withstand voltage (voltage withstand capability) caused by the formation of the second gate trench structure 321, which is located deeper than the gate trench structure 31, and, on the other hand, to achieve an increase in the withstand voltage effect, which is realized by the first source trench structure 41 in a region below the gate wiring electrode 131. Therefore, it is possible to provide a SiC semiconductor device 1 that can improve the electrical properties.

[0470] Preferably, in this structure, the gate trench structure 31 is formed on the first main surface 3 at the second depth D2, and the first source trench structure 41 is formed on the first main surface 3 at the third depth D3, extending beyond the second depth D2 (D2 < D3). According to this structure, it is possible to achieve a reinforcement effect for the tensile stress, which is realized by the deep first source trench structure 41.

[0471] Preferably, the SiC semiconductor device 1 has the source main surface electrode 122, which is formed on the first inorganic insulating film 110 remotely from the gate main surface electrode 121 and from the gate wiring electrode 131. Preferably, the source main surface electrode 122 is electrically connected to the first source trench structure 41 via the first inorganic insulating film 110 and faces the gate trench structure 31 with the first inorganic insulating film 110 between the gate trench structure 31 and the source main surface electrode 122.

[0472] Preferably, the SiC semiconductor device 1 has a source wiring electrode 132 that extends from the source main surface electrode 122 onto the first inorganic insulating film 110. Preferably, the source wiring electrode 132 is electrically connected to the first source trench structure 41 through the first inorganic insulating film 110 at a different location than the source main surface electrode 122. In this case, the source wiring electrode 132 is preferably located at a distance from the gate trench structure 31 in a top view.

[0473] Preferably, the SiC semiconductor device 1 has a second source trench structure 51, which is formed on the first main surface 3 at a distance from the gate trench structure 31 in a cutting direction (first direction X) that intersects a direction (second direction Y). According to this structure, it is possible to achieve a reinforcement effect for the withstand voltage, which is realized by the second source trench structure 51. Preferably, the second source trench structure 51 faces the gate trench structure 31 in one direction (first direction X) and faces the first source trench structure 41 in one cutting direction (second direction Y).

[0474] Preferably, in this case, the source main surface electrode 122 is arranged on the first inorganic insulating film 110 at a distance from the second source trench structure 51, the gate main surface electrode 121, and the gate wiring electrode 131 in a top view. Furthermore, the source main surface electrode 122 is preferably electrically connected to the first source trench structure 41 through the first inorganic insulating film 110 and faces the gate trench structure 31, with the first inorganic insulating film 110 being located between the gate trench structure 31 and the source main surface electrode 122.

[0475] Preferably, in this case, the source wiring electrode 132 extends from the source main surface electrode 122 onto the first inorganic insulating film 110 and is electrically connected through the first inorganic insulating film 110 to the second source trench structure 51. Particularly preferably, the source wiring electrode 132 is electrically connected through the first inorganic insulating film 110 to the first source trench structure 41 at a position different from that of the source main surface electrode 122. Preferably, the source wiring electrode 132 is arranged at a distance from the gate trench structure 31 in the top view.

[0476] Preferably, the SiC semiconductor device 1 has a source-side pn junction (well area 71) formed in a region along the first source trench structure 41 within the SiC chip 2. According to this structure, it is possible to improve the withstand voltage (voltage withstand capability) of the SiC semiconductor device 1 by using the first source trench structure 41. Preferably, in this structure, the gate wiring electrode 131 faces the source-side pn junction (well area 71) on the side of the first source trench structure 41 in the top view.

[0477] Preferably, the SiC semiconductor device 1 has a source-side pn junction (well area 71) formed in a region along the second source trench structure 51 within the SiC chip 2. According to this structure, it is possible to improve the withstand voltage (voltage withstand capability) of the SiC semiconductor device 1 by using the second source trench structure 51. Preferably, in this structure, the gate wiring electrode 131 faces the source-side pn junction on the side of the second source trench structure 51 (well area 71) in the top view.

[0478] Preferably, the SiC semiconductor device 1 has at least one gate-side pn junction (gate well region 72) formed in a region along the end section of the gate trench structure 31 within the SiC chip 2. According to this structure, it is possible to improve the withstand voltage (voltage withstand capability) of the SiC semiconductor device 1 by using the gate trench structure 31. Preferably, in this structure, the gate wiring electrode 131 faces the gate-side pn junction (gate well region 72) in the top view.

[0479] Preferably, the SiC semiconductor device 1 has a gate contact electrode 91 that covers the gate electrode 34 above the first main surface 3. Preferably, in this case, the first inorganic insulating film 110 covers the gate contact electrode 91, and the gate wiring electrode 131 is electrically connected to the gate contact electrode 91 through the first inorganic insulating film 110. According to this structure, it is possible to reduce the alignment tolerance of the gate wiring electrode 131 with respect to the gate electrode 34 by means of the gate contact electrode 91.

[0480] In other words, it is possible to compensate for a positional deviation of the gate wiring electrode 131 relative to the gate electrode 34 using the gate contact electrode 91. This makes it possible to electrically connect the gate wiring electrode 131 to the gate electrode 34 in a suitable manner. Preferably, in this configuration, the gate contact electrode 91 partially covers the gate electrode 34. Preferably, the main gate surface electrode 121 is also formed on the first inorganic insulating film 110 at a distance from the gate contact electrode 91 in the top view.

[0481] The SiC semiconductor device 1 can be used, which comprises the SiC chip 2, the gate trench structure 31, the second source trench structure 51, the first inorganic insulating film 110, the source wiring electrode 132, and the gate wiring electrode 131. The gate trench structure 31 is formed on the first main surface 3 and extends in one direction (first direction X) in the top view. The second source trench structure 51 is formed on the first main surface 3 in one direction (first direction X) at a distance from the gate trench structure 31 and extends in one direction (first direction X) in the top view.

[0482] The first inorganic insulating film 110 covers the gate trench structure 31 and the second source trench structure 51. The gate wiring electrode 131 is formed on the first inorganic insulating film 110 and is electrically connected to the gate trench structure 31 through the first inorganic insulating film 110. The source wiring electrode 132 is formed on the first inorganic insulating film 110 at a distance from the gate wiring electrode 131 and is electrically connected to the second source trench structure 51 through the first inorganic insulating film 110. According to this structure, it is possible to achieve a voltage-resistance amplification effect, which is realized by the second source trench structure 51 below the gate wiring electrode 131.

[0483] Preferably, the gate trench structures 31 are arranged on the first main surface 3 with intervals between them in a cutting direction (second direction Y) that intersects one direction (first direction X). Preferably, in this case, the second source trench structures 51 are arranged with intervals between them in the cutting direction (second direction Y) such that they are aligned one-to-one with the gate trench structures 31 in one direction (first direction X). Furthermore, the source wiring electrode 132 is preferably arranged in this structure at a distance from the gate trench structure 31 in the top view.

[0484] Fig. 34 corresponds Fig. 6 and is a top view of a SiC semiconductor device 331 according to a second preferred embodiment of the present invention. Fig. Figure 35 is a cross-sectional view along line XXXV-XXXV in Fig. 34. Fig. Figure 36 is a cross-sectional view along line XXXVI-XXXVI in Fig. 34. Fig. 37 is a cross-sectional view along line XXXVII-XXXVII in Fig. 34 shown.

[0485] The same reference symbol is used below to denote a structure corresponding to the structure described for the SiC semiconductor device 1, and a description of this structure is omitted. A structure on the side of the fourth interconnect surface (8D) corresponds to a structure on the side of the third interconnect surface (8C), therefore only the structure on the side of the third interconnect surface (8C) is described below as an example. A detailed structure on the side of the fourth interconnect surface 8D can be obtained by replacing "third interconnect surface 8C" with "fourth interconnect surface 8D" in the following description.

[0486] In the present embodiment according to Fig. 34 to Fig. The second source trench structures 51 of the SiC semiconductor device 331 have a first trench section 332 in which the inner side of the active surface 6 is flat, and a second trench section 333 in which the periphery edge region side (side of the third interconnect surface) of the active surface 6 is deep with respect to the first direction X. The second source trench structures 51 have a trench step section 334 that steps from the first trench section 332 to the second trench section 333 between the first trench section 332 and the second trench section 333. The individual second source trench structure 51 is described below.

[0487] The first trench section 332 is located on the side of the gate trench structure 31, is ribbon-shaped, and extends in the first direction X in plan view. The first trench section 332 is formed with the third distance P3 between the gate trench structure 31 and the first trench section 332 in the first direction X and faces the gate trench structure 31 in the first direction X. Furthermore, the first trench section 332 is formed with the second distance P2 between the first source trench structure 41 and the first trench section 332 in the second direction Y and faces the first source trench structure 41 in the second direction Y.

[0488] The first trench section 332 has a first trench depth DT1. The first trench depth DT1 is less than the first depth D1 of the outer surface 7 (DT1 < D3). The first trench depth DT1 is less than the third depth D3 of the first source trench structure 41 (DT1 < D3). Preferably, the first trench depth DT1 is substantially equal to the second depth D2 of the gate trench structure 31 (DT1 ≈ D2). Preferably, the first trench depth DT1 has a value that lies within ±10% of the value of the second depth D2. The first trench section 332 reduces a height difference to the active surface 6. Furthermore, the first trench section 332 brings the structure on the inner side of the second source trench structure 51 closer to the gate trench structure 31.

[0489] The first trench depth DT1 is preferably not less than 0.1 µm and not more than 3 µm. Preferably, the first trench depth DT1 is not less than 0.5 µm and not more than 2 µm. Preferably, the aspect ratio DT1 / W2 of the first trench section 332 is not less than 1 and not greater than 5. The aspect ratio DT...

Claims

[1] SiC semiconductor device comprising: a SiC chip (2) with a main surface (3) having a first surface (6), a second surface (7) recessed in a thickness direction to a first depth (D1) outside the first surface (6), and a connecting surface (8A-8D) connecting the first surface (6) and the second surface (7), and in which a mesa (9) is defined by the first surface (6), the second surface (7) and the connecting surface (8A-8D); a transistor structure (30) formed on an inner section of the first surface (6), wherein the transistor structure (30) has a gate trench structure (31) having a second depth (D2) that is less than the first depth (D1), and a source trench structure (41) having a third depth (D3) that is greater than the second depth (D2), and which is adjacent to the gate trench structure (31) in a direction (Y); a dummy structure (60, 60A) formed at a circumferential boundary section of the first surface (6), wherein the dummy structure (60, 60A) has a plurality of dummy source trench structures (61), each of which has the third depth (D3) and which adjoin each other in one direction (Y); and an insulating film (110) covering the gate trench structure (31) and the source trench structure (41) over the main surface (3), wherein the insulating film (110) is in direct contact with both the first gate trench structure (31) and the source trench structure (41). [2] SiC semiconductor device according to claim 1, wherein the source trench structure (41) is deeper than the gate trench structure (31) and the SiC semiconductor device further comprises: a trough area (71) of a first conductivity type covering a bottom wall of the source trench structure (41); a gate trough area (72) of the first conductivity type covering a bottom wall of the gate trench structure (31), wherein the gate trough area (72) has a lesser depth than the depth of the trough area (71) of the first conductivity type. [3] SiC semiconductor device according to claim 1 or 2, wherein the dummy source trench structures (61) are arranged successively with a distance between the dummy source trench structures (61) so that they are adjacent to each other. [4] SiC semiconductor device according to one of claims 1 to 3, wherein the dummy source trench structures (61) are arranged with a distance between them, without a further trench structure being arranged between two adjacent dummy source trench structures (61) which has a lesser depth than the third depth (D3). [5] SiC semiconductor device according to one of claims 1 to 4, wherein a gate potential is supplied to the gate trench structure (31), a source potential is supplied to the source trench structure (41), and the source potential is also supplied to the dummy source trench structures (61). [6] SiC semiconductor device according to one of claims 1 to 5, wherein the transistor structure (30) comprises the gate trench structures (31) arranged with a distance between the gate trench structures (31) in one direction (Y), and the source trench structures (41) arranged alternately with the gate trench structures (31) in one direction (Y) with distances between the source trench structures (41) and the gate trench structures (31). [7] SiC semiconductor device according to one of claims 1 to 6, wherein the gate trench structure (31) is formed at a distance from the interconnection surface (8A-8D) to an inside of the first surface (6). [8] SiC semiconductor device according to claim 7, wherein the transistor structure (30) has an intermediate source trench structure (51) with a third depth (D3) adjacent to the gate trench structure (31) in a cutting direction (X) that intersects one direction (Y). [9] SiC semiconductor device according to claim 8, wherein the intermediate source trench structure (51) is formed in a region between the gate trench structure (31) and the interconnection surface (8A-8D) in the first surface (6). [10] SiC semiconductor device according to any one of claims 1 to 9, further comprising: a second dummy structure (60, 60B) formed in a region between the transistor structure (30) and the dummy structure (60, 60A) in the circumferential boundary section of the first surface (6), wherein the second dummy structure (60, 60B) has a dummy gate trench structure (62) with the second depth (D2) and a second dummy source trench structure (63) with the third depth (D3) adjacent to the dummy gate trench structure (62) in one direction (Y). [11] SiC semiconductor device according to claim 10, wherein a source potential is supplied to the dummy gate trench structure (62), and the source potential is also supplied to the second dummy source trench structure (63). [12] SiC semiconductor device according to any one of claims 1 to 11, further comprising: a side wall structure (100) which is formed on the second surface (7) such that it covers the connecting surface (8A-8D). [13] SiC semiconductor device according to any one of claims 1 to 12, wherein the insulating film (110) covers the transistor structure (30) and the dummy structure (60, 60A) on the first surface (6) and wherein the SiC semiconductor device further comprises: a gate main surface electrode (121) formed on the insulating film (110); and a gate wiring (131) which is led from the gate main surface electrode (121) onto the insulating film (110) and which is electrically connected to the gate trench structure (31) through the insulating film (110) and which faces the source trench structure (41), wherein the insulating film (110) lies between the gate trench structure (31) and the gate wiring (131). [14] SiC semiconductor device according to claim 13, further comprising: a source main surface electrode (122) formed on the insulating film (110) remotely from the gate main surface electrode (121) and from the gate wiring (131), and electrically connected to the source trench structure (41) through the insulating film (110), and facing the gate trench structure (31), wherein the insulating film (110) lies between the gate trench structure (31) and the source main surface electrode (122). [15] SiC semiconductor device according to claim 14, wherein the source main surface electrode (122) is formed on the insulating film (110) in top view away from the dummy structure (60, 60A). [16] The SiC semiconductor device according to claim 14 or 15, further comprising: a source wiring (132) which extends from the source main surface electrode (122) onto the insulating film (110) and which is electrically connected to the source trench structure (41) at a location different from the source main surface electrode (122) through the insulating film (110). [17] SiC semiconductor device according to claim 16, wherein the source wiring (132) is electrically connected to the dummy source trench structure (61) through the insulating film (110). [18] SiC semiconductor device comprising: a SiC chip (2) with a main surface (3) having a first surface (6), a second surface (7) recessed in a thickness direction to a first depth (D1) outside the first surface (6), and a connecting surface (8A-8D) connecting the first surface (6) and the second surface (7), and in which a mesa (9) is defined by the first surface (6), the second surface (7) and the connecting surface (8A-8D); a transistor structure (30) formed on an inner section of the first surface (6), wherein the transistor structure (30) has a gate trench structure (31) having a second depth (D2) that is less than the first depth (D1), and a source trench structure (41) having a third depth (D3) that is greater than the second depth (D2), and which is adjacent to the gate trench structure (31) in a direction (Y); a dummy structure (60, 60A) formed on a circumferential boundary section of the first surface (6), wherein the dummy structure (60, 60A) has a dummy gate trench structure (62) of the second depth (D2) and a dummy source trench structure (63) of the third depth (D3) which adjoins the dummy gate trench structure (62) in one direction (Y); and an insulating film (110) covering the gate trench structure (31) and the source trench structure (41) over the main surface (3), wherein the insulating film (110) is in direct contact with both the gate trench structure (31) and the source trench structure (41).

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