MEMRISTOR STORAGE UNIT WITH A DRIFT AND DISTURBANCE CORRECTED MEMRISTIVE DEVICE AND METHOD FOR OPERATION

Abstract

Memristor storage unit comprising a plurality of memristor storage devices (100; 302), each of which comprises: a memristive memory cell (102, 202); an input port (104) and an output port (108) that are directly attached to the memristive memory cell (102, 202); and an electrically isolated gate terminal (112) from the memristive memory cell (102, 202) for volatile gate-induced modulation of a conductivity of the memristive memory cell (102, 202) by receiving electrical signals; the memristor storage unit further comprises: a temperature effect control unit (402) suitable for generating a portion of the received electrical signals based on a temperature-based resistance drift effect of each of the memristor storage devices (100, 302); and / or a resistance drift correction unit (404) which is suitable for generating a different part of the received electrical signals based on a time-dependent resistance drift effect of each of the memristor storage devices (100, 302).

Description

BACKGROUND

[0001] This document discloses a memristor storage device comprising a memristive memory cell. In particular, the disclosure relates to a method for operating a memristor storage device comprising a memristive memory cell.

[0002] Multilevel cell storage (MLC storage) is a typical approach to achieving increased capacity and thus lower cost per bit in storage technologies. Phase-change memory (PCM) is a new solid-state storage technology that utilizes the thermally induced resistance change of, for example, chalcogenide components for non-volatile data storage. PCM possesses certain characteristics such as long lifespan, low read / write latency, and excellent scalability, making it an attractive candidate not only for expanding and eventually replacing the prevalent flash memory, but also for enabling a revolutionary transformation of future data processing systems.The latter is due to the potential ability of a PCM to function as both storage (non-volatile, inexpensive, high capacity) and working memory (fast, durable) because of its universal properties.

[0003] Memristor storage units are known from publications US 10 553 793 B2, US 10 497 866 B1, US 9 570 169 B1 and US 2011 / 0 240 946 A1.

[0004] The task is to improve corresponding memristor storage units.

[0005] The problem is solved by the memristor storage unit according to claim 1 and the method for operating a memristor storage unit according to claim 11. Further embodiments are set out in the dependent claims. SUMMARY

[0006] According to one embodiment disclosed herein, a memristor storage device comprising a memristive memory cell can be provided. The memristive memory device can have an input terminal, an output terminal, and a gate terminal. The input and output terminals can be directly connected to the memristive memory cell, and the gate terminal can be electrically isolated from the memristive memory cell. The gate terminal can be configured to receive an electrical signal for transient modulation of the conductivity of the memristive memory cell. This allows non-ideal conductivity modulations of the memristor storage device to be corrected.

[0007] According to another embodiment disclosed herein, a method for operating a memristor storage device comprising a memristor memory cell can be provided. The memristor storage device can have an input terminal, an output terminal, and a gate terminal, wherein the input terminal and the output terminal can be directly connected to the memristive memory cell. The gate terminal can be electrically isolated from the memristive memory cell. The method can further comprise providing an electrical signal for volatile modulation of a conductivity of the memristive memory cell. This allows non-ideal conductivity modulations of the memristor storage device to be corrected. Brief description of the different views of the drawings

[0008] Embodiments of the invention are described with respect to various objects. In particular, some embodiments are described with respect to method claims, while other embodiments are described with respect to apparatus claims.

[0009] The forms defined above and further forms of the various embodiments will become apparent from the exemplary embodiments described below and will be explained with reference to these exemplary embodiments, to which the invention is not limited. Various embodiments may be described as having certain advantages; however, some embodiments may not have these potential advantages, and these potential advantages are not necessarily required for all embodiments.

[0010] The embodiments are described only as examples and with reference to the following drawings: Fig. Figure 1 is a block diagram of an embodiment of the inventive memristor storage device, which has a memristive storage cell, according to some embodiments. Fig. Figure 2 is a block diagram of the functional principle of the proposed system and method according to some embodiments. Fig. Figure 3 is a block diagram of an embodiment of a crossbar array with memristor storage devices according to some embodiments. Fig. Figure 4 is a block diagram of an embodiment of the crossbar array with temperature disturbance and resistance drift compensation units according to some embodiments. Fig. Figure 5 is a diagram of a first experimental proof of the proposed system and method according to some embodiments. Fig. Figure 6 is a diagram of a second experimental proof of the proposed system and method according to some embodiments. Fig. Figure 7 is a flowchart of an embodiment of the method for operating a memristor storage device which has a memristive storage cell, according to some embodiments. DETAILED DESCRIPTION

[0011] For PCM to become a viable technology for higher-volume manufacturing, several problems must be addressed. First and foremost, the reliability of the technology must be brought to levels comparable with existing technologies. Experimental results and simulations suggest that thermal disturbance and resistive drift are the most significant potential reliability issues for PCM storage technologies. Thermal disturbance refers to the problem of the cell's state being inappropriately altered by the programming of another cell and its neighbors (thermal process interference). Resistive drift, on the other hand, is a phenomenon whereby the resistivity of the amorphous phase, such as that found in many chalcogenide materials, increases over time.Drifting has been attributed to structural relaxation and stress reduction in the amorphous matrix and is particularly detrimental in multi-level cell storage, as random fluctuations in the programmed resistance of closely spaced levels can cause them to overlap, leading to decoding errors. This problem can also be addressed by the technical solution proposed here.

[0012] In the context of this description, the following conventions, terms and / or expressions may be used:

[0013] The term "memristor storage device" (memristor = a compound word from memory and resistor) can refer to a storage device based on a memristive cell, namely the memristor. It can denote a non-linear electrical component, typically with two terminals—though implemented here as a three-terminal device—that serves as a connection for electric charge and magnetic flux. Phase-change materials (PCMTs) are typically used in these devices. Such a PCMT can change its resistivity between multiple different phases by transitioning from an amorphous to a crystalline state. This transition can be heat-induced. In this way, multi-level cell (MLC) storage devices can be created, which incorporate multiple memristive memory cells.

[0014] The term "memristive memory cell" can refer to a memristor core unit or a memristive memory cell of a storage device. The memristive memory cell may contain phase-change material and can store data by changing its specific resistance. Typically, during readout, the selected bit line of a crossbar array, which has multiple memristive memory cells at its intersections, is biased to a constant voltage (typically a few hundred mV) by a voltage regulator. The detected current i read The signal can be integrated via a capacitor, and the resulting voltage is then digitized by an on-chip cyclic analog-to-digital converter. Additionally, the readout characteristic can be calibrated using an on-chip polysilicon reference resistor. For programming, the externally generated voltage can be converted into an on-chip programming current i. progThis value can then be converted. This value can then be mirrored onto a selected bit line for the desired duration of the programming pulse, thereby changing the mixture of the crystalline and amorphous phases of the PCM.

[0015] The term "gate terminal" can refer to a (third) electrode located near the PCM of the memristive memory cell, but electrically isolated from it. Charges at the gate terminal and the gate itself can influence the behavior of the PCM, i.e., of each individual memristive memory cell, and thus, depending on the wiring of the gates of the majority of the individual memristive memory cells, also within the memristor memory device.

[0016] The term “volatile modulation” – especially that induced by the gate – can refer to forced changes in the specific resistance of a memristive memory cell device due to an applied gate voltage.

[0017] The term “non-ideal conductivity modulations” can refer to effects in PCM-based devices, e.g., a memristor storage device which has a plurality of memristive memory cells in which the PCM is used, due to temperature-based effects and resistance drift effects.

[0018] The term "resistance drift" describes a phenomenon whereby the resistivity of the amorphous phase of phase-change materials—e.g., chalcogenide—increases over time. Drift can be caused by structural relaxation and stress reduction in the amorphous matrix of the PCM and is particularly detrimental in multi-level cell storage devices due to random fluctuations in the programmed resistance of closely spaced levels. Despite the use of adaptive level thresholds, the bit error rate in MLC PCM deteriorates over time because the noise margin between adjacent levels typically increases. This is because drift is a random process, and thus the increase in the resistance of each cell occurs stochastically. Furthermore, the rate of increase, i.e., the drift exponent, is itself a random variable.Although it is true that the mean drift exponent increases with cell resistance, significant fluctuations around the mean values ​​are typically observed. As a result, a small number of cells from each resistance distribution exhibit a noticeably different drift exponent than the rest. The drift trajectories against time of two such cells, programmed, for example, in adjacent levels "2" and "3", may eventually converge and eventually intersect at later times, due to the drift exponents deviating from the mean behavior, even though the cell levels were significantly separated after programming.

[0019] The term "drifting of resistance due to thermal disturbance" can describe the undesirable effect of thermal changes in memristic memory cells, namely, changing the state of one cell by programming another cell in its vicinity. This is relevant for PCMs, as they are family-based and utilize state changes, which, in small device dimensions, can cause thermal disturbances between adjacent cells. These disturbances in resistance states can also result from fluctuations in chip temperature due to thermal changes in the environment.

[0020] The term "filamentary memristor" can refer to the memristive switching effects in insulating or semiconducting solid electrolytes, which occur through the formation of conductive channels (filaments).

[0021] The term "crossbar array" can refer to a structure of electrically conductive lines that intersect. Horizontal lines can define word lines, while vertically oriented lines can be called bit lines. Each intersection of a word line and a bit line can have an electrical or electronic device connected to one end of the word line and the corresponding bit line. In this concept, each intersection has a memristive memory cell, so the crossbar array, which has multiple memristive memory cells, can form a core component of the memristor memory device.

[0022] The term "temperature effect control unit" can refer to an electronic unit that is suitable for counteracting the thermal disturbance effect described above.

[0023] The term "resistance drift correction unit" can refer to an electronic unit suitable for counteracting the resistance drift effect described above, which is present in PCM.

[0024] The proposed memristor storage device, which features a memristive memory cell, can offer several advantages, contributions, and technical effects.

[0025] Primarily, it can lay the foundation for overcoming the current problems of PCM-based memristive storage devices, enabling them to become a viable technology—potentially replacing flash memory—for manufacturing storage and potentially data processing devices in higher volumes. It can increase the reliability of PCM-based storage technology by overcoming negative effects, namely volatile conductivity modulations caused by thermal disturbance and resistive drift effects. In particular, the seemingly stochastic resistive drift effects have a significant negative impact on currently available PCM-based memristive storage devices, which can be overcome with the proposed concept.

[0026] In particular, a gate connection can be used to counteract resistive drift effects. The required additional electronic components, in the form of a temperature compensation unit and a resistive drift compensation unit, are marginal compared to the resulting technical benefits, as demonstrated by experimental evidence. The compensation units can be used for multiple memristor storage devices or even for a larger memristor array comprising multiple memristor storage devices. Specifically, the random process-based resistive drift effect can be exploited by the dynamically adjusted gate signal generated by the resistive drift compensation unit.

[0027] Further embodiments of the memristive storage device, which are also applicable to the corresponding method, are described below.

[0028] According to one embodiment of the memristor memory device, the non-ideal conductivity modulations can include at least time-dependent resistance drift and / or temperature-induced resistance disturbances. These can be the main effects that negatively impact the reliability of memristor memory devices. However, it is possible that by using a gate structure adjacent to the PCM of the memristive memory cell, other non-ideal conductivity modulations could be addressed and potentially mitigated.

[0029] According to one embodiment of the memristor memory, the memristive memory cell can comprise a phase-change material or a filamentary electrolyte. These can be typical examples of PCMs. However, as long as negative temperature effects and / or resistance drift affect the PCM and the device in question, other types of base material for the memristive memory cell can be used to implement the inventive concept proposed here.

[0030] According to a useful embodiment of the memristor storage device, the device can have a plurality of memristive memory cells—particularly two or more—with the gate terminal of the plurality of memristive memory cells being common to that plurality. In an industrial-scale memristor storage device, potentially millions of memristive memory cells can be combined to form the device. At least some of the memristive memory cells can have electrically connected gates. These gates can influence the memristor memory cells connected to a common gate line. Thus, groups of memristor memory cells in the device can be influenced by gate charges to counteract the negative temperature effect and resistance drift.

[0031] According to a useful embodiment of the memristor memory device, the plurality of memristive memory devices can be arranged in a crossbar array, which forms a memristor memory unit. The memristor memory unit can be a core component of the memristor memory device. In this way, the memristive memory cells can be addressed by word lines and bit lines, since one of the memristive memory cells can be located at each intersection of the word lines and the bit lines.

[0032] According to another advantageous embodiment, the memristor storage device can further comprise a temperature effect control unit whose output can be configured to provide a temperature effect control signal corresponding to a temperature difference ΔT between an ideal operating temperature of the memristor storage device and a non-ideal, dynamically changing temperature of the memristor storage device. This signal can advantageously reflect the temperature evolution of the memristor storage device over time, in particular the current temperature during a read operation and the historical temperature evolution since a write operation—i.e., a programming operation. By having access to the temperature evolution over time, the temperature effect control unit can compensate for the effects in question by anticipating the effects related to the temperature evolution over time.

[0033] According to a further advantageous embodiment of the memristor storage device, the temperature effect control unit can further include a temperature sensor electrically connected to the temperature effect control unit and a pre-calibrated ΔT-to-V T,gate -conversion unit which provides a voltage of value V to a group of gate terminals of selected memristor storage devices as the temperature effect control signal T,gate The group can range from a single memristive memory cell to all of them. Advantageously, memristive memory cells exhibiting a closely related temperature dependence can be grouped together. The temperature sensor can generate a signal that depends on the actual temperature of one or more memristor memory devices.

[0034] According to a further improved embodiment of the memristor storage device, the pre-calibrated ΔT-to-V T,gate -Conversion unit further comprises a first digital-to-analog converter for converting a digital temperature effect control signal into the analog value of V T,gate -signal is suitable and is connected to the gate terminals of the majority of memristor storage devices that form a memristor storage unit. Thus, volatile modulations due to a temperature effect of the resistance of groups of memristive memory cells (i.e., devices) can be corrected and / or compensated.

[0035] According to a further advantageous embodiment, the memristor memory device can also include a resistance drift correction unit whose output is suitable for providing a resistance drift control signal corresponding to a resistance difference ΔR between a target resistor of the memristor memory device and a read resistor of the memristor memory device. The read resistor can be measured directly after the programming / writing operation. This can define a reference value for the specific resistance of the corresponding memristive memory cell. Based on this value, a correction or compensation signal for the gate can be generated.

[0036] According to a further improved embodiment of the memristor storage device, the resistance drift correction unit can also perform a ΔR-to-V adjustment. R,gate-conversion unit which, as the resistance drift correction control signal of a group of gate terminals of selected majority of the memristor storage devices, provides a voltage of a value V R,gate provides. Similar to the case of temperature equalization, the group can range from a single memristive memory cell to the entirety of memristive memory cells. Advantageously, those memristive memory cells that exhibit a closely related temperature dependence can be grouped together.

[0037] According to a further improved embodiment of the memristor storage device, the ΔR-to-V R,gate -The conversion unit further comprises a second digital-to-analog converter, which is used to convert a digital resistance-effect control signal into the analog value of the V R,gate-signal suitable and connected to the gate terminals of the majority of memristor storage devices that form a memristor storage unit. Thus, volatile modulations due to a resistance drift effect of the resistance of groups of memristive memory cells can be corrected and / or compensated.

[0038] According to a further embodiment, the memristor storage unit can comprise a plurality of memristor storage devices arranged in a crossbar array, each memristor storage device having a memristive memory cell. The memristor storage device has an input terminal, an output terminal, and a gate terminal—particularly located adjacent to the memristive memory cell—and the input and output terminals can be directly connected to the memristive memory cell. This allows the gate terminal to be electrically isolated from the memristive memory cell, and the gate terminal can be configured to receive electrical signals for transient modulation of the conductivity of the memristive memory cell. This allows the non-ideal conductivity modulations of the memristor storage device to be compensated for.The memristor storage unit can further comprise a temperature-effect control unit, which is suitable for generating a portion of the received electrical signals based on the temperature-based resistance drift effect of each of the memristor storage devices, and a resistance drift correction unit, which is suitable for generating another portion of the received electrical signals based on a time-dependent resistance drift effect of each of the memristor storage devices. Thus, in a memristor storage device comprising multiple memristor storage units, each memristor storage unit can have a separate correction / compensation unit, allowing different areas within the memristor storage device to be treated differently, e.g., based on local differences between the memristor storage units.

[0039] The following is a detailed description of the figures. All instructions in the figures are schematic. First, a block diagram of an embodiment of the inventive memristor storage device, which includes a memristive memory cell, is shown. Subsequently, further embodiments and embodiments of the method for operating a memristor storage device, which includes a memristive memory cell, are described.

[0040] Fig. Figure 1 is a block diagram of an embodiment of the memristor storage device 100, which has a memristive memory cell 102. The memristor storage device (MME) can be based, for example, on PCM or filamentary electrolytes. The memristor storage device 100 has at least one memristive memory cell 102, as well as an input terminal (drain via the electrical connecting line 106) 104, an output terminal (source via the electrical connecting line 110) 108, and a gate terminal 112.

[0041] The input terminal 104 and the output terminal 108 are directly connected to the memristive memory cell 102, with the gate terminal 112 being electrically isolated from the memristive memory cell 102, e.g. by a dielectric (non-conductive) layer 116. The gate terminal 112 is configured to receive – via the line 114 – an electrical signal for a transient modulation of a conductivity of the memristive memory cell, which causes a correction or compensation of non-ideal conductivity modulations of the memristor storage device 102.

[0042] Fig. Figure 2 is a block diagram of the functional principle 200 of the proposed system and method. The memristive memory cell 202—as the core of the memristor memory device—can be programmed by a signal 204. After programming the memristive memory cell to a specific resistance level, the target resistance 206 is known (either by direct reading after programming or, for example, from a reference table). To correct resistance drift effects during read operations, the gate 212 of the memristive memory cell 202 can be used for volatile modulation of the device conductance. This allows the output of the gate V gate proportional to the difference ΔR between the measured resistance and the target resistance. A proportionality constant can be defined to correct drift with varying accuracies. The reference unit 208 can provide the required signal corresponding to the value ΔR. refcorresponds.

[0043] Furthermore, gate 212 can also be used to correct temperature disturbances (temperature-induced drift) on the resistance of the memristive cell 202 during the read process. For this purpose, gate 212 is used for transient modulations of the device conductivity (similar to resistance drift). The output of gate V gate is proportional to the difference ΔT between the temperature of the chip under ideal conditions and the temperature of chip 210 (measured by a sensor) under non-ideal, dynamically changing conditions (e.g., influenced by "programming heat" or other temperature changes in the environment). A proportionality constant can be defined to correct for drift with varying accuracies.

[0044] Thus, both resistance drift and thermal disturbances of the memristive memory cell unit during the read operation can be corrected. Furthermore, all non-ideal conductivity modulations can be corrected and / or compensated for by the effect of the gate signal, regardless of the conductivity state of the PCM of the memristive memory cell 202.

[0045] Fig. Figure 3 is a block diagram of an embodiment of a crossbar array 300 with memristor storage devices 302. The crossbar array 300 has horizontal word lines 304 (only one of which contains a reference number) and vertical bit lines 310 (only one of which contains a reference number) for addressing the majority of the memristor storage devices 302 at their respective intersections. The word lines 304 and the bit lines 310 are used to address the respective memristor storage devices 302. The word lines 304 can be activated by the terminals 306, 308, and 312. Terminals for the bit lines 310 are not explicitly shown. The crossbar array 300 represents an ixj matrix with rows of memristor storage devices 302.

[0046] Furthermore, gate contacts (no reference number) for each memristor storage device 302 are shown. These gate contacts are diagonally connected compared to the word lines 304 and the bit lines 310. The diagonal gate lines (no explicit reference numbers) connect a plurality of the memristor storage devices 302 via diagonally positioned intersections of the word lines 304 and the bit lines 310. Gate voltages can be applied to the gate terminals 314, ..., 320. The respective gate voltage only has an effect on the addressed memristor storage device 302. During a readout, the currents I i a bit line 310 (e.g., using a bias voltage of a few hundred mV) is integrated and converted by an analog-to-digital converter. Column 322 of the memristive elements R ij The resistors on the far right can be implemented as reference resistors.

[0047] Fig. Figure 4 is a block diagram 400 of an embodiment of the crossbar array 300 with temperature disturbance and resistance drift compensation units 402, 404. The output signals of the crossbar array 300 - including the output signal of column 322 (see Figure 4) Fig. 3) the reference resistors - are converted into a differential signal R by the analog-to-digital converter 406 11 -R ij converted, which is fed back to the drag-drift compensation unit 404. Here, a pre-calibrated AR-to-V is used. R,gate -Signal generated, converted by the digital-to-analog converter 408, which is connected to the gate signal unit (control signal unit) 410, in order to control - via the symbolic connection 412 - the respective gate lines in the crossbar array 300 in order to correct the effects of resistance drift during a read operation.

[0048] Furthermore, the temperature correction unit 402 incorporates a temperature sensor and converts the measured temperature of the crossbar array 300 into a signal corresponding to the temperature difference between the measured temperature of the crossbar array 300 and an ideal temperature of the memristive memory cells of the crossbar array 300. This compensates for thermal disturbances that negatively affect the expected resistance level of one or more memristive memory cells of the crossbar array 300. A pre-calibrated ΔT-to-V ratio is also used. T,gate -Conversion is performed, converted by this digital-to-analog converter 414, and leads to the gate signal unit (control signal unit) 410 to control respective gate lines in the crossbar array 300 via the symbolized connections 412.

[0049] Fig. Figure 500 is a diagram of a first experimental proof of the proposed system and method. The x-axis shows the time during which the resistance (y-axis, left side) changes over time. The voltage V is shown on the right y-axis. gate The graph shows the current, and the corresponding change in resistance drift can be observed after approximately 100 seconds. Drift correction using the gate can reduce the drift coefficient by more than three orders of magnitude.

[0050] Fig. Figure 6 shows diagrams 600 of a second experimental proof of the proposed system and method. The top diagram depicts a typical uncorrected resistance drift effect over time. The middle diagram shows the corrected resistance value, which exhibits a drift coefficient of only -0.006. The bottom sub-diagram shows the standard deviation of the drift coefficient of approximately 0.02.

[0051] Thus, the experimental results prove that the method and system proposed here can very effectively address thermal disturbances and resistance drifts for the practical use of memristor storage devices in industrial applications.

[0052] Fig. Figure 7 is a flowchart of an embodiment of Method 700 for operating the memristor storage device, which has a memristive memory cell. Method 700 comprises, in Operation 702, providing the memristor storage device, which has an input terminal, an output terminal, and a gate terminal, wherein the input terminal and the output terminal are directly attached to the memristive memory cell and wherein the gate terminal is electrically isolated from the memristive memory cell.

[0053] The procedure 700 also includes in operation 704 providing an electrical signal for a transient modulation of the conductivity of the memristive memory cell and thereby in operation 706 correcting non-ideal conductivity modulations - as described above - of the memristor storage device.

[0054] The descriptions of the various embodiments are presented for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or the technical improvement over commercially available technologies, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

[0055] The various embodiments can be represented as a system and a process. Aspects of the different embodiments are described herein with reference to flowcharts and / or block diagrams of processes and devices (systems). It is understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0056] The flowcharts and / or block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, processes, and computer program products according to various embodiments of the different implementations. In this regard, each block in the flowcharts or block diagrams can represent a module, segment, or part of instructions, which includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions specified in the block may occur in a different order than shown in the figures. For example, two blocks shown sequentially may, in reality, be executed essentially simultaneously, or the blocks may sometimes be executed in reverse order, depending on the functionality involved.It should also be noted that each block of the block diagrams and / or flowcharts and combinations of blocks in the block diagrams and / or flowcharts can be implemented by systems based on special hardware that perform the specified function or that activate or execute combinations of special hardware and computer instructions.

[0057] The terminology used herein serves only to describe specific embodiments and is not intended to limit the invention. As used herein, the singular forms "a", "an", and "the" are to include the plural forms as well, unless the context clearly indicates otherwise. It is further understood that the terms "shows", "shows", and / or "exhibit", when used in this description, describe the presence of specified features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0058] The corresponding structures, materials, actions, and equivalents of all means or step-plus-function elements in the following claims shall include any structure, material, or action for performing the function in combination with other claimed elements as specifically claimed. The description of the various embodiments serves for illustrative and descriptive purposes but is not intended to be exhaustive or limited to the invention as disclosed. Many modifications and variations will be apparent to the person skilled in the art without deviating from the scope and concept of the invention.The embodiments were selected and described to best explain the principles of the invention and its practical application, and to enable other skilled persons to understand the invention for different embodiments with different modifications suitable for the specific intended use.

Claims

[1] Memristor storage unit comprising a plurality of memristor storage devices (100; 302), each of which comprises: a memristive memory cell (102, 202); an input port (104) and an output port (108) that are directly attached to the memristive memory cell (102, 202); and an electrically isolated gate terminal (112) from the memristive memory cell (102, 202) for volatile gate-induced modulation of a conductivity of the memristive memory cell (102, 202) by receiving electrical signals; the memristor storage unit further comprises: a temperature effect control unit (402) suitable for generating a portion of the received electrical signals based on a temperature-based resistance drift effect of each of the memristor storage devices (100, 302); and / or a resistance drift correction unit (404) which is suitable for generating a different part of the received electrical signals based on a time-dependent resistance drift effect of each of the memristor storage devices (100, 302). [2] Memristor storage unit according to claim 1, wherein the memristive storage cell comprises a phase change material or a filamentary electrolyte; and wherein the electrical signals are electrical signals for correcting non-ideal conductivity modulations of the memristor storage device and the non-ideal conductivity modulations comprise at least one from a time-dependent resistance drift and a temperature-induced disturbance of the resistance. [3] Memristor storage unit according to claim 1 or 2, wherein the gate connection is common to the majority of the memristive memory cells. [4] Memristor storage unit according to one of the preceding claims, wherein the majority of the memristor storage devices (100, 302) are arranged in a crossbar array (300) which forms a memristor storage unit. [5] Memristor storage unit according to one of the preceding claims, wherein an output of the temperature effect control unit (402) is suitable for providing a temperature effect control signal which corresponds to a temperature difference ΔT between an ideal operating temperature of a memristor storage device and a non-ideal dynamically changing temperature of the memristor storage device. [6] Memristor storage unit according to claim 5, wherein the temperature effect control unit (402) further comprises: a temperature sensor which is electrically connected to the temperature effect control unit (402); and a pre-calibrated ΔT-to-V T,gate-Conversion unit, which provides a voltage of a value V to a group of gate terminals of selected majority of memristor storage devices as the temperature effect control signal. T provides. [7] Memristor storage unit according to claim 6, wherein the pre-calibrated ΔT-to-V T,gate -conversion unit further features: a first digital-to-analog converter (414) which is suitable for converting a digital temperature effect control signal into the gate signal with the analog value V T to convert, connected to the gate terminals of the majority of memristor storage devices that form a memristor storage unit. [8] Memristor storage unit according to one of the preceding claims, wherein an output of the resistance drift correction unit (404) is suitable for providing a resistance drift control signal which corresponds to a resistance difference ΔR between a target resistor of a memristor storage device and a read resistor of this memristor storage device. [9] Memristor storage unit according to claim 8, wherein the resistance drift correction unit (404) further comprises: a ΔR-to-V R,gate -Conversion unit, which provides a voltage of a value V to a group of gate terminals of selected majority of memristor storage devices as the resistance drift correction signal R provides. [10] Memristor storage unit according to claim 9, wherein the ΔR-to-V R,gate -conversion unit further features: a second digital-to-analog converter (408) which is suitable for converting a digital resistance-effect control signal into the other gate signal with the analog value V R to convert, connected to the gate terminals of the majority of memristor storage devices that form a memristor storage unit. [11] Method (700) for operating a memristor storage unit comprising a temperature effect control unit (402), a resistance drift correction unit (404) and a plurality of memristor storage devices (100; 302), each of which comprises: a memristive memory cell (102, 202), an input terminal (104), an output terminal (108) and a gate terminal (112) for volatile gate-induced modulation of a conductivity of the memristive memory cell by receiving electrical signals, wherein the input terminal and the output terminal are directly attached to the memristive memory cell and the gate terminal is electrically isolated from the memristive memory cell; the procedure includes: Providing (704) electrical signals for the volatile gate-induced modulation of a conductance of the memristive memory cell at its gate terminal, wherein a portion of the provided electrical signals is generated by the temperature effect control unit (402) based on a temperature-based resistance drift effect of the memristor memory device comprising the memory cell, and / or another portion of the provided electrical signals is generated by the resistance drift correction unit (404) based on a time-dependent resistance drift effect of the memristor memory device comprising the memory cell. [12] The method of claim 11, further comprising: Providing a temperature effect control signal, corresponding to a temperature difference ΔT between an ideal operating temperature of the memristor storage device and a non-ideal dynamically changing temperature of the memristor storage device, by the temperature effect control unit. [13] Method according to claim 12, wherein the temperature effect control unit further comprises a temperature sensor which is electrically connected to the temperature effect control unit, wherein the method further comprises: Providing a voltage of a value V T,gate to the gate terminal as the temperature effect control signal via a pre-calibrated ΔT-to-V T,gate -Conversion unit. [14] The method of claim 13, wherein the method further comprises: Converting a digital temperature effect control signal into the gate signal with the analog value V T,connected to the gate terminal, by a first digital-to-analog converter (414) which is part of the pre-calibrated ΔT-to-V T,gate -Conversion unit is. [15] Method according to any one of claims 11 to 13, further comprising: Providing a resistance drift control signal, corresponding to a resistance difference ΔR between a target resistor of the memristor storage device and a read resistor of this memristor storage device, by the resistance drift correction unit. [16] The method of claim 15, further comprising: Providing a voltage of a value V R to the gate terminal as the resistance drift correction control signal via a ΔR-to-V R,gate -Conversion unit, which is part of the resistance drift correction unit. [17] Method according to claim 16, wherein the ΔR-to-V R,gate The conversion unit further includes: Converting a digital resistance-effect control signal into the other gate signal with the analog value V R , connected to the gate terminal, by a second digital-to-analog converter (408). [18] Method according to any one of claims 11 to 17, wherein the memristive storage cell comprises a phase change material or a filamentary electrolyte. [19] Method according to any one of claims 11 to 18, wherein the gate connection is jointly assigned to the majority of the memristive memory cells. [20] Method according to any one of claims 11 to 18, wherein the electrical signals are provided to correct non-ideal conductivity modulations of the memristor storage device.

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