Resistive storage unit with resistively switching storage cell and method for manufacturing

Abstract

Resistive storage unit comprising: a first electrode (146, 148); a first resistive structure (130) in contact with the first electrode (146, 148); a dielectric layer (128) in contact with the first resistive structure (130); a second resistive structure (124, 125) in contact with the dielectric layer (128), wherein the second resistive structure (124, 125) comprises a layer (124) of resistive material and a core (125) of metal with high work function, both in contact with the dielectric layer (128), the core (125) of metal with high work function having a work function of > 4.9 eV; and a second electrode (112, 114) in contact with the second resistive structure (124, 125).

Description

BACKGROUNDThe present disclosure relates generally to manufacturing methods and obtained semiconductor-based electronic device structures. More particularly, the present disclosure relates to a resistive random access memory (ReRAM) cell structure with an integrated access transistor and high density design for neuromorphic data processing, wherein the ReRAM cell has decreased program voltages.ReRAM structures may be used as a type of non-volatile (NV) memory (RAM) in computing resources. ReRAM devices have a simple metal-insulator-metal structure that exhibits promising characteristics in terms of scalability, low power operation, and multi-level data storage capability, such that they may be suitable for next generation memory applications. A ReRAM usually operates by controlled resistance changes across a solid state dielectric material. The solid-state dielectric material may be referred to as a memristor. ReRAM can be considered a promising technology for synapse electronic devices (or memristors) for neuromorphic data processing and for high density, high speed non-volatile memory applications. In neuromorphic computing applications, a resistive memory device may be used as a connection (synapse) representing the connection weight in the form of resistance of the device between a pre-neuron and a post-neuron. Multiple pre-neurons and post-neurons may be connected by a crossbar array of ReRAMs, which may allow a fully connected neural network.Oxygen vacancies in a metal oxide layer of a ReRAM unit are the building blocks of a current-conducting filament. Therefore, it may be desirable to form ReRAM cells without introducing damage to an surrounding area thereof. Further, it may be desirable to form ReRAM cells with a robust encapsulation to prevent oxygen ingress in subsequent processes.US 2017 / 0 271 590 A1 relates to a semiconductor structure having a memory region. A memory structure is arranged on the memory area. The memory structure includes a first electrode, a variable resistance layer, a protective material, and a second electrode. The first electrode has an upper surface on the storage region. The variable resistance layer includes at least a first portion and a second portion. The first portion is disposed over the top of the first electrode, and the second portion extends upwardly from the first portion. The protective material surrounds the second portion of the variable resistance layer. The protective material is configurable to protect at least one conductive path in the variable resistance layer. The second electrode is disposed over the variable resistance layer.US 2020 / 0 106 011 A1 relates to an integrated chip comprising: one or more lower interconnect layers arranged in a dielectric structure over a substrate; a lower electrode arranged over one of the one or more lower interconnect layers, a lower surface of the lower electrode comprising a material having a first electronegativity; a data storage layer separating the lower electrode from an upper electrode; and a reactivity reducing layer contacting the lower surface of the lower electrode and having a second electronegativity greater than or equal to the first electronegativity.US 2013 / 0 248 809 A1 relates to a variable resistance element comprising a first electrode, a second electrode, and a variable resistor containing a metal oxide, the variable resistance being allowed between the first and second electrodes, the electrical resistance between the first and second electrodes being reversibly changed in response to application of an electric voltage between the first and second electrodes, the metal oxide comprising a current path in which the current density of a current flowing between the first and second electrodes is locally high, the resistivity of at least one specific electrode having a higher resistivity than the first electrode and the second electrode is 100 μΩcm or more, and a dimension of a contact area of the specific electrode having the variable resistance in a short side direction or a short axis direction is more than 1.4 times as long as a film thickness of the specific electrode.US 2017 / 0 250 222 A1 relates to a variable resistance memory device comprising: a selection pattern; an intermediate electrode contacting a first surface of the selection pattern; a variable resistance pattern on a side of the intermediate electrode opposite the selection pattern; and a first electrode contacting a second surface of the selection pattern and comprising an n-type semiconductor material, wherein the second surface of the selection pattern is opposite the first surface thereof.US 8 420 478 B2 relates to a method for forming a resistive switching memory element, comprising: forming a first electrode; forming a metal oxide layer on the first electrode; masking the metal oxide layer to form exposed regions and buried regions of a surface of the metal oxide layer; and altering the exposed regions of the metal oxide layer and forming localized defect paths below the exposed regions.US 2020 / 0 259 081 A1 relates to a self-aligned memory device comprising: a conductive bottom plug disposed within an insulating layer and having a coplanar top surface; a self-aligned planar bottom electrode disposed on the coplanar top surface and having a thickness in the range of 5.0 nm to 20.0 nm; a planar switching material layer disposed on the self-aligned planar bottom electrode; a planar active metal material layer disposed on the planar switching material layer; and a planar top electrode disposed over the planar active metal material layer, wherein the self-aligned planar bottom electrode, the planar switching material layer, the planar active metal material layer, and the planar top electrode form a columnar structure over the insulating layer. The object is to improve corresponding storage devices.SUMMARYThe object is achieved by the resistive memory unit according to claim 1 and the method for manufacturing a resistive memory unit according to claim 11.A resistive random access memory (ReRAM) device includes a first electrode, a first resistive structure in contact with the first electrode, a dielectric layer in contact with the first resistive structure, and a second resistive structure in contact with the dielectric layer. The second resistive structure includes a layer of resistive material and a core of high work function metal. Further, the ReRAM device includes a second electrode in contact with the second resistive structure.A method of manufacturing a resistive random access memory (ReRAM) device includes forming a first electrode, forming a first resistive structure in contact with the first electrode, forming a dielectric layer in contact with the first resistive structure, and forming a second resistive structure in contact with the dielectric layer, the second resistive structure including a layer of resistive material and a core of high work function metal. Further, the method includes forming a second electrode in contact with the second resistive structure.The foregoing summary is not intended to describe each illustrated embodiment or implementation of the present disclosure.BRIEF DESCRIPTION OF THE DRAWINGSThe drawings included in the present application are incorporated in and constitute a part of the specification. They illustrate embodiments of the present disclosure and together with the description explain the principles of the disclosure. FIG. 1 is a cross-sectional view of a ReRAM device at an intermediate stage of the fabrication method according to embodiments. FIG. 2 is a cross-sectional view of the ReRAM package of FIG. 1 at a subsequent stage of the fabrication method according to embodiments. FIG. 3 is a cross-sectional view of the ReRAM package of FIG. 2 at a subsequent stage of the fabrication method according to embodiments. FIG. 4 is a cross-sectional view of the ReRAM device of FIG. 3 at a subsequent stage of the fabrication method according to embodiments. FIG. 5 is a cross-sectional view of the ReRAM device of FIG. 4 at a subsequent stage of the fabrication method according to embodiments. FIG. 6 is a cross-sectional view of the ReRAM device of FIG. 5 at a subsequent stage of the fabrication method according to embodiments. FIG. 7 is a cross-sectional view of the ReRAM package of FIG. 6 at a subsequent stage of the fabrication method according to embodiments. FIG. 8 is a cross-sectional view of the ReRAM device of FIG. 7 at a subsequent stage of the fabrication method according to embodiments. FIG. 9 is a cross-sectional view of the ReRAM device of FIG. 8 at a subsequent stage of the fabrication method according to embodiments. FIG. 10 is a cross-sectional view of the ReRAM package of FIG. 9 at a subsequent stage of the fabrication method according to embodiments.DETAILED DESCRIPTIONThe present disclosure relates generally to manufacturing methods and obtained semiconductor-based electronic device structures. More particularly, the present disclosure relates to resistive random access memory (ReRAM) cell structures with an integrated access transistor and high density design that can be used in neuromorphic data processing applications and methods of making such ReRAM devices.The flow charts and cross-sectional diagrams in the figures illustrate methods for manufacturing ReRAM devices according to various embodiments. In some alternative implementations, the fabrication steps may proceed in a different order than that indicated in the figures, and certain additional fabrication steps may be implemented between the steps indicated in the figures. Furthermore, each of the layer structures illustrated in the figures may include a plurality of sub-layers.Herein, various embodiments of the present disclosure will be described with reference to the corresponding drawings. It should be noted that in the following description and drawings, various connections and positional relationships (e.g., above, below, adjacent, etc.) are indicated. These connections and / or positional relationships may be direct or indirect unless otherwise indicated. Accordingly, a coupling of entities may refer to a direct or an indirect coupling, and a positional relationship between entities may be a direct or an indirect positional relationship. As an example of indirect positional relationship, references in the present specification to forming layer "A" over layer "B" include situations where one or more intermediate layers (e.g., layer "C") are present between layer "A" and layer "B", as long as the relevant characteristics and functionalities of layer "A" and layer "B" are not substantially altered by the intermediate layer(s).The following definitions and abbreviations are to be used for the interpretation of the claims and the description. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "have," "contains," and "containing," and any other variations thereof, are intended to cover non-exclusive inclusion. For example, a composition, mixture, method, method, article, or device having / having a list of elements is not necessarily limited to only those elements, but may also contain other elements not expressly listed or inherent to that / composition, mixture, method, method, article, or device.For purposes of the following description, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof are intended to refer to the described structures and methods as oriented in the drawings of the figures. The terms "overlying", "on", "arranged on", and "arranged on top" mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interfacial structure, may be present between the first element and the second element. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without intervening conductive, insulating or semiconducting layers. It should be noted that the term "selective to", such as "a first element selective to a second element", means that a first element may be etched and the second element may act as an etch stop.For brevity, conventional methods associated with the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Further, the various tasks and method steps described herein may be incorporated into a more comprehensive method or method having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, so that, for brevity, many conventional steps may be mentioned herein only briefly or omitted altogether without describing the well-known details of the methods.The various methods used to fabricate a microchip that will be packaged into an IC generally fall into four general categories, namely, thin film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any method that grows, layers, or otherwise transfers a material onto the wafer. Available technologies include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and current atomic layer deposition (ALD). Removal / etching is any method that removes material from the wafer. Examples include etching (wet or dry) and chemical mechanical planarization (CMP), and the like. Semiconductor doping is modifying electrical properties by doping, for example, sources and drains of transistors, generally by diffusion and / or ion implantation. These doping methods are followed by oven annealing or rapid heat annealing (RTA). Annealing serves to activate the implanted dopants. Thin films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of different regions of the semiconductor substrate enables changing the conductivity of the substrate by applying voltage. By creating structures from these various components, millions of transistors can be built and wired together to form the complex circuit of a modern microelectronic device. Semiconductor lithography is the formation of three-dimensional relief images or structures on the semiconductor substrate for the subsequent transfer of the structure to the substrate. In semiconductor lithography, the structures are formed by a photosensitive polymer called "photoresist". To build up the complex structures that form a transistor and the multiple wires that connect the millions of transistors of a circuit, lithography and etch structure transfer steps are repeated multiple times. Each pattern printed on the wafer is aligned with the previously formed patterns and the conductors, insulators and selectively doped regions are slowly built into the final unit.Turning now to an overview of technologies more specifically relevant to aspects of the present disclosure, in neuromorphic computing applications, a resistive memory device (e.g., a ReRAM device) may be used as a connection (synapse) representing the connection weight in the form of resistance of the device between a pre-neuron and a post-neuron.Multiple pre-neurons and post-neurons may be connected by a crossbar array of RRAMs, thus embodying a fully connected neural network.An RRAM crossbar array may be fabricated in conjunction with resistively switching material formed on the bottom electrodes. The top electrodes are formed on the resistive switching material interconnect to form a crossbar array of RRAMs.Nonvolatile, resistively switching metal oxides, such as HfO x, TaO x and TiO x, are integrated into nanocrossbar arrays and nanocross points defined by lithography methods. This allows a fast manufacturing path for prototype high density test structures of two-port passive memory cores. The structures and integrated material are electrically characterized to gain insight into the general characteristics of nanocrossbar arrays with resistively switching metal oxides and to define the requirements for an external CMOS control system.Non-volatile and resistively switching two-state materials, such as HfO 2, are integrated as two-terminal memory units to effectively produce a ReRAM bit pattern. These cells can be integrated into crossbar arrays. The switching material present at each connection at a crosspoint is a addressable cell of a ReRAM. Since the array is made up of passive elements, additional active external circuitry is required for operation to address the cells, set and reset their state, and read the stored information.Artificial neural networks (ANNs) may be formed from crossbar arrays of resistive processing units (RPUs) that provide local data storage and local data processing without the need for additional processing elements beyond the RPU. The trainable resistive crosspoint devices are referred to as RPUs.The neurons are integrated into CMOS circuits with a crossbar array of units storing a matrix. The input neurons form a neural network together with the hidden neuron layers and the output neurons. Input signals can be passed forward and backward through the network and can also be used to update the weights in the matrix.Crossbar (cross point) arrays are high density, low cost circuit architectures used for various electronic circuits and devices, including ANN architectures, neuromorphic microchips, and ultra high density nonvolatile memories. A basic configuration of a crossbar array includes a set of conductive row wires and a set of conductive column wires configured to overlap the set of conductive row wires. The crossing points between the two sets of wires are separated by so-called cross point units, which may be formed of thin film material. Indeed, cross point units act as the weighted connections of the ANN between neurons. Two terminal nano-scale units, for example memristors having conductivity state switching properties, are often used as the cross point units to mimic synaptic plasticity with high energy efficiency. The conductivity state (e.g., resistance) of the resistive material may be varied by controlling the voltages applied between individual wires of the row and column wires.The resistive processing unit (RPU) may further improve the functionality of neuromorphic data processing. The new class of devices (RPU) can be used as processing devices to speed up various algorithms, including neural network training.In certain of the present embodiments, the ReRAM devices include a metal oxide layer disposed between an upper electrode and a lower electrode (i.e., a metal-insulator-metal structure). Oxygen vacancies in the metal oxide layer allow electrical formation of a current conducting filament (CF) therein. In many ReRAM devices, the mechanism that allows for information storage relies on forming and interrupting this CF formed between the two electrodes, with the result of repeatable resistive switching between high resistance states (HRS) and low resistance states (LRS). As for the CF, when an oxide metal is sandwiched between two electrodes and a sufficient positive voltage is applied to the upper electrode, the CF will form between the two electrodes, with the result of a low resistance state. On the other hand, when a sufficient negative voltage is applied to the lower electrode, the CF breaks and a high resistance state is produced. In certain embodiments of the oxide ReRAM device, the formation of the CF is triggered by field assisted oxygen ion migration, resulting in a change in the electronic conductivity (or resistivity) of the switching unit as discussed above. For oxide ReRAM devices, electrical forming of the CF is required.The method of forming the conductive filament may be associated with some degree of randomness, and the position of the filament produced cannot always be well controlled. This may result in the need for a higher forming voltage when scaling the ReRAM cell, which may result in higher unit variability. For certain ReRAM devices, Si implantation may be used by the reactive ion etching (RIE) process of pillars, which may allow a substantial reduction in CF forming voltage.Referring now to the drawings, wherein like numerals designate like or similar elements, first FIG. 1 shows a cross-sectional view of a ReRAM device at an intermediate stage of the fabrication process, in accordance with certain embodiments. As shown in FIG. 1, the ReRAM device 100 includes a substrate 102. The semiconductor substrate 102 may include any semiconductor material having semiconducting properties. The semiconductor material providing the semiconductor substrate 102 may include, for example, silicon (Si), germanium (Ge), a silicon-germanium alloy (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), a III-V compound semiconductor, or a II-VI compound semiconductor. Shallow trench isolation (STI) regions 104 are formed in the substrate 102 to isolate one transistor from another transistor. A source region 106 and a drain region 108 are formed, which are doped regions of the silicon substrate 102. A gate electrode 116 is formed in a region between the source region 106 and the drain region 108 on the substrate 102. A dielectric spacer 118 is formed around the gate electrode 116. The dielectric spacer 118 may include SiN or another suitable type of dielectric material. A first interlayer dielectric (ILD) layer 110 is formed on the substrate 102 over the STI regions 104, the source region 106, the drain region 108, and the dielectric spacer 118. Although not shown in FIG. 1, through-holes are formed in the first ILD layer 110 to accommodate the fabrication of lower electrodes that include a through-hole cladding layer 112 and a through-hole core 114. The via liner layer 112 may include TaN or TiN or any other suitable material. The through-hole core 114 may include W, for example. After forming the bottom electrodes, the ReRAM device 100 may be subjected to chemical mechanical planarization (CMP) to planarize the top surface of the device. Subsequently, a first SiN layer 120 is formed on the upper surface of the first ILD layer 110 and the upper surfaces of the through-hole cores 114.FIG. 2 shows a sectional view of the ReRAM unit 100 of FIG. 1 at a subsequent stage of the manufacturing method according to embodiments. As shown in FIG. 2, a through hole 122 is formed in the first SiN layer 120. The through hole 122 may be formed by an RIE process or any other suitable material removal process.FIG. 3 shows a cross-sectional view of the ReRAM package of FIG. 2 at a subsequent stage of the fabrication method according to embodiments. As shown in FIG. 3, a trim layer 124 is formed to partially fill the through hole 122. The cladding layer 124 may comprise TiN or another suitable material. The material of the trim layer 124 may be the same material as that of the through-hole trim layer 112 described above with reference to FIG. 1, or may be a different material. Because the cladding layer 124 is configured to only partially fill the through hole 122, a space remains that allows the high WF metal layer 125 to be formed. This can be seen by embedding (or forming) the high WF metal layer 125 (or the high work function metal core (WF)) in the cladding layer 124 (or resistive material layer). That is, certain methods of fabricating a ReRAM device include filling a portion of the through hole (or through hole 122) with the high resistive material layer (or cladding layer 124) and then filling a remaining portion of the through hole 122 with the high work function metal core (or high WF metal layer 125) at a center of the first resistive structure (i.e., a combination of the cladding layer 124 and the high WF metal layer 125). The high WF metal layer 125 may be, for example, Ru or any other suitable high WF material (e.g., > 4.9 eV), such as Ir or Pt. After forming the high WF metal layer 125, the ReRAM device 100 may be subjected to a CMP process to planarize the structure. As shown in FIG. 3, a width of the high WF metal layer 125 is smaller than the width of the through hole core 114. As described in more detail herein, the structure and material of the high WF metal layer 125 (e.g., the narrow width) enhances the electric field near the bottom electrode, via core 114, during electroforming and facilitates CF formation near the center of the device. Thus, problems associated with the randomness of CF formation discussed above can be alleviated or eliminated.FIG. 4 shows a cross-sectional view of the ReRAM unit 100 of FIG. 3 at a subsequent stage of the manufacturing method according to embodiments. As shown in FIG. 4, a metal oxide layer 128 is first formed over the entire ReRAM device 100. The metal oxide layer 128 may comprise HfO 2 or any other suitable metal oxide material or combination of metal oxide materials. Over the entire surface of the metal oxide layer 128, an upper electrode 130 is formed. The top electrode 130 may comprise TiN or any other suitable material. The material of the upper electrode 130 may be the same material as or different from that of the through-hole cladding layer 112 and / or the cladding layer 124. A hard mask 132 is then deposited over the entire surface of the top electrode 130. The hard mask 132 may include SiN or any other suitable material. Depositing the material of the hard mask 132 may include any deposition method, such as chemical vapor deposition or plasma enhanced chemical vapor deposition.FIG. 5 shows a cross-sectional view of the ReRAM unit 100 of FIG. 4 at a subsequent stage of the manufacturing method according to embodiments. As shown in FIG. 5, etching is performed on the hard mask layer 132, the top electrode 130, and the metal oxide layer 128 to pattern these layers into a ReRAM pillar. In certain examples, to facilitate manufacturing integration, the width of the patterned hard mask layer 132, the top electrode 130, and the metal oxide layer 128 may be slightly greater than the width of the bottom electrode structure to prevent unwanted etching of the liner layer 124.FIG. 6 shows a cross-sectional view of the ReRAM package of FIG. 5 at a subsequent stage of the fabrication method according to embodiments. As shown in FIG. 6, additional material (e.g., SiN) is added to expand the hard mask 132 and form an encapsulation layer over the entire surface of the ReRAM device 100. The hard mask 132 may include, for example, SiN or any other suitable material. A second ILD layer 136 may then be deposited over the entire surface of the hard mask 132. Note that although the hardmask 132 is shown as a single layer, a separate encapsulation layer (i.e., of a different material than that of the hardmask 132) may be formed over the hardmask 132. The second ILD layer 136 may include. In certain embodiments, after forming the second ILD layer 136, the ReRAM device 100 is subjected to a CMP process to planarize the surface of the device.FIG. 7 shows a cross-sectional view of the ReRAM package of FIG. 6 at a subsequent stage of the fabrication method according to embodiments. As shown in FIG. 7, a contact via 138 is formed by etching through the second ILD layer 136 and the hard mask 132. The contact via 138 may provide space for forming the upper electrode.FIG. 8 shows a cross-sectional view of the ReRAM device of FIG. 7 at a subsequent stage of the fabrication method according to embodiments. As shown in FIG. 8, the upper electrode includes an upper electrode via cladding layer 146 and an upper electrode via core 148. The top electrode via liner layer 146 may include TaN or TiN or any other suitable material. The upper electrode through hole core 148 may include, for example, W. After forming the top electrode, the ReRAM device 100 may be subjected to chemical mechanical planarization (CMP) to planarize the top surface of the device.FIG. 9 shows a cross-sectional view of the ReRAM unit of FIG. 8 at a subsequent stage of the manufacturing method according to embodiments. As shown in FIG. 9, a second SiN layer 150 is deposited over the entire surface of the ReRAM device 100. Subsequently, a peripheral contact via 152 is formed by etching through the second SiN layer 150, the second ILD layer 136, the hard mask 132, and the first SiN layer 120 to expose the via core 114.FIG. 10 shows a cross-sectional view of the ReRAM package of FIG. 9 at a subsequent stage of the fabrication method according to embodiments. As shown in FIG. 10, after forming the peripheral contact via 152, a peripheral contact via cladding layer 154 is deposited. The peripheral contact via liner layer 154 may include TaN or TiN or any other suitable material. The core 156 of the contact peripheral via may include, for example, W. After forming the peripheral contact, additional material is added to the second SiN layer 150 to cover the upper surface of the core 156 of the peripheral contact via hole. In certain examples, the ReRAM device 100 may then be subjected to chemical mechanical planarization (CMP) to planarize the top surface of the device.By having a layer of the high work function metal core smaller in width than the lower electrode, the location of forming the conductive filament (CF) can be controlled to correspond to this location, thereby eliminating some randomness of the location of CF formation. Further, by making the conductive filament localized (or centralized), the amount of voltage that must be applied to change the resistance state from a high resistance state to a low resistance state can be reduced.In the above-described embodiments, the layer of the core of high work function metal is described as being formed in the lower electrode (i.e., the electrode closest to the underlying substrate). However, it should be appreciated that in other embodiments, the high WF metal core layer may be formed in the top electrode or in both the top and bottom electrodes.

Claims

A resistive memory device comprising: a first electrode (146, 148); a first resistive structure (130) in contact with the first electrode (146, 148); a dielectric layer (128) in contact with the first resistive structure (130); a second resistive structure (124, 125) in contact with the dielectric layer (128), the second resistive structure (124, 125) including a layer (124) of resistive material and a core (125) of high work function metal both in contact with the dielectric layer (128), the core (125) of high work function metal having a work function > 4.9 eV; and a second electrode (112, 114) in contact with the second resistive structure (124, 125).The resistive memory device of claim 1, wherein the high work function metal core (125) comprises at least one selected from the group consisting of Ru, Ir, and Pt.The resistive memory device of claim 1, wherein the high work function metal core (125) has a width that is less than a width of the first electrode (146, 148) and a width of the second electrode (112, 114).The resistive memory device of claim 3, wherein the high work function metal core (125) is disposed in a center of the second resistive structure (124, 125).The resistive memory device of claim 1, wherein the high work function metal core (125) is embedded in the resistive material layer (124).The resistive memory device of claim 1, wherein the dielectric layer (128) comprises a metal oxide material.The resistive memory device of claim 6, wherein the metal oxide material is HfO 2.The resistive memory device of claim 1, wherein an interface between the high work function metal core (125) and the dielectric layer (128) has a width that is less than a width of an interface between the first resistive structure (130) and the dielectric layer (128) and / or a width of an interface between the second resistive structure (124, 125, respectively) and the dielectric layer (128).The resistive memory device of claim 1, further comprising an encapsulation layer formed over the first electrode (146, 148), and an interlayer dielectric layer (136) formed over the encapsulation layer.The resistive memory device of claim 1, wherein the first electrode (146, 148) and the second electrode (112, 114) each include a cladding layer (146, 112, 112, respectively) and a through-hole core (148, 114, respectively) formed on the cladding layer.A method of manufacturing a resistive memory device, comprising: forming a first electrode (112, 114); forming a first resistive structure (124, 125) in contact with the first electrode (112, 114); forming a dielectric layer (128) in contact with the first resistive structure (124, 125); forming a second resistive structure (130) in contact with the dielectric layer (128); and forming a second electrode (146, 148) in contact with the second resistive structure (130), wherein the first resistive structure (124, 125) includes a layer (124) of resistive material and a core (125) of high work function metal both in contact with the dielectric layer (128), wherein the core (125) of high work function metal has a work function > 4.9 eV.The method for manufacturing the resistive memory device according to claim 11, wherein the high work function metal core (125) includes at least one selected from the group consisting of Ru, Ir, and Pt.The method of manufacturing the resistive memory device of claim 11, wherein the high work function metal core (125) has a width that is less than a width of the first electrode (112, 114) and a width of the second electrode (146, 148).The method of manufacturing the resistive memory device of claim 11, wherein the high work function metal core (125) is embedded in the resistive material layer (124).The method of manufacturing the resistive memory device of claim 11, wherein the dielectric layer (128) comprises a metal oxide material.The method of manufacturing the resistive memory device of claim 15, wherein the metal oxide material is HfO 2.The method of manufacturing the resistive memory device of claim 11, further comprising forming an encapsulation layer over the second resistive structure (130) and forming an interlayer dielectric layer (136) over the encapsulation layer.The method for manufacturing the resistive memory device according to claim 11, wherein the first electrode (112, 114) and the second electrode (146, 148) each include a cladding layer (112, 146, respectively) and a through-hole core (114, 148, respectively) formed on the cladding layer (112, 146, respectively).

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