Magnetoresistive two-bit random access memory cell

Abstract

Two-bit MRAM cell based on spin-orbit torque, wherein the two-bit MRAM cell has: a first layer of heavy metals; a first magnetic tunnel junction connected to the first heavy metal layer, wherein the first magnetic tunnel junction has a first cross-sectional area; a second magnetic tunnel junction connected in series with the first magnetic tunnel junction, wherein the second magnetic tunnel junction has a second cross-sectional area that is different from the first cross-sectional area, wherein the second magnetic tunnel junction has a common reference layer with the first magnetic tunnel junction, wherein the first magnetic tunnel junction is stacked on top of the second magnetic tunnel junction, and wherein a difference in the first and second cross-sectional areas ensures that four unique resistive states exist for the stacked magnetic tunnel junctions; and a second heavy metal layer connected to the second magnetic tunnel junction, wherein: the first heavy metal layer is connected via a first transistor to a first word line and a bit line; the second heavy metal layer is connected via a second transistor to a second word line and the bit line; the first heavy metal layer is connected via a third transistor to a third word line and a source line; and the second heavy metal layer is directly connected to the source line.

Description

BACKGROUND

[0001] The present disclosure relates to the fields of electrical engineering, electronics, and computing. In particular, the present disclosure relates to magnetoresistive two-bit direct-access memory cells (two-bit MRAM cells) comprising three transistors, and methods for their manufacture.

[0002] MRAM is a type of non-volatile memory used in computers and other electronic devices to store data. Unlike conventional read-access memory (e.g., dynamic read-access memory (DRAM)), which stores data as electrical charges or current flows (e.g., using capacitors), MRAM stores data in magnetic domains using magnetic memory elements. These magnetic memory elements consist of two ferromagnetic disks, each capable of holding a magnetization, separated by an insulating layer. The magnetization of the disk can then be changed to match that of an external field to store data.

[0003] In this context, document US 2019 / 0334080A1 already exists. This document describes a memory cell, an array of memory cells, a method for manufacturing them, and a method for operating the memory cell. The memory cell comprises: a first cell electrode, a first insulating layer, and a first magnetically free layer between the first cell electrode and the first insulating layer. Furthermore, the memory cell comprises a second cell electrode, a second insulating layer, and two magnetically free layers between the second cell electrode and the second insulating layer. A magnetically pinned layer may be located between the first insulating layer and the second insulating layer.

[0004] Despite these advances, there is still a need to improve the function of MRAM cells and, in particular, to optimize the control options. SUMMARY

[0005] This task is solved by the subject matter of the independent patent claims. Further details arise from the respective dependent patent claims.

[0006] Embodiments of the present disclosure comprise a magnetoresistive random-access memory cell (MRAM cell). The MRAM cell has a first heavy metal layer and a first magnetic tunnel junction (MTJ) connected to the first heavy metal layer. The first MTJ has a first surface. The MRAM cell further comprises a second MTJ. The second MTJ is connected in series with the first MTJ, and the second MTJ has a second surface that is different from the first surface. The second MTJ has a common reference layer with the first MTJ. The MRAM cell further comprises a second heavy metal layer connected to the second MTJ.

[0007] Further embodiments of the present disclosure include a method for forming a two-bit MRAM cell. The method includes forming a second heavy metal layer. The method further includes forming an MTJ stack. The MTJ stack comprises a first MTJ having a first surface and a second MTJ having a second surface that is different from the first surface. The second MTJ is formed over the second heavy metal layer. The first and second MTJ share a common reference layer. The method further includes forming a first heavy metal layer over the first MTJ.

[0008] Further embodiments of the present disclosure include a method, a system, and a computer program product for programming a two-bit MRAM cell. The method comprises receiving a write command for programming a first bit in the two-bit MRAM cell. The two-bit MRAM cell has a first MTJ in series with a second MTJ, wherein: an area of ​​the first MTJ is different from an area of ​​the second MTJ; the first MTJ is connected to a first heavy metal layer; the first heavy metal layer is connected to a bit line using a first transistor; the first heavy metal layer is connected to a source line using a second transistor; the second MTJ is connected to a second heavy metal layer; the second heavy metal layer is connected to the bit line using a third transistor; and the second heavy metal layer is directly connected to the source line.The method further includes determining that the first bit is to be stored in a specific MTJ. The specified MTJ is one of the first MTJ and the second MTJ. The method further includes selectively activating one or more of the first, second, and third transistors to cause current to flow through a heavy metal layer belonging to the specified MTJ.

[0009] Further embodiments of the present disclosure comprise a method, a system, and a computer program product for reading a two-bit MRAM cell. The method comprises receiving a read command to read a two-bit MRAM cell, which has a first MTJ in series with a second MTJ. The area of ​​the first MTJ is different from the area of ​​the second MTJ. The method further comprises driving a current through the two-bit MRAM cell. The method further comprises determining a resistance of the two-bit MRAM cell. The method further comprises determining a two-bit value of the two-bit MRAM cell based on the determined resistance.

[0010] The above summary is not intended to describe every illustrated embodiment or every realization of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings contained in the present disclosure are incorporated into the patent specification and form part thereof. They illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. Fig. Figure 1 is a block diagram of an exemplary configuration of a magnetoresistive two-bit random access memory cell (two-bit MRAM cell) according to embodiments of the present disclosure. Fig. Figure 2 shows an example truth table illustrating how the states of the two magnetic tunnel junctions (MTJs) of the two-bit MRAM cell of the Fig. 1 correspond to a bit value state of the two-bit MRAM cell, according to embodiments of the present disclosure. Fig. Figure 3 is a diagram showing a section of an MRAM array composed of two-bit MRAM cells according to embodiments of the present disclosure. Fig. Figure 4 is a block diagram of a second exemplary configuration of a two-bit MRAM cell according to embodiments of the present disclosure. Fig. Figure 5A is a cross-sectional view showing a two-bit MRAM cell in an intermediate stage of the manufacturing process according to embodiments of the present disclosure. Fig. 5B is a cross-sectional view of a two-bit MRAM cell of the Fig. 5A after further manufacturing operations according to embodiments of the present disclosure. Fig. 5C is a cross-sectional view of a two-bit MRAM cell of the Fig. 5B after further manufacturing operations according to embodiments of the present disclosure. Fig. 5D is a cross-sectional view of a two-bit MRAM cell of the Fig. 5C after further manufacturing operations according to embodiments of the present disclosure. Fig. 5E is a cross-sectional view of a two-bit MRAM cell of the Fig. 5D after further manufacturing operations according to embodiments of the present disclosure. Fig. 5F is a cross-sectional view of a two-bit MRAM cell of the Fig. 5E after further manufacturing operations according to embodiments of the present disclosure. Fig. 5G is a cross-sectional view of a two-bit MRAM cell of the Fig. 5F after further manufacturing operations according to embodiments of the present disclosure. Fig. Figure 6 shows a flowchart of an exemplary procedure for programming a first bit of a two-bit MRAM cell according to embodiments of the present disclosure. Fig. Figure 7 shows a flowchart of an exemplary procedure for programming a second bit of a two-bit MRAM cell according to embodiments of the present disclosure. Fig. Figure 8 shows a flowchart of an exemplary method for reading data stored in a two-bit MRAM cell according to embodiments of the present disclosure. Fig. Figure 9 shows a higher-level block diagram of an exemplary computer system which can be used in implementing one or more of the methods, tools and modules and any associated functions described herein according to embodiments of the present disclosure.

[0012] Although the embodiments described herein are accessible to various modifications and alternative forms, specific properties thereof have been illustrated by way of example in the drawings and are described in detail. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure relate to the fields of electrical engineering, electronics and computers, and in particular to magnetoresistive two-bit direct access memory cells (two-bit MRAM cells) comprising three transistors, and methods for their manufacture.

[0014] Various embodiments of the present disclosure are described herein with reference to the accompanying drawings. Alternative embodiments may be derived without deviating from the scope of the present disclosure. It should be noted that in the following description and in the drawings, various connections and positional relationships (e.g., above, below, adjacent to, etc.) between elements are shown. These connections and / or positional relationships may be direct or indirect unless otherwise specified, and the present disclosure is not intended to be limiting in this respect. Accordingly, a connection between units may refer to either a direct or an indirect connection, and a positional relationship between units may be either a direct or an indirect positional relationship.As an example of an indirect positional relationship, references in the present description to the formation of a layer “A” over a layer “B” include situations in which one or more intermediate layers (e.g. a layer “C”) are located between layer “A” and layer “B”, provided that the relevant properties and functionalities of layer “A” and layer “B” are not substantially altered by the intermediate layer(s).

[0015] The following definitions and abbreviations shall be used for the interpretation of the claims and the description. As used herein, the terms "includes," "include," "comprising," "incorporating," "containing," or any other variation thereof shall cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus which includes a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or associated with such composition, mixture, process, method, article, or apparatus.

[0016] For descriptive purposes, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof shall refer to the described structures and processes as oriented in the diagrams. The terms "overlying," "on," "above," "positioned on," or "positioned on top of" mean that a first element, e.g., a first structure, is located on top of a second element, e.g., a second structure, whereby intermediate elements, e.g., an interface structure, may be present between the first and second elements. The term "direct contact" means that a first element, e.g., a first structure, and a second element, e.g., a second structure, are connected at the interface of the two elements without any intervening conductive, insulating, or semiconductor layers.It should be noted that the term “selective to”, such as “a first element selectively to a second element”, means that a first element can be etched and the second element can act as an etch stop.

[0017] For the sake of brevity, conventional techniques relating to the fabrication of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, the various tasks and process steps described herein may be part of a broader procedure or process that includes additional steps or functionalities not detailed here. In particular, several steps in the fabrication of semiconductor devices and ICs are well known, and therefore, for the sake of brevity, many conventional steps are only briefly mentioned or omitted entirely, without presenting the well-known details of the process.

[0018] In general, the various processes used to form a microchip that is assembled into an IC fall under four different categories: thin-film deposition, removal / etching, semiconductor doping, and structuring / lithography.

[0019] Deposition is any process by which a material grows, layers, or is otherwise transferred onto a wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and atomic layer deposition (ALD). Another deposition technology is plasma-enhanced chemical vapor deposition (PECVD), which uses the energy within the plasma to induce reactions at the wafer surface that would otherwise require higher temperatures in conjunction with conventional CVD.Energetic ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the thin film.

[0020] Removal / etching is any process by which material is removed from the wafer. Examples include etching processes (either wet or dry), chemical-mechanical planarization (CMP), and similar techniques. One example of a removal process is ion beam etching (IBE). Generally, IBE (or milling) refers to a dry plasma etching process that uses a wide-beam ion / plasma source to remove substrate material using a physical inert gas and / or a chemically reactive gas. As with other plasma etching techniques, IBE offers advantages such as etching speed, anisotropy, selectivity, uniformity, aspect ratio, and minimizing substrate damage. Another example of a dry removal process is reactive ion etching (RIE). Generally, RIE uses chemically reactive plasma to remove material deposited on wafers.In RIE, the plasma is generated at low pressure (vacuum) by an electromagnetic field. High-energy ions from the RIE plasma attack and react with the wafer surface, thereby removing material.

[0021] Semiconductor lithography is the process of creating three-dimensional relief images or structures on a semiconductor substrate for subsequent transfer of the structure to the substrate. In semiconductor lithography, the structures are formed using a light-sensitive polymer called a photoresist. To create the complex structures that make up a transistor and the many wires that connect the millions of transistors in a circuit, the lithography and etching structure transfer steps are repeated multiple times. Each structure printed onto the wafer is aligned with the previously created structures, and gradually the conductors, insulators, and selectively doped regions are built up to form the finished unit.

[0022] Now, moving on to an overview of technologies more specifically relevant to aspects of the present disclosure, a two-bit MRAM cell generally refers to any material or combination of materials capable of storing two values ​​(e.g., two information bits) using magnetic storage elements. Two-bit MRAM cell values, which can be binary ('01' or '00') or analog (e.g., 0.65), are stored in the memory cells as a function of the cell's electrical resistance, similar to how values ​​are stored in resistive random-access memory cells (ReRAM cells or RRAM cells) and / or memristors. In other words, the relative orientation of the magnetization of the disks within the two-bit MRAM cell affects the electrical resistance of the two-bit MRAM cell.This electrical resistance can be measured by passing a current through the two-bit MRAM cell, and the measured electrical resistance can be converted into a value.

[0023] Some of the disadvantages of conventional two-terminal MRAM units include oxide reliability and high write power. Three-terminal spin Hall effect (SHE) or spin orbit torque (SOT) MRAM cells overcome these limitations by providing decoupled paths for read and write operations. However, conventional SOT MRAM cells require two transistors connected by a magnetic tunnel junction (MTJ) to store a single bit of information. This limits the bit density of the MRAM unit.

[0024] Attempts to increase the low bit density of MRAM units have focused on creating multi-bit MRAM cells by (1) using a common heavy metal with different MTJ columns and (2) using stacked MTJs, one utilizing SHE and the other spin-transfer torque (STT). However, both solutions have significant drawbacks. With different MTJs sharing a common heavy metal structure, the MTJs cannot be programmed independently. With stacked MTJs, where one MTJ is driven by SHE and the other by STT, all the limitations of STT persist, such as tunnel barrier reliability, high write energy, etc.

[0025] Embodiments of the present disclosure can overcome these and other disadvantages of current solutions by using a two-bit SOT MRAM cell that employs three transistors and provides separate write paths for each bit. In the two-bit SOT MRAM cell disclosed herein, two MTJs are used in a series configuration with a common reference layer. Two heavy metals (e.g., Pt, Ta, W, etc.) are in contact with two free layers (these can be ferromagnets in the plane or perpendicular to the plane). The MTJ stack has a common reference layer with two free layers. The areas of the two free layers are different. In this structure, two free layers can be independently programmed using the SOT effect by passing current through the heavy metals.The structure of the revelation can offer a speed improvement (for the same energy) and an energy improvement (for the same speed) compared to two-bit STT-based MRAM cells.

[0026] In some embodiments, the two-bit SOT MRAM cell has two ferromagnetic free layers (FL1 and FL2) of different areas in contact with two heavy metals (e.g., Pt, Ta, W, etc.). In some embodiments, the upper free layer has a smaller area than the lower one. The ferromagnets may exhibit magnetic anisotropy within the plane or perpendicular to the plane.

[0027] A common ferromagnetic reference layer is shared by the two free layers. The reference layer (RL) is separated from each free layer by a tunnel barrier (e.g., MgO), so that the MTJ stack is formed by FL1 / MgO / RL / MgO / FL2. With the two heavy metal layers at each end, the overall stack in some embodiments consists of HM1 / FL1 / MgO / RL / MgO / FL2 / HM2.

[0028] The two free layers can be programmed independently by passing a write current through each of the two heavy metals. In other words, by selectively activating one or two of the transistors, current can be allowed to flow through a single heavy metal layer, thereby independently setting the magnetic orientation of the layers based on the current. This made it possible to write each bit individually into the two-bit MRAM cell.

[0029] The state of the two-bit MRAM cell is determined by passing a read current through the MTJ stack and measuring the corresponding resistance state of the MTJ stack. Since each MTJ in the stack has a different area / size, its effect on the overall resistance of the MTJ stack is different. This allows the MTJ stack to have four resistance states instead of two. As a simplified example, the first MTJ can be programmed to have a resistance of either 10 or 20 kilohms, and the second MTJ can be programmed to have a resistance of either 1 or 5 kilohms. Because the MTJs are connected in series, the entire stack has a resistance of 11, 15, 21, or 25 kilohms, depending on the magnetic orientation of the two MTJ stacks. Each of these resistance values ​​can be translated into a state for the two-bit MRAM cell.For example, an effective resistance of 11 kiloohms can correspond to a two-bit value of 00. Similarly, 15, 21, and 25 kiloohms can correspond to 01, 10, and 11, respectively.

[0030] It is understood that, although this simplified example illustrates the procedure, in practice the MTJs may not be programmable to exact resistances. Therefore, each resistance state can have a corresponding range of resistances. Following the example above, and assuming that the MTJ stack can be programmed to within 1.5 kilohms of the intended value, a two-bit value of 00 can be assigned to resistances in the range of [9.5 to 12.5] kilohms. Similarly, the two-bit values ​​01, 10, and 11 can have corresponding resistance ranges of [13.5 to 16.5] kilohms, [19.5 to 22.5] kilohms, and [23.5 to 26.5] kilohms, respectively.

[0031] By decoupling the write paths, the MTJs can be written to independently instead of sequentially, as is the case with conventional stacked MTJs. This results in a significant time saving when writing to the two-bit MRAM cell. Since reading from the two-bit MRAM cell involves reading both bits simultaneously, the improvement in read speed compared to conventional two-bit MRAM cells is not as large as the improvement in write speed, but the read speed can still be approximately two or three times faster than conventional MRAM in some embodiments. Furthermore, decoupling the write paths and using MTJs of different sizes allows for greater separation between resistance states based on how the tunnel barriers are fabricated. Other embodiments of the present disclosure include a method for forming a two-bit SOT MRAM cell.A timed IBE or RIE process is used to etch HM1, FL1, and TB1 using a hard mask. HM1, FL1, and TB1 are then encapsulated with a dielectric material along with an upper electrode material. A timed IBE or RIE process is used to etch RL, TB2, and FL2. Etching is stopped at the lower heavy metal. A dielectric material (low-k material) is deposited and polished by CMP, exposing the upper surface of HM1. Heavy metal is then deposited on top of the structured HM1, making contact with the FL1 surface.

[0032] As used herein, a “heavy metal” such as those found in the “heavy metal layer” is any metal that possesses a sufficiently strong spin-orbit coupling property to induce a torque on the magnetization of the free layer, causing the magnetic orientation of the free layer to switch (e.g., from parallel to antiparallel). These metals are sometimes also referred to as spin Hall metals and spin-orbit torque metals.

[0033] It is understood that the advantages mentioned above are exemplary and should not be interpreted as limiting. Embodiments of the present disclosure may have all, some, or none of the advantages mentioned above and still remain within the concept and scope of the present disclosure.

[0034] Now, let's turn to the characters, Fig. Figure 1 shows a block diagram of an exemplary configuration of a magnetoresistive two-bit random-access memory cell (two-bit MRAM cell) 100 according to embodiments of the present disclosure. The two-bit MRAM cell 100 comprises two MTJs 102, 104 in an MTJ stack. The first MTJ 102 comprises a first free layer (FL1) 116, a first tunnel barrier (TB1) 118, and a reference layer (RL) 120. The second MTJ 104 comprises a second free layer (FL2) 124, a second tunnel barrier (TB2) 122, and the RL 120. As shown in Figure 1, the two MTJs 102 and 104 are arranged in a stack. Fig. As shown in Figure 1, the first and second MTJ 102, 104 use the RL 120 together.

[0035] FL1 116 and FL2 124 are separated from RL 120 by TB1 118 and TB2 122, respectively. The tunnel barriers act as an insulator between the free layer and the reference layer. TB1 118 and TB2 122 can be made of any suitable material. For example, in some embodiments, TB1 118 and TB2 122 are layers of epitaxial (crystalline) MgO. In other embodiments, other suitable materials (e.g., amorphous aluminum oxide) can be used as one or both of the tunnel barriers.

[0036] As in Fig. As shown in Figure 1, the first MTJ 102 has a significantly smaller area than the second MTJ 104. Since the resistance of an MTJ is proportional to its area, using an MTJ stack with one MTJ that is smaller than the other MTJ ensures that four unique resistance states exist for the MTJ stack.

[0037] The first MTJ 102 is connected to a first heavy metal layer (HM1) 112 via FL1 116. Similarly, the second MTJ 104 is connected to a second heavy metal layer (HM2) 114 via FL2 124. HM1 112 and HM2 114 can be one or more layers of any metal or alloy exhibiting spin-orbit torque interactions. For example, HM1 112 and HM2 114 can be one or more of platinum, tungsten, tantalum, and / or manganese. In some embodiments, HM1 112 and HM2 114 are the same material, while in other embodiments, HM1 112 and HM2 114 are different metals.

[0038] HM1 112 is connected via a first transistor T1 to the bit line and a first word line (word line 1). HM1 112 is also connected via a third transistor T3 to the source line and a third word line (word line 3). Similarly, HM2 114 is connected via a second transistor T2 to the bit line and a second word line (word line 2). HM2 114 is directly connected (i.e., without an intervening transistor) to the source line.

[0039] FL1 116 and FL2 124 can be programmed independently to store different values. Each of FL1 116 and FL2 124 must be programmed at a different time to ensure that no current passes between the two layers (i.e., to prevent current from passing through the MTJ stack).

[0040] FL1 is programmed (e.g., written) by passing current only through HM1 112. This is achieved by turning on the first and third transistors, T1 and T3, while the second transistor, T2, remains off. Enabling the transistors in this way allows current to flow from the bit line through HM1 112 to the source line without passing through the stack. The current flowing through HM1 112 sets the magnetic orientation of FL1 116 and can therefore be used to change its resistance.

[0041] Similarly, FL2 is programmed (e.g., written) by passing current only through HM2 114. This is achieved by turning on the second transistor, T2, while the first transistor, T1, and the third transistor, T3, are off. Enabling the transistors in this way allows current to flow from the bit line through HM2 114 to the source line without passing through the stack. The current flowing through HM2 114 sets the magnetic orientation of FL2 124 and can therefore be used to change its resistance.

[0042] The state (i.e., bit values) of the two-bit MRAM cell 100 can be read by passing current through the MTJ stack (i.e., through both the first MTJ 102 and the second MTJ 104). This is done by activating the first transistor T1 while the second transistor T2 and the third transistor T3 are off. As in Fig. As shown in Figure 1, activating the transistors in this way generates a read current (Iread) 130, which flows from the bit line through the first transistor T1, into HM1 112, through the MTJ stack, into HM2 114, and finally to the source line. Using the read current 130, the resistance of the two-bit MRAM cell 100 can be determined. The determined resistance can then be converted into a two-bit value (e.g., using a truth table similar to the one in Figure 1). Fig. 2 shown).

[0043] Now, referring to Fig. 2, there is an exemplary truth table 200, which illustrates how the states of the two MTJs of the two-bit MRAM cell of the Fig. 1 corresponding to a bit value state of the two-bit MRAM cell, as illustrated in embodiments of the present disclosure. As in Fig. As shown in Figure 2, each MTJ can be programmed into a parallel state (P) or an antiparallel state (AP). Each state has a corresponding resistance value that depends on the area of ​​the MTJ. For example, the first MTJ 102 has a first resistance when it is in the parallel state and a second resistance when it is in the antiparallel state. Similarly, the second MTJ 104 has a third resistance when it is in the parallel state and a fourth resistance when it is in the antiparallel state.

[0044] By controlling the relative sizes of the MTJs, the resistances of each MTJ in both states can be made sufficiently different so that the state of the MTJs can be determined independently from the effective resistance of the stack. This can then be converted into a state for the two-bit MRAM cell (i.e., a two-bit value). In the example shown in Fig. As shown in Figure 2, a parallel state corresponds to a value of 0 and an antiparallel state corresponds to a bit value of 1. Therefore, when both MTJs are in a parallel state, the two-bit value is 00, while when both MTJs are in an antiparallel state, it is 11. If the first MTJ 102 is in the parallel state and the second MTJ 104 is in the antiparallel state, the two-bit value of the MRAM cell is 01. Similarly, the two-bit value of the MRAM cell is 10 when the first MTJ 102 is in the antiparallel state and the second MTJ 104 is in the parallel state.

[0045] Now, referring to Fig. Figure 3 shows a diagram depicting a section of an MRAM array 300, which is composed of a plurality of two-bit MRAM cells, according to embodiments of the present disclosure. The section of the MRAM array 300 shown in Fig. Figure 3 shows four MRAM cells. The four RAM cells are connected by six word lines (310 to 320), two bit lines (bit line 1 and bit line 2), and one source line. Each MRAM cell has two heavy metal layers, one MTJ stack, and three transistors.

[0046] For example, the first MRAM cell has a first heavy metal layer 302A, a second heavy metal layer 304A, and a first MTJ stack 306A. The first heavy metal layer 302A is connected to the first bit line and the first word line 310 via the first transistor T1. The first heavy metal layer 302A is also connected to the source line and a third word line 314 via a third transistor. The first heavy metal layer 302A is connected to the second heavy metal layer 304A via the first MTJ stack 306A. The second heavy metal layer 304A is connected to the first bit line and the second word line 312 via the second transistor T2.

[0047] Similarly, the second MRAM cell has two heavy metal layers (302B and 304B), one MTJ stack (306B), and three transistors. Like the first MRAM cell, the second MRAM cell is connected to the first, second, and third word lines (310 to 314) and the source line. However, unlike the first MRAM cell, the second MRAM cell is connected to a second bit line (bit line 2). This allows the second MRAM cell to be controlled independently of the first MRAM cell.

[0048] The third MRAM cell features two heavy metal layers (302C and 304C), an MTJ stack (306C), and three transistors. Like the first MRAM cell, the third MRAM cell is connected to the first bit line (bit line 1) and the source line. However, unlike the first MRAM cell, the third MRAM cell is connected to a fourth word line (316), a fifth word line (318), and a sixth word line (320). This allows the third MRAM cell to be controlled independently of the first and second MRAM cells.

[0049] The fourth MRAM cell has two heavy metal layers (302D and 304D), one MTJ stack (306D), and three transistors. Like the second MRAM cell, the fourth MRAM cell is connected to the second bit line (bit line 2) and the source line. However, unlike the second MRAM cell, the fourth MRAM cell is connected to the fourth word line (316), the fifth word line (318), and the sixth word line (320). This allows the fourth MRAM cell to be controlled separately from the first, second, and third MRAM cells.

[0050] Although in Fig. While only four MRAM cells are shown in Figure 3, an MRAM array can contain any number of MRAM cells. In other words, the depicted structure of MRAM cells can be extended for any number of word lines and / or bit lines to accommodate a much higher number of MRAM cells in a single array. The total number of MRAM cells (and their arrangement) may be limited by other aspects of the processor, such as the number of individually addressable elements supported by the processor.

[0051] Now, referring to Fig. Figure 4 shows a block diagram of a second exemplary configuration of a two-bit MRAM cell 400 according to embodiments of the present disclosure. The Fig. The two-bit MRAM cell 400 shown in Figure 4 can be essentially similar to the one in Figure 4. Fig. 1 Two-bit MRAM cell 100 shown, except that the shape of the MTJ stack may be different. Thus, the first heavy metal layer 412 may be essentially similar to or the same as that shown in Fig. 1 first heavy metal layer 112 shown. Similarly, the second heavy metal layer 414 may be essentially similar to or the same as that shown in Fig. 1 shown second heavy metal layer 114.

[0052] As the in Fig. The first MTJ 102 shown in section 1 can be the first MTJ 402 in Fig. 4. A first free layer 416, a first tunnel barrier 418, and a reference layer 420. The first free layer 416, the first tunnel barrier 418, and the reference layer 420 can be substantially similar to or the same as the first free layer 116, the first tunnel barrier 118, and the reference layer 120, which, with respect to Fig. 1 can be described, except that the shapes are different. Similarly, the second MTJ 404 can have a first second layer 424, a second tunnel barrier 422, and the reference layer 420. The first second layer 424 and the second tunnel barrier 422 can be essentially similar to or the same as the second free layer 124 and the second tunnel barrier 122, which are described with respect to Fig. 1 can be described, except that the forms are different.

[0053] Since the first MTJ 402 and the second MTJ 404 have different faces, the two-bit MRAM cell 400 still ultimately has four resistance states, for the same reason that the two-bit MRAM cell 100 ultimately has four resistance states. Furthermore, the operation of the two-bit MRAM cell 400 is identical to the operation of the two-bit MRAM cell 100. For example, reading the two-bit value of MRAM cell 400 can be achieved by activating the first transistor T1 while the second transistor T2 and the third transistor T3 are off. Therefore, the trapezoidal / pyramidal shape of the [unclear] can be described. Fig. The MTJ stack shown in section 4 is an alternative to the form shown in the diagram. Fig. The MTJ stack shown in Figure 1 can be used. This can be done due to the ease of manufacture, the overall surface area of ​​the MTJ stack, or other considerations, as is apparent to a person skilled in the art.

[0054] It goes without saying that the forms / the configuration that are in Fig. 1 and Fig. Figure 4 shows only examples of possible forms that can be used to create a two-bit MRAM cell. However, numerous other suitable forms exist, as is apparent to the person skilled in the art, and the present disclosure is not limited to these exemplary embodiments.

[0055] In some embodiments, the heavy metal layers can be local to each cell (as in Fig. (4 shown). In other embodiments, however, the heavy metal layers of several MRAM cells in the same row can be shared. These embodiments may be more complex and require additional write cycles.

[0056] Now, referring to Fig. Figure 5A shows a cross-sectional view of a two-bit MRAM cell 500 in an intermediate stage of the manufacturing process according to embodiments of the present disclosure. Fig. Figure 5A shows the two-bit MRAM cell 500 after the initial material stack has been produced and before the first etching step. The two-bit MRAM cell 500 has one or more dielectric layers 504, 506, 508 on a substrate 502. Together, these are referred to as the dielectric layers 550.

[0057] On top of the dielectric layers 550 is a heavy metal layer 510, which is formed by any suitable manufacturing process. The heavy metal layer 510 can be formed on the dielectric layers 550 by any suitable manufacturing process for depositing a heavy metal (e.g., Pt) onto a dielectric layer. A free layer 512 is formed on top of the heavy metal layer 510. The free layer 512 can be any suitable ferromagnetic material.

[0058] A tunnel barrier 514 is formed on top of the free layer 512 by any suitable manufacturing process. The tunnel barrier 514 can, for example, be MgO. The tunnel barrier 514 can be formed by epitaxial growth or material deposition of MgO on the free layer 512.

[0059] A reference layer 516 is formed on top of the tunnel barrier 514 by any suitable manufacturing process. A second tunnel barrier layer 518 can be formed on top of the reference layer 516 by any suitable manufacturing process. The second tunnel barrier layer 518 can be essentially similar to or the same as the first tunnel barrier layer 514.

[0060] A free layer 520 is formed on top of the tunnel barrier 518 by any suitable manufacturing process. The free layer 520 can be any suitable ferromagnetic material. In some embodiments, the free layer 520 is the same material as the free layer 512. In other embodiments, however, the two free layers 512 and 520 are made of different materials.

[0061] A heavy metal layer 522 is formed on top of the free layer 520 by any suitable manufacturing process. The heavy metal layer 522 can be any suitable heavy metal (e.g., any metal exhibiting spin-orbit torque properties). The heavy metal layer 522 can be essentially similar to or the same as the heavy metal layer 510.

[0062] An upper electrode 524 is formed on the heavy metal layer 522 by any suitable manufacturing process. The upper electrode 524 can be made of any suitable electrode material, such as copper. A dielectric hard mask 526 is formed on top of the upper electrode 524. The dielectric hard mask 526 can be made of any suitable material known to those skilled in the art. An optical planarization layer (OPL) 528 is formed on top of the dielectric hard mask 526.

[0063] A silicon anti-reflective coating (SiARC) 530 is formed on top of the OPL 528. A resist 532 is formed on top of the SiARC 530.

[0064] Now, referring to Fig. In step 5B, a hard mask etching process is performed to remove sections of the dielectric hard mask 526 and the upper electrode 524. The hard mask etching process etchs down to the top surface of the heavy metal layer 522. The area of ​​the remaining section of the dielectric hard mask 526 and the upper electrode 524 is based on the area of ​​the first MTJ in the two-bit MRAM cell 500 at the end of the manufacturing process.

[0065] Now, referring to Fig. In embodiment 5C, time-controlled etching of the heavy metal layer 522, the free layer 520, and the tunnel barrier 518 is performed. In some embodiments, ion beam etching methods are used for the time-controlled etching. In other embodiments, a RIE (ion beam etching) is performed to etch the heavy metal layer 522, the free layer 520, and the tunnel barrier 518.

[0066] Now, referring to Fig. In step 5D, a dielectric encapsulation of the etched heavy metal layer 522, the etched free layer 520, and the etched tunnel barrier 518 is performed. The dielectric encapsulation includes forming a dielectric material (e.g., a low-k material) 534 along the lateral edges of the etched heavy metal layer 522, the etched free layer 520, and the etched tunnel barrier 518.

[0067] Now, referring to Fig. In step 5E, the reference layer 516, the tunnel barrier 514, and the free layer 512 are etched. Timed ion beam etching (RIE) can be performed to etch the reference layer 516, the tunnel barrier 514, and the free layer 512. The encapsulated top layers can act as a hard mask for etching, so that the lateral edges of these etched layers are essentially coplanar with the dielectric encapsulation layers 534. Etching can be performed down to the top of the heavy metal layer 510.

[0068] Now, referring to Fig. In step 5F, dielectric deposition and CMP of any remaining upper electrode material are performed to expose the top surface of the heavy metal layer 522. The dielectric deposition includes depositing a low-k dielectric material 536 on top of the exposed portions of the heavy metal layer 510. In some embodiments, a second dielectric encapsulation of the entire stack may be performed prior to this step.

[0069] Now, referring to Fig. In 5G, a heavy metal layer 538 is deposited on top of the structure such that it is in contact with the structured heavy metal 522, the dielectric encapsulation layer 534, and the deposited low-k dielectric layer 536. In the resulting two-bit MRAM cell 500, HM1522 and HM2 510 can be present in two metal layers in the back-end-of-line (BEOL) and are oriented perpendicular to each other. However, for illustrative purposes, they are shown as parallel in this figure.

[0070] Now, referring to Fig. Section 6 presents a flowchart of an exemplary method 600 for programming a first bit of a two-bit MRAM cell according to embodiments of the present disclosure. Method 600 can be performed by hardware, firmware, software executed on a processor, or any combination thereof. For example, method 600 can be performed by a memory controller (e.g., in a processor). Referring to Fig. 1, Fig. 2 and Fig. 6, the procedure 600 begins with operation 602, where the memory controller receives a write command to program a first bit in the two-bit MRAM cell 100.

[0071] In the example that is in Fig. As described in section 6, the first bit is stored in the first MTJ 102. The write instruction also specifies a value for the first bit (e.g., 0 or 1). In response to receiving the write instruction, the memory controller determines an associated current required to program the value into the first MTJ 102. The associated current depends on whether the first MTJ 102 is in the parallel state (e.g., corresponding to a 0 in the example described in section 6). Fig. 2 is shown) or in the antiparallel state (e.g., corresponding to a 1 in the example shown in Fig. (as shown in Figure 2) is to be set. Based on the current required to program the correct state into the first MTJ 102, a voltage is applied to the bit line. The voltage can be high or low.

[0072] After the bit line is charged to the correct voltage, the first transistor T1 and the third transistor T3 are activated during operation 604. This is done by increasing the voltage on the first and third word lines. The second transistor T2 remains off. This causes current to flow through the first heavy metal layer 112, which programs the first MTJ 102 to store the value contained in the write command. After the first MTJ 102 of the two-bit MRAM cell 100 has been programmed based on the write command, procedure 600 ends.

[0073] Now, referring to Fig. Reference 7 presents a flowchart of an exemplary method 700 for programming a second bit of a two-bit MRAM cell according to embodiments of the present disclosure. Method 700 can be performed by hardware, firmware, software executed on a processor, or any combination thereof. For example, method 700 can be performed by a memory controller (e.g., in a processor). Referring to Fig. 1, Fig. 2 and Fig. 7, the procedure 700 begins with operation 702, where the memory controller receives a write command to program a second bit in the two-bit MRAM cell 100.

[0074] In the example that is in Fig. As described in section 7, the second bit is stored in the second MTJ 104. The write instruction also specifies a value for the second bit (e.g., 0 or 1). In response to receiving the write instruction, the memory controller determines an associated current required to program the value into the second MTJ 104. The associated current depends on whether the second MTJ 104 is in the parallel state (e.g., corresponding to a 0 in the example described in section 7). Fig. 2 is shown) or in the antiparallel state (e.g., corresponding to a 1 in the example shown in Fig. (as shown in Figure 2) is to be set. Based on the current required to program the correct state into the second MTJ 104, a voltage is applied to the bit line. The voltage can be high or low.

[0075] After the bit line is charged to the correct voltage, the second transistor T2 is activated in operation 704. This is done by increasing the voltage on the second word line. The first transistor T1 and the third transistor T3 remain switched off. This causes current to flow through the second heavy metal layer 114, which programs the second MTJ 104 to store the value contained in the write command. After the second MTJ 104 of the two-bit MRAM cell 100 has been programmed based on the write command, procedure 700 ends.

[0076] Now, referring to Fig. Reference 8 presents a flowchart of an exemplary method 800 for reading data stored in a two-bit MRAM cell according to embodiments of the present disclosure. Method 800 can be performed by hardware, firmware, software running on a processor, or any combination thereof. For example, method 800 can be performed by a memory controller (e.g., in a processor). Referring to Fig. 1, Fig. 2 and Fig. 8, the procedure 800 begins with operation 802, where a memory controller receives a read instruction to read a two-bit MRAM cell 100.

[0077] In operation 804, the first transistor T1 is activated. This can be achieved by increasing the voltage of the first word line. Meanwhile, the second transistor T2 and the third transistor T3 remain switched off throughout the entire read operation. The activation of the first transistor T1 (while the other two transistors are switched off) causes a read current to flow through transistor T1, the first heavy metal layer 112, the MTJs 102 and 104, and the second heavy metal layer 114.

[0078] Operation 806 determines the resistance of the MTJ stack. The resistance can be determined by measuring the read current and applying Ohm's law to the measured current using the known pre-charge voltage of the bit line.

[0079] In operation 808, the bit values ​​for the two-bit MRAM cell are determined based on the calculated resistance of the MTJ stack. Since the first and second MTJs have different faces, and each MTJ has two resistance states depending on whether they are in parallel or antiparallel orientation, the two-bit MRAM cell as a whole ultimately has four resistance states. Each of the four resistance states corresponds to a two-bit value (as in, for example, Fig. (2 shown). Accordingly, the calculated resistance of the two-bit MRAM cell can be compared with the four resistance states to determine the two-bit values ​​of the two-bit MRAM cell. After determining the two-bit value of the two-bit MRAM cell, the memory controller can send the two-bit value back to the originator of the read request, and procedure 800 can end.

[0080] Now, referring to Fig. Figure 9 shows a general block diagram of an exemplary computer system 901, which can be used in implementing one or more of the methods, tools, and modules described herein and any associated functions (e.g., using one or more processor circuits or computer processors of the computer), according to embodiments of the present disclosure. In some embodiments, the main components of the computer system 901 may include one or more CPUs 902, a memory subsystem 904, an interface 912, a memory interface 916, an input / output unit interface 914, and a network interface 918, all of which may be directly or indirectly connected for data exchange between components via a memory bus 903, an I / O bus 908, and an I / O bus interface unit 910.

[0081] The Computer System 901 can include one or more programmable general-purpose central processing units (CPUs) 902A, 902B, 902C, and 902D, collectively referred to herein as the CPU 902. In some embodiments, the Computer System 901 can include multiple processors, which is typical for a relatively large system; however, in other embodiments, the Computer System 901 can alternatively be a single-CPU system. Each CPU 902 can execute instructions stored in the Memory Subsystem 904 and can include one or more levels of onboard cache.

[0082] The system memory 904 may comprise computer system-readable media in the form of volatile memory, such as random access memory (RAM) 922 or cache memory 924. The computer system 901 may further comprise other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the memory system 926 may be designed to read from or write to a non-removable, non-volatile magnetic medium, such as a "hard disk". Although not shown, a magnetic disk drive may be designed to read from or write to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), or an optical disk drive may be designed to read from or write to a removable, non-volatile optical medium, such as a CD-ROM, DVD-ROM, or other optical media. In addition, the memory 904 may comprise flash memory, e.g.,B. a flash memory stick or a flash drive. Memory units can be connected to the memory bus 903 via one or more data media interfaces. The memory 904 can comprise at least one program product, which has a group of program modules (e.g., at least one) configured to perform the functions of different embodiments.

[0083] Memory 904 can store one or more programs / utilities 928, each comprising at least one group of program modules 930. The programs / utilities 928 can include a hypervisor (also called a virtual machine monitor), one or more operating systems, one or more application programs, other program modules, and program data. Each of the operating systems, one or more application programs, other program modules, and program data, or a combination thereof, can include a network environment implementation. The program modules 930 generally execute the functions or methodologies of various implementations.

[0084] Although the memory bus 903 in Fig. While the I / O bus 903 is depicted as a single-bus structure providing a direct data exchange path between the CPUs 902, the memory subsystem 904, and the I / O bus interface 910, in some embodiments the memory bus 903 may comprise several different buses or data exchange paths, which may be arranged in any number of different configurations, such as point-to-point connections in hierarchical, star, or net configurations, multiple hierarchical buses, parallel and redundant paths, or any other suitable configuration. Furthermore, although the I / O bus interface 910 and the I / O bus 908 are each depicted as separate units, in some embodiments the computer system 901 may contain multiple I / O bus interface units 910, multiple I / O buses 908, or both.Furthermore, although several I / O interface units are shown which separate the I / O bus 908 from various data exchange paths leading to the different I / O units, in other embodiments some or all of the I / O units may be directly connected to one or more system I / O buses.

[0085] In some embodiments, the computer system 901 can be a multi-user mainframe computer system, a single-user system, a server computer, or a similar unit that has few or no direct user interfaces but receives requests from other computer systems (clients). Furthermore, in some embodiments, the computer system 901 can be implemented as a desktop computer, a portable computer, a laptop or notebook computer, a tablet computer, a handheld computer, a telephone, a smartphone, network switches or routers, or any other suitable type of electronic unit.

[0086] It should be noted that Fig. Figure 9 is intended to show the representative main components of an exemplary computer system 901. However, in some embodiments, individual components may have a higher or lower complexity than shown. Fig. 9 shown, other components may be used than in Fig. The modules shown in Figure 9, or additional modules to these, may exist, and the number, type, and configuration of such components may vary. Furthermore, the modules are listed and described for illustrative purposes according to one embodiment and are not intended to indicate the necessity of a particular module or the exclusivity of other possible modules (or functions / purposes applied to a specific module).

[0087] The present invention may comprise a system, a method, and / or a computer program product with any possible level of integration of technical details. The computer program product may include a computer-readable storage medium (or media) containing computer-readable program instructions to instruct a processor to execute aspects of the present invention.

[0088] The computer-readable storage medium can be a physical unit capable of retaining and storing instructions for use by a system for executing instructions. For example, the computer-readable storage medium can be an electronic storage unit, a magnetic storage unit, an optical storage unit, an electromagnetic storage unit, a semiconductor storage unit, or any suitable combination thereof, without limitation.A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a removable computer floppy disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), removable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically coded unit such as punched cards or raised structures in a groove on which instructions are stored, and any suitable combination thereof. For the purposes of this text, a computer-readable storage medium shall not be understood as volatile signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., a wireless communication device).Optical fiber cables (transmitting light pulses) or electrical signals transmitted through a wire.

[0089] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to individual data processing units or, via a network such as the internet, a local area network, a wide area network, and / or a wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic cables, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each data processing unit receives computer-readable program instructions from the network and forwards them for storage on a computer-readable storage medium within the respective data processing unit.

[0090] The computer-readable program instructions for executing the steps of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or either source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., as well as conventional procedural programming languages ​​such as the programming language "C" or similar programming languages.The computer-readable program instructions can be executed entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter case, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, via the internet using an internet service provider).In some embodiments, electronic circuits, including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), can execute the computer-readable program instructions by using state information from the computer-readable program instructions to personalize the electronic circuits to perform aspects of the present invention.

[0091] Aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of processes, devices (systems), and computer program products according to embodiments of the invention. It is noted that each block of the flowcharts and / or block diagrams, as well as combinations of blocks in the flowcharts and / or block diagrams, can be executed by means of computer-readable program instructions.

[0092] These computer-readable program instructions can be provided to a processor of a computer or other programmable data processing device to create a machine such that the instructions executed through the processor of the computer or other programmable data processing device generate means for carrying out the functions / actions specified in the block or blocks of the flowcharts and / or block diagrams.These computer-readable program instructions may also be stored on a computer-readable storage medium capable of controlling a computer, programmable data processing device and / or other units to function in a particular manner, such that the computer-readable storage medium on which instructions are stored comprises a manufactured product, including instructions that implement aspects of the function / action specified in the block or blocks of the flowchart and / or block diagrams.

[0093] The computer-readable program instructions can also be loaded onto a computer, other programmable data processing device or other unit to cause the execution of a series of process steps on the computer or other programmable device or other unit to produce a process executed on a computer, such that the instructions executed on the computer, other programmable device or other unit implement the functions / actions specified in the block or blocks of the flowcharts and / or block diagrams.

[0094] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, processes, and computer program products according to various embodiments of the present invention. In this context, each block in the flowcharts or block diagrams can represent a module, segment, or part of instructions comprising one or more executable instructions for performing the specified logical function(s). In some alternative embodiments, the functions specified in the block may occur in a different sequence than shown in the figures.Two blocks depicted sequentially may, for example, actually be executed as one step, simultaneously, essentially simultaneously, partially or completely overlapping in time, or the blocks may sometimes be executed in reverse order depending on the corresponding functionality. It should also be noted that each block in the block diagrams and / or flowcharts, as well as combinations of blocks in the block diagrams and / or flowcharts, can be implemented by special hardware-based systems that perform the specified functions or actions, or by combinations of special hardware and computer instructions.

[0095] The terminology used herein serves to describe specific embodiments. As used herein, the singular forms "a", "an", and "the" are to include the plural forms as well, unless the context clearly indicates otherwise. It is further understood that the terms "includes" and / or "comprise," when used in this description, describe the presence of specified features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.In the preceding detailed description of exemplary embodiments of the various embodiments, reference has been made to the accompanying drawings (where identical numbers represent identical elements), which form a part thereof and in which specific embodiments are shown for illustration, illustrating how the various embodiments can be implemented. These embodiments have been described in sufficient detail to enable a person skilled in the art to implement them; however, other embodiments may be used, and logical, mechanical, electrical, and other modifications may be made without altering the scope of the various embodiments. Numerous specific details have been included in the preceding description to ensure a thorough understanding of the various embodiments.However, the various embodiments can also be implemented without these specific details. In other cases, well-known circuits, structures, and techniques have not been described in detail to avoid obscuring the embodiments.

[0096] As used herein, “a number of”, when referring to elements, means one or more elements. For example, “a number of different types of networks” refers to one or more different types of networks.

[0097] When different reference numbers include a common number followed by different letters (e.g., 100a, 100b, 100c), the use of the reference number alone without the letter (e.g., 100) can refer to the group of elements as a whole, a subset of the group, or an exemplary element of the group.

[0098] Various embodiments are referred to in the foregoing. However, it is understood that the present disclosure is not limited to the specific embodiments described. Instead, any combination of the described features and elements is provided for, with reference to different embodiments or not, to realize and implement the present disclosure. Many modifications, changes, and variations may be apparent to the person skilled in the art without deviating from the scope and concept of the described embodiments. Furthermore, although embodiments of the present disclosure may offer advantages over other possible solutions or over the prior art, the present disclosure is not limited by whether or not a particular advantage is achieved by a given embodiment.

Claims

[1] Two-bit MRAM cell based on spin-orbit torque, wherein the two-bit MRAM cell has: a first layer of heavy metals; a first magnetic tunnel junction connected to the first heavy metal layer, wherein the first magnetic tunnel junction has a first cross-sectional area; a second magnetic tunnel junction connected in series with the first magnetic tunnel junction, wherein the second magnetic tunnel junction has a second cross-sectional area that is different from the first cross-sectional area, wherein the second magnetic tunnel junction has a common reference layer with the first magnetic tunnel junction, wherein the first magnetic tunnel junction is stacked on top of the second magnetic tunnel junction, and wherein a difference in the first and second cross-sectional areas ensures that four unique resistive states exist for the stacked magnetic tunnel junctions; and a second heavy metal layer connected to the second magnetic tunnel junction, wherein: the first heavy metal layer is connected via a first transistor to a first word line and a bit line; the second heavy metal layer is connected via a second transistor to a second word line and the bit line; the first heavy metal layer is connected via a third transistor to a third word line and a source line; and the second heavy metal layer is directly connected to the source line. [2] Two-bit MRAM cell according to claim 1, wherein the first magnetic tunnel junction comprises: a first free layer in direct contact with the first heavy metal layer; the reference layer; and a first tunnel barrier that is positioned between the first free layer and the reference layer. [3] Two-bit MRAM cell according to claim 2, wherein the second magnetic tunnel junction comprises: a second free layer in direct contact with the second heavy metal layer; the reference layer; and a second tunnel barrier located between the second free layer and the reference layer. [4] Two-bit MRAM cell according to claim 2, wherein the first tunnel barrier is an MgO layer. [5] Two-bit MRAM cell according to claim 1, wherein the first cross-sectional area is smaller than the second cross-sectional area. [6] Two-bit MRAM cell according to claim 5, wherein the common reference layer has the same cross-sectional area as the cross-sectional area of ​​the second magnetic tunnel junction. [7] Two-bit MRAM cell according to claim 1, wherein the first heavy metal layer and the second heavy metal layer comprise one or more layers of a metal having spin-orbit torque properties. [8] Two-bit MRAM cell according to claim 1, wherein the first heavy metal layer and the second heavy metal layer comprise one or more layers of metals selected from the group consisting of platinum, tungsten, tantalum and manganese. [9] Two-bit MRAM cell according to claim 1, wherein the two-bit MRAM cell is part of a memory array comprising a plurality of two-bit MRAM cells. [10] Two-bit MRAM cell according to claim 1, wherein each of the first and second heavy metal layers comprises one or more metals selected from the group comprising Pt, Ta, Mn and W; and the common reference layer comprises a ferromagnetic metal. [11] Method for forming a two-bit MRAM cell based on spin-orbit torque, wherein the method comprises: Formation of a second heavy metal layer; Forming a magnetic tunnel transition stack, which includes: a second magnetic tunnel transition above the second heavy metal layer, wherein the second magnetic tunnel transition has a second cross-sectional area; and a first magnetic tunnel junction in series with the second magnetic tunnel junction, wherein the first magnetic tunnel junction has a first cross-sectional area, the first cross-sectional area being different from the second cross-sectional area, and wherein the first magnetic tunnel junction has a common reference layer with the second magnetic tunnel junction, wherein the first magnetic tunnel junction is stacked on top of the second magnetic tunnel junction, and wherein a difference between the first and second cross-sectional areas ensures that four unique resistive states exist for the stacked magnetic tunnel junctions; and Formation of an initial heavy metal layer above the first magnetic tunnel transition, whereby the first heavy metal layer is connected via a first transistor to a first word line and a bit line; the second heavy metal layer is connected via a second transistor to a second word line and the bit line; the first heavy metal layer is connected via a third transistor to a third word line and a source line; and the second heavy metal layer is directly connected to the source line. [12] Method according to claim 11, wherein the formation of the magnetic tunnel junction stack comprises: Forming an initial stack of material, wherein the initial stack of material has: a second free shift; a second tunnel barrier, which is located on top of the second free layer; the reference layer, which is located on top of the second tunnel barrier; a first tunnel barrier, which is located on top of the reference layer; and a first free layer, which is arranged on top of the first tunnel barrier; Etching of sections of the first heavy metal layer, the first free layer and the first tunnel barrier to a first width; Encapsulation of the etched first heavy metal layer, the etched first free layer, and the etched first tunnel barrier using a dielectric material; and Etching the reference layer, the second tunnel barrier and the second free layer using the encapsulated layers as a hard mask, such that a cross-sectional area of ​​the second tunnel barrier and the second free layer is larger than a cross-sectional area of ​​the first tunnel barrier and the first free layer. [13] Method according to claim 11, wherein the first cross-sectional area is smaller than the second cross-sectional area. [14] Method according to claim 11, wherein the first heavy metal layer and the second heavy metal layer comprise one or more layers of a metal having spin orbit torque properties. [15] Method according to claim 11, wherein the first heavy metal layer and the second heavy metal layer comprise one or more layers of metals selected from the group consisting of platinum, tungsten, tantalum and manganese. [16] A method for programming a two-bit MRAM cell according to any one of claims 1-10, wherein the method comprises: Receiving a write command to program a first bit into the two-bit MRAM cell, Determine that the first bit is to be stored in a specific magnetic tunnel junction, where the specified MTJ is either the first MTJ or the second magnetic tunnel junction; and Selective activation of one or more of the first, second and third transistors to cause current to flow through a heavy metal layer belonging to the specific magnetic tunnel junction. [17] Method according to claim 16, wherein the specified magnetic tunneling junction is the first magnetic tunneling junction, and wherein the selective activation of one or more of the first, second and third transistors comprises: Activating the first and third transistors to cause current to flow through the first heavy metal layer, where the second transistor is not activated. [18] Method according to claim 16, wherein the specified magnetic tunneling junction is the second magnetic tunneling junction and wherein the selective activation of one or more of the first, second and third transistors comprises: Activating the second transistor to cause current to flow through the second heavy metal layer, with the first and third transistors remaining inactive. [19] A system for programming a two-bit MRAM cell according to any one of claims 1-10, wherein the system comprises: the two-bit MRAM cell; a processor configured to perform a procedure that includes: Receiving a write command to program the first bit in the two-bit MRAM cell; Determine that the first bit is to be stored in a specific magnetic tunnel junction, where the specific magnetic tunnel junction is either the first magnetic tunnel junction or the second magnetic tunnel junction; and Selective activation of one or more of the first, second and third transistors to cause current to flow through a heavy metal layer belonging to the specific magnetic tunnel junction. [20] System according to claim 19, wherein the specified magnetic tunneling junction is the first magnetic tunneling junction and wherein the selective activation of one or more of the first, second and third transistors comprises: Activating the first and third transistors to cause current to flow through the first heavy metal layer, where the second transistor is not activated. [21] System according to claim 19, wherein the specified magnetic tunnel junction is the second magnetic tunnel junction and wherein the selective activation of one or more of the first, second and third transistors comprises: Activating the second transistor to cause current to flow through the second heavy metal layer, with the first and third transistors remaining inactive.

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