SEMICONDUCTOR DEVICES

Abstract

Semiconductor device, comprising: a chip (2) having a first main surface (3) on one side and a second main surface (4) on another side, wherein the chip (2) has a first layer (6) formed in a region inside the chip (2) on the side of the second main surface (4), a second layer (7) formed in a region inside the chip (2) on the side of the first main surface (3), and a third layer (8) formed between the first layer (6) and the second layer (7) inside the chip (2); a pn junction section (J) which is formed inside the chip (2) such that it extends along the first main surface (3); a device region (9) provided in the first main surface (3); a first trench structure (11) which is formed in the first main surface (3) such that it penetrates the pn transition section (J) and delimits the device region (9) in the first main surface (3); a second trench structure (12) formed in the first main surface (3) such that it penetrates the pn transition section (J) and delimits the device region (9) in a region further towards the side of the device region than the first trench structure (11); and a contamination region (22) which has a contamination concentration that is higher than a contamination concentration of the first layer (6), wherein the contamination region (22) in the first layer (6) is formed such that it covers a bottom wall of the first trench structure (11) and a bottom wall of the second trench structure (12).

Description

Technical area

[0001] This application, published as WO 2022 / 153693 A1, corresponds to Japanese Patent Application No. 2021-005307, filed with the Japan Patent Office on January 15, 2021, Japanese Patent Application No. 2021-005308, filed with the Japan Patent Office on January 15, 2021, Japanese Patent Application No. 2021-005309, filed with the Japan Patent Office on January 15, 2021, and Japanese Patent Application No. 2021-005310, filed with the Japan Patent Office on January 15, 2021, and the entire disclosures of these applications are incorporated herein by reference. The present invention relates to a semiconductor device. State of the art

[0002] Patent Literature 1 discloses a semiconductor device including a p-type region, a first p-epitaxy region, an n-type embedded region, a second p-epitaxy region, and a DTI (Deep Trench Isolation Structure) structure. The first p-type epitaxial layer is formed on the p-type region. The n-type embedded region is formed on the first p-epitaxy region. The second p-epitaxy region is formed on the n-type embedded region. The DTI structure surrounds a formation region of a high-voltage withstandable lateral MOS transistor in plan view. The DTI structure penetrates through the second p-epitaxy region, the n-type embedded region, and the first p-epitaxy region to reach the p-type region. List of citationsPatent literature

[0003] Patent Literature 1: Japanese Patent Application Publication No. JP 2015-122 543 A Further state of the art is shown in US 2018 / 0 053 765 A1 and US 2016 / 0 163 583 A1. Brief description of the inventionTechnical problem

[0004] An embodiment provides a semiconductor device capable of improving a withstand voltage. Solution to the problem

[0005] To solve the problem, semiconductor devices according to claims 1, 17 and 19 are provided.

[0006] An embodiment provides a semiconductor device that may include a first layer of a first conductivity type, a second layer of the first conductivity type or a second conductivity type laminated on the first layer, a third layer of the second conductivity type located between the first layer and the second layer, a device region provided in the second layer, a first trench structure penetrating through the second layer and the third layer to reach the first layer and define the device region in the second layer, and a second trench structure penetrating through the second layer and the third layer to reach the first layer and define the device region in a region of the second layer that is farther toward the device region side than the first trench structure.

[0007] An embodiment provides a semiconductor device that may include a first layer of a first conductivity type, a second layer of a second conductivity type laminated on the first layer, a device region provided in the second layer, a first trench structure penetrating through the second layer to reach the first layer and defining the device region in the second layer, and a second trench structure penetrating into the second layer to reach the first layer and defining the device region in a region of the second layer that is further toward the device region side than the first trench structure.

[0008] An embodiment provides a semiconductor device that may include a chip having a first main surface on one side and a second main surface on another side, a pn junction portion formed in an interior of the chip so as to extend along the first main surface, a device region provided in the first main surface, a first trench structure formed in the first main surface so as to penetrate through the pn junction portion and define the device region in the first main surface, a second trench structure formed in the first main surface so as to penetrate through the pn junction portion and define the device region in a region further toward the side of the device region than the first trench structure, and an intermediate trench region.which is defined in a region between the first trench structure and the second trench structure and to which a potential of at least 0 V is to be applied.,

[0009] An embodiment provides a semiconductor device that may include a chip having a first main surface on one side and a second main surface on another side, a pn junction portion formed in an interior of the chip to extend along the first main surface, a device region provided in the first main surface, a first trench structure formed in the first main surface to penetrate through the pn junction portion and define the device region in the first main surface, and a second trench structure formed in the first main surface to penetrate through the pn junction portion and define the device region in a region further toward the device region side than the first trench structure, and to which a potential different from that of the first trench structure is to be applied.

[0010] One embodiment provides a semiconductor device including a chip having a first main surface on one side and a second main surface on another side, a pn junction portion formed in an interior of the chip so as to extend along the first main surface, a device region provided in the first main surface, a trench structure formed in the first main surface so as to penetrate through the pn junction portion and define the device region in the first main surface, and a pn junction portion led out from a branch portion of the pn junction portion and the trench structure to a sidewall side of the trench structure to extend the pn junction portion in the device region.

[0011] One embodiment provides a semiconductor device including a chip having a first main surface on one side and a second main surface on another side, a pn junction portion formed in an interior of the chip to extend along the first main surface, a device region provided in the first main surface, a first trench structure formed in the first main surface to penetrate through the pn junction portion and define the device region in the first main surface, a second trench structure formed in the first main surface to penetrate through the pn junction portion and define the device region in a region further toward the device region side than the first trench structure, and a pn junction portion,which is led out from a branch portion of the pn junction portion and the second trench structure to a sidewall of the second trench structure to extend the pn junction portion in the device region.,

[0012] One embodiment provides a semiconductor device including a first layer of a first conductivity type, a second layer of a second conductivity type laminated on the first layer, a device region provided in the second layer, a trench structure penetrating through the second layer to reach the first layer and define the device region in the second layer, and an embedded layer of the second conductivity type formed in the device region to extend over a portion of the boundary between the first layer and the second layer at a distance from the trench structure.

[0013] One embodiment provides a semiconductor device including a first layer of a first conductivity type, a second layer of a second conductivity type laminated on the first layer, a device region provided in the second layer, a first trench structure penetrating through the second layer so as to be electrically connected to the first layer and electrically insulated from the second layer, and defining the device region in the second layer, a second trench structure penetrating into the second layer so as to be electrically insulated from the first layer and the second layer, and defining the device region in a portion of the second layer that is further toward the device region side than the first trench structure, and an embedded layer of the second conductivity type formed in the device region so thatthat it extends over a boundary section between the first layer and the second layer at a distance from the second trench structure.,

[0014] The above and other objects, features and effects of the present invention will become more apparent from the following description of the embodiments made with reference to the accompanying drawings. Brief description of the drawings [ Fig. 1] Fig. 1 is a schematic plan view of a semiconductor device according to a first embodiment. [ Fig. 2] Fig. 2 is an enlarged view of the Fig. Region II shown in Figure 1. [ Fig. 3] Fig. 3 is a sectional view showing a sectional structure along a Fig. 2 together with a second trench structure according to a first configuration example. [ Fig. 4] Fig. 4 is an enlarged sectional view of the main sections of the Fig. 3 shown structure. [ Fig. 5A] Fig. 5A is a sectional view showing the Fig. 4 together with the second trench structure according to a second configuration example. [ Fig. 5B] Fig. 5B is a sectional view showing the Fig. 4 together with the second trench structure according to a third configuration example. [ Fig. 6] Fig. 6 is a diagram showing the breakdown voltages of the Fig. 1, Fig. 5A and Fig. 5B together with a breakdown voltage of a semiconductor device according to a reference example. [ Fig. 7] Fig. 7 corresponds to Fig. 3 and is a sectional view of a semiconductor device according to a second embodiment. [ Fig. 8] Fig. 8 is a diagram showing the breakdown voltage of the Fig. 7 shows the semiconductor device shown. [ Fig. 9] Fig. 9 corresponds to Fig. 7 and is a sectional view of a semiconductor device according to a third embodiment. [ Fig. 10] Fig. 10 is a diagram showing the breakdown voltage of the Fig. 9 shows the semiconductor device shown. [ Fig. 11] Fig. 11 corresponds to Fig. 7 and is a sectional view of a semiconductor device according to a fourth embodiment. [ Fig. 12] Fig. 12 corresponds to Fig. 3 and is a sectional view of a semiconductor device according to a fifth embodiment. [ Fig. 13] Fig. 13 is an enlarged sectional view of the main sections of the Fig. 12 shown structure. [ Fig. 14] Fig. 14 is a diagram showing the breakdown voltage of the Fig. 12 shows the semiconductor device shown. [ Fig. 15] Fig. 15 corresponds to Fig. 12 is a sectional view of a semiconductor device according to a sixth embodiment. [ Fig. 16] Fig. 16 corresponds to Fig. 12 is a sectional view of a semiconductor device according to a seventh embodiment. [ Fig. 17] Fig. 17 corresponds to Fig. 3 and is a sectional view of a semiconductor device according to an eighth embodiment. [ Fig. 18] Fig. 18 is a diagram showing the breakdown voltage of the Fig. 17 shows the semiconductor device shown. [ Fig. 19] Fig. 19 corresponds to Fig. 17 is a sectional view of a semiconductor device according to a ninth embodiment. [ Fig. 20] Fig. 20 corresponds to Fig. 4 and is a sectional view showing a semiconductor device according to a tenth embodiment together with the trench structure according to the first configuration example. [ Fig. 21A] Fig. 21A is a sectional view showing the Fig. 20 together with the trench structure according to the second configuration example. [ Fig. 21B] Fig. 21B is a sectional view showing the Fig. 20 together with the trench structure according to the third configuration example. [ Fig. 22] Fig. 22 is a diagram showing a breakdown voltage of the Fig. 20 together with a breakdown voltage of a semiconductor device according to a reference example. [ Fig. 23] Fig. 23 is a sectional view showing a first modification example of a chip according to any one of the first to tenth embodiments. [ Fig. 24] Fig. 24 is a sectional view showing a second modification example of the chip according to any one of the first to tenth embodiments. [ Fig. 25] Fig. 25 is a sectional view showing a third modification example of the chip according to any one of the first to tenth embodiments. [ Fig. 26] Fig. 26 is a sectional view showing a fourth modification example of the chip according to any one of the first to tenth embodiments. [ Fig. 27] Fig. 27 is a sectional view showing a modification example of sinker regions according to any one of the first to tenth embodiments. Description of embodiments

[0015] The attached drawings are not necessarily precisely drawn, but are schematic views and do not necessarily correspond in scale, etc. The phrase "substantially the same" in this specification includes cases where a numerical value of a measured object (a measured location) completely agrees with a numerical value of a compared object (a compared location), as well as cases where a numerical value of a measured object (a measured location) is within a range that can be treated as equivalent to a numerical value of a compared object (a compared location) (e.g., within a range of not less than 0.9 times to not more than 1.1 times).

[0016] Fig. 1 is a schematic plan view of a semiconductor device 1 according to a first embodiment. Fig. 2 is an enlarged view of the Fig. Region II shown in Figure 1. Fig. 3 is a sectional view showing a sectional structure along a Fig. 2 together with a second trench structure 12 according to a first configuration example. Fig. 4 is an enlarged sectional view of the main sections of the Fig. 3 shown structure.

[0017] As in Fig. 1 to Fig. As shown in Figure 4, the semiconductor device 1 includes a chip 2 (semiconductor chip) of rectangular parallelepiped shape. The chip 2, in this embodiment, is constructed from a Si chip (silicon chip). The chip 2 has a first main surface 3 on one side, a second main surface 4 on another side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4.

[0018] The first main surface 3 and the second main surface 4 are quadrangular in shape when viewed from a normal direction Z thereto (hereinafter simply referred to as a "top view"). The normal direction Z is also a thickness direction of the chip 2. The first lateral surface 5A and the second lateral surface 5B extend in a first direction X along the first main surface 3 and face each other in a second direction Y that intersects (more precisely, is orthogonal to) the first direction X. The third lateral surface 5C and the fourth lateral surface 5D extend in the second direction Y and face each other in the first direction X.

[0019] The semiconductor device 1 includes a first layer 6 of a p-type (first conductivity type), a second layer 7 of a p-type or an n-type (second conductivity type), and a third layer 8 of an n-type formed inside the chip 2. The first layer 6 may be referred to as a "base layer." The second layer 7 may be referred to as a "device formation layer." The third layer 8 may be referred to as an "embedded layer." The first layer 6, the second layer 7, and the third layer 8 can be considered constituent elements of the chip 2.

[0020] The first layer 6 is formed in a region inside the chip 2 on the second main surface 4 side, and forms the second main surface 4 and the portions of the first to fourth lateral surfaces 5A to 5D. The first layer 6 has a concentration gradient such that the p-type impurity concentration on the first main surface 3 side is lower than the p-type impurity concentration on the second main surface 4 side. Specifically, the first layer 6 has a laminated structure including a high-concentration layer 6a and a low-concentration layer 6b laminated in this order from the second main surface 4 side.

[0021] The high-concentration layer 6a has a comparatively high p-type impurity concentration. The p-type impurity concentration in the high-concentration layer 6a may not be less than 1×10 16 cm -3 and not more than 1×10 20 cm -3 The high-concentration layer 6a may have a thickness of not less than 100 µm and not more than 1000 µm. In this embodiment, the high-concentration layer 6a is composed of a p-type semiconductor substrate (Si substrate). The low-concentration layer 6b has a lower p-type impurity concentration than the high-concentration layer 6a and is laminated on the high-concentration layer 6a. The p-type impurity concentration in the low-concentration layer 6b may be not less than 1×10 14 cm -3 and not more than 1×10 17 cm -3The low concentration layer 6b has a smaller thickness than the high concentration layer 6a. The low concentration layer 6b may have a thickness of not less than 0.5 µm and not more than 20 µm. In this embodiment, the low concentration layer 6b is composed of a p-type epitaxial layer (Si epitaxial layer).

[0022] The second layer 7 is formed in a region inside the chip 2 on the first main surface 3 side, and forms the first main surface 3 and portions of the first to fourth lateral surfaces 5A to 5D. A conductivity type (n-type or p-type) of the second layer 7 is arbitrary and is selected according to the specifications of the semiconductor device 1. Although an example in which the second layer 7 has an n-type conductivity type is described in this embodiment, this is not intended to imply that the conductivity type of the second layer 7 is limited to the n-type.

[0023] The second layer 7 may have an n-type impurity concentration that is uniform with respect to the thickness direction, or may have a gradient of the n-type impurity concentration that increases toward the first main surface 3. The impurity concentration of the second n-type layer 7 may be not less than 1×10 14 cm -3 and not more than 1×10 17 cm -3 The second layer 7 may have a thickness of not less than 0.5 µm and not more than 20 µm. In this embodiment, the second layer 7 is composed of an n-type epitaxial layer (Si epitaxial layer).

[0024] The third layer 8 is located between the first layer 6 and the second layer 7 in a region inside the chip 2 and forms portions of the first to fourth lateral surfaces 5A to 5D of the chip 2. The third layer 8 forms a pn junction portion J in a boundary portion with the first layer 6. That is, inside the chip 2, the pn junction portion J, which extends in a horizontal direction (orthogonal to the thickness direction) along the first main surface 3, is formed in an intermediate portion in the thickness direction between the first main surface 3 and the second main surface 4. The pn junction portion J may be referred to as a "pn junction portion" or a "pn boundary portion."

[0025] The third layer 8 has a higher n-type impurity concentration than the second layer 7. In particular, the third layer 8 has a concentration gradient such that the p-type impurity concentration on the first side of the main surface 3 is higher than the p-type impurity concentration on the second side of the main surface 4. In particular, the third layer 8 has a laminated structure including a low-concentration embedded layer 8a and a high-concentration embedded layer 8b laminated in this order from the first layer 6 side.

[0026] The low-concentration embedded layer 8a has a comparatively low n-type impurity concentration and is laminated on the low-concentration layer 6b of the first layer 6. The low-concentration embedded layer 8a forms the pn junction section J with the low-concentration layer 6b. The low-concentration embedded layer 8a may have a lower n-type impurity concentration than the second layer 7 or a higher n-type impurity concentration than the second layer 7. The n-type impurity concentration in the low-concentration embedded layer 8a may be not less than 1×10 14 cm -3 and not more than 1×10 18 cm -3The low-concentration embedded layer 8a may have a thickness of not less than 0.1 µm and not more than 5 µm. In this embodiment, the low-concentration embedded layer 8a is composed of an n-type epitaxial layer (Si epitaxial layer).

[0027] The high-concentration embedded layer 8b has a higher n-type impurity concentration than the low-concentration embedded layer 8a and is laminated on the low-concentration embedded layer 8a. The high-concentration embedded layer 8b preferably has a higher n-type impurity concentration than the second layer 7. The n-type impurity concentration in the high-concentration embedded layer 8b may be not less than 1×10 16 cm -3 and not more than 1×10 21 cm -3The embedded high-concentration layer 8b may have a thickness of not less than 0.1 µm and not more than 5 µm. In this embodiment, the embedded high-concentration layer 8b is composed of an n-type epitaxial layer (Si epitaxial layer).

[0028] The semiconductor device 1 includes a plurality of device regions 9 provided in the first main surface 3 (second layer 7). The plurality of device regions 9 are regions in which different functional devices are respectively formed. The plurality of device regions 9 are respectively defined in inner portions of the first main surface 3 at intervals from the first to fourth side portions 5A to 5D in plan view. The number, placement, and shape of the device regions 9 are arbitrary and are not limited to any specific number, placement, and shape.

[0029] The plurality of device regions may include at least one semiconductor switching device, one semiconductor rectifier device, and one passive device. The semiconductor switching device may include at least one of a JFET (JFET field-effect transistor), a MISFET (metal-insulator-semiconductor field-effect transistor), a BJT (bipolar transistor), and an IGBT (insulated-gate bipolar transistor).

[0030] The semiconductor rectification device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse. In this embodiment, the plurality of device regions 9 include at least one transistor region 9A. A structure on the transistor region 9A side will be described in more detail below.

[0031] With reference to Fig. 2 to Fig. 4, the semiconductor device 1 includes a trench separation structure 10 as an example of a region separation structure that defines the transistor region 9A in the first main surface 3. The trench separation structure 10 includes a plurality of trench structures and defines the transistor region 9A with a predetermined shape in plan view.

[0032] The trench separation structure 10 has a multi-trench structure including at least one first trench structure 11 and at least one second trench structure 12 having a different structure than the first trench structure 11. In this embodiment, the trench separation structure 10 has a double trench structure including the single first trench structure 11 and the single second trench structure 12. The first trench structure 11 may also be referred to as a "first trench electrode structure." The second trench electrode structure 12 may also be referred to as a "second trench electrode structure."

[0033] With reference to Fig. 2, the first trench structure 11 is formed in the shape of a stripe extending along the transistor region 9A in plan view. In this embodiment, the first trench structure 11 has a ring shape in plan view (a square ring shape in this embodiment) and defines the transistor region 9A of the predetermined shape (a square shape in this embodiment). In this embodiment, four corners of the first trench structure 11 are bent in directions away from the transistor region 9A in plan view. The planar shape of the first trench structure 11 (planar shape of the transistor region 9A) is arbitrary. The first trench structure 11 may have a polygonal, circular, or elliptical ring shape in plan view and may define the transistor region 9A in a polygonal, circular, or elliptical shape in plan view.

[0034] The first trench structure 11 has a first trench width W1. The first trench width W1 is a width in a direction orthogonal to a direction in which the first trench structure 11 extends in plan view. The first trench width W1 can be no less than 0.5 µm and no more than 10 µm. The first trench width W1 is preferably no less than 2 µm and no more than 4 µm.

[0035] With reference to Fig. 3 and Fig. 4, the first trench structure 11 is formed in the first main surface 3 so as to penetrate through the pn junction portion J and define the transistor region 9A in the first main surface 3. Specifically, the first trench structure 11 penetrates through the second layer 7 and the third layer 8 to reach the first layer 6 and define the transistor region 9A in the second layer 7. In this embodiment, the first trench structure 11 extends from the first main surface 3 to the second main surface 4 side so as to reach the high-concentration layer 6a of the first layer 6 and penetrate through the second layer 7, the third layer 8, and the low-concentration layer 6b of the first layer 6.

[0036] The first trench structure 11 includes an inner peripheral wall on the transistor region 9A side, an outer peripheral wall on a side opposite the inner peripheral wall (peripheral edge of the chip 2), and a bottom wall connected to the inner peripheral wall and the outer peripheral wall. The first trench structure 11 may be formed in a vertical shape with an opening width that is substantially fixed in the sectional view. The first trench structure 11 may be formed in a converging shape with an opening width that narrows toward the second main surface 4 side in the sectional view. The bottom wall of the first trench structure 11 may be formed in a curved shape toward the second main surface 4. The bottom wall of the first trench structure 11 may have a flat surface parallel to the first main surface 3.

[0037] With reference to Fig. 4, the first trench structure 11 protrudes by a first value P1 from the pn junction section J (boundary section between the first layer 6 and the third layer 8) toward the second side of the main surface 4. The first value P1 can be no less than 1 µm and no more than 30 µm. The first value P1 is preferably no less than 5 µm.

[0038] The first trench structure 11 is electrically connected to the chip 2 at the bottom wall and electrically insulated from the chip 2 at the sidewalls (inner peripheral wall and outer peripheral wall). That is, the first trench structure 11 has a lower end portion electrically connected to the chip 2. Specifically, the first trench structure 11 is electrically connected to the first layer 6 and electrically insulated from the second layer 7 and the third layer 8. That is, the first trench structure 11 is fixed at the same potential as the first structure 6.

[0039] The first trench structure 11 includes a first trench 13, a first insulating film 14, and a first electrode 15. The first trench 13 is formed in the first main surface 3 so as to penetrate into the pn junction portion J. Specifically, the first trench 13 penetrates the second layer 7 and the third layer 8 to reach the first layer 6. In this embodiment, the first trench 13 extends from the first main surface 3 to the second main surface 4 side so as to reach the high-concentration layer 6a of the first layer 6 and penetrate through the second layer 7, the third layer 8, and the low-concentration layer 6b of the first layer 6.

[0040] The first insulating film 14 covers the inner walls of the first trench 13 such that the chip 2 is visible from a bottom wall of the first trench 13. Specifically, the first insulating film 14 exposes the first layer 6 from the bottom wall of the first trench 13. In this embodiment, the first insulating film 14 exposes the high-concentration layer 6a of the first layer 6 at the bottom wall of the first trench 13. The first insulating film 14 preferably covers the entire inner peripheral wall and the entire outer peripheral wall of the first trench 13. The first insulating film 14 may include a silicon oxide layer. The first insulating film 14 preferably includes a silicon oxide layer composed of an oxide of the chip 2.

[0041] The first electrode 15 is embedded in the first trench 13 with the first insulating film 14 therebetween and is electrically connected to the chip 2 at the bottom wall of the first trench 13. Specifically, the first electrode 15 is electrically connected to the first layer 6 and electrically insulated from the second layer 7 and the third layer 8. Specifically, the first electrode 15 has an exposed portion exposed from the bottom wall of the first trench 13 and is mechanically and electrically connected to the high-concentration layer 6a of the first layer 6 at the exposed portion. The first electrode 15 preferably includes a conductive polysilicon. The first electrode 15 preferably includes a conductive polysilicon composed of the same type as the first layer 6 (p-type in this embodiment). A p-type impurity of the first electrode 15 is preferably boron.

[0042] With reference to Fig. 2, the second trench structure 12 is formed at a distance from the transistor region 9A laterally from the first trench structure 11 in plan view and extends in the shape of a stripe along the transistor region 9A. In this embodiment, the second trench structure 12 is formed in an annular shape (a square ring shape in this embodiment) extending parallel to the first trench structure 11 in plan view and delimiting the transistor region 9A of the predetermined shape (a square shape in this embodiment). In this embodiment, four corners of the second trench structure 12 are bent along the four corners of the first trench structure 11 and in directions away from the transistor region 9A in plan view.

[0043] The planar shape of the second trench structure 12 (planar shape of the transistor region 9A) is arbitrary. The second trench structure 12 can be polygonal, circular, or elliptical in plan view, and can delimit the transistor region 9A in a polygonal, circular, or elliptical shape in plan view. The planar shape of the second trench structure 12 does not necessarily have to be similar to the planar shape of the first trench structure 11.

[0044] The second trench structure 12 has a second trench width W2. The second trench width W2 is a width in a direction orthogonal to a direction in which the second trench structure 12 extends in plan view. The second trench width W2 is preferably not greater than the first trench width W1 (W2 ≤ W1). The second trench width W2 is more preferably smaller than the first trench width W1 (W2 < W1). The second trench width W2 can be not less than 0.5 µm and not more than 10 µm. The second trench width W2 is preferably not less than 1 µm and not more than 2 µm.

[0045] The second trench structure 12 is formed at a predetermined trench interval IT from the first trench structure 11. The trench interval IT can be no less than 0.5 µm and no more than 20 µm. The trench interval IT is preferably no less than 1 µm and no more than 5 µm. The trench interval IT is preferably smaller than the first trench width W1 (IT < W1).

[0046] With reference to Fig. 3 and Fig. 4, the second trench structure 12 is formed in the first main surface 3 so as to penetrate through the pn junction portion J and define the transistor region 9A in a region of the first main surface 3 that is farther from the transistor region 9A than the first trench structure 11. Specifically, the second trench structure 12 penetrates through the second layer 7 and the third layer 8 to reach the first layer 6, and defines the transistor region 9A in a region of the second layer 7 that is farther from the transistor region 9A than the first trench structure 11. In this embodiment, the second trench structure 12 extends from the first main surface 3 to the second main surface 4 side so as to reach the high concentration layer 6a of the first layer 6 and penetrate through the second layer 7, the third layer 8, and the low concentration layer 6b of the first layer 6.

[0047] The second trench structure 12 includes an inner peripheral wall on the transistor region 9A side, an outer peripheral wall on the first trench structure 11 side, and a bottom wall connecting the inner peripheral wall and the outer peripheral wall. The second trench structure 12 may be formed in a vertical shape with an opening width that is substantially fixed in the sectional view. The second trench structure 12 may be formed in a converging shape with an opening width that narrows toward the first layer 6 side in the sectional view. The bottom wall of the second trench structure 12 may be formed in a curved shape toward the second main surface 4. The bottom wall of the second trench structure 12 may have a flat surface parallel to the first main surface 3.

[0048] With reference to Fig. 4, the second trench structure 12 protrudes by a second value P2 from the pn junction section J (boundary section between the first layer 6 and the third layer 8) toward the second side of the main surface 4. The second value P2 is preferably substantially equal to the first value P1 of the first trench structure 11 (P1 ≈ P2). That is, the second trench structure 12 may have a depth that substantially corresponds to the depth of the first trench structure 11. The second value P2 may be smaller than the first value P1 (P2 < P1). That is, the second trench structure 12 may have a shallower depth than that of the first trench structure 11. The second value P2 may be no less than 1 µm and no more than 30 µm. The second value P2 is preferably no less than 5 µm.

[0049] The second trench structure 12 has a different structure than the first trench structure 11 and is electrically insulated from the first layer 6, the second layer 7, and the third layer 8. The second trench structure 12 is electrically separated from the first trench structure 11. In this embodiment, the second trench structure 12 is formed in an electrically floating state. A potential occurring in (applied to) the second trench structure 12 varies according to a potential (electric field) applied to the transistor region 9A. The potential occurring in the second trench structure 12 is not greater than a maximum potential applied to the transistor region 9A.

[0050] The second trench structure 12 includes a second trench 16, a second insulating film 17, and a second electrode 18. The second trench 16 is formed in the first main surface 3 so as to penetrate into the pn junction portion J. Specifically, the second trench 16 penetrates through the second layer 7 and the third layer 8 to reach the first layer 6. In this embodiment, the second trench 16 extends from the first main surface 3 to the second main surface 4 side so as to reach the high concentration layer 6a of the first layer 6 and penetrate through the second layer 7, the third layer 8, and the low concentration layer 6b of the first layer 6.

[0051] The second insulating film 17 covers the inner walls of the second trench 16. Specifically, the second insulating film 17 covers the entire inner walls (inner peripheral wall, outer peripheral wall, and bottom wall) of the second trench 16. The second insulating film 17 may include a silicon oxide layer. The second insulating film 17 preferably includes the silicon oxide film composed of the oxide of the chip 2.

[0052] In this embodiment, the second insulating film 17 forms a bottom insulator 19, which is thicker in a portion covering the bottom wall of the second trench 16 than in a portion covering the side walls (inner peripheral wall and outer peripheral wall) of the second trench 16. That is, the second trench structure 12 includes the bottom insulator 19 embedded in the bottom wall of the second trench 16 so as to be continuously connected to the second insulating film 17 and having a thickness exceeding the thickness of the second insulating film 17.

[0053] The bottom-side insulator 19 is preferably embedded in a region that is farther toward the bottom wall side of the second trench than the pn junction portion J (boundary portion between the first layer 6 and the third layer 8) with respect to a depth direction of the second trench 16. More preferably, the bottom-side insulator 19 contacts the high-concentration layer 6a and the low-concentration layer 6b of the first layer 6 with respect to the depth direction of the second trench 16. Of course, the bottom-side insulator 19 may be embedded so as to cross the pn junction portion J (boundary portion between the first layer 6 and the third layer 8) with respect to the depth direction of the second trench 16. In this case, the bottom-side insulator 19 may contact the embedded low-concentration layer 8a or the embedded high-concentration layer 8b of the third layer 8 at the bottom.In addition, the bottom-side insulator 19 can contact a portion of the second layer 7.

[0054] The second electrode 18 is embedded in the second trench 16 with the second insulating film 17 therebetween and is electrically insulated from the chip 2. Specifically, the second electrode 18 is electrically insulated from the first layer 6, the second layer 7, and the third layer 8 with the second insulating film 17 therebetween. In this embodiment, the second electrode 18 faces the first layer 6 (more precisely, the high-concentration layer 6a) with the comparatively thick bottom insulator 19 therebetween on the bottom wall side of the second trench 16. A parasitic capacitance between the second electrode 18 and the first layer 6 is reduced by the bottom insulator 19.

[0055] The second electrode 18 is electrically separated from the first electrode 15 of the first patterned trench structure 11. In this embodiment, the second electrode 18 is formed in an electrically floating state. The second electrode 18 preferably includes a conductive polysilicon. The second electrode 18 preferably includes a conductive polysilicon composed of the same type as the first layer 6 (p-type in this embodiment). A p-type impurity of the second electrode 18 is preferably boron.

[0056] The semiconductor device 1 includes an inter-trench region 20 defined in a region of the chip 2 between the first trench structure 11 and the second trench structure 12. The inter-trench region 20 is defined between the inner peripheral wall of the first trench structure 11 and the outer peripheral wall of the second trench structure 12 and includes a portion of the first layer 6, a portion of the third layer 8, and a portion of the second layer 7. The width of the inter-trench region 20 is determined by the trench interval IT.

[0057] The inter-trench region 20 is electrically isolated from the first trench structure 11. The inter-trench region 20 is electrically isolated from the second trench structure 12. In this embodiment, the inter-trench region 20 is formed in an electrically floating state. A potential occurring (applied) in the inter-trench region 20 varies according to a potential (electric field) to be applied to the transistor region 9A. The potential occurring in the inter-trench region 20 is not greater than a maximum potential applied to the transistor region 9A.

[0058] The semiconductor device 1 includes n-type sinker regions 21 covering the sidewalls of the second trench structure 12 inside the chip 2. The sinker regions 21 are formed within the second layer 7 so as to extend along the sidewalls of the second trench structure 12. In this embodiment, the sinker regions 21 are formed as films extending along both the inner peripheral wall and the outer peripheral wall of the second trench structure 12. The sinker regions 21 have a higher n-type impurity concentration than the second layer 7. The n-type impurity concentration in the sinker regions 21 may be not less than 1×10 15 cm -3 and not more than 1×10 19 cm -3 be.

[0059] The sinker regions 21 are annular and extend, in plan view, along the sidewalls of the second trench 16. The lower end portions of the sinker regions 21 are connected to the third layer 8 (high-concentration embedded layer 8b). In this embodiment, the sinker regions 21 are formed along the second trench structure 12 at intervals from the first trench structure 11 and do not cover one or both (in this embodiment, both) of the inner peripheral wall and the outer peripheral wall of the first trench structure 11.

[0060] The semiconductor device 1 includes a p-type impurity region 22 formed in a region inside the chip 2 along the bottom wall of the first trench structure 11. The impurity region 22 is formed in the first layer 6 so as to cover the bottom wall of the first trench structure 11. The impurity region 22 has a higher p-type impurity concentration than the first layer 6. Specifically, the impurity region 22 is formed within the high-concentration layer 6a in the first layer 6 and has a higher p-type impurity concentration than the high-concentration layer 6a.

[0061] In this embodiment, the first electrode 15 is formed as a supply source of a p-type impurity for the first layer 6, and the impurity region 22 encloses the p-type impurity of the first layer 6 and the p-type impurity of the first electrode 15. The impurity region 22 also covers the sidewall(s) of the first trench structure 11. In this embodiment, the impurity region 22 bulges in lateral directions along the first main surface 3 from the bottom surface of the first trench structure 11 and covers the bottom surface of the second trench structure 12. The impurity region 22 is preferably formed within the high-concentration layer 6a of the first layer 6 at a distance from the low-concentration layer 6b of the first layer 6.

[0062] With reference to Fig. 3, the semiconductor device 1 includes a planar gate type MISFET 30 as an example of a functional device formed in the transistor region 9A. The illustration of the MISFET 30 is shown in Fig. 2 is omitted. Depending on the drain-source voltage to be applied between the drain and source, the MISFET 30 may take the form of an HV (high voltage) MISFET (e.g., not less than 100 V and not more than 1000 V), an MV (medium voltage) MISFET (e.g., not less than 30 V and not more than 100 V), or an LV (low voltage) MISFET (e.g., not less than 1 V and not more than 30 V). Although an example in which the MISFET 30 is constructed from an HV MISFET is described in this embodiment, this is not intended to limit the MISFET 30 to an HV MISFET.

[0063] The MISFET 30 is constructed of at least one MISFET cell formed in the transistor region 9A. In this embodiment, the MISFET cell includes at least one (one in this embodiment) of an n-type first well region 31, at least one (a plurality in this embodiment) of a p-type second well region 32, at least one (a plurality in this embodiment) of an n-type drain region 33, at least one (a plurality in this embodiment) of an n-type source region 34, at least one (a plurality in this embodiment) of a p-type channel region 35, at least one (a plurality in this embodiment) of a p-type contact region 36, a plurality of shallow trench structures 37, and at least one (a plurality in this embodiment) of a planar gate structure 38 in cross-sectional view. The shallow trench structures 37 may be referred to as "STI (Shallow Trench Isolation) structures."

[0064] The first well region 31 is formed in a surface layer portion of the second layer 7 in the transistor region 9A. The first well region 31 has a higher n-type impurity concentration than the second layer 7. The plurality of second well regions 32 are formed in surface layer portions of the second layer 7 at intervals from the first well region 31 in the transistor region 9A. A second well region 32 is formed at a distance to one side in the first direction X from the first well region 31, and another second well region 32 is formed at a distance to another side in the first direction X from the first well region 31.

[0065] The drain region 33 is formed in a surface layer portion of the first well region 31, in sections inward from the edges of the first well region 31. The plurality of source regions 34 are each formed in a surface layer portion of the corresponding second well region 32, in sections inward from the edges of the corresponding second well region 32. The plurality of channel regions 35 are each formed between the second layer 7 and the corresponding source region 34 in a surface layer portion of the corresponding second well region 32. The plurality of contact regions 36 are each formed in a surface layer portion of the corresponding second well region 32, in sections within the peripheral edges of the corresponding second well region 32. The plurality of contact regions 36 are adjacent to the corresponding source regions 34.

[0066] The plurality of shallow trench structures 37 are each formed in the second layer 7 at a distance from the third layer 8 with respect to the thickness direction of the second layer 7. The plurality of shallow trench structures 37 are preferably formed at deep positions at distances from the first main surface 3 laterally from a side portion of the first well region 31 and side portions of the second well regions 32. The plurality of shallow trench structures 37 are formed along the peripheral edges of the drain region 33 and delimit the drain region 33 from other regions.

[0067] The plurality of shallow trench structures 37 are formed along the outer edges (peripheral edges on the sides of the trench separation structure 10) of the plurality of second well regions 32 and delimit the plurality of second well regions 32 from other regions. The plurality of shallow trench structures 37 each include a shallow trench 39 and an embedded insulator 40. Each shallow trench 39 is formed in the first main surface 3. Each embedded insulator 40 is embedded in the shallow trench 39.

[0068] The plurality of planar gate structures 38 are each formed on the second layer 7 (first main surface 3) to cover the corresponding channel region 35 and control the switching on and off of the corresponding channel region 35. In this embodiment, the plurality of planar gate structures 38 are each formed to extend between the first well region 31 and the corresponding well region 34. The plurality of planar gate structures 38 may cover portions of the shallow trench structures 37 that define the drain region 33.

[0069] The plurality of planar gate structures 38 each include an insulating film 41 and a gate electrode 42, which are laminated in this order from the second layer 7 side. The gate insulating film 41 may include a silicon oxide layer. The gate insulating film 41 preferably includes the silicon oxide layer composed of the oxide of the chip 2. The gate electrode 42 preferably includes a conductive polysilicon. The gate electrode 42 preferably includes a conductive polysilicon that is of the same type as the first layer 6 (i.e., p-type). A p-type impurity of the gate electrode 42 is preferably boron. Of course, the gate electrode 42 may have an n-type conductivity type.

[0070] The second trench structure 12 may take a different shape than that shown in Fig. 3 and Fig. 4. Further configuration examples for the second trench structure 12 are described below with reference to Fig. 5A and Fig. 5B illustrates. Fig. 5A is a sectional view showing the Fig. 4 together with the second trench structure 12 according to a second configuration example. The following are the structures corresponding to the Fig. 1 to Fig. 4 are provided with the same symbols and their description is omitted.

[0071] With reference to Fig. 5A, the second trench structure 12 may be assumed to have no bottom insulator 19. That is, the second trench structure 12 may include the second insulating film 17 covering the inner walls (inner peripheral wall, outer peripheral wall, and bottom wall) of the second trench 16 with a substantially uniform thickness. In this case, the second insulating film 17 preferably has a thickness less than half the second trench width W2 of the second trench structure 12. The thickness of the second insulating film 17 is a thickness along a normal direction to a wall surface of the second trench structure 12 (second trench 16).

[0072] The thickness of the second insulating film 17 is preferably less than half the width of the bottom wall of the second trench structure 12. The width of the bottom wall of the second trench structure 12 is a width in a direction orthogonal to the direction in which the second trench structure 12 extends in plan view. Under this condition, the second trench width W2 may be not smaller than the first trench width W1 of the first trench structure 11 (W1≤W2) or may be smaller than the first trench width W1 (W1>W2).

[0073] Fig. 5B is a sectional view showing the Fig. 4 together with the second trench structure 12 according to a third configuration example. The following are the structures corresponding to the Fig. 1 to Fig. 4 are provided with the same symbols and their description is omitted.

[0074] With reference to Fig. 5B, the second trench structure 12 may be assumed to have no second electrode 18. That is, the second trench structure 12 may include the second insulating film 17 embedded as an integral element in the second trench 16. In this case, the second trench structure 12 may be referred to as an "insulating trench structure." Under this condition, the second trench width W2 may be not smaller than the first trench width W1 of the first trench structure 11 (W1 ≤ W2) or may be smaller than the first trench width W1 (W1 > W2).

[0075] Fig. 6 is a diagram showing the breakdown voltages VB of the Fig. 1, Fig. 5A and Fig. 5B together with a breakdown voltage VB of a semiconductor device according to a reference example. In Fig. In Figure 6, the ordinate represents the breakdown voltage VB [V], and the abscissa represents the object (the semiconductor device under test). Here, a potential of 0 V is applied to the first layer 6 and the first trench structure 11. The voltages here are voltages based on the potential (= 0 V) ​​of the first layer 6.

[0076] A first chart bar G1, a second chart bar G2, a third chart bar G3 and a fourth chart bar G4 are in Fig. 6. The first graph bar G1 shows the breakdown voltage VB of the semiconductor device according to the reference example. The semiconductor device according to the reference example has the same structure as semiconductor device 1, except that it does not include the second trench structure 12. Other descriptions of the semiconductor device according to the reference example are omitted.

[0077] The second diagram bar G2 shows the breakdown voltage VB of the semiconductor device 1 including the second trench structure 12 according to the third configuration example (see Fig. 5B). The third diagram bar G3 shows the breakdown voltage VB of the semiconductor device 1 including the second trench structure 12 according to the second configuration example (see Fig. 5A). The fourth diagram bar G4 shows the breakdown voltage VB of the semiconductor device 1 including the second trench structure 12 according to the first configuration example (see Fig. 3 and Fig. 4).

[0078] Referring to the first to fourth chart bars G1 to G4, the breakdown voltage VB increased in the order of the semiconductor device according to the reference example, the semiconductor device 1 including the second trench structure 12 according to the third configuration example, the semiconductor device 1 including the second trench structure 12 according to the second configuration example, and the semiconductor device 1 including the second trench structure 12 according to the first configuration example.

[0079] These results have shown that the trench separation structure 10 preferably comprises a multi-trench structure including the first trench structure 11 and the second trench structure 12 (see the second to fourth diagram bars G2 to G4). In this structure, an electric field concentration with respect to the first trench structure 11 is relieved by the second trench structure 12, and the breakdown voltage VB is improved.

[0080] It has been shown that when the trench separation structure 10 has the multi-trench structure, it is particularly advantageous if the first trench structure 11 has the first trench electrode structure including the first electrode 15, and the second trench structure 12 has the second trench electrode structure including the second electrode 18 (see the third and fourth diagram bars G3 and G4). With this structure, an electric field concentration with respect to the second trench structure 12 is further relaxed, and the breakdown voltage VB is further improved.

[0081] Furthermore, it has been shown that the second trench structure 12 preferably includes the bottom insulator 19 in the structure containing the second electrode 18 (see the fourth diagram bar G4). When the bottom insulator 19 is included, the area where the first layer 6 and the second electrode 18 face each other in the second trench structure 12 is reduced, and the parasitic capacitance of the second trench structure 12 is reduced. Consequently, the electric field concentration with respect to the second trench structure 12 is further relaxed, and the breakdown voltage VB is further improved.

[0082] As described above, the semiconductor device 1 includes the chip 2, the pn junction portion J, the transistor region 9A (device region 9), the first trench structure 11, and the second trench structure 12. The chip 2 has the first main surface 3 on one side and the second main surface 4 on the other side. The pn junction portion J is formed to extend horizontally along the first main surface 3 in an intermediate portion within the chip 2 between the first main surface 3 and the second main surface 4. The transistor region 9A is provided in the first main surface 3.

[0083] The first trench structure 11 is formed in the first main surface 3 so as to penetrate into the pn junction portion J and define the transistor region 9A in the first main surface 3. The second trench structure 12 is formed in the first main surface 3 so as to penetrate through the pn junction portion J and define the transistor region 9A in the region that is further toward the transistor region 9A side than the first trench structure 11. With this structure, a semiconductor device 1 can be provided with which the withstand voltage (in particular, the breakdown voltage VB) can be improved.

[0084] Viewed from another angle, the semiconductor device 1 includes the p-type first layer 6, the p-type or n-type second layer 7 (the n-type in this embodiment), the n-type third layer 8, the transistor region 9A (Embodiment 9), the first trench structure 11 (first trench electrode structure), and the second trench structure 12 (second trench electrode structure). The second layer 7 is laminated on the first layer 6. The third layer 8 is sandwiched between the first layer 6 and the second layer 7. The device region 9 is provided in the second layer 7.

[0085] The first trench structure 11 penetrates through the second layer 7 and the third layer 8 and thus reaches the first layer 6. The first trench structure 11 defines the transistor region 9A in the second layer 7. The second trench structure 12 penetrates through the second layer 7 and the third layer 8 and thus reaches the first layer 6. The second trench structure 12 defines the transistor region 9A in the region of the second layer 7 further toward the transistor region 9A than the first trench structure 11. With this structure, a semiconductor device 1 can be provided with which the withstand voltage (in particular, the breakdown voltage VB) can be improved.

[0086] Preferably, the first trench structure 11 is electrically connected to the chip 2. In particular, the first trench structure 11 is preferably constructed from the first trench electrode structure, which is electrically connected to the first layer 6 and electrically insulated from the second layer 7 and the third layer 8. Preferably, the second trench structure 12 is electrically insulated from the chip 2. In particular, the second trench structure 12 is preferably constructed from the second trench electrode structure, which is electrically insulated from the first layer 6, the second layer 7, and the third layer 8. That is, the second trench structure 12 preferably has an electrode structure that is different from the first trench structure 11. With this structure, the concentration of the electric field with respect to the second trench structure 12 can be relaxed, and the breakdown voltage VB can thereby be further improved.

[0087] The second trench structure 12 is preferably electrically separated from the first trench structure 11. The second trench structure 12 is preferably formed in an electrically floating state. Preferably, a different potential should occur in the second trench structure 12 than in the first structure 11.

[0088] Preferably, the first trench structure 11 has the first trench width W1, and the second trench structure 12 has the second trench width W2, which is not greater than the first trench width W1 (W2 < W1). Preferably, the second trench structure 12 is formed at a distance that is not greater than the first trench width W1. The first trench width W1 can be no less than 0.5 µm and no more than 10 µm.

[0089] Preferably, the first trench structure 11 is formed in a shape that converges with the thickness direction (second main surface 4 side). Preferably, the second trench structure 12 is formed in a shape that converges with the thickness direction (second main surface 4 side). Preferably, the first trench structure 11 surrounds the device region 9 in plan view. Preferably, the second trench structure 12 surrounds the device region 9 in plan view.

[0090] Preferably, the first trench structure 11 includes the first trench 13 penetrating through the second layer 7 and the third layer 8 to reach the first layer 6, the first insulating film 14 covering the inner walls of the first trench 13 to expose the first layer 6, and the first electrode 15 embedded in the first trench 13 with the first insulating film 14 therebetween to be electrically connected to the first layer 6 and electrically insulated from the second layer 7 and the third layer 8.

[0091] Preferably, the second trench structure 12 includes the second trench 16 penetrating through the second layer 7 and the third layer 8 to reach the first layer 6, the second insulating film 17 covering the inner walls of the second trench 16, and the second electrode 18 embedded in the second trench 16 with the second insulating film 17 therebetween so as to be electrically insulated from the first layer 6, the second layer 7, and the third layer 8.

[0092] Preferably, the first electrode 15 includes a p-type conductive polysilicon. Preferably, the second electrode 18 includes a p-type conductive polysilicon. Preferably, the second trench structure 12 includes the bottom insulator 19 embedded in the bottom wall of the second trench 16 so as to be continuously connected to the second insulating film 17 and having a thickness exceeding the thickness of the second insulating film 17. Preferably, the second electrode 18 is embedded in the second trench 16 with the second insulating film 17 and the bottom insulator 19 interposed therebetween. With this structure, the electric field concentration with respect to the second trench structure 12 can be relaxed, and the breakdown voltage VB can thereby be further improved.

[0093] Preferably, the first layer 6 includes the p-type high-concentration layer 6a, which has a comparatively high impurity concentration, and the p-type low-concentration layer 6b, which is laminated on the high-concentration layer 6a and has a lower impurity concentration than the high-concentration layer 6a. Preferably, the third layer 8 is laminated on the low-concentration layer 6b. In this case, the high-concentration layer 6a is preferably formed from the p-type semiconductor substrate.

[0094] Preferably, the third layer 8 includes the n-type low-concentration embedded layer 8a laminated on the first layer 6 and having a comparatively low impurity concentration, and the n-type high-concentration embedded layer 8b laminated on the low-concentration embedded layer 8a and having a higher impurity concentration than the low-concentration embedded layer 8a. In this case, the second layer 7 is preferably laminated on the high-concentration embedded layer 8b. With this structure, the electric field concentration with respect to the second trench structure 12 can be relaxed by the low-concentration embedded layer 8a.Therefore, compared with a case where the third layer 8 has a single-layer structure composed only of the embedded high-concentration layer 8b, the dielectric strength can be improved.

[0095] Preferably, the semiconductor device 1 includes the p-type impurity region 22 formed in the region inside the chip 2 along the bottom wall of the first trench structure 11. Preferably, the impurity region 22 is formed in the first layer 6 and has a higher impurity concentration than the first layer 6. Preferably, the impurity region 22 covers the bottom wall of the second trench structure 12. Preferably, the semiconductor device 1 includes the n-type sinker region 21 covering the sidewall of the second trench structure 12 inside the chip 2. Preferably, the sinker region 21 is formed within the second layer 7 so as to extend along the sidewall of the second trench structure 12.

[0096] Fig. 7 corresponds to Fig. 3 is a sectional view showing a semiconductor device 51 according to a second embodiment. Hereinafter, structures corresponding to those described for the first embodiment are provided with the same symbols, and their descriptions are omitted.

[0097] As in the first embodiment, the semiconductor device 51 includes the first trench structure 11 electrically connected to the chip 2 (first layer 6) and the second trench structure 12 electrically isolated from the chip 2. The second trench structure 12 is formed in an electrically floating state. In this embodiment, the semiconductor device 51 includes the inter-trench region 20, to which, unlike in the first embodiment, an inter-trench potential VI of not less than 0 V is to be applied. The inter-trench potential VI is applied to the inter-trench region 20 from outside the chip 2.

[0098] Preferably, the inter-trench potential VI is set to any value within a potential range of not less than 0 V and not more than a maximum value of the potential to be applied to the transistor region 9A (MISFET 30). Preferably, the inter-trench potential VI is greater than 0 V. Preferably, the inter-trench potential VI differs from the potential to be applied to the first trench structure 11. Preferably, the inter-trench potential VI differs from the potential to be applied to the second trench structure 12.

[0099] Preferably, the inter-trench potential VI differs from the potential applied to the MISFET 30 (transistor region 9B). The potential in the inter-trench region 20 is raised to the inter-trench potential VI. In a state where the inter-trench potential VI is to be applied, a potential gradient is formed in the inter-trench region 20, gradually decreasing from the first main surface 3 side to the first layer 6 side.

[0100] In this embodiment, the semiconductor device 51 includes a first contact electrode 52 that is electrically connected to the inter-trench region 20 on the chip 2 (second layer 7). Fig. In Figure 7, the first contact electrode 52 is simply illustrated by a line. The first contact electrode 52 applies the inter-trench potential VI to the inter-trench region 20.

[0101] Fig. Figure 8 is a diagram showing the breakdown voltage VB of the Fig. 7 shows the semiconductor device 51. In Fig. In Figure 8, the ordinate shows the breakdown voltage VB [V] and the abscissa the inter-trench potential VI [V]. Here, arbitrary inter-trench potentials VI in a range between 0 V and 30 V are applied to the inter-trench region 20. Here, a potential of 0 V is also applied to the first layer 6 and the first trench structure 11. The voltages here are voltages based on the potential (= 0 V) ​​of the first layer 6. The inter-trench potentials VI can be replaced by inter-trench voltages based on the potential (= 0 V) ​​of the first layer 6.

[0102] A first polygonal line L1 (see solid line through the drawn black circles), a second polygonal line L2 (see dashed line through the drawn white circles) and a third polygonal line L3 (see dashed line through the drawn squares) are in Fig. 8. The first polygonal line L1 shows the breakdown voltage VB of the semiconductor device 51. The second polygonal line L2 shows a voltage at the second trench structure 12. The third polygonal line L3 shows a differential voltage resulting from subtracting the voltage at the second trench structure 12 from the breakdown voltage VB.

[0103] With reference to the first polygonal line L1, the breakdown voltage VB increases with the increase in the inter-trench potential VI. With reference to the second polygonal line L2, the voltage in the second trench structure 12 increases with the increase in the inter-trench potential VI. In contrast, for the third polygonal line L3, the differential voltage remains essentially constant regardless of the increase in the inter-trench potential VI.

[0104] The above explanations have shown that it is better to fix the inter-trench region 20 at an inter-trench potential VI of at least 0 V than to form it in an electrically floating state. Furthermore, it has been shown that if the voltage across the second trench structure 12 when the inter-trench potential VI is 0 V is set as a reference value, an amount of the voltage across the second trench structure 12 from the reference value is added to the breakdown voltage VB. In this embodiment, the amount of voltage increase across the second trench structure 12 was in a range of not less than 40% and not more than 50% of the inter-trench potential VI. In other words, a value in the range of not less than 40% and not more than 50% of the inter-trench potential VI was added to the breakdown voltage VB (voltage across the second trench structure 12).

[0105] As described above, the semiconductor device 51 includes the inter-trench region 20, to which the inter-trench potential VI of not less than 0 V is to be applied in the region between the first trench structure 11 and the second trench structure 12. With this structure, a semiconductor device 51 capable of improving the withstand voltage (particularly, the breakdown voltage VB) can be provided.

[0106] Fig. 9 corresponds to Fig. 7 is a sectional view showing a semiconductor device 53 according to a third embodiment. Hereinafter, structures corresponding to those described in the first and second embodiments are provided with the same symbols, and their descriptions are omitted.

[0107] As in the first embodiment, the semiconductor device 53 includes the first trench structure 11 electrically connected to the chip 2 (first layer 6) and the inter-trench region 20 formed in an electrically floating state. In this embodiment, the semiconductor device 53 includes the second trench structure 12, to which, unlike the first embodiment, a trench potential VT of not less than 0 V is to be applied. The trench potential VT is applied to the second trench structure 12 from the outside of the chip 2.

[0108] Preferably, the trench potential VT is set to any value within a potential range of not less than 0 V and not more than a maximum value of the potential to be applied to the transistor region 9A (MISFET 30). Preferably, the trench potential VT is greater than 0 V. Preferably, the trench potential VT is different from the potential to be applied to the first trench structure 11. Preferably, the inter-trench potential VT is different from the potential applied to the inter-trench region 20. Preferably, the inter-trench potential VI is different from the potential applied to the MISFET 30 (transistor region 9B). The potential at the second trench structure 12 is raised to the trench potential VT.In a state in which the trench potential VT is to be applied, a potential gradient is formed in the second trench structure 12, which gradually decreases from the side of the first main surface 3 to the side of the first structure layer 6.

[0109] In this embodiment, the semiconductor device 53 includes a second contact electrode 54 on the chip 2 (second structural layer 7) that is electrically connected to the second trench structure 12. In Fig. In Figure 9, the first contact electrode 52 is simply illustrated by a line. The second contact electrode 54 applies the trench potential VT to the second trench structure 12.

[0110] Fig. 10 is a diagram showing the breakdown voltage VB of the Fig. 9 shows the semiconductor device 53. In Fig. In Figure 10, the ordinate shows the breakdown voltage VB [V] and the abscissa the trench potential VT [V]. Here, arbitrary trench potentials VT in a range between 0 V and 60 V are applied to the second trench structure 12. Here, too, a potential of 0 V is applied to the first layer 6 and the first trench structure 11. The voltages here are voltages based on the potential (= 0 V) ​​of the first layer 6. The trench potential VT can be replaced by inter-trench potentials based on the potential (= 0 V) ​​of the first layer 6.

[0111] A single polygonal line LA is in Fig. 10. The single polygonal line LA indicates the breakdown voltage VB of the semiconductor device 53. Relative to the polygonal line LA, the breakdown voltage VB increases with the increase in the trench potential VT. It has been shown that it is better to fix the second trench structure 12 at a trench potential VT of at least 0 V than to form it in an electrically floating state.

[0112] As described above, the semiconductor device 53 includes the second trench structure 12 to which the trench potential VT of not less than 0 V is to be applied. With this structure, a semiconductor device 53 can be provided with which the withstand voltage (particularly the breakdown voltage VB) can be improved.

[0113] Fig. 11 corresponds to Fig. 7 is a sectional view showing a semiconductor device 55 according to a fourth embodiment. Hereinafter, structures corresponding to those described in the first to third embodiments are provided with the same symbols, and their descriptions are omitted.

[0114] With reference to Fig. 11, the semiconductor device 55 has a structure in which the semiconductor device 51 according to the second embodiment and the semiconductor device 53 according to the third embodiment are combined. That is, the semiconductor device 55 includes the first trench structure 11 electrically connected to the chip 2 (first layer 6), the second trench structure 12 to which the inter-trench potential VT of not less than 0 V is to be applied, and the inter-trench region 20 to which the inter-trench potential VI of not less than 0 V is to be applied. In addition, the semiconductor device 55 on the chip 2 (second layer 7) includes the first contact electrode 52 electrically connected to the inter-trench region 20 and the second contact electrode 54 electrically connected to the second structure 12. In Fig. 11, the first contact electrode 52 and the second contact electrode 54 are simply illustrated by lines.

[0115] As described above, the semiconductor device 55 can achieve an effect of improving the withstand voltage using the inter-trench potential VI and an effect of improving the withstand voltage using the trench potential VT. Thus, a semiconductor device 55 capable of improving the withstand voltage (specifically, the breakdown voltage VB) can be provided.

[0116] Fig. 12 corresponds to Fig. 3 and is a sectional view showing a semiconductor device 61 according to a fifth embodiment. Fig. 13 is an enlarged sectional view of the main sections of the Fig. 12. Hereinafter, structures corresponding to those described for the first to fourth embodiments are provided with the same symbols, and their descriptions are omitted.

[0117] With reference to Fig. 12 and Fig. 13, the semiconductor device 61 includes n-type sidewall buffer layers 62. The sidewall buffer layers 62 protrude from the branch portions 63 of the third layer 8 and the sidewalls of the second trench structure 12 toward the first layer 6 in the device region 9 and extend as film layers along the sidewalls of the second trench structure 12. The branch portions 63 are also branch portions of the pn junction portion J and the sidewalls of the second trench structure 12.

[0118] The sidewall buffer layers 62 extend from the branch portions 63 of the second trench structure 12, which is closest to the device region 9 of the trench separation structure 10, toward the bottom wall of the second trench structure 12. In this embodiment, the branch portions 63 are formed by the low-concentration embedded layer 8a of the third layer 8 and the second trench structure 12. The sidewall buffer layers 62 therefore protrude from the low-concentration embedded layer 8a toward the bottom wall of the second trench 16.

[0119] In this embodiment, the sidewall buffer layers 62 include the sidewall buffer layer 62 on one side and the sidewall buffer layer 62 on another side. The sidewall buffer layer 62 on one side extends from the branch portion 63 on the inner peripheral wall side of the second trench structure 12 toward the bottom wall of the second trench structure 12. The sidewall buffer layer 62 on the other side extends from the branch portion 63 on the outer peripheral wall side of the second trench structure 12 toward the bottom wall of the second trench structure 12. In this embodiment, the sidewall buffer layers 62 are formed at intervals from the first trench structure 11, which is not near the device region 9, and only along the second trench structure 12, which is near the device region 9.

[0120] Preferably, the sidewall buffer layers 62 are formed at deep positions between the third layer 8 and the bottom wall of the second trench structure 12. Preferably, the sidewall buffer layers 62 are formed at intervals from the third layer 8 laterally from the bottom wall of the second trench structure 12. Preferably, the sidewall buffer layers 62 protrude from the branch portions 63 into the low-concentration layer 6b. Preferably, the sidewall buffer layers 62 are formed within the low-concentration layer 6b at intervals from the third layer 8 laterally from the high-concentration layer 6a. The sidewall buffer layers 62 have an n-type impurity concentration that is lower than the p-type impurity concentration of the high-concentration layer 6a.The n-type impurity concentration in the sidewall buffer layers 62 exceeds the p-type impurity concentration in the low concentration layer 6b.

[0121] The sidewall buffer layers 62 face the second electrode 18, sandwiching the second insulating film 17 between them. The sidewall buffer layers 62 are formed on the first side of the main surface 3 relative to a depth position of the bottom-side insulator 19. Therefore, in this embodiment, the sidewall buffer layers 62 face only the second electrode 18, sandwiching the second insulating film 17 between them. Of course, the sidewall buffer layers 62 can also be formed covering the bottom-side insulator 19.

[0122] Each sidewall buffer layer 62 has a predetermined region width WB. The region width WB is a width in a direction orthogonal to a direction in which the sidewall buffer layer 62 extends in plan view. In other words, the region width WB is the width of the sidewall buffer layer 62 that appears when a portion of the second trench structure 12 extending in the first direction X (second direction Y) is patterned section by section in the second direction Y (first direction X).

[0123] Preferably, the region width WB is smaller than the first trench width W1 of the first trench structure 11 (WB < W1). Preferably, the region width WB is smaller than the second trench width W2 of the second trench structure 12 (WB < W2). Preferably, the region width WB is smaller than the width of the intermediate trench region 20 (trench interval IT) (WB < IT). The region width WB may exceed 0 µm, but may not exceed 10 µm. The region width WB is preferably not more than 3 µm.

[0124] In this embodiment, the semiconductor device 61 includes a p-type compensation region 64 formed in a region of the first layer 6 on the bottom wall side of the second trench structure 12. In Fig. 12 and Fig. 13, the compensation region 64 is indicated by dashed lines. The compensation region 64 may also be referred to as an "offset region" or "offset compensation region." The compensation region 64 includes both an n-type and a p-type impurity and is a p-type region having a p-type impurity concentration that exceeds the n-type impurity concentration.

[0125] The compensation region 64 is formed along the surfaces of the walls (sidewalls and bottom wall) of the second trench structure 12 in a region of the first layer 6 that is farther toward the bottom wall side of the second trench structure 12 than the sidewall buffer layers 62. In this embodiment, the sidewall buffer layers 62 are formed by introducing an n-type impurity into the interior of the chip 2 via the inner walls of the second trench 16 using an ion implantation method. The region width WB of each sidewall buffer layer 62 is adjusted by adjusting the amount of the n-type impurity introduced via the inner walls of the second trench 16.

[0126] The n-type impurity concentration of a portion of the impurity introduced into the high-concentration layer 6a is lower than the p-type impurity concentration in the high-concentration layer 6a. Therefore, the n-type impurity introduced into the high-concentration layer 6a is supported by the p-type impurity in a manner of maintaining the function of the high-concentration layer 6a and forms the p-type compensation region 64 with the high-concentration layer 6a. On the other hand, the impurity concentration of a portion of the n-type impurity introduced into the low-concentration layer 6b exceeds the p-type impurity concentration in the low-concentration layer 6b.Therefore, the n-type impurity introduced into the low concentration layer 6b is replaced by the p-type impurity in the form of canceling the function of the low concentration layer 6b, and the low concentration layer 6b is replaced by the sidewall buffer layers 62.

[0127] Due to the p-type impurities diffusing from the high-concentration layer 6a, the low-concentration layer 6b has a concentration gradient in which the p-type impurity concentration gradually increases toward the high-concentration layer 6a. Therefore, a portion of the n-type impurity introduced into a lower portion of the low-concentration layer 6b is displaced by the p-type impurity in the form of an offset from the high-concentration layer 6a side to the third layer 8 (embedded low-concentration layer 8a) side. The sidewall buffer layers 62 are formed within the low-concentration layer 6b at intervals from the third layer 8 (embedded low-concentration layer 8a) from the high-concentration layer 6a side.On the other hand, the compensation region 64 is formed along the sidewalls and bottom wall of the second trench structure 12 by a thickness-direction middle portion of the low-concentration layer 6b. The compensation region 64 may be connected to the impurity region 22 at a lower portion of the end portion.

[0128] Each sidewall buffer layer 62 forms a pn junction portion JE that extends the pn junction portion J to the first layer 6 (more precisely, the low-concentration layer 6b). That is, the semiconductor device 61 includes the pn junction portions JE that extend from the branch portions 63 to the sidewall of the second trench structure 12 side to extend portions of the pn junction portion J to the sidewall of the second trench structure 12 side within the chip 2 (transistor region 9A). The pn junction portion JE may also be referred to as a "pn junction portion" or a "pn boundary portion." The pn junction portion JE is synonymous with the "sidewall buffer layer 62." A description of the “pn junction section JE” is determined by replacing “sidewall buffer layer 62” with “pn junction section JE”.

[0129] Fig. 14 is a diagram showing the breakdown voltage VB of the Fig. 12 shows the semiconductor device 61. In Fig. 14, the ordinate shows the breakdown voltage VB [V] and the abscissa the region width WB [µm]. A single polygonal line LB is shown in Fig. 14. The single polygonal line LB indicates the breakdown voltage VB of the semiconductor device 61. Here, the region width WB is set in a range between 0 µm and 2 µm. Here, too, a potential of 0 V is applied to the first layer 6 and the first trench structure 11. The voltages here are voltages based on the potential (= 0 V) ​​of the first layer 6.

[0130] With respect to the single polygonal line LB, the breakdown voltage VB increased with increasing region width WB. This demonstrated that the pn junction portions JE (sidewall buffer layers 62) should be preferentially formed. This is because the pn junction portions JE (sidewall buffer layers 62) relieve the electric field concentrations with respect to the branch portions 63.

[0131] As described above, the semiconductor device 61 includes the pn junction portion JE extending from the branch portion 63 of the pn junction portion J and the sidewall of the second trench structure 12 toward the bottom wall side of the second trench structure 12 to expand the pn junction portion J in the transistor region 9A (device region 9). With this structure, the electric field concentration at the branch portion 63 can be relaxed by the pn junction portion JE. Thus, a semiconductor device 61 capable of improving the withstand voltage (specifically, the breakdown voltage VB) can be provided.

[0132] Viewed from another angle, the semiconductor device 61 includes the n-type sidewall buffer layer 62, which protrudes from the branch portion 63 of the third layer 8 and the second trench structure 12 toward the first layer 6 in the device region 9 and extends along the sidewall of the second trench structure 12. With this structure, the electric field concentration at the branch portion 63 can be relaxed by the sidewall buffer layer 62. Thus, a semiconductor device 61 capable of improving the withstand voltage (specifically, the breakdown voltage VB) can be provided.

[0133] Of course, the features according to the second to fourth embodiments may be combined in the semiconductor device 61. That is, the semiconductor device 61 may include the second trench structure 12 to which the trench potential VT of not less than 0 V is to be applied. Furthermore, the semiconductor device 61 may include the inter-trench region 20 to which the inter-trench potential VI of not less than 0 V is to be applied.

[0134] Fig. 15 corresponds to Fig. 12 is a sectional view showing a semiconductor device 65 according to a sixth embodiment. The semiconductor device 65 has a shape in which the semiconductor device 61 is modified. Hereinafter, structures corresponding to those described in the first to fifth embodiments are provided with the same symbols, and their descriptions are omitted.

[0135] In the semiconductor device 61, the sidewall buffer layers 62 were formed directly along the second trench structure 12. On the other hand, see Fig. 15, the semiconductor device 65 includes a plurality of sidewall buffer layers 62 aligned along the first trench structure 11 and the second trench structure 12. One set of sidewall buffer layers 62 is formed along the second trench structure 12 in the same manner as in the fifth embodiment, and another set of sidewall buffer layers 62 is formed along the first trench structure 11 in the same manner as the one set of sidewall buffer layers 62.

[0136] A specific description of the sidewall buffer layers 62 on the first trench structure 11 side is determined by replacing "second trench structure 12" with "first trench structure 11" in the above description of the semiconductor device 61. The sidewall buffer layer 62 on the second trench structure 12 side can be integrated with the sidewall buffer layer 62 on the first trench structure 11 side in the inter-trench region 20. As described above, the same effects as those described for the semiconductor device 61 also occur in the semiconductor device 65.

[0137] Fig. 16 corresponds to Fig. 12 is a sectional view showing a semiconductor device 66 according to a seventh embodiment. The semiconductor device 66 has a shape in which the semiconductor device 61 is modified. Hereinafter, structures corresponding to those described in the first to sixth embodiments are provided with the same symbols, and their descriptions are omitted.

[0138] With the semiconductor device 61, the trench separation structure 10 includes the first trench structure 11 and the second trench structure 12, and the sidewall buffer layers 62 are formed along the second trench structure 12. On the other hand, see Fig. 16, the trench separation structure 10 including the semiconductor device 66 does not include the second trench structure 12, but includes only the first trench structure 11, and the sidewall buffer layers 62 are formed only along the first trench structure 11. A specific description of the sidewall buffer layers 62 is determined by replacing "second trench structure 12" with "first trench structure 11" in the above description of the semiconductor device 61. As described above, the same effects as those described for the semiconductor device 61 also occur in the semiconductor device 66.

[0139] In each of the fifth to seventh embodiments, an example was described in which the sidewall buffer layers 62 are formed by introducing the n-type impurity into the interior of the chip 2 by the ion implantation method via the inner walls of the first trench 13 and / or the inner walls of the second trench 16. However, the sidewall buffer layers 62 may be introduced into the interior of the chip 2 by an ion implantation method via the first main surface 3 before the first trench 13 and / or the second trench 16 are formed.

[0140] After a step of forming the sidewall buffer layers 62, the first trench 13 and / or the second trench 16 are formed in the first main surface 3 such that they penetrate through the sidewall buffer layers 62. In this step, the compensation region 64 according to any of the fifth to seventh embodiments is not formed. In this case, the sidewall buffer layers 62 may be connected to the high-concentration layer 6a of the first layer 6 or may be formed at intervals from the third layer 8 laterally of the high-concentration layer 6a. The sidewall buffer layers 62 may be formed at the same time as the sinker regions 21.

[0141] Fig. 17 corresponds to Fig. 3 is a sectional view showing a semiconductor device 71 according to an eighth embodiment. Hereinafter, structures corresponding to those described in the first to seventh embodiments are provided with the same symbols, and their descriptions are omitted.

[0142] With reference to Fig. 17, the semiconductor device 71 includes the first layer 6, the second layer 7, the third layer 8, the transistor region 9A (device embodiment 9), the trench separation structure 10 (trench structure), and the MISFET 30, as in the first embodiment. In this embodiment, the second layer 7 is directly laminated on the first layer 6. In this embodiment, the third layer 8 is formed in the transistor region 9A so as to extend across a boundary portion between the first layer 6 and the second layer 7 at a distance from the trench separation structure 10 (in this embodiment, the second trench structure 12). The third layer 8 forms the pn junction portion J with the first layer 6.

[0143] As in the first embodiment, the third layer 8 includes the low-concentration embedded layer 8a and the high-concentration embedded layer 8b. The low-concentration embedded layer 8a is formed in a region on the first layer 6 side with respect to the boundary portion between the first layer 6 and the second layer 7. Specifically, the embedded layer 8a is formed within the low-concentration layer 6b at a distance from a boundary portion between the low-concentration layer 6b of the first layer 6 and the second layer 7 with respect to the thickness direction of the chip 2. The low-concentration embedded layer 8a is formed within the low-concentration layer 6b at a distance to the second layer 7 side from the high-concentration layer 6a of the first layer 6 with respect to the thickness direction of the chip 2.The low-concentration embedded layer 8a is formed at a distance from the second trench structure 12 with respect to a width direction of the device region 9. The low-concentration embedded layer 8a forms the pn junction portion J with the first layer 6 (high-concentration layer 6a).

[0144] The high-concentration embedded layer 8b is formed to extend across the boundary portion between the first layer 6 and the second layer 7. Specifically, the high-concentration embedded layer 8b is interposed between the low-concentration embedded layer 8a and the second layer 7 so as to extend across the boundary portion between the low-concentration layer 6b of the first layer 6 and the second layer 7, and is electrically connected to the low-concentration embedded layer 8a and the second layer 7. The high-concentration embedded layer 8b is formed at a distance from the second trench structure 12 with respect to the width direction of the device region 9.

[0145] The third layer 8 (low-concentration embedded layer 8a and high-concentration embedded layer 8b) is formed at a predetermined region interval IR from the trench separation structure 10 (second trench structure 12). That is, the third layer 8 exposes the first layer 6 between itself and the trench separation structure 10. The region interval IR may exceed 0 µm but may not exceed 10 µm. The region interval IR is preferably not more than 5 µm.

[0146] In this embodiment, the above-described sinker regions 21 are formed in a region between the third layer 8 and the trench separation structure 10 (second trench structure 12) in plan view. The sinker regions 21 are preferably formed at intervals from the trench separation structure 10 (second trench structure 12) laterally from the third layer 8 in plan view. That is, the sinker regions 21 are preferably not connected to the third layer 8. The lower end portions of the sinker regions 21 may be connected to the first layer 6 or formed inside the second layer 7 at intervals from the first layer 6.

[0147] Fig. 18 is a diagram showing the breakdown voltage VB of the Fig. 17 shows the semiconductor device 71. In Fig. In Figure 18, the ordinate shows the breakdown voltage VB [V] and the abscissa the region interval IR [µm]. Here, the region interval IR is set between 0 µm and 5 µm. Here, too, a potential of 0 V is applied to the first layer 6 and the first trench structure 11. The voltages here are voltages based on the potential (= 0 V) ​​of the first layer 6.

[0148] A single polygonal line LC is in Fig. 18. The single polygonal line LC shows the breakdown voltage VB of the semiconductor device 71. With respect to the single polygonal line LC, the breakdown voltage VB increased as the region interval IR increased. This is because the electric field concentration with respect to the second trench structure 12 is relaxed by forming the third layer 8 to be recessed with respect to the second trench structure 12.

[0149] As described above, the semiconductor device 71 includes the p-type first layer 6, the p-type or n-type second layer 7, the transistor region 9A (device region 9), the trench separation structure 10 (trench structure), and the n-type third layer 8 (embedded layer). The second layer 7 is laminated on the first layer 6. The transistor region 9A is provided in the second layer 7. The trench separation structure 10 penetrates into the third layer 8 so as to reach the first layer 6 and define the transistor region 9A in the third layer 8. The third layer 8 is formed in the transistor region 9A so as to extend beyond the boundary portion between the first layer 6 and the third layer 8 at a distance from the trench separation structure 10. With this structure, a semiconductor device 71 can be provided with which the withstand voltage (in particular, the breakdown voltage VB) can be improved.

[0150] Specifically, the trench separation structure 10 includes the multi-trench structure including a plurality of trench structures each formed to penetrate through the second layer 7 to reach the first layer 6 and aligned at intervals in directions away from the transistor region 9A to define the transistor region 9A in the second layer 7.

[0151] In this embodiment, the plurality of trench structures includes the first trench structure 11 and the second trench structure 12. The first trench structure 11 is electrically connected to the first layer 6 and electrically insulated from the second layer 7. The second trench structure 12 is electrically insulated from the first layer 6 and the second layer 7. In this embodiment, the third layer 8 is formed at a distance from the second trench structure 12. The withstand voltage (more precisely, the breakdown voltage VB) of the semiconductor device 71 is increased by such a structure.

[0152] Fig. 19 corresponds to Fig. 17 is a sectional view showing a semiconductor device 72 according to a ninth embodiment. The semiconductor device 72 has a shape in which the semiconductor device 71 is modified. Hereinafter, structures corresponding to those described in the first to eighth embodiments are provided with the same symbols, and their descriptions are omitted.

[0153] In the semiconductor device 71, the trench separation structure 10 includes the first trench structure 11 and the second trench structure 12, and the third layer 8 is formed at a distance from the second trench structure 12. On the other hand, see Fig. 19, the trench separation structure 10 in the semiconductor device 72 does not include the second trench structure 12, but includes only the first trench structure 11, and the third layer 8 is formed at a distance from the first trench structure 11. A specific description of the third layer 8 is determined by replacing "second trench structure 12" with "first trench structure 11" in the above description of the semiconductor device 71. As described above, the same effects as those described for the semiconductor device 71 also occur in the semiconductor device 72.

[0154] Fig. 20 corresponds to Fig. 4 is a sectional view showing a semiconductor device 81 according to a tenth embodiment, together with a trench structure according to a first configuration example. Hereinafter, structures corresponding to those described for the first to ninth embodiments are provided with the same symbols, and their descriptions are omitted.

[0155] With reference to Fig. 20, in the semiconductor device 81, the second trench structure 12 is formed at a deeper position than the first trench structure 11 so as to penetrate through the pn junction portion J. Specifically, the second trench structure 12 penetrates through the second layer 7 and the third layer 8 so as to reach the first layer 6 at a deeper position than the first trench structure 11. The first trench structure 11 protrudes by the first value P1 from the pn junction portion J toward the second side of the main surface 4. On the other hand, the second trench structure 12 protrudes by the second value P2, which is smaller than the first value P1 (P2 < P1), from the pn junction portion J toward the second side surface 4. Descriptions of the second trench structure 12 according to the first embodiment apply to other descriptions of the second trench structure 12 according to this embodiment.

[0156] The above-described impurity region 22 is formed in this embodiment at a distance from the bottom wall of the second trench structure 12, away from the bottom wall of the first trench structure 11. Thus, the impurity region 22 does not cover the bottom wall of the second trench structure 12. With respect to the thickness direction of the first layer 6, the impurity region 22 may face the bottom wall of the second trench structure 12, with a portion of the first layer 6 (high-concentration layer 6a) interposed therebetween.

[0157] The second trench structure 12 may take a different shape than that shown in Fig. 20. Further configuration examples for the second trench structure 12 are described below with reference to Fig. 21A and Fig. 21B illustrates. Fig. 21A is a sectional view showing the Fig. 20 together with the second trench structure 12 according to the second configuration example. The following are the structures corresponding to the Fig. 20 are provided with the same symbols and their description is omitted.

[0158] With reference to Fig. 21A, the second trench structure 12 may be assumed to have no bottom insulator 19. That is, the second trench structure 12 may include the second insulating film 17 covering the inner walls (inner peripheral wall, outer peripheral wall, and bottom wall) of the second trench 16 with a substantially uniform thickness. In this case, the second insulating film 17 preferably has a thickness less than half the second trench width W2 of the second trench structure 12. The thickness of the second insulating film 17 is the thickness along the normal direction to the wall surface of the second trench structure 12 (second trench 16).

[0159] The thickness of the second insulating film 17 is preferably less than half the width of the bottom wall of the second trench structure 12. The width of the bottom wall of the second trench structure 12 is a width in a direction orthogonal to the direction in which the second trench structure 12 extends in plan view. Under this condition, the second trench width W2 may be not smaller than the first trench width W1 of the first trench structure 11 (W1≤W2) or may be smaller than the first trench width W1 (W1>W2).

[0160] Fig. 21B is a sectional view showing the Fig. 20 together with the second trench structure 12 according to the third configuration example. In the following, the structures corresponding to the Fig. 20 are provided with the same symbols and their description is omitted.

[0161] With reference to Fig. 21B, the second trench structure 12 may be assumed to have no second electrode 18. That is, the second trench structure 12 may include the second insulating film 17 embedded as an integral element in the second trench 16. In this case, the second trench structure 12 may be referred to as the "insulating trench structure." Under this condition, the second trench width W2 may be not smaller than the first trench width W1 of the first trench structure 11 (W1 ≤ W2) or may be smaller than the first trench width W1 (W1 > W2).

[0162] Fig. 22 is a diagram showing a breakdown voltage VB of the Fig. 20 together with a breakdown voltage VB of a semiconductor device according to a reference example. In Fig. In Figure 22, the ordinate represents the breakdown voltage VB [V], and the abscissa represents the object (the semiconductor device under test). Here, a potential of 0 V is applied to the first layer 6 and the first trench structure 11. The voltages here are voltages based on the potential (= 0 V) ​​of the first layer 6.

[0163] A first chart bar GA and a second chart bar GB are in Fig. 22. The first graph bar GA indicates the breakdown voltage VB of the semiconductor device according to the reference example. The second graph bar GB indicates the breakdown voltage VB of the semiconductor device 81. The semiconductor device according to the reference example has the same structure as the semiconductor device 81, except that it does not include the second trench structure 12. Other descriptions of the semiconductor device according to the reference example are omitted.

[0164] Referring to the first and second graph bars GA and GB, the breakdown voltage VB has increased due to the formation of the second trench structure 12, which is shallower than the first trench structure 11. It has been shown that the breakdown voltage VB is also improved when the second trench structure 12 is shallower than the first trench structure 11.

[0165] In comparison to the second trench structure 12 of the semiconductor device 1 (see Fig. 3 and Fig. 4) In the second trench structure 12 of the semiconductor device 81, an area of ​​the first layer 6 and the second electrode 18 (ie, a parasitic capacitance of the second trench structure 12) is reduced. Therefore, the breakdown voltage VB increases even when the second trench structure 12, which is shallower than the first trench structure 11, is formed. Even if the Fig. 21A and Fig. 21B are applied, the parasitic capacitance of the second trench structure 12 is reduced. The breakdown voltage VB thus also increases in the cases of Fig. 21A and Fig. 21B.

[0166] As described above, the semiconductor device 81 has the second trench structure 12 which is shallower than the first trench structure 11. With this structure, a semiconductor device 81 can be provided with which the withstand voltage (in particular, the breakdown voltage VB) can be improved.

[0167] Modification examples applied to the first to tenth embodiments will be described below with reference to Fig. 23 to Fig. 27 illustrates. Fig. 23 is a sectional view showing a first modification example of the chip 2 according to any one of the first to tenth embodiments. Although an application of the chip 2 according to the first modification example to the semiconductor device 1 according to the first embodiment will be described here, the chip 2 according to the first modification example is also applicable to the second to tenth embodiments. Hereinafter, structures corresponding to those described for the first to tenth embodiments are provided with the same symbols, and their descriptions are omitted.

[0168] In the first embodiment, the first layer 6 has the laminated structure including the high concentration layer 6a and the low concentration layer 6b. As shown in Fig. However, as shown in Figure 23, the chip 2 may instead include a first layer 6 having a single-layer structure. The first layer 6 may be constructed of a p-type semiconductor substrate. In this case, the first layer 6 may have the impurity concentration of the high-concentration layer 6a or the impurity concentration of the low-concentration layer 6b. In this case, too, the pn junction portion J is formed at the boundary portion between the first layer 6 and the third layer 8 (low-concentration embedded layer 8a).

[0169] Fig. 24 is a sectional view showing a second modification example of the chip 2 according to any one of the first to tenth embodiments. Although an application of the chip 2 according to the second modification example to the semiconductor device 1 according to the first embodiment will be described here, the chip 2 according to the first modification example is also applicable to the second to tenth embodiments. Hereinafter, structures corresponding to those described for the first to tenth embodiments are provided with the same symbols, and their descriptions are omitted.

[0170] In the first embodiment, the third layer 8 has a laminated structure including the low-concentration embedded layer 8a and the high-concentration embedded layer 8b. As shown in Fig. 24, however, the chip 2 may instead include a third layer 8 having a single-layer structure. In this case, the third layer 8 may have the impurity concentration of the low-concentration embedded layer 8a or the high-concentration impurity concentration of the high-concentration embedded layer 8b. In this case, too, the pn junction portion J is formed at the boundary portion between the first layer 6 (low-concentration layer 6b) and the third layer 8. When the n-type second layer 7 is deposited, the second layer 7 may have a lower impurity concentration than the third layer 8.

[0171] Fig. 25 is a sectional view showing a third modification example of the chip 2 according to any one of the first to tenth embodiments. Although an application of the chip 2 according to the third modification example to the semiconductor device 1 according to the first embodiment will be described here, the chip 2 according to the third modification example is also applicable to the second to tenth embodiments. Hereinafter, structures corresponding to those described for the first to tenth embodiments are provided with the same symbols, and their descriptions are omitted.

[0172] In the first embodiment, the second n-type layer 7 (n-type epitaxial layer) is formed. As shown in Fig. However, as shown in Figure 25, the chip 2 may instead include the second p-type layer 7 (p-type epitaxial layer). When the second p-type layer 7 is deposited, the structure within the transistor region 9A is adjusted accordingly. An example structure within the transistor region 9A is described below.

[0173] In this embodiment, the semiconductor device 1 includes a p-type separator 92 as an example of a region separation structure that defines a cell region 91 in the transistor region 9A. The separation region 92 is formed at a distance inward from the inner peripheral wall of the second trench structure 12 in plan view. The separation region 92 has a cylindrical shape surrounding an inner portion of the second layer 7 from a bottom layer side to a surface layer side of the second layer 7. In this embodiment, the separation region 92 includes a p-type buried region 93 and a p-type column region 94.

[0174] The embedded region 93 is formed at a boundary portion between the third layer 8 (specifically, the high-concentration embedded layer 8b) and the second layer 7. The embedded region 93 is formed at a distance inward from the inner peripheral wall of the second trench structure 12 and exposes a portion of the third layer 8 between it and the second trench structure 12. The column region 94 is formed in a region of the second layer 7 between the first surface 3 and a peripheral portion of the edge of the embedded region 93 and is electrically connected to the embedded region 93. The number of laminated layers of the column region 94 is arbitrary, and two or more column regions 94 may be laminated from the embedded region 93 side to the first main surface 3 side.

[0175] The above-described sinker region 21 is formed in a region of the transistor region 9A between the second trench structure 12 and the isolation region 92. The sinker region 21 is formed within the second layer 7 and extends along a sidewall of the second trench structure 12. In this embodiment, the sinker region 21 is formed as a film extending only along the inner peripheral wall of the second trench structure 12. In plan view, the sinker region 21 is formed in a ring shape and extends along the inner peripheral wall of the second trench structure 12, surrounding the isolation region 92. The lower end portion of the sinker region 21 is electrically connected to the third layer 8 (high-concentration embedded layer 8b).

[0176] The above-described MISFET 30 is formed in the same manner as in the first embodiment within the cell region 91 defined by the separation region 92. In this embodiment, the channel regions 35 are formed in regions between the first well region 31 and the source regions 34 in surface layer portions of the second layer 7. Other descriptions of the MISFET 30 are omitted because the descriptions of the MISFET 30 according to the first embodiment apply to it.

[0177] Fig. 26 is a sectional view showing a fourth modification example of the chip 2 according to any one of the first to tenth embodiments. Although an application of the chip 2 according to the fourth modification example to the semiconductor device 1 according to the first embodiment will be described here, the chip 2 according to the third modification example is also applicable to the second to tenth embodiments. Hereinafter, structures corresponding to those described for the first to tenth embodiments are provided with the same symbols, and their descriptions are omitted.

[0178] In the first embodiment, an example was described in which the chip 2 includes the first layer 6, the second layer 7 and the third layer 8. As shown in Fig. However, as shown in Fig. 26, a chip 2 including the p-type first layer 6 and the n-type second layer 7, but not including the third layer 8, may also be used. In this embodiment, the second layer 7 forms the pn junction portion J with the first layer 6. Of course, the chip 2 may include the first layer 6 having a single-layer structure. In this case, the first layer 6 may have the impurity concentration of the high-concentration layer 6a or the impurity concentration of the low-concentration layer 6b.

[0179] Features of the chips 2 according to the first to fourth modification examples can be combined with each other in any way. Therefore, the chip 2 that includes at least two of the features of the chips 2 according to the first to fourth embodiments at the same time can be combined in any of the first to tenth embodiments.

[0180] Fig. 27 is a sectional view showing a modification example of the sinker regions 21 according to any one of the first to tenth embodiments. Although an application of the sinker regions 21 according to the modification example to the semiconductor device 1 according to the first embodiment will be described here, the sinker regions 21 according to the modification example are also applicable to the second to tenth embodiments. Hereinafter, structures corresponding to those described for the first to tenth embodiments are provided with the same symbols, and their descriptions are omitted.

[0181] In the first embodiment, a configuration example was described in which the sinker regions 21 only cover the second trench structure 12. As shown in Fig.However, as shown in Figure 27, the sinker regions 21 may also cover the first trench structure 11 in addition to the second trench structure 12. The sinker regions 21 are formed either along the inner peripheral wall or along the outer peripheral wall of the first trench structure 11, or along both (in this embodiment). The sinker region 21 covering the inner peripheral wall of the first trench structure 11 may be integrated with the sinker region 21 covering the outer peripheral wall of the second trench structure 12 in the intermediate trench region 20.

[0182] The embodiments of the present invention can be implemented in still other embodiments. In each of the embodiments described above, a configuration example was described in which the trench separation structure 10 defines the transistor region 9A. However, the device region 9 defined by the trench separation structure 10 is not limited to the transistor region 9A. That is, the trench separation structure 10 may define the device region 9, which is not limited to the transistor region 9A and in which at least one semiconductor device, a semiconductor rectifier device, or a passive device is formed.

[0183] In each of the embodiments described above, the trench separation structure 10 may include any number of the first trench structures 11 and any number of the second trench structures 12. That is, the trench separation structure 10 may include a plurality of the first trench structures 11 and a plurality of the second trench structures 12. The trench separation structure 10 may include a single first trench structure 11 and a plurality of second trench structures 12. The trench separation structure 10 may include a plurality of first trench structures 11 and a single second trench structure 12.

[0184] When the trench separation structure 10 includes a plurality of first trench structures 11, the plurality of first trench structures 11 may be formed at a distance (e.g., the trench interval IT) from each other so as to surround the device region 9. When the trench separation structure 10 includes a plurality of second trench structures 12, the plurality of second trench structures 12 may be formed at a distance (e.g., the trench interval IT) from each other so as to surround the device region 9 in a region between the device region 9 and the first trench structure 11.

[0185] Although in each of the above-described embodiments, an example was described in which the first conductivity type is p-type and the second conductivity type is n-type, the first conductivity type may instead be n-type and the second conductivity type may be p-type. Specific configurations in this case are determined by replacing the n-type regions with p-type regions and replacing the p-type regions with n-type regions in the above description and the attached drawings. Although in each of the above-described embodiments, an example was described in which the p-type was expressed as "first conductivity type" and the n-type as "second conductivity type," these expressions are used to clarify the order of description, and the p-type may instead be expressed as "second conductivity type" and the n-type as "first conductivity type."

[0186] Features of the first to tenth embodiments described above can be arbitrarily combined with each other. Therefore, a semiconductor device can be adopted that includes at least two of the features of the first to tenth embodiments at the same time.

[0187] That is, the features of the second embodiment can be combined with the features of the first embodiment. Furthermore, the features of the third embodiment can be combined with any of the features of the first and second embodiments. Furthermore, the features of the fourth embodiment can be combined with any of the features of the first to third embodiments. Furthermore, the features of the fifth embodiment can be combined with any of the features of the first to fourth embodiments. Furthermore, the features of the sixth embodiment can be combined with any of the features of the first to fifth embodiments.

[0188] Furthermore, the features of the seventh embodiment can be combined with any of the features of the first to sixth embodiments. Furthermore, the features of the eighth embodiment can be combined with any of the features of the first to seventh embodiments. Furthermore, the features of the ninth embodiment can be combined with any of the features of the first to eighth embodiments. Furthermore, the features of the tenth embodiment can be combined with any of the features of the first to ninth embodiments.

[0189] The following are examples of features extracted from this specification and the drawings. The following [A1] to [A20], [B1] to [B20], [C1] to [C22], and [D1] to [D20] each provide a semiconductor device capable of improving the withstand voltage. Although alphanumeric characters in parentheses below represent corresponding components, etc., in the embodiments described above, these are not intended to limit the scope of the respective clauses to the embodiments.

[0190] [A1] The semiconductor device (1, 51, 53, 55, 61, 65, 66, 71, 72, 81 (hereinafter simply referred to as “1 etc.")), comprising: a chip (2) having a first main surface (3) on one side and a second main surface (4) on another side; a pn junction portion (J) formed in an interior of the chip (2) so as to extend along the first main surface (3); a device region (9, 9A) provided in the first main surface (3); a first trench structure (11) formed in the first main surface (3) so as to penetrate through the pn junction portion (J) and define the device region (9, 9A) in the first main surface (3); and a second trench structure (12) formed in the first main surface (3) so as to penetrate through the pn junction portion (J) and define the device region (9, 9A) in a region further than the first trench structure (11) toward the side of the device region (9, 9A) demarcates.

[0191] [A2] The semiconductor device (1, etc.) according to A1, wherein the first trench structure (11) is constructed of a first trench electrode structure (11) electrically connected to the chip (2), and the second trench structure (12) is constructed of a second trench electrode structure (12) electrically insulated from the chip (2).

[0192] [A3] The semiconductor device (1, etc.) according to A1 or A2, wherein the first trench structure (11) has a lower end portion electrically connected to the chip (2).

[0193] [A4] The semiconductor device (1, etc.) according to any one of items A1 to A3, wherein the second trench structure (12) is electrically separated from the first trench structure (11).

[0194] [A5] The semiconductor device (1, etc.) according to any one of items A1 to A4, wherein the second trench structure (12) is formed in an electrically floating state.

[0195] [A6] The semiconductor device (1, etc.) according to any one of items A1 to A5, wherein a different potential occurs in the second trench structure (12) than in the first trench structure (11).

[0196] [A7] The semiconductor device (1, etc.) according to any one of items A1 to A6, wherein the first trench structure (11) has a first width (W1) and the second trench structure (12) has a second width (W2) not greater than the first width (W1).

[0197] [A8] The semiconductor device (1, etc.) according to A7, wherein the second trench structure (12) is formed at a distance or interval (IT) of not more than the first width (W1) from the first trench structure (11).

[0198] [A9] The semiconductor device (1, etc.) according to any one of A1 to A8, wherein the first trench structure (11) includes a first trench (13) penetrating through the pn junction portion (J), a first insulating film (14) covering an inner wall of the first trench (13) so that the chip (2) is exposed from a bottom wall of the first trench (13), and a first electrode (15) embedded in the first trench (13) with the first insulating film (14) therebetween and electrically connected to the chip (2) at the bottom wall of the first trench (13), and the second trench structure (12) includes a second trench (16) penetrating through the pn junction portion (J), a second insulating film (17) covering an inner wall of the second trench (16), and a second electrode (18), which is embedded in the second trench (16) with the second insulating film (17) therebetween and is electrically insulated from the chip (2).

[0199] [A10] The semiconductor device (1, etc.) according to A9, wherein the second trench structure (12) comprises a bottom-side insulator (19) embedded in a sidewall of the second trench (16) so as to be continuous with the second insulating film (17) and having a thickness exceeding a thickness of the second insulating film (17), and the second electrode (18) is embedded in the second trench (16) with the second insulating film (17) and the bottom-side insulator (19) therebetween.

[0200] [A11] The semiconductor device (1, etc.) according to any one of A1 to A10, further comprising: a first layer (6) of a first conductivity type formed in a region inside the chip (2) on the second main surface (4) side; a second layer (7) of the first conductivity type or a second conductivity type formed in a region inside the chip (2) on the first main surface (3) side; and a third layer (8) of the second conductivity type arranged in a region inside the chip (2) between the first layer (6) and the second layer (7) and forming the pn junction portion (J) with the first layer (6);wherein the first trench structure (11) penetrates through the second layer (7) and the third layer (8) to reach the first layer (6) and defines the device region (9, 9A) in the second layer (7), and the second trench structure (12) penetrates through the second layer (7) and the third layer (8) to reach the first layer (6) and defines the device region (9, 9A) in a region of the second layer (7) that is further toward the device region (9, 9A) side than the first trench structure (11);

[0201] [A12] The semiconductor device (1, etc.) according to A11, wherein the first trench structure (11) is electrically connected to the first layer (6) and electrically insulated from the second layer (7) and the third layer (8), and the second trench structure (12) is electrically insulated from the first layer (6), the second layer (7) and the third layer (8).

[0202] [A13] The semiconductor device (1, etc.) according to any one of A1 to A10, further comprising: a first layer (6) of a first conductivity type formed in a region inside the chip (2) on the second main surface (4) side; and a second layer (7) of a second conductivity type formed in a region inside the chip (2) on the first main surface (3) side and forming the pn junction portion (J) with the first layer (6); wherein the first trench structure (11) penetrates into the second layer (7) so as to reach the first layer (6) and define the device region (9, 9A) in the second layer (7), and the second trench structure (12) penetrates through the second layer (7) to reach the first layer (6) and defines the device region (9, 9A) in a region of the second layer (7) which is further toward the side of the device region (9, 9A) than the first trench structure (11).

[0203] [A14] The semiconductor device (1, etc.) according to A13, wherein the first trench structure (11) is electrically connected to the first layer (6) and electrically insulated from the second layer (7), and the second trench structure (12) is electrically insulated from the first layer (6) and the second layer (7).

[0204] [A15] The semiconductor device (1, etc.) according to any one of A1 to A14, further comprising: an inter-trench region (20) defined in a region between the first trench structure (11) and the second trench structure (12) and formed in an electrically floating state.

[0205] [A16] The semiconductor device (1, etc.) according to any one of A1 to A15, further comprising: a transistor (30) formed in the device region (9, 9A).

[0206] [A17] A semiconductor device (1 etc.), comprising: a first layer (6) of a first conductivity type; a second layer (7) of the first conductivity type or a second conductivity type laminated on the first layer (6); a third layer (8) of the second conductivity type disposed between the first layer (6) and the second layer (7); a device region (9, 9A) provided in the second layer (7); a first trench structure (11) penetrating through the second layer (7) and the third layer (8) to reach the first layer (6) and defining the device region (9, 9A) in the second layer (7); and a second trench structure (12) penetrating through the second layer (7) and the third layer (8) to reach the first layer (6) and define the device region (9, 9A) in a region of the second layer (7) that is further toward the side of the device region (9, 9A) than the first trench structure (11).

[0207] [A18] The semiconductor device (1, etc.) according to A17, wherein the first trench structure (11) is constructed of a first trench electrode structure (11) electrically connected to the first layer (6) and electrically insulated from the second layer (7) and the third layer (8), and the second trench structure (12) is constructed of a second trench electrode structure (12) electrically insulated from the first layer (6), the second layer (7) and the third layer (8).

[0208] [A19] A semiconductor device (1, etc.) comprising: a first layer (6) of a first conductivity type; a second layer (7) of a second conductivity type laminated on the first layer (6); a device region (9, 9A) provided in the second layer (7); a first trench structure (11) penetrating through the second layer (7) to reach the first layer (6) and defining the device region (9, 9A) in the second layer (7); and a second trench structure (12) penetrating through the second layer (7) to reach the first layer (6) and defining the device region (9, 9A) in a region of the second layer (7) that is further toward the device region (9, 9A) side than the first trench structure (11).

[0209] [A20] The semiconductor device (1, etc.) according to A19, wherein the first trench structure (11) is constructed of a first trench electrode structure (13) electrically connected to the first layer (6) and electrically insulated from the second layer (7), and the second trench structure (12) is constructed of a second trench electrode structure (16) electrically insulated from the first layer (6) and the second layer (7).

[0210] [B1] A semiconductor device (51, 53, 55 (hereinafter simply referred to as "51, etc.")) comprising: a chip (2) having a first main surface (3) on one side and a second main surface (4) on another side; a pn junction portion (J) formed in an interior of the chip (2) so as to extend along the first main surface (3); a device region (9, 9A) provided in the first main surface (3); a first trench structure (11) formed in the first main surface (3) so as to penetrate through the pn junction portion (J) and define the device region (9, 9A) in the first main surface (3);a second trench structure (12) formed in the first main surface (3) so as to penetrate through the pn junction portion (J) and define the device region (9, 9A) in a region further than the first trench structure (11) toward the side of the device region (9, 9A); and an intermediate trench region (20) defined in a region between the first trench structure (11) and the second trench structure (12) and to which a potential (VI) of not less than 0 V is to be applied;

[0211] [B2] The semiconductor device (51 etc.) according to B1, wherein the potential (VI) different from that of the first trench structure (11) is to be applied to the intermediate trench region (20).

[0212] [B3] The semiconductor device (51 etc.) according to B1 or B2, wherein the potential (VI) different from that of the second trench structure (12) is to be applied to the inter-trench region (20).

[0213] [B4] The semiconductor device (51 etc.) according to any one of B1 to B3, wherein the second trench structure (12) is electrically separated from the first trench structure (11).

[0214] [B5] The semiconductor device (51 etc.) according to any one of B1 to B4, wherein the second trench structure (12) is formed in an electrically floating state.

[0215] [B6] The semiconductor device (51 etc.) according to any one of B1 to B4, wherein the potential (VT) different from that of the first trench structure (11) is to be applied to the second trench structure (12).

[0216] [B7] The semiconductor device (51, etc.) according to any one of B1 to B6, further comprising: a contact electrode (52) electrically connected to the inter-trench region (20).

[0217] [B8] A semiconductor device (51 etc.) comprising: a chip (2) having a first main surface (3) on one side and a second main surface (4) on another side; a pn junction portion (J) formed in an interior of the chip (2) so as to extend along the first main surface (3); a device region (9, 9A) provided in the first main surface (3); a first trench structure (11) formed in the first main surface (3) so as to penetrate through the pn junction portion (J) and define the device region (9, 9A) in the first main surface (3);and a second trench structure (12) formed in the first main surface (3) so as to penetrate through the pn junction portion (J) and define the device region (9, 9A) in a region further toward the side of the device region (9, 9A) than the first trench structure (11) and to which a potential (VT) different from that of the first trench structure (11) is to be applied;

[0218] [B9] The semiconductor device (51 etc.) according to B8, wherein the potential (VT) of not less than 0 V is to be applied to the second trench structure (12).

[0219] [B10] The semiconductor device (51, etc.) according to B8 or B9, further comprising: a contact electrode (54) electrically connected to the second trench structure (12).

[0220] [B11] The semiconductor device (51, etc.) according to any one of B1 to B10, wherein the first trench structure (11) has a first width (W1) and the second trench structure (12) has a second width (W2) not greater than the first width (W1).

[0221] [B12] The semiconductor device (51, etc.) according to B11, wherein the second trench structure (12) is formed at a distance (IT) of not more than the first width (W1) from the first trench structure (11).

[0222] [B13] The semiconductor device (51 etc.) according to any one of B1 to B12, wherein the first trench structure (11) is electrically connected to the chip (2) and the second trench structure (12) is electrically insulated from the chip (2).

[0223] [B14] The semiconductor device (51 etc.) according to any one of B1 to B13, wherein the first trench structure (11) includes a first trench (13) penetrating through the pn junction portion (J), a first insulating film (14) covering an inner wall of the first trench (13) so that the chip (2) is exposed from a bottom wall of the first trench (13), and a first electrode (15) embedded in the first trench (13) with the first insulating film (14) therebetween and electrically connected to the chip (2) at the bottom wall of the first trench (13), and the second trench structure (12) includes a second trench (16) penetrating through the pn junction portion (J), a second insulating film (17) covering an inner wall of the second trench (16), and a second electrode (18) which is embedded in the second trench (16) with the second insulating film (17) therebetween and is electrically insulated from the chip (2).

[0224] [B15] The semiconductor device (51, etc.) according to B14, wherein the second trench structure (12) includes a bottom insulator (19) embedded in a sidewall of the second trench (16) so as to be continuous with the second insulating film (17) and having a thickness exceeding a thickness of the second insulating film (17), and the second electrode (18) is embedded in the second trench (16) with the second insulating film (17) and the bottom insulator (19) therebetween.

[0225] [B16] The semiconductor device (51, etc.) according to any one of B1 to B15, further comprising: a first layer (6) of a first conductivity type formed in a region inside the chip (2) on the second main surface (4) side; a second layer (7) of the first conductivity type or a second conductivity type formed in a region inside the chip (2) on the first main surface (3) side; and a third layer (8) of the second conductivity type arranged in a region inside the chip (2) between the first layer (6) and the second layer (7) and forming the pn junction portion (J) with the first layer (6);wherein the first trench structure (11) penetrates through the second layer (7) and the third layer (8) to reach the first layer (6) and defines the device region (9, 9A) in the second layer (7), and the second trench structure (12) penetrates through the second layer (7) and the third layer (8) to reach the first layer (6) and defines the device region (9, 9A) in a region of the second layer (7) that is further toward the device region (9, 9A) side than the first trench structure (11);

[0226] [B17] The semiconductor device (51 etc.) according to B16, wherein the first trench structure (11) is electrically connected to the first layer (6) and electrically insulated from the second layer (7) and the third layer (8), and the second trench structure (12) is electrically insulated from the first layer (6), the second layer (7) and the third layer (8).

[0227] [B18] The semiconductor device (51, etc.) according to any one of B1 to B15, further comprising: a first layer (6) of a first conductivity type formed in a region inside the chip (2) on the second main surface (4) side; and a second layer (7) of a second conductivity type formed in a region inside the chip (2) on the first main surface (3) side and forming the pn junction portion (J) with the first layer (6); wherein the first trench structure (11) penetrates through the second layer (7) to reach the first layer (6) and defines the device region (9, 9A) in the second layer (7), and the second trench structure (12) penetrates through the second layer (7) to reach the first layer (6) and defines the device region (9, 9A) in a region of the second layer (7) that is further toward the side of the device region (9, 9A) than the first trench structure (11).

[0228] [B19] The semiconductor device (51 etc.) according to B18, wherein the first trench structure (11) is electrically connected to the first layer (6) and electrically insulated from the second layer (7), and the second trench structure (12) is electrically insulated from the first layer (6) and the second layer (7).

[0229] [B20] The semiconductor device (51, etc.) according to any one of A1 to A15, further comprising: a transistor (30) formed in the device region (9, 9A).

[0230] [C1] A semiconductor device (61, 65, 66 (hereinafter simply referred to as “61, etc.")), comprising: a chip (2) having a first main surface (3) on one side and a second main surface (4) on another side; a pn junction portion (J) formed in an interior of the chip (2) so as to extend along the first main surface (3); a device region (9, 9A) provided in the first main surface (3); a trench structure (10, 11, 12) formed in the first main surface (3) so as to penetrate through the pn junction portion (J) and define the device region (9, 9A) in the first main surface (3); and a pn junction portion (JE) led out from a branch portion (63) of the pn junction portion (J) and the trench structure (10, 11, 12) to a bottom wall side of the trench structure (10, 11, 12 to extend the pn junction section (J) in the device region (9, 9A).

[0231] [C2] The semiconductor device (61 etc.) according to C1, wherein the pn junction portion (JE) is formed at a distance to the first lateral surface (3) from the bottom surface of the trench structure (10, 11, 12).

[0232] [C3] The semiconductor device (61, etc.) according to C1 or C2, wherein the pn junction portion (JE) has a width which is smaller than a width of the trench structure (10, 11, 12).

[0233] [C4] The semiconductor device (61 etc.) according to any one of C1 to C3, wherein the trench structure (10, 11, 12) is electrically isolated from the chip (2).

[0234] [C5] The semiconductor device (61 etc.) according to any one of C1 to C4, wherein the trench structure (10, 11, 12) is formed in an electrically floating state.

[0235] [C6] The semiconductor device (61 etc.) according to any one of C1 to C4, wherein a different potential (VT) than that of the chip (2) is to be applied to the trench structure (10, 11, 12).

[0236] The semiconductor device (61, etc.) according to any one of C4 to C6, wherein the trench structure (10, 11, 12) includes a trench (13, 16) penetrating through the pn junction portion (J), an insulating film (14, 17) covering an inner wall of the trench (13, 16), and an electrode (15, 18) embedded in the trench (13, 16) with the insulating film (14, 17) therebetween and electrically insulated from the chip (2), and the pn junction portion (JE) faces the electrode (15, 18) with the insulating film (14, 17) therebetween.

[0237] [C8] The semiconductor device (61 etc.) according to any one of C1 to C3, wherein the trench structure (10, 11, 12) is connected to the chip (2).

[0238] [C9] The semiconductor device (61, etc.) according to C8, wherein the trench structure (10, 11, 12) includes a trench (13, 16) penetrating through the pn junction portion (J), an insulating film (14, 17) covering an inner wall of the trench (13, 16) so that the chip (2) is exposed from the bottom wall of the trench (13, 16), and an electrode (15, 18) embedded in the trench (13, 16) with the insulating film (14, 17) therebetween and electrically connected to the chip (2) at the bottom wall of the trench (13, 16), and the pn junction portion (JE) is opposed to the electrode (15, 18) with the insulating film (14, 17) therebetween.

[0239] [C10] The semiconductor device (61, etc.) according to any one of C1 to C9, further comprising: a first layer (6) of a first conductivity type formed in a region inside the chip (2) on the second main surface (4) side; a second layer (7) of the first conductivity type or a second conductivity type formed in a region inside the chip (2) on the first main surface (3) side; a third layer (8) of the second conductivity type disposed in a region inside the chip (2) between the first layer (6) and the second layer (7) and forming the pn junction portion (J) with the first layer (6); the trench structure (10, 11, 12) penetrating through the second layer (7) and the third layer (8) to reach the first layer (6) and defining the device region (9, 9A) in the second layer (7);and a sidewall buffer layer (62) of the second conductivity type led out from a branch portion (63) of the third layer (8) and the trench structure (10, 11, 12) to the bottom wall side of the trench structure (10, 11, 12) to extend the pn junction portion (J) in the device region (9, 9A) and form the pn junction portion (JE) with the first layer (6);

[0240] [C11] The semiconductor device (61, etc.) according to any one of C1 to C9, further comprising: a first layer (6) of a first conductivity type formed in a region inside the chip (2) on the second main surface (4) side; a second layer (7) of a second conductivity type formed in a region inside the chip (2) on the first main surface (3) side and forming the pn junction portion (J) with the first layer (6); the trench structure (10, 11, 12) penetrating through the second layer (7) to reach the first layer (6) and defining the device region (9, 9A) in the second layer (7);and a sidewall buffer layer (62) of the second conductivity type led out from a branch portion (63) of the second layer (7) and the trench structure (10, 11, 12) to the bottom wall side of the trench structure (10, 11, 12) to extend the pn junction portion (J) in the device region (9, 9A) and form the pn junction portion (JE) with the first layer (6);

[0241] [C12] The semiconductor device (61, etc.) according to C10 or C11, wherein the first layer (6) includes a high concentration layer (6a) of the first conductivity type formed in a region on the second main surface (4) side, and a low concentration layer (6b) of the first conductivity type formed in a region on the first main surface (3) side and having a lower impurity concentration than the high concentration layer (6a), and the sidewall buffer layer (62) extends from the branch portion (63) into the low concentration layer (6b).

[0242] [C13] The semiconductor device (61 etc.) according to C12, wherein the sidewall buffer layer (62) is formed at a distance from the first main surface (3) laterally from the high concentration layer (6a).

[0243] [C14] The semiconductor device (61, etc.) according to C12 or C13, wherein the sidewall buffer layer (62) has an impurity concentration higher than the low concentration layer (6b) and lower than the high concentration layer (6a).

[0244] [C15] A semiconductor device (61 etc.) comprising: a chip (2) having a first main surface (3) on one side and a second main surface (4) on another side; a pn junction portion (J) formed in an interior of the chip (2) so as to extend along the first main surface (3); a device region (9, 9A) provided in the first main surface (3); a first trench structure (11) formed in the first main surface (3) so as to penetrate through the pn junction portion (J) and define the device region (9, 9A) in the first main surface (3); a second trench structure (12) formed in the first main surface (3) so as to penetrate through the pn junction portion (J) and define the device region (9, 9A) in a region further than the first trench structure (11) toward the side of the device region (9, 9A);and a pn junction portion (JE) led out from a branch portion (63) of the pn junction portion (J) and a sidewall of the second trench structure (12) to a bottom wall side of the second trench structure (12) to extend the pn junction portion (J) in the device region (9, 9A);

[0245] [C16] The semiconductor device (61 etc.) according to C15, wherein the pn junction portion (JE) is formed at a distance from the first main surface (3) laterally from the lower surface of the second trench structure (12).

[0246] [C17] The semiconductor device (61 etc.) according to C15 or C16, wherein the second trench structure (12) is electrically separated from the first trench structure (11).

[0247] [C18] The semiconductor device (61 etc.) according to any one of C15 to C17, wherein the first trench structure (11) is electrically connected to the chip (2) and the second trench structure (12) is electrically insulated from the chip (2).

[0248] [C19] The semiconductor device (61, etc.) according to any one of C15 to C18, wherein the second trench structure (12) is formed in an electrically floating state.

[0249] [C20] The semiconductor device (61 etc.) according to any one of C15 to C19, wherein the potential (VT) different from that of the first trench structure (11) is to be applied to the second trench structure (12).

[0250] [C21] A semiconductor device (61 etc.) comprising: a first layer (6) of a first conductivity type; a second layer (7) of the first conductivity type or a second conductivity type laminated on the first layer (6); a third layer (8) of the second conductivity type arranged in a region between the first layer (6) and the second layer (7); a device region (9, 9A) provided in the second layer (7); a trench structure (10, 11, 12) penetrating through the second layer (7) and the third layer (8) to reach the first layer (6) and defining the device region (9, 9A) in the second layer (7); and a sidewall buffer layer (62) of the second conductivity type, which is led out from a branch portion (63) of the third layer (8) and the trench structure (10, 11, 12) to a bottom wall side of the trench structure (10, 11, 12).

[0251] [C22] A semiconductor device (61 etc.) comprising: a first layer (6) of a first conductivity type; a second layer (7) of a second conductivity type laminated on the first layer (6); a device region (9, 9A) provided in the second layer (7); a trench structure (10, 11, 12) penetrating through the second layer (7) to reach the first layer (6) and defining the device region (9, 9A) in the second layer (7); and a sidewall buffer layer (62) of the second conductivity type led out from a branch portion (63) of the second layer (7) and the trench structure (10, 11, 12) to a bottom wall side of the trench structure (10, 11, 12).

[0252] [D1] A semiconductor device (71 etc.) comprising: a first layer (6) of a first conductivity type; a second layer (7) of a second conductivity type laminated on the first layer (6); a device region (9, 9A) provided in the second layer (7); a trench structure (10, 11, 12) penetrating through the second layer (7) to reach the first layer (6) and defining the device region (9, 9A) in the second layer (7); and an embedded layer (8) of the second conductivity type formed in the device region (9, 9A) so as to extend across a boundary portion between the first layer (6) and the second layer (7) at a distance from the trench structure (10, 11, 12).

[0253] [D2] The semiconductor device (71, etc.) according to D1, wherein the embedded layer (8) includes a low concentration embedded layer (8a) of the second conductivity type formed on the first layer (6) side, and a high concentration embedded layer (8b) of the second conductivity type formed on the second layer (7) side and having a higher impurity concentration than the low concentration embedded layer (8a).

[0254] [D3] The semiconductor device (71 etc.) according to D2, wherein the low concentration embedded layer (8a) is formed in a region on the first layer (6) side with respect to the boundary portion between the first layer (6) and the second layer (7), and the high concentration embedded layer (8b) extends over the boundary portion.

[0255] [D4] The semiconductor device (71, etc.) according to D2 or D3, wherein the low concentration embedded layer (8a) is formed at a distance from the trench structure (10, 11, 12) and the high concentration embedded layer (8b) is formed at a distance from the trench structure (10, 11, 12).

[0256] [D5] The semiconductor device (71, etc.) according to any one of D1 to D4, wherein the first layer (6) includes a high concentration layer (6a) of the first conductivity type and a low concentration layer (6b) of the first conductivity type laminated on the high concentration layer (6a) and having a lower impurity concentration than the high concentration layer (6a), the second layer (7) is laminated on the low concentration layer (6b), and the embedded layer (8) is embedded so as to extend over a boundary portion of the low concentration layer (6b) and the second layer (7).

[0257] [D6] The semiconductor device (71 etc.) according to D5, wherein the high concentration layer (6a) is formed of a semiconductor substrate and the low concentration layer (6b) is formed of an epitaxial layer.

[0258] [D7] The semiconductor device (71 etc.) according to any one of D1 to D6, wherein the trench structure (10, 11, 12) is electrically connected to the first layer (6) and is electrically insulated from the second layer (7).

[0259] [D8] The semiconductor device (71 etc.) according to any one of D1 to D6, wherein the trench structure (10, 11, 12) is electrically insulated from the first layer (6) and the second layer (7).

[0260] [D9] The semiconductor device (71, etc.) according to any one of D1 to D6, comprising: a plurality of trench structures (10, 11, 12) each formed to penetrate through the second layer (7) to reach the first layer (6) and aligned at intervals in a direction away from the device region (9, 9A) to define the device region (9, 9A) in the second layer (7); wherein the embedded layer (8) is formed at a distance from the trench structure (10, 11, 12) closest to the device region (9, 9A).

[0261] [D10] The semiconductor device (71, etc.) according to D7, wherein the trench structure (10, 11, 12) includes a trench (13) penetrating through the second layer (7) to reach the first layer (6), an insulating film (14) covering an inner wall of the trench (13) to expose the first layer (6), and an electrode (15) embedded in the trench (13) with the insulating film (14) therebetween to be electrically connected to the first layer (6) and electrically insulated from the second layer (7).

[0262] [D11] The semiconductor device (71 etc.) according to D8, wherein the trench structure (10, 11, 12) includes a trench (16) penetrating through the second layer (7) to reach the first layer (6), an insulating film (17) covering an inner wall of the trench (16), and an electrode (18) embedded in the trench (16), the insulating film (17) being interposed therebetween to be electrically insulated from the first layer (6) and the second layer (7).

[0263] [D12] The semiconductor device (71, etc.) according to D9, wherein each of the trench structures (10, 11, 12) includes a trench (14, 17) penetrating through the second layer (7) to reach the first layer (6), an insulating film (14, 17) covering an inner wall of the trench (14, 17), and an electrode (15, 18) embedded in the trench (14, 17) with the insulating film therebetween.

[0264] [D13] The semiconductor device (71, etc.) according to any one of D10 to D12, wherein the electrode (15, 18) includes a conductive polysilicon of the first conductivity type.

[0265] [D14] The semiconductor device (71 etc.) according to any one of D1 to D13, wherein the trench structure (10, 11, 12) is formed in a shape converging to the first layer (6).

[0266] [D15] The semiconductor device (71, etc.) according to any one of D1 to D14, wherein the trench structure (10, 11, 12) surrounds the device region (9, 9A) in plan view.

[0267] [D16] The semiconductor device (71, etc.) according to any one of D1 to D15, further comprising: a sinker region (21) of the second conductivity type formed within the second layer (7) so as to cover a sidewall of the trench structure (10, 11, 12) in the device region (9, 9A).

[0268] [D17] The semiconductor device (71, etc.) according to any one of D1 to D16, further comprising: an impurity region (22) of the first conductivity type formed along a bottom wall of the trench structure (10, 11, 12) in the first layer (6) and having a higher impurity concentration than the first layer (6).

[0269] [D18] The semiconductor device (71, etc.) according to any one of D1 to D17, further comprising: a transistor (30) formed in the device region (9, 9A).

[0270] [D19] A semiconductor device (71 etc.) comprising: a first layer (6) of a first conductivity type; a second layer (7) of a second conductivity type laminated on the first layer (6); a device region (9, 9A) provided in the second layer (7); a first trench structure (11) penetrating into the second layer (7) so as to be electrically connected to the first layer (6) and electrically insulated from the second layer (7), and defining the device region (9, 9A) in the second layer (7); a second trench structure (12) penetrating into the second layer (7) so as to be electrically insulated from the first layer (6) and the second layer (7), and defining the device region (9, 9A) in a region of the second layer (7) that is further toward the device region (9, 9A) side than the first trench structure (11);and an embedded layer (8) of the second conductivity type formed in the device region (9, 9A) so as to extend over a boundary portion between the first layer (6) and the second layer (7) at a distance from the second trench structure (12);

[0271] [D20] The semiconductor device (71 etc.) according to D19, wherein the first trench structure (11) includes a first trench (13) penetrating through the second layer (7) to reach the first layer (6), a first insulating film (14) covering an inner wall of the first trench (13) so as to expose the first layer (6), and a first electrode (15) embedded in the first trench (13) with the first insulating film (14) therebetween so as to be electrically connected to the first layer (6) and electrically insulated from the second layer (7), and the second trench structure (12) includes a second trench (16) penetrating through the second layer (7) to reach the first layer (6), a second insulating film (17) covering an inner wall of the second trench (16), and a second electrode (18) embedded in the second trench (16) with the second insulating film (17) embedded therebetween,to be electrically insulated from the first layer (6) and the second layer (7).

[0272] Although the features of the semiconductor devices according to each item have been described here, the features described in [A1] to [A20], the features described in [B1] to [B20], the features described in [C1] to [C22], and the features described in [D1] to [D20] may be arbitrarily combined with each other. While embodiments of the present invention have been described in detail above, these are merely specific examples used to clarify the technical content of the present invention. The present invention should not be construed as being limited to these specific examples, and the scope of the present invention is limited only by the appended claims. List of reference symbols 1 semiconductor device 6 first layer 6a layer with high concentration 6b Low concentration layer 7 second layer 8 third layer (embedded layer) 8a embedded layer with low concentration 8b embedded layer with high concentration 9 Device region 9A transistor region 10 Trench separation structure (trench structure) 11 first trench structure 12 second trench structure 13 first ditch 14 first insulating film 15 first electrode 16 second ditch 17 second insulating film 18 second electrode 19 bottom insulator 20 Intermediate graben region 21 Sinker region 22 Contamination region 30 MISFET (transistor) 51 semiconductor device 52 first contact electrode 53 Semiconductor device 54 second contact electrode 55 semiconductor device 61 semiconductor device 62 Sidewall buffer layer 63 branch section 65 semiconductor device 66 semiconductor device 71 semiconductor device 72 semiconductor device 81 semiconductor device J pn junction section JE pn junction section of the extension W1 first trench width W2 second trench width

Claims

[1] A semiconductor device comprising: a chip (2) having a first main surface (3) on one side and a second main surface (4) on another side, the chip (2) having a first layer (6) formed in a region in an interior of the chip (2) on the side of the second main surface (4), a second layer (7) formed in a region in the interior of the chip (2) on the side of the first main surface (3), and a third layer (8) formed between the first layer (6) and the second layer (7) in the interior of the chip (2); a pn junction portion (J) formed in the interior of the chip (2) so as to extend along the first main surface (3); a device region (9) provided in the first main surface (3); a first trench structure (11) formed in the first main surface (3) so as to penetrate through the pn junction portion (J) and define the device region (9) in the first main surface (3); a second trench structure (12) formed in the first main surface (3) so as to penetrate through the pn junction portion (J) and define the device region (9) in a region further toward the device region side than the first trench structure (11); and an impurity region (22) having an impurity concentration higher than an impurity concentration of the first layer (6), wherein the impurity region (22) in the first layer (6) is formed to cover a bottom wall of the first trench structure (11) and a bottom wall of the second trench structure (12). [2] A semiconductor device according to claim 1, wherein the first trench structure (11) is constructed from a first trench electrode structure which is electrically connected to the chip (2), and the second trench structure (12) is constructed from a second trench electrode structure which is electrically insulated from the chip (2). [3] A semiconductor device according to claim 1 or 2, wherein the first trench structure (11) has a lower end portion electrically connected to the chip (2). [4] A semiconductor device according to any one of claims 1 to 3, wherein the second trench structure (12) is electrically separated from the first trench structure (11). [5] A semiconductor device according to any one of claims 1 to 4, wherein the second trench structure (12) is formed in an electrically floating state. [6] Semiconductor device according to one of claims 1 to 5, wherein a different potential is to occur in the second trench structure (12) than in the first trench structure (11). [7] Semiconductor device according to one of claims 1 to 6, wherein the first trench structure (11) has a first width (W1), and the second trench structure (12) has a second width (W2) which is not greater than the first width (W1). [8] A semiconductor device according to claim 7, wherein the second trench structure (12) is formed at a distance of not more than the first width (W1) from the first trench structure (11). [9] Semiconductor device according to one of claims 1 to 8, wherein the first trench structure (11) includes a first trench (13) penetrating through the pn junction portion (J), a first insulating film (14) covering an inner wall of the first trench (13) such that the chip (2) is exposed from a bottom wall of the first trench (13), and a first electrode (15) embedded in the first trench (13) with the first insulating film (14) therebetween and electrically connected to the chip (2) at the bottom wall of the first trench (13), and the second trench structure (12) includes a second trench (16) penetrating through the pn junction portion (J), a second insulating film (17) covering an inner wall of the second trench (16), and a second electrode (18) embedded in the second trench (16) with the second insulating film (17) therebetween and electrically insulated from the chip (2). [10] A semiconductor device according to claim 9, wherein the second trench structure (12) includes a bottom-side insulator (19) embedded in a bottom wall side of the second trench (16) so as to be continuously continuous with the second insulating film (17) and having a thickness exceeding a thickness of the second insulating film (17), and the second electrode (18) is embedded in the second trench (16) with the second insulating film (17) and the bottom insulator (19) therebetween. [11] A semiconductor device according to any one of claims 1 to 10, wherein the first trench structure (11) penetrates through the second layer (7) and the third layer (8) to reach the first layer (6) and delimits the device region (9) in the second layer (7), and the second trench structure (12) penetrates through the second layer (7) and the third layer (8) to reach the first layer (6) and defines the device region (9) in a region of the second layer (7) further toward the side of the device region than the first trench structure (11). [12] A semiconductor device according to claim 11, wherein the first trench structure (11) is electrically connected to the first layer (6) and electrically insulated from the second layer (7) and the third layer (8), and the second trench structure (12) is electrically insulated from the first layer (6), the second layer (7) and the third layer (8). [13] A semiconductor device according to any one of claims 1 to 10, wherein the first trench structure (11) penetrates through the second layer (7) to reach the first layer (6) and delimits the device region (9) in the second layer (7), and the second trench structure (12) penetrates into the second layer (7) to reach the first layer (6) and defines the device region (9) in a region of the second layer (7) further toward the side of the device region than the first trench structure (11). [14] A semiconductor device according to claim 13, wherein the first trench structure (11) is electrically connected to the first layer (6) and electrically insulated from the second layer (7), and the second trench structure (12) is electrically insulated from the first layer (6) and the second layer (7). [15] A semiconductor device according to any one of claims 1 to 14, further comprising: an intermediate trench region (20) defined in a region between the first trench structure (11) and the second trench structure (12) and formed in an electrically floating state. [16] A semiconductor device according to any one of claims 1 to 15, further comprising: a transistor (30) formed in the device region (9). [17] A semiconductor device comprising: a first layer (6) of a first conductivity type; a second layer (7) of the first conductivity type or a second conductivity type laminated on the first layer (6); a third layer (8) of the second conductivity type arranged between the first layer (6) and the second layer (7); a device region (9) provided in the second layer (7); a first trench structure (11) penetrating through the second layer (7) and the third layer (8) to reach the first layer (6) and defining the device region (9) in the second layer (7); a second trench structure (12) penetrating through the second layer (7) and the third layer (8) to reach the first layer (6) and defining the device region (9) in a region of the second layer (7) further toward the device region side than the first trench structure (11); and an impurity region (22) having an impurity concentration higher than an impurity concentration of the first layer (6), wherein the impurity region (22) in the first layer (6) is formed to cover a bottom wall of the first trench structure (11) and a bottom wall of the second trench structure (12). [18] A semiconductor device according to claim 17, wherein the first trench structure (11) is constructed from a first trench electrode structure which is electrically connected to the first layer (6) and electrically insulated from the second layer (7) and the third layer (8), and the second trench structure (12) is constructed from a second trench electrode structure which is electrically insulated from the first layer (6), the second layer (7) and the third layer (8). [19] A semiconductor device comprising: a first layer (6) of a first conductivity type; a second layer (7) of a second conductivity type laminated to the first layer (6); a device region (9) provided in the second layer (7); a first trench structure (11) penetrating through the second layer (7) to reach the first layer (6) and defining the device region (9) in the second layer (7); a second trench structure (12) penetrating through the second layer (7) to reach the first layer (6) and defining the device region (9) in a region of the second layer (7) further toward the side of the device region than the first trench structure (11); and an impurity region (22) having an impurity concentration higher than an impurity concentration of the first layer (6), wherein the impurity region (22) is formed in the first layer (6) to cover a bottom wall of the first trench structure (11) and a bottom wall of the second trench structure (12). [20] A semiconductor device according to claim 19, wherein the first trench structure (11) is constructed from a first trench electrode structure which is electrically connected to the first layer (6) and electrically insulated from the second layer (7), and the second trench structure (12) is constructed from a second trench electrode structure which is electrically insulated from the first layer (6) and the second layer (7).

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