SEMICONDUCTOR DEVICE

Abstract

Semiconductor device (1), comprising: a semiconductor substrate (4, 15); a first electrically conductive element (25) formed above the semiconductor substrate (4, 15) and having a first linear section (36) extending along a major surface (11) of the semiconductor substrate (4, 15); and an organic insulating layer (55) formed over the semiconductor substrate (4, 15) and covering the first electrically conductive element (25), wherein the first linear section (36) includes a first side edge section (46) formed by a curve (47) which is alternately curved to one side and to the opposite side in a direction (Y1) which, in a top view, intersects a longitudinal direction (X1) of the first linear section (36). wherein the first electrically conductive element (25) includes a first base layer (26) and a first cover layer (27) which is stacked on the first base layer (26) such that it projects laterally from an end face (29) of the first base layer (26) in a cross-sectional view, and wherein the first side edge section (46) is selectively formed on the first cover layer (27).

Description

TECHNICAL AREA

[0001] The present disclosure relates to a semiconductor device. State of the art

[0002] For example, patent literature 1 discloses a semiconductor package that includes an electrically conductive element, a semiconductor device, a compound layer, and a sealing resin. The semiconductor device is a flip-chip LSI. The semiconductor device comprises an element body, a plurality of electrodes, and a front-side protective film. The front-side protective film is made of polyimide and covers a base section of the plurality of electrodes. List of oppositions patent literature

[0003] Patent literature 1: Japanese patent application publication no. JP 2020-167330A

[0004] Furthermore, US patent application 2019 / 0326329A1 discloses an electronic device, in particular a flexible display device. This device comprises a substrate on which conductive elements and organic insulating layers are arranged. To improve mechanical reliability under bending, one conductive element has a corrugated or wavy edge.

[0005] Publication WO 2015 / 030 891 A2 discloses a semiconductor structure with an electro-optic modulator. Brief description of the invention: Technical problem

[0006] There is a case in which a high mechanical residual stress occurs in a linear section of an electrically conductive element when a change in the ambient temperature of a structure occurs in which the electrically conductive element, such as a wiring conductor or an electrode, is covered with an organic insulating layer. This mechanical stress is thought to exert an external force on the adjacent organic insulating layer as the electrically conductive element expands or contracts due to the temperature change.

[0007] A preferred embodiment of the present disclosure provides a semiconductor device capable of reducing the mechanical stress of a side section of a linear section of an electrically conductive element. Solution to the problem

[0008] A semiconductor device according to a preferred embodiment of the present disclosure according to claim 1 includes a semiconductor substrate, a first electrically conductive element formed on the semiconductor substrate and having a first linear section extending along a major surface of the semiconductor substrate, and an organic insulating layer formed on the semiconductor substrate and covering the first electrically conductive element, wherein the first linear section includes a first side edge section formed by a curve that is alternately curved to one side and to an opposite side in a direction that intersects a longitudinal direction of the first linear section in a top view. Advantageous effects of the invention

[0009] In the semiconductor device according to a preferred embodiment of the present disclosure, it is possible to reduce a mechanical stress (“stress”) of the side section of the linear section of the electrically conductive element. Brief description of the drawings [ Fig. 1] Fig. Figure 1 is a schematic perspective view of a semiconductor device according to a preferred embodiment of the present disclosure. [ Fig. 2] Fig. Figure 2 is an enlarged top view of a semiconductor chip. Fig. 1. [ Fig. 3] Fig. Figure 3 is an enlarged view (first form) of a part of Fig. 2, which is surrounded by an alternating long and double short dashed line III. [ Fig. 4] Fig. 4 is a cross-sectional view along the in Fig. 3 shown line IV-IV. [ Fig. 5] Fig. Figure 5 is an enlarged view (second form) of a part defined by an alternating long and double short dashed line III of Fig. 2 is surrounded. [ Fig. 6] Fig. 6 is a cross-sectional view along the in Fig. 3 shown line VI-VI. [ Fig. 7] Fig. 7 is a flowchart that shows part of the manufacturing process of the semiconductor chip of Fig. 1 shows the order of the process steps. [ Fig. 8] Fig. Figure 8 is a view to describe a voltage relaxation effect caused by the semiconductor device. Description of embodiments<Bevorzugte Ausführungsform der vorliegenden Offenbarung>

[0010] First, a preferred embodiment of the present disclosure is described in a specified form.

[0011] A semiconductor device (1) according to a preferred embodiment of the present disclosure includes a semiconductor substrate (4, 15), a first electrically conductive element (25) formed on the semiconductor substrate (4, 15) and having a first linear section (36) extending along a major surface (11) of the semiconductor substrate (4, 15), and an organic insulating layer (55) formed on the semiconductor substrate (4, 15) and covering the first electrically conductive element (25), wherein the first linear section (36) includes a first side edge section (46) formed by a curve (47) that is alternately curved to one side and to an opposite side in a direction that intersects a longitudinal direction of the first linear section (36) in a top view.

[0012] There is a case where a high stress is generated in the first side segment of the first linear section due to a difference in the coefficient of thermal expansion between the first electrically conductive element and the organic insulating layer when the ambient temperature changes, for example, if the first side segment of the first linear section is straight. If this stress exerts an external force on the organic insulating layer, and if expansion and contraction are caused by a temperature change, deformation occurs in the organic insulating layer, and the mechanical properties of the organic insulating layer could decrease.When the semiconductor device is used according to the preferred embodiment, it is therefore possible to distribute the stress generated in the first side segment of the first linear section, since the first side edge segment is formed by a curve. This makes it possible to reduce the stress on the first side segment of the first linear section of the first electrically conductive element as a whole. Consequently, it is possible to limit deformation that occurs in the organic insulating layer when expansion and contraction are caused by a temperature change.

[0013] In the semiconductor device (1) according to a preferred embodiment of the present disclosure, the first linear section (36) can include a base section (40) to which a connecting element can be attached, and a first side section (41) which includes a convex section (44, 48) which projects from the base section (40) in the direction which intersects a longitudinal direction of the first linear section (36), and a concave section (45, 49) which is hollowed out with respect to the convex section (44, 48), and the first side edge section (46) can be formed by a curve (47) which, in a top view, continuously connects the convex section (44, 48) and the concave section (45, 49) along the longitudinal direction of the first linear section (36).

[0014] In this configuration, the stress generated in the first side section, which includes the convex and concave sections, is distributed. Therefore, it is possible to mitigate a decrease in the mechanical properties of the organic insulating layer, even when stress continues to be applied to the first linear section if a connecting element is attached to its base. Furthermore, a stress distribution structure is formed by selectively shaping the convex and concave sections on the first side section of the first linear section, not by the fact that the entire first electrically conductive element twists to assume the shape of the letter S.Therefore, there is no need to enlarge the installation space for the first electrically conductive element according to the preferred embodiment, and therefore it is possible to prevent the semiconductor device from being enlarged.

[0015] In the semiconductor device (1) according to a preferred embodiment of the present disclosure, the base section (40) can be formed in a ribbon shape with a first width (W2), and the first width (W2) of the base section (40) can have ten times or more than ten times the length of an extent (P1) of the projection of the convex section (44, 48) from the base section (40).

[0016] In this configuration, it is possible to achieve a stress distribution effect in the first electrically conductive element, for example, by forming a convex section with a projection whose extent corresponds to approximately 1 / 10 of the width of an existing first electrically conductive element (e.g., wiring conductor or electrode). Conversely, it is possible to maintain a relatively large initial width of the base section, even if the stress distribution structure is formed by both the convex and concave sections. Consequently, it is possible to allow for many options (e.g., shape, thickness, etc.) for the connecting element that can be joined to the base section.

[0017] In the semiconductor device (1) according to a preferred embodiment of the present disclosure, the first electrically conductive element (25) can include a front end section (39) which includes a part of the first linear section (36), and a second linear section (37) which is connected to the first linear section (36) by a corner section (38), and the first side edge section (46) can be selectively formed on the first linear section (36), which is one of the first linear section (36) and the second linear section (37).

[0018] In this configuration, the first side edge section is formed with a curved shape at the first linear section that includes the front end section, where a stress is easily caused by a change in ambient temperature, and therefore it is possible to effectively distribute the stress in the first electrically conductive element.

[0019] In the semiconductor device (1) according to a preferred embodiment of the present disclosure, the front end section (39) of the first electrically conductive element (25) may have a first side surface (52) formed in a top view by a first circular arc (51) with a first radius of curvature (R1), and the first side edge section (46) of the first electrically conductive element (25) may have a second side surface (54) formed in a top view by a second circular arc (53) with a second radius of curvature (R2) that is smaller than the first radius of curvature (R1).

[0020] In the semiconductor device (1) according to an embodiment of the present disclosure, the first electrically conductive element (25) includes a first base layer (26) and a first cover layer (27) which is stacked on the first base layer (26) to project laterally from an end face (29) of the first base layer (26) in a cross-sectional view, and the first side edge section (46) is selectively formed on the first cover layer (27).

[0021] In this configuration, the first side edge segment with a curved shape is selectively formed on the first top layer and does not need to be formed on the first base layer. Therefore, it is possible to reduce the number of steps in the process for forming the first side edge segment.

[0022] In the semiconductor device (1) according to a preferred embodiment of the present disclosure, the organic insulating layer (55) can have a pad opening (56) that exposes the base section (40) of the first linear section (36) as a pad.

[0023] In this configuration, it is possible to connect a connecting element such as a bond wire to the base section of the first linear section through the pad opening.

[0024] The semiconductor device (1) according to a preferred embodiment of the present disclosure may further include a second electrically conductive element (59) which is connected to the base section (40) of the first linear section (36) in the organic insulating layer (55).

[0025] In this configuration, the aforementioned stress distribution structure prevents a reduction in the mechanical properties of the organic insulating layer surrounding the second electrically conductive element. Therefore, it is possible to improve the connection reliability between the first electrically conductive element (first linear section) and the second electrically conductive element.

[0026] In the semiconductor device (1) according to a preferred embodiment of the present disclosure, the second electrically conductive element (59) may have a third linear section (72) extending along the main surface (11) of the semiconductor substrate (4, 15), and the third linear section (72) may include a second side edge section (79) formed by a curve (80) that is alternately curved to one side and to an opposite side in a direction which, in a top view, intersects a longitudinal direction of the third linear section (72).

[0027] In this configuration, it is possible to distribute the stress generated in the second side segment of the third linear section, since the second side edge segment is formed by a curve. This makes it possible to reduce the stress on the second side segment of the third linear section of the second electrically conductive element as a whole. Consequently, it is possible to contain deformation that occurs in the organic insulating layer when expansion and contraction are caused by temperature changes.

[0028] In the semiconductor device (1) according to a preferred embodiment of the present disclosure, the second electrically conductive element (59) can include a second base layer (60) and a second cover layer (61) which is stacked on the second base layer (60) to project laterally from an end face (63) of the second base layer (60) in a cross-sectional view, and the second side edge section (79) can be selectively formed on the second cover layer (61).

[0029] In this configuration, the second side edge section with a curved shape is selectively formed on the second top layer and does not need to be formed on the second base layer. Therefore, it is possible to reduce the number of steps in the process for forming the second side edge section.

[0030] The semiconductor device (1) according to a preferred embodiment of the present disclosure can include an insulating layer layer structure (17) formed between the first electrically conductive element (25) and the semiconductor substrate (4, 15) and comprising at least a first inorganic insulating layer (18, 57) and a second inorganic insulating layer (19, 58) stacked on the first inorganic insulating layer (18, 57).

[0031] The semiconductor device (1) according to a preferred embodiment of the present disclosure can include an integrated circuit element (16) formed on the semiconductor substrate (4, 15) and electrically connected to the first electrically conductive element (25).

[0032] With this configuration, it is possible to reduce the voltage of the first side section of the first linear section of the first electrically conductive element as described above, and therefore it is possible to provide a semiconductor device that includes an integrated circuit in which the insulation reliability of an organic insulating layer is high.

[0033] In the preceding description, each numeric character or the like in parentheses represents a reference to a corresponding component named in the detailed description below. However, each component named above should not be considered by its reference to be an equivalent of each component named below. <Ausführliche Beschreibung einer bevorzugten Ausführungsform der vorliegenden Offenbarung>

[0034] Next, a preferred embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. In the following detailed description, there exists a plurality of components, each of which has a name to which an ordinal number has been assigned; however, this ordinal number and an ordinal number of a component specified in the claims do not necessarily coincide.

[0035] Fig. Figure 1 is a schematic perspective view of a semiconductor device 1 according to a preferred embodiment of the present disclosure.

[0036] In the preferred embodiment, the semiconductor device 1 is a so-called SOP (Small Outline Package). The semiconductor device 1 includes a sealing resin 2, a chip pad 3, a semiconductor chip 4, a conductive interconnect 5, a plurality of connecting conductors 6, and a plurality of connecting wires 7.

[0037] The sealing resin 2 can, for example, enclose an epoxy resin. The sealing resin 2 can be referred to as a resin housing. The sealing resin 2 is rectangular cuboid in shape. The sealing resin 2 encloses a first main surface 8 on one side, a second main surface 9 on the other side, and four side surfaces 10A, 10B, 10C, and 10D, which connect the first main surface 8 and the second main surface 12. In detail, the four side surfaces 10A to 10D enclose a first side surface 10A, a second side surface 10B, a third side surface 10C, and a fourth side surface 10D. The first side surface 10A and the second side surface 10B face each other. The third side surface 10C and the fourth side surface 10D also face each other.

[0038] The chip pad 3 is arranged in the sealing resin 2. The chip pad 3 can be exposed from the second main surface 9. The chip pad 3 encloses a metal plate that is rectangular in shape. The chip pad 3 can enclose at least one of Fe, Au, Ag, Cu and Al. The chip pad 3 can have an outer surface on which at least one of a Ni-plated layer, an Au-plated layer, an Ag-plated layer and a Cu-plated layer is formed.

[0039] A multitude of connection conductors 6 includes a first connection conductor 6A, a second connection conductor 6B, a third connection conductor 6C, a fourth connection conductor 6D, a fifth connection conductor 6E, a sixth connection conductor 6F, a seventh connection conductor 6G, and an eighth connection conductor 6H. The number of connection conductors 6 is adapted according to the function of the semiconductor chip 4 and is not dependent on the one specified by the Fig. 1 limited.

[0040] The four connecting conductors 6A to 6D are arranged on the side of the first surface 10A of the sealing resin 2. The four connecting conductors 6A to 6D are arranged at a distance from the chip pad 3. The four connecting conductors 6A to 6D are spaced apart from each other in the direction in which the first surface 10A extends. The four connecting conductors 6A to 6D cross the first surface 10A from the inside of the sealing resin 2 and extend outwards from the sealing resin 2.

[0041] The four connecting conductors 6E to 6H are arranged on the side of the second surface 10B of the sealing resin 2. The four connecting conductors 6E to 6H are arranged at a distance from the chip pad 3. The four connecting conductors 6E to 6H are spaced apart from each other in the direction in which the second surface 10B extends. The four connecting conductors 6E to 6H cross the second surface 10B from the inside of the sealing resin 2 and extend outwards from the sealing resin 2.

[0042] The plurality of connecting conductors 6 can include at least one of Fe, Au, Ag, Cu and Al. The plurality of connecting conductors 6 can have an outer surface on which at least one of a Ni-plated layer, an Au-plated layer, an Ag-plated layer and a Cu-plated layer is formed.

[0043] Semiconductor chip 4 includes, for example, an LSI (Large Scale Integration) chip. Semiconductor chip 4 is located on chip pad 3. Semiconductor chip 4 has a first main surface 11 on one side and a second main surface 12 on the other side. On the first main surface 11 of semiconductor chip 4, a plurality of element regions 13 are formed, in which elements are formed that constitute an LSI circuit. The plurality of element regions 13 can include, for example, a diode region 13A, a transistor region 13B, a resistor region 13C, and the like. A plurality of pads 14 are formed on the first main surface 11 of semiconductor chip 4. The plurality of pads 14 are located on the side of the four terminals 6A-6D and on the side of the four terminals 6E-6H on the first main surface 11 of semiconductor chip 4.The multitude of pads 14 is electrically connected to a functional element 16 (circuit element that forms the LSI), which will be described later.

[0044] The conductive interconnect material 5 is arranged between the semiconductor chip 4 and the chip pad 3 and connects the semiconductor chip 4 to the chip pad 3. The conductive interconnect material 5 includes a solder or an electrically conductive paste. The solder can be lead-free. The solder can include at least one of SnAgCu, SnZnBi, SnCu, SnCuNi, and SnSbNi. The metal paste can include at least one of Au, Ag, and Cu. Preferably, the conductive interconnect material 5 is made of a silver paste. Particularly preferably, the silver paste includes a sintered silver paste. The sintered silver paste can include a paste in which Ag particles, each having a nanoscale or microscale, are dispersed in an organic solvent.

[0045] The number of connecting wires 7 is adapted according to the function of the semiconductor chip 4 and is not limited to the number in Fig. The plurality of connecting wires 7 shown is limited to the plurality of connecting wires 7. The plurality of connecting wires 7 electrically connects the plurality of connecting conductors 6 and the plurality of pads 14. In the preferred embodiment, the plurality of connecting wires 7 includes an aluminum wire, which is an example of a bond wire. The plurality of connecting wires 7 can be gold or copper wires instead of the aluminum wires.

[0046] The package shape of semiconductor device 1 may differ from SOP. For example, semiconductor device 1 may have a package shape such as TO (Transistor Outline), QFN (Quad for Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package) or SOJ (Small Outline J-leaded Package), or may be in various package shapes similar to these shapes.

[0047] Fig. Figure 2 is an enlarged top view of semiconductor chip 4. Fig. 1 and shows the area around pads 14. Fig. Figure 3 is an enlarged view (first form) of a part defined by an alternating long and double short dashed line III of Fig. 2 is surrounded. Fig. 4 is a cross-sectional view along the in Fig. 3 shown line IV-IV.

[0048] Next, the first form of the semiconductor chip 4 will be discussed in relation to Fig. 2 to Fig. 4 described.

[0049] First, a cross-sectional structure of the semiconductor chip 4 is described. With reference to Fig. The semiconductor chip 4 encloses a semiconductor substrate 15. The semiconductor substrate 15 can be an epitaxial substrate, for example, a base substrate containing silicon and an epitaxial layer that grows on the base substrate. Additionally, the semiconductor chip 4 is formed in a layered form and can therefore be referred to as a semiconductor layer.

[0050] The first main surface 11 and the second main surface 12 of the semiconductor chip 4 can be the first main surface 11 and the second main surface 12 of the semiconductor substrate 15. A plurality of functional elements 16 are formed on the first main surface 11 of the semiconductor substrate 15. The plurality of functional elements 16 can include, for example, circuit elements such as a diode, a transistor, and a resistor, which make up the LSI.

[0051] An insulating layer structure 17 is formed on the first main surface 11 of the semiconductor substrate 15. The insulating layer structure 17 comprises a layered structure of a plurality of inorganic insulating layers. In the preferred embodiment, the insulating layer structure 17 includes a first insulating layer 18, a second insulating layer 19, a third insulating layer 20, a fourth insulating layer 21, and a fifth insulating layer 22, which are layered in this order starting from the first main surface 11 of the semiconductor substrate 15. Each of the insulating layers 18 to 22 of the insulating layer structure 17 comprises inorganic insulating materials such as silicon dioxide (SiO2) and silicon nitride (SiN).

[0052] Each of the insulating layers 18 to 22 is provided with a plurality of wiring leads 23 and a plurality of vias 24, through which the wiring leads 23, positioned in alternating top / bottom positions, are interconnected. The wiring lead 23 is electrically connected to the functional element 16 via the via 24. Thus, the insulating layer structure 17 is formed as a multilayer wiring structure, with the wiring lead 23, which is electrically connected to the functional element 16, being provided on the plurality of insulating layers 18 to 22. The plurality of wiring leads 23 can include known wiring materials such as Cu and Al. The plurality of vias 24 can include known via materials such as W.

[0053] A first electrically conductive element 25 is formed on the insulating layer structure 17. In the preferred embodiment, the first electrically conductive element 25 is a wiring conductor of an uppermost layer, which forms the pad 14 of the semiconductor chip 4, and can be referred to as the first wiring layer. Additionally, the first electrically conductive element 25 is formed by a plurality of conductive layers and can be referred to as the first conductive layer.

[0054] The first electrically conductive element 25 includes a first base layer 26 and a first cover layer 27, which are shown in a cross-sectional view of Fig. 4 is stacked on the first base layer 26. The first base layer 26 encloses, for example, Cu and, in the preferred embodiment, can enclose a Cu-clad layer. The first base layer 26 is connected, for example, to the via 24. This electrically connects the first electrically conductive element 25 to the functional element 16 via the via 24 and the wiring conductor 23.

[0055] The first cover layer 27 covers the first base layer 26. The first cover layer 27 integrally includes a first cover section 28, which contacts a top surface of the first base layer 26 and covers the first base layer 26, and a first projection section 30, which projects laterally from an end face 29 of the first base layer 26. This creates a first height difference 32, corresponding to the extent of the projection of the first projection section 30, between the end face 29 of the first base layer 26 and an end face 31 of the first cover layer 27. The first projection section 30 can slope downwards with respect to the first cover section 28 towards a lower side (i.e., the side near the first main surface 11 of the semiconductor substrate 15). Therefore, on a top surface 33 of the first cover layer 27, portions on both sides of the top surface 33 can be inclined downwards with respect to a portion of the top surface 33 on the first base layer 26.The first top layer 27 can be thinner than the first base layer 26. For example, the first base layer 26 can have a thickness of not less than 2 µm and not more than 3 µm, and the first top layer 27 can have a thickness of not less than 1 µm and not more than 2 µm.

[0056] In the preferred embodiment, the first cover layer 27 includes a plurality of cover layers. The first cover layer 27 can, for example, include a first layer 34 adjacent to the first base layer 26 and a second layer 35 stacked on top of the first layer 34. The first layer 34 includes, for example, Ni and, in the preferred embodiment, can include a Ni-plated layer. The second layer 35 includes, for example, Pd and, in the preferred embodiment, can include a Pd-plated layer. The first cover layer 27 can further include an Au-plated layer at its outermost surface (not shown). The first layer 34 and the second layer 35 are stacked at both the first cover section 28 and the first projecting section 30. This allows a boundary between the first layer 34 and the second layer 35 to be exposed at the end face 31 of the first cover layer 27.

[0057] Next, a planar structure of the first electrically conductive element 25 is described. With reference to Fig. 2 The first electrically conductive element 25 extends extensively through a region on the first main surface 11 of the semiconductor substrate 15. In the preferred embodiment, the first electrically conductive element 25 includes a first linear section 36 and a second linear section 37. The first linear section 36 and the second linear section 37 are each formed in a ribbon shape in a top view and are integrally connected to each other by a corner section 38. The first linear section 36 and the second linear section 37 are each comparatively extensive in terms of their length in Fig. 2 are shown and are therefore each defined as having a band shape. On the other hand, the first linear section 36 and the second linear section 37 can each be defined as having a linear shape or the like if the width of the first linear section 36 and the second linear section 37 is very small in relation to its length.

[0058] The first linear section 36 includes a front end section 39, which is an end section of the first electrically conductive element 25. The other end (not shown) on the opposite side of the front end section 39 of the first electrically conductive element 25 can be connected to the aforementioned via 24. The first linear section 36 and the second linear section 37 can be connected in the corner section 38 in the same way as the first two electrically conductive elements 25 on the left side of Fig. 2 intersect at obtuse angles to each other. Furthermore, the first linear section 36 and the second linear section 37 can intersect each other at right angles in the corner section 38 in the same way as the first two electrically conductive elements 25 on the right side of Fig. 2. In other words, the angle of corner section 38 can be an obtuse angle, or it can be a right angle, or of course it can be an acute angle.

[0059] A more detailed form of the first linear section 36 is given with reference to Fig. 3 described. Fig. 3 is the longitudinal direction (extension direction) of the first linear section 36 represented as a first direction X1, and the direction perpendicular to the first direction X1 is represented as a second direction Y1.

[0060] The first linear section 36 includes a ribbon-shaped first base section 40 extending in the first direction X1 and a first side section 41 formed integrally on both sides of the first base section 40 in the second direction Y1. The first base section 40 is a region obtained by conveniently adjusting a ribbon-shaped area extractable from the first linear section 36 while retaining essentially the same external shape as the first linear section 36, such as an internal region of the first boundary section 42, which is in Fig. 3 is shown by a dashed line, or like an inner area of ​​the first boundary section 43, which is shown by an alternating long and short dashed line in Fig. 3 is shown.

[0061] The first base section 40 only needs to have a width that allows the connection of a connecting element, such as the aforementioned connecting wire 7. Furthermore, the first base section 40 can have a first width W2 that is equal to or greater than 80%, preferably 90%, of the width W1 of the first linear section 36. For example, the width W1 of the first linear section 36 may be not less than 12 µm and not more than 25 µm, and the first width W2 of the first base section 40 may be not less than 10 µm and not more than 20 µm. The width W1 of the first linear section 36 can be a distance between an upper section of a first convex section 44 on one side and an upper section of the first convex section 44 on the other side in the second direction Y1.

[0062] In the preferred embodiment, the first side section 41 is an outer region of the first boundary section 42 or an outer region of the first boundary section 43 and has a non-uniform structure designed so as not to affect the outer shape of the first linear section 36. More precisely, the first side section 41 includes a first convex section 44 projecting from the first base section 40 in the second direction Y1, and a first concave section 45 that is hollow with respect to the first convex section 44. In the preferred embodiment, the first linear section 36 has a first side edge section 46 formed by a curve that is alternately curved to one side (left side of the paper plane) and to the opposite side (right side of the paper plane) in the second direction Y1.The first side edge section 46 is an outer shape line that, in a plan view, extends in the first direction X1 of the first linear section 36 and forms a side surface of the first linear section 36. Therefore, the first side section 41 of the first linear section 36 is a region between the first base section 40 and the first side edge section 46, and the first convex section 44 and the first concave section 45, which both form the first side section 41, are formed by the first side edge section 46, which has a curved shape and is continuously connected along the first direction X1.

[0063] The extent P1 of the projection of the first convex section 44 of the first side section 41 need only be the extent of the projection that substantially does not alter the external shape of the first linear section 36. For example, compared to the first width W2 of the first base section 40, the extent P1 of the projection can be equal to or less than 1 / 10 of the first width W2 (i.e., the first width W2 has ten times or more than ten times the extent P1 of the projection). In other words, it is possible to maintain the first width W2 of the first base section 40 relatively largely unchanged, even when a stress dispersion structure is formed by the first convex section 44 and the first concave section 45. Consequently, it is possible to make many choices (e.g., shape, thickness, etc.)., a wiring line or wiring system) for a connecting element that can be connected to the first base section 40.

[0064] Furthermore, the curved first side-edge section 46 can be a sine curve 47 which, in the preferred embodiment, extends along the first direction X1. Thus, the first side section 41 includes a plurality of first curved convex sections 48 and a plurality of first curved concave sections 49 formed alternately along the first direction X1. In this case, the first width W2 of the first base section 40 can have five times or more than five times the length of an amplitude A1 of the sine curve 47 from a first reference line 50 defined by an alternating long and double short dashed line. Fig. 3 is shown.

[0065] The first boundary sections 42 and 43 between the first side section 41 and the first base section 40 can be defined by a line (alternating long and short dashed line of Fig. 3) can be set, for example by connecting the upper sections of the plurality of first concave sections 45 together along the first direction X1, or can be set by a line (dashed line of Fig. 3) be set parallel to the line described above, which is formed by joining the upper sections and which is formed in a position that is directed slightly more inwards than the upper sections of the plurality of first concave sections 45.

[0066] The front end section 39 of the first electrically conductive element 25 has, in a plan view, a first side surface 52 formed by a first circular arc 51 with a first radius of curvature R1. Compared to this first side surface 52, in a plan view, the first side edge section 46 can have a second side surface 54 formed by a second circular arc 53 having a second radius of curvature R2, which is smaller than the first radius of curvature R1. If the first side edge section 46 encloses the sine curve 47, a curved surface of each of the first curved convex section 48 and the first curved concave section 49 can be formed by the second circular arc 53.

[0067] In the preferred embodiment, the first side-edge section 46, which encloses the sine curve 47, is formed as a pair of first side-edge sections along the first direction X1. In other words, both side edges of the first linear section 36 can be the first side-edge section 46 including the sine curve 47. The pair of sine curves 47 can enclose one sine curve 47A and the other sine curve 47B. In contrast, the sine curve 47A and the other sine curve 47B can differ in the formation position of the first curved convex section 48 in the first direction X1. For example, the first curved convex section 48 of the sine curve 47A can differ from the first curved convex section 48 of the other sine curve 47B in the second direction Y1.

[0068] In the preferred embodiment, the first curved convex section 48 of the sine curve 47A faces the first curved concave section 49 of the other sine curve 47B in the second direction Y1. Furthermore, the first curved convex section 48 of the other sine curve 47B faces the first curved concave section 49 of the sine curve 47A. Thus, the first curved convex section 48 (the first curved concave section 49) is formed alternately between the first side section 41 including the sine curve 47A and the first side section 41 including the other sine curve 47B in the first direction X1.

[0069] As described, the first linear section 36 has the first side section 41, which includes both the first curved convex section 48 and the first curved concave section 49. On the other hand, there is a case in which the first curved convex section 48 of the sine curve 47 and a curved section of the first curved concave section 49 appear as pointed, for example, when the magnification is low when viewing the first linear section 36. In this case, the first side section 41 can be defined as zigzag-shaped in a top view. The shape of the upper portion of the first convex section 44, which projects outside the zigzag shape, can correspond to the shape of the curved surface of the first curved convex section 48.

[0070] Furthermore, the aforementioned first convex section 44 and the first concave section 45 can be selectively formed on the first cover layer 27, which is one of the first base layer 26 and the first cover layer 27, both of which are components of the first electrically conductive element 25. Of course, the first convex section 44 and the first concave section 45 can be formed on both the first base layer 26 and the first cover layer 27. In addition, the first convex section 44 and the first concave section 45 can be selectively formed on the first linear section 36, as shown in Fig. 3 shown, may be formed or may be selectively formed on the second linear section 37 or may be formed on both the first linear section 36 and the second linear section 37.

[0071] With reference to Fig. 4 A protective layer 55 is formed on the insulating layer structure 17 to cover the first electrically conductive element 25. The protective layer 55 includes an organic insulating resin. The organic insulating resin can include, for example, epoxy resin, phenolic resin, polyimide, etc. The protective layer 55 can be a resin layer that has a higher coefficient of thermal expansion than the first electrically conductive element 25. For example, the first coefficient of thermal expansion of Cu, which forms a base layer of the first electrically conductive element 25, can be at least 16 × 10 -6 / °C and not more than 18 × 10 -6 / °C, while the second coefficient of thermal expansion of a resin (for example, epoxy resin) forming the protective layer 55 is not less than 45 × 10 -6 / °C and not more than 65 × 10 -6The temperature can be / °C. A pad opening 56, which exposes the first base section 40 of the first linear section 36 as pad 14, is formed in the protective layer 55. The aforementioned connecting wire 7 is connected to the first electrically conductive element 25 through pad 14.

[0072] Fig. Figure 5 is an enlarged view (second form) of a section defined by an alternating long and double short dashed line III of Fig. 2 is surrounded. Fig. 6 is a cross-sectional view along the in Fig. 3 shown line VI-VI.

[0073] Next, the second form of semiconductor chip 4 will be described. One example is given below with reference to Fig. 2 to Fig. The same reference symbol is assigned to the structure described in section 4, and a description of this structure is omitted.

[0074] First, with reference to Fig. 6. The wiring conductor 23 and the via 24 are not formed in a part of the insulating layer structure 17 arranged directly beneath the first electrically conductive element 25 in the thickness direction of the semiconductor substrate 15 in the second form. In other words, the first electrically conductive element 25 cannot face the semiconductor substrate 15 through the electrically conductive element, such as the wiring conductor 23 or the via 24, but only through the insulating layer of the insulating layer structure 17. The insulating layer structure 17 in the second form comprises a layer structure composed of a plurality of inorganic insulating layers, i.e., it includes, for example, a first insulating layer 57 and a second insulating layer 58.Each of the insulating layers of the insulating layer structure 17 includes inorganic insulating materials such as silicon oxide (SiO2) and silicon nitride (SiN).

[0075] The first insulating layer 57 and the second insulating layer 58 are insulating layers made of the same type of insulating material, but they can also be insulating layers formed by different manufacturing processes. For example, the first insulating layer 57 can be a thermal silicon dioxide film, and the second insulating layer 58 can be a CVD (chemical vapor deposition) silicon dioxide film. In this case, the first insulating layer 57 can have a film quality that is denser than the second insulating layer 58.

[0076] The wiring lead 23 and the via 24 are not formed directly beneath the first electrically conductive element 25, and therefore the first electrically conductive element 25 does not necessarily have to be electrically connected to the functional element 16 formed on the semiconductor substrate 15. Instead of this connection, the first electrically conductive element 25 can be electrically connected to the functional element 16, which is mounted in a different semiconductor device 1 that differs from the semiconductor device 1, for example, by connecting the connecting wire 7 to the pad 14.

[0077] A second electrically conductive element 59 is formed on the first electrically conductive element 25. The second electrically conductive element 59 is a wiring of a second layer stacked on the first electrically conductive element 25 and can be referred to as the second wiring layer. Additionally, the second electrically conductive element 59 is formed by a plurality of conductive layers and can be referred to as the second conductive layer.

[0078] The second electrically conductive element 59 includes a second base layer 60 and a second cover layer 61, which are stacked on the second base layer 60. The second base layer 60 includes, for example, copper and, in the preferred embodiment, can include a copper-clad layer. The second base layer 60 is connected to the first cover layer 27 of the first electrically conductive element 25. This physically connects the second electrically conductive element 59 to the first electrically conductive element 25.

[0079] The second cover layer 61 covers the second base layer 60. The second cover layer 61 integrally includes a second cover section 62, which abuts a top surface of the second base layer 60 and covers the second base layer 60, and a second projecting section 64, which projects laterally from an end surface 63 of the second base layer 60. This forms a second height difference 66, corresponding to the extent of the projection of the second projecting section 64, between the end surface 63 of the second base layer 60 and an end surface 65 of the second cover layer 61. The second projecting section 64 may face the first base layer 26 of the first electrically conductive element 25 via a portion of the protective layer 55.

[0080] The second projecting section 64 can slope downwards towards a lower side (i.e., the side near the first main surface 11 of the semiconductor substrate 15) relative to the second cover section 62. Therefore, the two side parts of a top surface 67 of the second cover layer 61 can be inclined downwards relative to their portion on the second base layer 60. The second cover layer 61 can be thinner than the second base layer 60. For example, the second base layer 60 can have a thickness of not less than 2 µm and not more than 3 µm, and the second cover layer 61 can have a thickness of not less than 1 µm and not more than 2 µm.

[0081] In the preferred embodiment, the second cover layer 61 includes a plurality of cover layers. For example, the second cover layer 61 can include a first layer 68 adjacent to the second base layer 60 and a second layer 69 stacked on top of the first layer 68. The first layer 68 includes, for example, Ni and, in the preferred embodiment, can include a Ni-clad layer. The second layer 69 includes, for example, Pd and, in the preferred embodiment, can include a Pd-clad layer. The second cover layer 61 can further include an Au-clad layer on its outermost surface (not shown). The first layer 68 and the second layer 69 are stacked at both the second cover section 62 and the second projecting section 64. This allows a boundary between the first layer 68 and the second layer 69 to be exposed at the end surface 65 of the second cover layer 61.

[0082] Next, with reference to Fig. 5 The second electrically conductive element 59 is formed on a part that is positioned higher than the first electrically conductive element 25, on the inside of the protective layer 55, and extends such that it coincides with the first electrically conductive element 25 in a top view. The second electrically conductive element 59 has a connecting section 70 that is connected to the front end section 39 of the first electrically conductive element 25. The connecting section 70 of the second electrically conductive element 59 is in Fig. 5 is represented by dashed hatching. For the sake of clarity, this hatching only applies to the single second electrically conductive element 59.

[0083] The second electrically conductive element 59 is curved upwards in the connecting section 70 and extends obliquely and upwards away from the first electrically conductive element 25. A straight line shown at an end section of the connecting section 70 is a curved section 71 of the second electrically conductive element 59 in Fig. 5. Furthermore, in the preferred embodiment, the first electrically conductive element 25 extends to one side in the first direction X1, and the second electrically conductive element 59 extends to the other side in the first direction X1, the connecting section 70 between the first electrically conductive element 25 and the second electrically conductive element 59 forming a boundary in a top view. This ensures that the first electrically conductive element 25 and the second electrically conductive element 59 are arranged linearly along the first direction X1.

[0084] In the preferred embodiment, the second electrically conductive element 59 encloses a third linear section 72. The third linear section 72 is formed in a ribbon shape in a top view. The third linear section 72 is comparatively extensive in terms of its length. Fig. 5 is shown and is thus defined as having a band shape. On the other hand, the third linear section 72 can be defined as linear, for example, if its width is very small in relation to its length. The third linear section 72 includes a front end section 73, which is an end section of the second electrically conductive element 59. The front end section 73 of the second electrically conductive element 59 is a section that is physically connected to the first electrically conductive element 25.

[0085] Below, the longitudinal direction (extension direction) of the third linear section 72 is defined as a third direction X2, and the direction perpendicular to the third direction X2 is defined as a fourth direction Y2. In the preferred embodiment, the third direction X2 and the fourth direction Y2 coincide with the first direction X1 and the second direction Y1, respectively.

[0086] The third linear section 72 includes a ribbon-shaped second base section 74 extending in the third direction X2, and a second side section 75 formed integrally on both sides of the second base section 74 in the fourth direction Y2. The second base section 74 is a region obtained by expediently setting a ribbon-shaped area extractable from the third linear section 72 while retaining essentially the same external shape as the third linear section 72, like an internal region of the second boundary section 76, which is in Fig. 5 is shown by a dashed line.

[0087] The second base section 74 can have a second width W4 that is equal to or greater than 80%, preferably 90%, of the width W3 of the third linear section 72. For example, the width W3 of the third linear section 72 may be not less than 8 µm and not more than 20 µm, and the second width W4 of the second base section 74 may be not less than 7 µm and not more than 16 µm. The width W3 of the third linear section 72 may be a distance between an upper section of a second convex section 77 on one side and an upper section of the second convex section 77 on the other side in the fourth direction Y2. Furthermore, the width W3 of the third linear section 72 may be less than the width W1 of the first linear section 36 of the first electrically conductive element 25.This makes it possible to provide a connecting edge next to the second electrically conductive element 59 when the second electrically conductive element 59 is connected to the first electrically conductive element 25.

[0088] In the preferred embodiment, the second side section 75 is an outer region of the second boundary section 76 and has a non-uniform structure designed so as not to affect the outer shape of the third linear section 72. More precisely, the second side section 75 includes a second convex section 77 projecting from the second base section 74 in the fourth direction Y2, and a second concave section 78 that is hollow with respect to the second convex section 77. In the preferred embodiment, the third linear section 72 has a second side edge section 79 formed by a curve that is alternately curved to one side (left side of the paper plane) and to the opposite side (right side of the paper plane) in the fourth direction Y2.The second side edge section 79 is an outer shape line that extends in a top view in the third direction X2 of the third linear section 72 and forms a side surface of the third linear section 72. Therefore, the second side section 75 of the third linear section 72 is a region between the second base section 74 and the second side edge section 79, and the second convex section 77 and the second concave section 78, which both form the second side section 75, are formed by the second side edge section 79, which has a curved shape and is continuously connected along the third direction X2.

[0089] The extent P2 of the projection of the second convex section 77 of the second side section 75 need only be such that the external shape of the third linear section 72 is substantially unchanged. For example, compared to the second width W4 of the second base section 74, the extent P2 of the projection may be equal to or less than 1 / 10 of the second width W4 (i.e., the second width W4 has ten times or more than ten times the extent P2 of the projection). Furthermore, the curved second side edge section 79 may be a sine curve 80 extending along the third direction X2 in the preferred embodiment. Thus, the second side section 75 includes a plurality of second curved convex sections 81 and a plurality of second curved concave sections 82 formed alternately along the third direction X2.In this case, the second width W4 of the second base section 74 may be five times or more than five times the length of an amplitude A2 of the sine curve 80 from a second reference line 83, which is defined by an alternately long and twice short dashed line in . Fig. 5 is shown.

[0090] The front end section 73 of the second electrically conductive element 59 has, in a plan view, a third side surface 85 formed by a third circular arc 84 with a third radius of curvature R3. Compared to this third side surface 85, in a plan view, the second side edge section 79 can have a fourth side surface 87 formed by a fourth circular arc 86 having a fourth radius of curvature R4, which is smaller than the third radius of curvature R3. If the second side edge section 79 encloses the sine curve 47, a curved surface of each of the second curved convex section 81 and the second curved concave section 82 can be formed by the fourth circular arc 86.

[0091] In the preferred embodiment, the second side-edge section 79, which encloses the sine curve 80, is configured as a pair of second side-edge sections along the third direction X2. In other words, both side edges of the third linear section 72 can be the second side-edge section 79 that encloses the sine curve 80. The pair of sine curves 80 can enclose one sine curve 80A and the other sine curve 80B. In contrast, the sine curve 80A and the other sine curve 80B can differ in the configuration of the second curved convex section 81 in the third direction X2. For example, the second curved convex section 81 of sine curve 80A can differ from the second curved convex section 81 of the other sine curve 80B in the fourth direction Y2.

[0092] In the preferred embodiment, the second curved convex section 81 of the sine curve 80A faces the second curved concave section 82 of the other sine curve 80B in the fourth direction Y2. Furthermore, the second curved convex section 81 of the other sine curve 80B faces the second curved concave section 82 of the sine curve 80A. Thus, the second curved convex section 81 (the second curved concave section 82) is formed alternately between the second side section 75 including the sine curve 80A and the second side section 75 including the other sine curve 80B in the third direction X2.

[0093] As thus described, the third linear section 72 has the second side section 75, which includes both the second curved convex section 81 and the second curved concave section 82, as shown in Fig. Figure 5 shows. On the other hand, there is a case in which the second curved convex section 81 of the sine curve 80 and a curved section of the second curved concave section 82 appear as pointed, for example, when the magnification is low when viewing the first linear section 72. In this case, the second side section 75 may appear zigzag-shaped in a top view. The shape of the upper section of the second convex section 77, which projects outside the zigzag shape, may correspond to the shape of the curved surface of the second curved convex section 81.

[0094] Furthermore, the aforementioned second convex section 77 and the second concave section 78 can be selectively formed on the second cover layer 61, which is one of the second base layer 60 and the second cover layer 61, both of which are components of the second electrically conductive element 59. Of course, the second convex section 77 and the second concave section 78 can be formed on both the second base layer 60 and the second cover layer 61.

[0095] Fig. Figure 7 is a flowchart showing part of a manufacturing process of the semiconductor chip 4 in the sequence of process steps.

[0096] For example, a semiconductor wafer is prepared for the fabrication of the semiconductor chip 4 (step S1). The semiconductor wafer serves as the basis of the semiconductor substrate 15. The functional element 16 is then formed on the main surface of the semiconductor wafer (step S2). The functional element 16 can be formed by performing a known procedure, such as the implantation of impurities into the semiconductor substrate 15 or the deposition of resistant, electrically conductive materials. The insulating layer structure 17 is then formed on the semiconductor substrate 15 (step S3). The insulating layer structure 17 can, for example, be formed by a technique for forming a known multilayer wiring structure.

[0097] The first electrically conductive element 25 is then formed on the insulating layer structure 17 (step S4). For example, the first electrically conductive element 25 is formed by subjecting the material of the first base layer 26 and the material of the first cover layer 27 to a plating growth on the insulating layer structure 17. The first electrically conductive element 25 is then subjected to structuring (step S5). This forms the first side section 41, which includes both the first convex section 44 and the first concave section 45, on the first linear section 36 of the first electrically conductive element 25.In detail, a mask having the structure of the first side edge section 46 (sine curve 47) is arranged on a layer structure consisting of the first base layer 26 and the first top layer 27. The first top layer 27 and the first base layer 26 are selectively etched through this mask, thereby forming the first convex section 44 and the first concave section 45. If the semiconductor chip 4 includes the second electrically conductive element 59, the first electrically conductive element 25 is first subjected to structuring, and then it is recommended to form the second electrically conductive element 59 by repeatedly performing steps S4 and S5.

[0098] The protective layer 55 is then formed on the insulating layer structure 17 to cover the first electrically conductive element 25 (step S6). For example, the protective layer 55 can be formed by placing a semiconductor wafer in a mold and then filling this mold with a resin material. A heat treatment is then performed, and consequently the protective layer 55 is cured.

[0099] The pad opening 56 is then formed in the protective layer 55, thereby exposing part of the first electrically conductive element 25 as the pad 14. The semiconductor wafer is then sliced, and a multitude of semiconductor chips 4 are cut out. The semiconductor chip 4 described above is obtained by a process that includes these steps.

[0100] Fig. Figure 8 is a view used to describe a stress relaxation effect caused by introducing a non-uniform structure. More specifically, it shows Fig. 8 a result obtained by performing a stress simulation applied to sample 1 and sample 2. Sample 1 is a wiring line 89 in which the side edge section 88 was formed by the aforementioned sine curve 47. Sample 2 is a wiring line 91 in which a side edge section 90 was formed linearly. In Fig. 8 is an area that has been given a dashed hatch, an area where the stress reaches 0.1% to 10%, if the stress of a contoured area outside the hatched area is defined as 100%. With reference to Fig. 8 understands that in sample 1, where the non-uniform structure is used, the voltage applied to the side section of the wiring line 89 is distributed and made smaller as a whole than in sample 2, where the non-uniform structure is not used.

[0101] Additionally, a thermal cycling test was performed on sample 1. The test conditions were -65 °C to 150 °C, and the number of cycles was 500 (30 minutes at high temperature and 30 minutes at low temperature). After the test, a SEM cross-sectional image of sample 1 was examined, and no cracks originating at the edge section 88 of the wiring conductor 89 were detected in the protective layer 55 made of an organic insulating resin. Based on this result, it is assumed that in sample 1, the stress applied to the side section of the wiring conductor 89 was distributed by the non-uniform structure of the side edge section 88 of the wiring conductor 89.

[0102] The first side edge section 46 is formed by the sine curve 47 in the semiconductor chip 4 according to the preferred embodiment, and therefore it is possible to measure the voltage generated in the first side section 41 of the first linear section 36, as in the simulation result of Fig. As shown in Figure 8, this makes it possible to distribute the stress on the first side section 41 of the first linear section 36 of the first electrically conductive element 25 as a whole. Consequently, it is possible to contain deformation that occurs in the protective layer 55 when expansion and contraction are caused by a change in ambient temperature (for example, a temperature change when the protective layer 55 has cured).

[0103] Furthermore, the voltage distribution structure is formed by selectively forming the first convex section 44 and the first concave section 45 on the first side section 41 of the first linear section 36, not by the fact that the first electrically conductive element 25 as a whole coils to assume the shape of the letter S. Therefore, it is not necessary to enlarge the installation space for the first electrically conductive element 25, and therefore it is possible to prevent the semiconductor chip 4 from becoming larger.

[0104] Furthermore, it is possible to distribute the voltage generated in the second side section 75 of the third linear section 72 if the semiconductor chip 4 includes the second electrically conductive element 59 and if the second side edge section 79 of this second electrically conductive element 59 is also formed by the sine curve 80. This makes it possible to reduce the voltage of the second side section 75 of the third linear section 72 of the second electrically conductive element 59 as a whole. Consequently, it is possible to contain deformation that occurs in the protective layer 55 when expansion and contraction are caused by a temperature change.

[0105] While the preferred embodiment of the present disclosure has been described above, the present disclosure may nevertheless be implemented in other modes.

[0106] While, for example, the wiring layer of the LSI chip was used as an example for the first and second electrically conductive elements 25 and 59 in the preferred embodiment described above, the characteristic structure of the first and second electrically conductive elements 25 and 59 can nevertheless also be used for the structure of, for example, wires, electrodes, and coils of other semiconductor elements. More precisely, it is also possible to use the characteristic structure for a front-surface wiring of a wafer-level CSP (wafer-level chip size package), a coil interconnect section of an isolation transformer element, or the like.

[0107] The preferred embodiments described so far in the present disclosure are examples in every respect and should not be understood as limited and are intended to include modifications in every respect.

[0108] The following features are to be found in this description and the drawings. In the following features, each numerical symbol or the like in parentheses represents a reference to a corresponding component named in the detailed description. However, each component named below should not be construed as equivalent to any component named above by its reference symbol. [Annex 1-1]

[0109] Semiconductor device (1), including: a semiconductor chip (4, 15); a first conductive layer (25) formed on the semiconductor chip (4, 15) and having a first linear section (36) extending along a main surface (11) of the semiconductor chip (4, 15); and an organic insulating layer (55) formed on the semiconductor chip (4, 15) and covering the first conductive layer (25), wherein the first linear section (36) includes a base section (40) having a connection area to which a connecting element can be connected, and a first side section (41) including a convex section (44, 48) projecting from the base section (40) in a direction intersecting a longitudinal direction of the first linear section (36), and a concave section (45, 49) which is hollow with respect to the convex section (44, 48).

[0110] There is a case where high mechanical stress is generated in the first side segment of the first linear section due to a difference in the coefficient of thermal expansion between the first electrically conductive element and the organic insulating layer when the ambient temperature changes, for example, if the first side segment of the first linear section is a straight line. If this stress exerts an external force on the organic insulating layer, and if expansion and contraction are caused by a temperature change, deformation occurs in the organic insulating layer, and the mechanical properties of the organic insulating layer could decrease.When the semiconductor device is used according to the preferred embodiment, it is therefore possible to distribute the stress generated in the first side segment of the first linear section, since the first side segment of the first linear section includes the convex and concave sections. This makes it possible to reduce the stress on the first side segment of the first linear section of the first electrically conductive element as a whole. Consequently, it is possible to limit deformation that occurs in the organic insulating layer when expansion and contraction are caused by temperature changes. [Appendix 1-2]

[0111] Semiconductor device (1) according to Annex 1-1, wherein the convex section (44, 48) and the concave section (45, 49) include a plurality of curved convex sections (48) and a plurality of curved concave sections (49) formed alternately by a sine curve (47) extending along the longitudinal direction of the first linear section (36).

[0112] In this configuration, the convex section and the concave section are curved convex sections and curved concave sections, respectively, and therefore it is possible to prevent stress from concentrating at certain points on the convex and concave sections. [Appendix 1-3]

[0113] Semiconductor device (1) according to Annex 1-2, wherein the first side section (41) of the first linear section (36) is formed by a pair of sine curves (47A, 47B) extending along the longitudinal direction of the first linear section (36).

[0114] In this configuration, it is possible to distribute a voltage in each of the pair of first side sections of the first linear section. [Appendix 1-4]

[0115] Semiconductor device (1) according to Annex 1-3, wherein the curved convex section (48) of the sine curve (47A), which is one of the pair of sine curves, faces the curved concave section (49) of the sine curve (47B), which is the other of the pair of sine curves, and the curved convex section (48) of the sine curve (47B), which is the other of the pair of sine curves, faces the curved concave section (49) of the sine curve (47A), which is one of the pair of sine curves in a direction which intersects the longitudinal direction of the first linear section (36).

[0116] In this configuration, the curved convex section (curved concave section) is formed alternately at the first side section on one side and at the first side section on the other side along the longitudinal direction of the first linear section. For example, consider a case in which a stress in at least one (e.g., curved convex section) of the curved convex and concave sections is less than a stress in another (e.g., curved concave section) of the curved convex and concave sections. In this case, a stress-relaxation portion of the first linear section does not appear continuously along the longitudinal direction of the first linear section, but rather appears alternately and continuously at the first side section on one side and at the first side section on the other side.Therefore, it is possible to reduce the prestressed stress relaxation section of the first linear segment. [Appendix 1-5]

[0117] Semiconductor device (1) according to one of Annex 1-2 to Annex 1-4, wherein the base section (40) is formed in a band shape with a first width (W2) and the first width (W2) of the base section (40) has five times or more than five times the length of an amplitude (A1) of the sine wave (47).

[0118] In this configuration, it is possible to achieve a stress distribution effect in the first electrically conductive element, for example, by forming a curved convex section and a curved concave section using a sine wave with an amplitude approximately 1 / 5 of the width of any existing first electrically conductive layer (e.g., wiring or electrode). Conversely, it is possible to maintain a relatively large initial width of the base section, even when the stress distribution structure is formed by both the curved convex and concave sections. Consequently, there is a wide range of options available for the connecting element to the base section (e.g., shape, thickness, etc.). [Appendix 1-6]

[0119] Semiconductor device (1) according to one of Annex 1-2 to Annex 1-5, wherein the first conductive layer (25) includes a front end section (39) which includes part of the first linear section (36) and a second linear section (37) which is connected to the first linear section (36) by a corner section (38), and the sine wave (47) is selectively formed at the first linear section (36) which is one of the first linear section (36) and the second linear section (37).

[0120] In this configuration, the curved convex section and the curved concave section are formed by the sine curve on the first linear section, which includes the front end section, where a voltage is easily caused by a change in ambient temperature, and therefore it is possible to effectively distribute the voltage in the first electrically conductive element. [Appendix 1-7]

[0121] Semiconductor device (1) according to Annex 1-6, wherein the front end section (39) of the first conductive layer (25) has a first side surface (52) formed in a top view by a first circular arc (51) with a first radius of curvature (R1), and at least one of the curved convex section (48) and the curved concave section (49) of the sine curve (47) has a second side surface (54) formed in a top view by a second circular arc (53) with a second radius of curvature (R2) which is smaller than the first radius of curvature (R1). [Appendix 1-8]

[0122] Semiconductor device (1) according to one of Annex 1-1 to Annex 1-7, wherein the first conductive layer (25) includes a first base layer (26) and a first cover layer (27) stacked on the first base layer (26) to project laterally from an end face (29) of the first base layer (26) in a cross-sectional view, and the first side section (41) which includes the convex section (44, 48) and the concave section (45, 49) is selectively formed on the first cover layer (27).

[0123] In this configuration, the first side section, which includes the convex and concave sections, is selectively formed on the first top layer and does not need to be formed on the first base layer. Therefore, it is possible to reduce the number of steps in the process for forming the convex and concave sections. [Appendix 1-9]

[0124] Semiconductor device (1) according to one of Annex 1-1 to Annex 1-8, wherein the organic insulating layer (55) has a pad opening (56) which exposes the base section (40) of the first linear section (36) as a pad (14).

[0125] In this configuration, it is possible to connect a connecting element such as a bond wire to the base section of the first linear section through the pad opening. [Appendix 1-10]

[0126] Semiconductor device (1) according to one of Annex 1-1 to Annex 1-8, which further includes a second conductive layer (59) connected to the base section (40) of the first linear section (36) in the organic insulating layer (55).

[0127] In this configuration, the aforementioned stress distribution structure prevents a reduction in the mechanical properties of the organic insulating layer surrounding the second electrically conductive element. Therefore, it is possible to improve the connection reliability between the first electrically conductive element (first linear section) and the second electrically conductive element. [Appendix 1-11]

[0128] Semiconductor device (1) according to Annex 1-10, wherein the second conductive layer (59) has a third linear section (72) extending along the main surface (11) of the semiconductor chip (4, 15), and the third linear section (72) includes a second side section (75) which includes a second convex section (77, 81) projecting in a direction intersecting a longitudinal direction of the third linear section (72), and a second concave section (78, 82) which is hollow in a top view with respect to the second convex section (77, 81).

[0129] In this configuration, it is possible to distribute the stress generated in the second side segment of the third linear section, since the second side segment of the third linear section includes the second convex section and the second concave section. This makes it possible to reduce the stress on the second side segment of the third linear section of the second conductive layer as a whole. Consequently, it is possible to contain deformation that occurs in the organic insulating layer when expansion and contraction are caused by temperature changes. [Appendix 1-12]

[0130] Semiconductor device (1) according to Annex 1-11, wherein the second conductive layer (59) includes a second base layer (60) and a second cover layer (61) stacked on the second base layer (60) to project laterally from an end face (63) of the second base layer (60) in a cross-sectional view, and the second side section (75) which includes the second convex section (77, 81) and the second concave section (78, 82) is selectively formed on the second cover layer (61).

[0131] In this configuration, the second side section, which includes the second convex section and the second concave section, is selectively formed on the second top layer and does not need to be formed on the second base layer. Therefore, it is possible to reduce the number of steps in the process for forming the second convex section and the second concave section. [Appendix 1-13]

[0132] Semiconductor device (1) according to one of Annex 1-1 to Annex 1-12, including an insulating layer layer structure (17) formed between the first conductive layer (25) and the semiconductor chip (4, 15) and including at least a first inorganic insulating layer (18, 57) and a second inorganic insulating layer (19, 58) stacked on top of the first inorganic insulating layer (18, 57). [Appendix 1-14]

[0133] Semiconductor device (1) according to one of Annex 1-1 to Annex 1-13, including an integrated circuit element (16) formed on the semiconductor chip (4, 15) and electrically connected to the first conductive layer (25).

[0134] With this configuration, it is possible to reduce the voltage of the first side section of the first linear section of the first electrically conductive element as described above, and therefore it is possible to provide a semiconductor device that includes an integrated circuit in which the insulation reliability of an organic insulating layer is high. [Annex 2-1]

[0135] Semiconductor device (1), including: a semiconductor chip (4, 15); a first wiring layer (25) formed on the semiconductor chip (4, 15) and extending along a main surface (11) of the semiconductor chip (4, 15); and an organic insulating layer (55) formed on the semiconductor chip (4, 15) and covering the first wiring layer (25), wherein the first wiring layer (25) has a first side section (41) which includes a zigzag shape (47) which is formed in a top view along an extension direction of the first wiring layer (25).

[0136] There is a case where a high stress is generated in the first side segment of the first wiring layer due to a difference in the coefficient of thermal expansion between the first wiring layer and the organic insulation layer when the ambient temperature changes, for example, if the first side segment of the first wiring layer is straight. If this stress exerts an external force on the organic insulation layer, and if expansion and contraction are caused by a temperature change, deformation occurs in the organic insulation layer, and its mechanical properties could decrease.When the semiconductor device is used according to the preferred embodiment, it is therefore possible to distribute the stress generated in the first side section of the first wiring layer, since the first side section of the first wiring layer encloses the zigzag shape. This makes it possible to reduce the stress of the first side section of the first wiring layer as a whole. Consequently, it is possible to contain deformation that occurs in the organic insulating layer when expansion and contraction are caused by a temperature change. [Annex 2-2]

[0137] Semiconductor device (1) according to Annex 2-1, wherein an upper section of (47) having the zigzag shape is formed by a first circular arc (53) having a first radius of curvature (R2) in a top view.

[0138] In this configuration, the upper section is curved with a zigzag shape, and therefore it is possible to prevent stress from concentrating on the upper section. [Appendix 2-3]

[0139] Semiconductor device (1) according to Annex 2-2, wherein the first side section (41) of the first wiring layer (25) is formed by a pair of zigzag shapes (47A, 47B) extending along the extension direction of the first wiring layer (25).

[0140] With this configuration, it is possible to distribute the voltage in each of the pair of first side sections of the first wiring layer. [Appendix 2-4]

[0141] Semiconductor device (1) according to Annex 2-3, wherein a convex section (44, 48) of the zigzag shape (47A), which is one of the pair of zigzag shapes, faces a concave section (45, 49) of the zigzag shape (47B), which is the other of the pair of zigzag shapes, and a convex section (44, 48) of the zigzag shape (47B), which is the other of the pair of zigzag shapes, faces a concave section (45, 49) of the zigzag shape (47A), which is one of the pair of zigzag shapes in a direction which intersects the extension direction of the first wiring layer (25).

[0142] In this configuration, the convex (concave) section is formed alternately at the first side section on one side and the first side section on the other side along the longitudinal direction of the first wiring layer. For example, consider a case where the stress in at least one (e.g., convex) of the convex and concave sections is less than the stress in another (e.g., concave) of the convex and concave sections. In this case, a stress-relaxation section of the first wiring layer does not appear continuously along its longitudinal direction, but rather alternately and continuously at the first side section on one side and the first side section on the other side. Therefore, it is possible to reduce the size of the prestressed stress-relaxation section of the first wiring layer. [Annex 2-5]

[0143] Semiconductor device (1) according to one of Annex 2-2 to Annex 2-4, wherein the first wiring layer (25) includes a first linear section (36) which includes a front end section (39) and a second linear section (37) which is connected to the first linear section (36) by a corner section (38), and the zigzag shape (47) is selectively formed on the first linear section (36), which is one of the first linear section (36) and the second linear section (37).

[0144] In this configuration, the zigzag shape is formed on the first linear section, which includes the front end section where a stress is easily caused by a change in ambient temperature, and therefore it is possible to effectively distribute the stress in the first wiring layer. [Annex 2-6]

[0145] Semiconductor device (1) according to Annex 2-5, wherein the front end section of the first wiring layer (25) is formed by a second circular arc (51) with a second radius of curvature (R1) which is larger than the first radius of curvature (R2) in a top view. [Annex 2-7]

[0146] Semiconductor device (1) according to one of Annex 2-1 to Annex 2-6, wherein the first wiring layer (25) includes a first base layer (26) and a first cover layer (27) which is stacked on the first base layer (26) to project laterally from an end face (29) of the first base layer (26) in a cross-sectional view, and the first side section (41) which includes the zigzag shape (47) is selectively formed on the first cover layer (27).

[0147] In this configuration, the first side section, which encloses the zigzag shape, is selectively formed on the first top layer and does not need to be formed on the first base layer. Therefore, it is possible to reduce the number of steps in the process for forming the zigzag shape. [Appendix 2-8]

[0148] Semiconductor device (1) according to one of Annex 2-1 to Annex 2-7, wherein the organic insulating layer (55) has a pad opening (56) which exposes the first wiring layer (25) as a pad (14).

[0149] In this configuration, it is possible to connect a connecting element, such as a bond wire, to the first wiring layer through the pad opening. [Annex 2-9]

[0150] Semiconductor device (1) according to one of Annex 2-1 to Annex 2-7, which further includes a second wiring layer (59) connected to the first wiring layer (25) in the organic insulating layer (55).

[0151] In this configuration, the aforementioned voltage distribution structure prevents the mechanical properties of the organic insulation layer surrounding the second wiring layer from being reduced. Therefore, it is possible to improve the connection reliability between the first and second wiring layers. [Appendix 2-10]

[0152] Semiconductor device (1) according to Annex 2-9, wherein the second wiring layer (59) has a second side section (75) which includes a second zigzag shape (80) formed in a top view along an extension direction of the second wiring layer (59).

[0153] In this configuration, it is possible to distribute the stress generated in the second side section of the second wiring layer, since the second side section of the second wiring layer encloses the second zigzag shape. This allows for a reduction in the stress of the second side section of the second wiring layer as a whole. Consequently, it is possible to contain deformation that occurs in the organic insulation layer when expansion and contraction are caused by temperature changes. [Appendix 2-11]

[0154] Semiconductor device (1) according to Annex 2-10, wherein the second wiring layer (59) includes a second base layer (60) and a second cover layer (61) stacked on the second base layer (60) to project laterally from an end face (63) of the second base layer (60) in a cross-sectional view, and the second side section (75) which includes the second zigzag shape (80) is selectively formed on the second cover layer (61).

[0155] In this configuration, the second side section, which encloses the second zigzag shape, is selectively formed on the second top layer and does not need to be formed on the second base layer. Therefore, it is possible to reduce the number of steps in the process for forming the second zigzag shape. [Appendix 2-12]

[0156] Semiconductor device (1) according to one of Annex 2-1 to Annex 2-11, including an insulating layer layer structure (17) formed between the first wiring layer (25) and the semiconductor chip (4, 15) and including at least a first inorganic insulating layer (18, 57) and a second inorganic insulating layer (19, 58) stacked on top of the first inorganic insulating layer (18, 57). [Appendix 2-13]

[0157] Semiconductor device (1) according to one of Annex 2-1 to Annex 2-12, including an integrated circuit element (16) formed on the semiconductor chip (4, 15) and electrically connected to the first wiring layer (25).

[0158] With this configuration, it is possible to reduce the voltage of the first side section of the first wiring layer as described above, and therefore it is possible to provide a semiconductor device that includes an integrated circuit in which the insulation reliability of an organic insulating layer is high. [Annex 3-1]

[0159] Semiconductor device (1), including: a semiconductor substrate (4, 15); a first electrically conductive element (25) formed on the semiconductor substrate (4, 15) having a first linear section (36) extending along a major surface (11) of the semiconductor substrate (4, 15) and having a first coefficient of thermal expansion; and a resin layer (55) formed on the semiconductor substrate (4, 15) covering the first electrically conductive element (25), and having a second coefficient of thermal expansion that is higher than the first coefficient of thermal expansion, wherein the first linear section (36) includes a first side edge section (46) formed by a curve (47) which is alternately curved to one side and to the other side in a direction which, in a top view, intersects a longitudinal direction of the first linear section (36).

[0160] There is a case in which a high stress is generated in the first side segment of the first linear section due to a difference in the coefficient of thermal expansion. This difference arises because the resin layer expands more than the first electrically conductive element when the ambient temperature changes, for example, if the first side segment of the first linear section is a straight line. If this stress exerts an external force on the resin layer, and if the expansion and contraction are caused by a temperature change, deformation occurs in the resin layer, and its mechanical properties could decrease. Therefore, when the semiconductor device is used according to the preferred embodiment, it is possible to distribute the stress generated in the first side segment of the first linear section, since the first side segment is formed by the curve.This makes it possible to reduce the stress on the first side segment of the first linear segment of the first electrically conductive element as a whole. Consequently, it is possible to limit deformation that occurs in the resin layer when expansion and contraction are caused by temperature changes. [Annex 3-2]

[0161] Semiconductor device (1) according to Annex 3-1, wherein the first linear section (36) includes a base section (40) to which a connecting element can be attached, and a first side section (41) which includes a convex section (44, 48) which projects from the base section (40) in a direction which intersects the longitudinal direction of the first linear section (36), and a concave section (45, 49) which is hollow with respect to the convex section (44, 48), and the first side edge section (46) is formed by a curve (47) which, in a top view, continuously connects the convex section (44, 48) and the concave section (45, 49) along the longitudinal direction of the first linear section (36).

[0162] In this configuration, the stress generated in the first side section, which includes the convex and concave sections, is distributed. Therefore, it is possible to mitigate a decrease in the mechanical properties of the resin layer, even when stress continues to be applied to the first linear section if a connecting element is attached to its base. Furthermore, a stress distribution structure is formed by selectively shaping the convex and concave sections on the first side section of the first linear section, not by the fact that the entire first electrically conductive element twists to assume the shape of the letter S.Therefore, there is no need to enlarge the installation space for the first electrically conductive element according to the preferred embodiment, and therefore it is possible to prevent the semiconductor device from being enlarged. [Appendix 3-3]

[0163] Semiconductor device (1) according to Annex 3-2, wherein the base section (40) is formed in a ribbon shape with a first width (W2), and the first width (W2) of the base section (40) has ten times or more than ten times the length of the extent of the projection (P1) of the convex section (44, 48) of the base section (40).

[0164] In this configuration, it is possible to achieve a stress distribution effect in the first electrically conductive element, for example, by forming a convex section with a projection whose extent corresponds to approximately 1 / 10 of the width of an existing first electrically conductive element (e.g., wiring conductor or electrode). Conversely, it is possible to maintain a relatively large initial width of the base section, even if the stress distribution structure is formed by both the convex and concave sections. Consequently, it is possible to allow for many options (e.g., shape, thickness, etc.) for the connecting element that can be joined to the base section. [Appendix 3-4]

[0165] Semiconductor device (1) according to one of Annex 3-1 to Annex 3-3, wherein the first electrically conductive element (25) includes a front end section (39) which includes part of the first linear section (36) and a second linear section (37) which is connected to the first linear section (36) by a corner section (38), and the first side edge section (46) is selectively formed on the first linear section (36) which is one of the first linear section (36) and the second linear section (37).

[0166] In this configuration, the first side edge section is formed with a curved shape at the first linear section that includes the front end section, where a stress is easily caused by a change in ambient temperature, and therefore it is possible to effectively distribute the stress in the first electrically conductive element. [Annex 3-5]

[0167] Semiconductor device (1) according to Annex 3-4, wherein the front end section (39) of the first electrically conductive element (25) has a first side surface (52) formed in a top view by a first circular arc (51) with a first radius of curvature (R1), and the first side edge section (46) of the first electrically conductive element (25) has a second side surface (54) formed in a top view by a second circular arc (53) with a second radius of curvature (R2) which is smaller than the first radius of curvature (R1). [Annex 3-6]

[0168] Semiconductor device (1) according to one of Annex 3-1 to Annex 3-5, wherein the first electrically conductive element (25) includes a first base layer (26) and a first cover layer (27) stacked on the first base layer (26) to project laterally from an end face (29) of the first base layer (26) in a cross-sectional view, and the first side edge section (46) is selectively formed on the first cover layer (27).

[0169] In this configuration, the first side edge segment with a curved shape is selectively formed on the first top layer and does not need to be formed on the first base layer. Therefore, it is possible to reduce the number of steps in the process for forming the first side edge segment. [Annex 3-7]

[0170] Semiconductor device (1) according to Annex 3-2, wherein the resin layer (55) has a pad opening (56) which exposes the base section (40) of the first linear section (36) as a pad (14).

[0171] In this configuration, it is possible to connect a connecting element such as a bond wire to the base section of the first linear section through the pad opening. [Appendix 3-8]

[0172] Semiconductor device (1) according to Annex 3-2, further comprising a second electrically conductive element (59) connected to the base section (40) of the first linear section (36) in the resin layer (55).

[0173] In this configuration, the aforementioned stress distribution structure prevents a reduction in the mechanical properties of the resin layer surrounding the second electrically conductive element. Therefore, it is possible to improve the connection reliability between the first electrically conductive element (first linear section) and the second electrically conductive element. [Appendix 3-9]

[0174] Semiconductor device (1) according to Annex 3-8, wherein the second electrically conductive element (59) has a third linear section (72) extending along the main surface (11) of the semiconductor substrate (4, 15), and the third linear section (72) includes a second side edge section (79) formed by a curve (80) that is alternately curved to one side and to the other side in a direction which, in a top view, intersects a longitudinal direction of the third linear section (72).

[0175] In this configuration, it is possible to distribute the stress generated in the second side segment of the third linear section, since the second side edge segment is formed by a curve. This makes it possible to reduce the stress on the second side segment of the third linear section of the second electrically conductive element as a whole. Consequently, it is possible to contain deformation that occurs in the resin layer when expansion and contraction are caused by temperature changes. [Appendix 3-10]

[0176] Semiconductor device (1) according to Annex 3-8 or Annex 3-9, wherein the second electrically conductive element (59) includes a second base layer (60) and a second cover layer (61) stacked on the second base layer (60) to project laterally from an end face (63) of the second base layer (60) in a cross-sectional view, and the second side edge section (79) is selectively formed on the second cover layer (61).

[0177] In this configuration, the second side edge section with a curved shape is selectively formed on the second top layer and does not need to be formed on the second base layer. Therefore, it is possible to reduce the number of steps in the process for forming the second side edge section. [Appendix 3-11]

[0178] Semiconductor device (1) according to one of Annex 3-1 to Annex 3-10, including an insulating layer layer structure (17) formed between the first electrically conductive element (25) and the semiconductor substrate (4, 15) and including at least a first inorganic insulating layer (18, 57) and a second inorganic insulating layer (19, 58) stacked on the first inorganic insulating layer (18, 57). [Appendix 3-12]

[0179] Semiconductor device (1) according to one of Annex 3-1 to Annex 3-11, including an integrated circuit element (16) formed on the semiconductor substrate (4, 15) and electrically connected to the first electrically conductive element (25).

[0180] With this configuration, it is possible to reduce the voltage of the first side section of the first linear section of the first electrically conductive element as described above, and therefore it is possible to provide a semiconductor device that includes an integrated circuit in which the insulation reliability of a resin layer is high. LIST OF REFERENCE MARKS 1 Semiconductor device 2 Sealing resin 3 Chippad 4 Semiconductor chips 5 Conductive connecting material 6 connecting conductors 7 Connecting wire 8 First main surface 9 Second main surface 10A First side surface 10B Second side surface 10C Third side surface 10D Fourth Side Surface 11 First main surface 12 Second main surface 13 Element area 13A diode range 13B transistor area 13C Resistor Element Range 14 pads 15 Semiconductor substrate 16 Functional element 17 Insulation layer layer structure 18 First insulation layer 19 Second insulation layer 20 Third insulation layer 21 Fourth insulation layer 22 Fifth insulation layer 23 Wiring line 24 vias 25 First electrically conductive element 26 First base layer 27 First top layer 28 First deck section 29 End surface 30 First lead section 31 End surface 32 First elevation difference 33 Top 34 First shift 35 Second shift 36 First linear section 37 Second linear section 38 Corner section 39 Front End Section 40 First Basic Section 41 First page section 42 First border section 43 First border section 44 First convex section 45 First concave section 46 First side edge section 47 Sine curve 47A Sine wave 47B Sine curve 48 First curved convex section 49 First curved concave section 50 First reference line 51 First circular arc 52 First side surface 53 Second circular arc 54 Second side surface 55 Protective layer 56 pad opening 57 First insulation layer 58 Second insulation layer 59 Second electrically conductive element 60 Second base layer 61 Second top layer 62 Second deck section 63 End surface 64 Second lead section 65 End area 66 Second elevation difference 67 Top 68 First shift 69 Second shift 70 Connecting section 71 Curved Section 72 Third linear section 73 Front End Section 74 Second Base Section 75 Second section 76 Second border section 77 Second convex section 78 Second concave section 79 Second side edge section 80 sine curve 80A sine wave 80B sine wave 81 Second curved convex section 82 Second curved concave section 83 Second reference line 84 Third circular arc 85 Third side surface 86: Fourth circular arc 87 Fourth side surface 88 Side edge section 89 Wiring line 90 Side edge section 91 Wiring line A1 Amplitude A2 Amplitude P1 Extent of the lead P2 Extent of the lead R1 First radius of curvature R2 Second radius of curvature R3 Third radius of curvature R4 Fourth radius of curvature W1 width W2 First Broad W3 width W4 Second Width X1 First direction X2 Third direction Y1 Second direction Y2 Fourth Direction

Claims

Semiconductor device (1) comprising: a semiconductor substrate (4, 15); a first electrically conductive element (25) formed over the semiconductor substrate (4, 15) and having a first linear section (36) extending along a major surface (11) of the semiconductor substrate (4, 15); and an organic insulating layer (55) formed over the semiconductor substrate (4, 15) and covering the first electrically conductive element (25), wherein the first linear section (36) includes a first side edge section (46) formed by a curve (47) that is alternately curved to one side and to the opposite side in a direction (Y1) which, in a top view, intersects a longitudinal direction (X1) of the first linear section (36).wherein the first electrically conductive element (25) includes a first base layer (26) and a first cover layer (27) which is stacked on the first base layer (26) such that it projects laterally from an end face (29) of the first base layer (26) in a cross-sectional view, and wherein the first side edge section (46) is selectively formed on the first cover layer (27). Semiconductor device (1) according to claim 1, wherein the first linear section (36) includes a base section (40) to which a connecting element can be connected, and a first side section (41) comprising a convex section (44, 48) projecting from the base section (40) in the direction (Y1) intersecting a longitudinal direction (X1) of the first linear section (36), and a concave section (45, 49) which is hollow with respect to the convex section (44, 48), and wherein the first side edge section (46) is formed by a curve (47) which, in a top view, continuously connects the convex section (44, 48) and the concave section (45, 49) along the longitudinal direction of the first linear section (36). Semiconductor device (1) according to claim 2, wherein the base section (40) is formed in a ribbon shape with a first width (W2), and wherein the first width (W2) of the base section (40) has ten times or more than ten times the length of the extent (P1) of the projection of the convex section (44, 48) from the base section (40). Semiconductor device (1) according to one of claims 1 to 3, wherein the first electrically conductive element (25) includes a front end section (39) which includes a part of the first linear section (36) and a second linear section (37) which is connected to the first linear section (36) by a corner section (38), and wherein the first side edge section (46) is selectively formed on a linear section (36) which is one of the first linear section (36) and of the second linear section (37). Semiconductor device (1) according to claim 4, wherein the front end section (39) of the first electrically conductive element (25) has a first side surface (52) which in a top view is formed by a first circular arc (51) with a first radius of curvature (R1), and wherein the first side edge section (46) of the first electrically conductive element (25) has a second side surface (54) which in a top view is formed by a second circular arc (53) with a second radius of curvature (R2) which is smaller than the first radius of curvature (R1). Semiconductor device (1) according to claim 2, wherein the organic insulating layer (55) has a pad opening (56) that exposes the base section (40) of the first linear section (36) as a pad (14). Semiconductor device (1) according to claim 2, further comprising a second electrically conductive element (59) connected to the base section (40) of the first linear section (36) in the organic insulating layer (55). Semiconductor device (1) according to claim 7, wherein the second electrically conductive element (59) has a third linear section (72) extending along the main surface (11) of the semiconductor substrate (4, 15), and wherein the third linear section (72) includes a second side edge section (79) formed by a curve (80) that is alternately curved to one side and to the opposite side in a direction (Y2) which, in a top view, intersects a longitudinal direction (X2) of the third linear section (72). Semiconductor device (1) according to claim 8, wherein the second electrically conductive element (59) includes a second base layer (60) and a second cover layer (61) stacked on the second base layer (60) such that it projects laterally from an end face (63) of the second base layer (60) in a cross-sectional view, and wherein the second side edge section (79) is selectively formed on the second cover layer (61). Semiconductor device (1) according to one of claims 1 to 9, comprising an insulating layer layer structure (17) formed between the first electrically conductive element (25) and the semiconductor substrate (4, 15) and including at least a first inorganic insulating layer (18, 57) and a second inorganic insulating layer (19, 58) stacked on the first inorganic insulating layer (18, 57). Semiconductor device (1) according to one of claims 1 to 10, comprising an integrated circuit element (16) formed on the semiconductor substrate (4, 15) and electrically connected to the first electrically conductive element (25).

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