COMPOUND SEMUBTRACTOR SUBSTRATE

Abstract

This compound semiconductor substrate has a base layer with a lattice constant in the plane of a, a voltage relaxation layer which relaxes a voltage received from the base layer, and a functional layer with a lattice constant in the plane of b (a ≠ b), wherein the base layer, the voltage relaxation layer and the functional layer are arranged in the order of base layer, voltage relaxation layer and functional layer in the functional layer in a region where a lattice is relaxed by a crystal lattice of the base layer dominates and the threading offset density of the functional layer is less than 2.0 × 10 9 cm -2.

Description

Compound semiconductor substrate

[0001] The present invention relates to a compound semiconductor substrate. This application claims priority to Japanese Patent Application No. 2021-212419, filed on December 27, 2021, the contents of which are incorporated herein by reference.

[0002] Numerous optoelectronic devices (compound semiconductor devices) using compound semiconductors, such as light-emitting diodes (LEDs), semiconductor lasers (LDs, VCSELs), and field-effect transistors (FETs), have been put to practical use. To fabricate compound semiconductor devices tailored to specific applications, crystal growth is required, in which a material identical to or different from the substrate is layered on the substrate. Crystal growth of different materials is called heteroepitaxial growth, and compressive or tensile strain is introduced in the plane due to differences in in-plane lattice constants and thermal expansion coefficients. For example, the in-plane lattice constant of the c-plane of GaN is approximately 2.4% larger than that of AlN, so when GaN is epitaxially grown on an AlN substrate, the GaN epitaxial layer is subjected to compressive strain within the substrate plane. Increasing the thickness of the epitaxial layer required for a semiconductor device accumulates strain energy in the epitaxial layer, ultimately causing lattice relaxation to relieve the strain energy, resulting in the introduction of misfit dislocations and surface roughness.

[0003] By controlling the Al / Ga composition ratio, the band gap of AlGaN compound semiconductors can be varied from 3.4 eV to 6.2 eV, which corresponds to an emission wavelength of 360 nm to 200 nm. For example, as shown in Non-Patent Document 1, deep-ultraviolet LEDs using AlGaN with an Al composition ratio of approximately 0.7 to 0.5 cover an emission wavelength range of 300 nm to 250 nm. Because the above-mentioned deep-ultraviolet LEDs have a wide range of applications, such as the sterilization effect of bacteria and viruses, technical studies are currently being conducted to improve their performance. In particular, the effect of dislocation density present in the crystal of the AlGaN functional layer on the luminous efficiency of LEDs is being studied.

[0004] For example, Non-Patent Document 2 describes an AlN freestanding substrate and an AlN freestanding substrate having a repetition period of 10. ｘ Ga １－ｘ N / Al ｙ Ga １－ｙ The document discloses the crystallographic characteristics of a semiconductor substrate comprising a superlattice structure made of N, an AlGaN functional layer (Al = 0.5) on the superlattice layer, an active layer formed on the functional layer, and a contact layer formed on the active layer. It has been found that there is a linear relationship between the lattice relaxation rate of the AlGaN functional layer (Al = 0.5) relative to the AlN freestanding substrate and the half-width of the X-ray rocking curve at the asymmetric plane (102) of the AlGaN functional layer, with the half-width increasing from 180 to 420 arcsec as the lattice relaxation rate increases from 0% to 70%, and the half-width increasing to 720 arcsec at 100%, and an LED formed on the AlGaN functional layer emits light at 300 nm.

[0005] For example, Non-Patent Document 3 discloses the structure and crystalline characteristics of a semiconductor substrate comprising an AlN freestanding substrate, a 400 nm AlN underlayer formed on the AlN freestanding substrate, a 50 nm graded layer formed on the underlayer in which the Al composition ratio is linearly changed from 0, and an n-type AlGaN functional layer (Al = 0.45 to 0.75) having a thickness of 0.5 to 1.3 μm formed on the graded layer. The X-ray rocking curve half-widths of the symmetric plane (002) and asymmetric plane (102) of the AlGaN functional layer are in a pseudomorphic state in which the in-plane lattice constants of the functional layer and the underlayer match, with the (002) half-width ranging from 64 to 81 arcsec and the (102) half-width ranging from 84 to 104 arcsec. When the Al composition of the functional layer is low or when the thickness of the functional layer is thick, the in-plane lattice constant of the functional layer does not match the in-plane lattice constant of the AlN underlayer, causing lattice relaxation, resulting in a significant deterioration in the X-ray rocking curve half-width of the symmetric plane (002) to 239 arcsec and the X-ray rocking curve half-width of the asymmetric plane (102) to 302 arcsec.Furthermore, it was found that the functional layer with an Al composition ratio of 0.6 and a thickness of 0.5 μm, in which lattice relaxation occurred, showed significant surface roughness.

[0006] Instead of AlN freestanding substrates, AlGaN deep-ultraviolet LEDs on sapphire substrates have been reported. Sapphire substrates are relatively inexpensive, and large-diameter substrates are available, so mass production is expected. However, since the in-plane lattice constant difference between the sapphire substrate and the AlGaN functional layer is 13% to 16%, if the AlGaN functional layer is grown directly on the sapphire substrate, the dislocation density will be 10 １０ cm －２ Therefore, an AlN underlayer is first formed on the sapphire substrate. However, the dislocation density in the AlN underlayer is 10 ８ ~10 ９ cm －２ This is about three orders of magnitude higher than the AlN freestanding substrate, which has a significant impact on the light-emitting efficiency of deep-ultraviolet LEDs. In other words, it is even more important to improve the quality of the AlGaN functional layer formed on the AlN underlayer.

[0007] For example, Non-Patent Document 4 discloses the structure and crystalline characteristics of a semiconductor substrate comprising a sapphire substrate, an AlN underlayer in contact with the sapphire substrate, a superlattice layer made of AlN / AlGaN selectively formed on a portion of the underlayer, an n-type AlGaN functional layer (Al composition ratio = 0.55) formed on the superlattice layer, an active layer formed on the functional layer, and a contact layer formed on the active layer. Non-Patent Document 4 acknowledges that the LED emits light at a wavelength of 290 nm. However, there is no description of the thickness of the superlattice structure, the Al composition ratio of the AlGaN, its structure, or in-plane strain.

[0008] For example, Non-Patent Document 5 discloses the structure and crystalline characteristics of a semiconductor substrate consisting of a sapphire substrate, a 900 nm AlN underlayer formed on the sapphire substrate, an n-type AlGaN functional layer formed on the underlayer, and an active layer formed on the functional layer. X-ray reciprocal lattice mapping from the diffraction plane (114) reveals that the functional layer, with an Al composition ratio of 0.57 and a thickness of 27 nm, is in a pseudomorphic state with respect to the underlayer, while the functional layer, with an Al composition ratio of 0.47 and a thickness of 350 nm, is in a partially relaxed state with respect to the underlayer, with a lattice relaxation rate of 55%, and a photoluminescence spectrum (photoluminescence) at room temperature having a peak at 289 nm. Furthermore, it has been observed that the dislocation density estimated from the X-ray rocking curve shows a very slight improvement when the state changes from pseudomorphic to partially relaxed. For example, the screw dislocation density is 6.7 × 10 ９ cm －２ From 5.6 x 10 ９ cm －２ The edge dislocation density was reduced to 1.6 × 10 ９ cm －２ From 1.5 x 10 ９ cm －２ It can be seen that the number of cases has decreased.

[0009] For example, Non-Patent Document 6 discloses the crystalline characteristics of a semiconductor substrate consisting of a sapphire substrate, an AlN underlayer in contact with the sapphire substrate, a superlattice layer formed on the underlayer and made of AlN (2.5 nm thick) / GaN (1.0 to 2.5 nm thick), an n-type AlGaN functional layer formed on the superlattice layer, an active layer formed on the functional layer, and a contact layer formed on the active layer. Non-Patent Document 6 reveals that, by X-ray reciprocal lattice mapping from the diffraction plane (105), the functional layer is in a partially relaxed (metamorphic) state with respect to the underlayer, an LED formed on the superlattice structure emits light at a wavelength of 310 nm, and the roughness of the semiconductor substrate surface is very noticeable.

[0010] For example, Non-Patent Document 7 discloses a method for fabricating a sapphire substrate, an AlN underlayer in contact with the sapphire substrate, and an AlN underlayer having a repetition period of 30 to 70 and a thickness of 14 to 7 nm formed on the underlayer. ０．３７ Ga ０．６３ N / Al ０．２７ Ga ０．７３ The document discloses the structure and crystalline characteristics of a semiconductor substrate comprising a superlattice layer made of N, an n-type AlGaN functional layer formed on the superlattice, an active layer formed on the functional layer, and a contact layer formed on the active layer. The document also reveals that the total thickness of the superlattice structure is 430 nm, the lattice relaxation rate of the functional layer relative to the underlayer is 87%, the X-ray rocking curve half-width of the diffraction plane (102) of the functional layer is 793 arcsec, and the LED emits light at a wavelength of 341 nm.

[0011] For example, Non-Patent Document 8 discloses the structure and crystalline characteristics of a semiconductor substrate comprising a sapphire substrate, an AlN underlayer in contact with the sapphire substrate, a first layer formed on the underlayer and made of AlGaN with an Al composition ratio of 0.6, a second layer formed on the first layer and made of AlGaN with an Al composition ratio of 0.6 or less, the Al composition ratio gradually decreasing with increasing distance from the substrate, an n-type AlGaN functional layer formed on the second layer, an active layer formed on the functional layer, and a contact layer formed on the active layer. The lattice relaxation rate of the functional layer relative to the underlayer is 30% at most, and the dislocation density is 1×10 ９ cm －２and it is recognized in Non-Patent Document 8 that the LED emits light at wavelengths from 316 nm to 295 nm.

[0012] For example, Patent Document 1 discloses a nitride semiconductor device including a substrate, an AlN strain buffer layer made of AlN formed on the substrate, a superlattice strain buffer layer formed on the AlN strain buffer layer, and a nitride semiconductor layer formed on the superlattice strain buffer layer, wherein the superlattice strain buffer layer is made of Al ｘ Ga １－ｘ Patent Document 1 discloses a nitride semiconductor device characterized by having a superlattice structure formed by alternately stacking a first layer made of GaN (0≦x≦0.25) and containing Mg and a second layer made of AlN that intentionally does not contain Mg. Patent Document 1 describes that in order to form a superlattice strain buffer layer on a substrate with good flatness, which combines GaN or AlGaN with a low Al content with AlN, the thickness of the superlattice strain buffer layer is made as thin as possible and Mg is added to promote lateral crystal growth of AlGaN or GaN, thereby improving the crystallinity of the nitride semiconductor layer stacked on the superlattice strain buffer layer.

[0013] For example, Patent Document 2 discloses a method for fabricating a template substrate by forming an AlN underlayer having a substantially atomically flat surface on the substrate, and forming an AlGaN functional layer on the AlN underlayer, wherein the AlGaN functional layer is grown at a temperature higher than 1000° C. and lower than 1100° C. ｘ Ga １－ｘ A first unit layer represented by a composition formula of N (0.5<x≦1) and Al ｙ Ga １－ｙ Patent Document 2 discloses a method for forming the AlGaN layer so as to have a superlattice structure in which second unit layers expressed by a composition formula of N (0.5≦y<1 and y<x) are alternately and repeatedly stacked. Patent Document 2 describes that the superlattice structure is preferably formed to a thickness within a range in which lattice relaxation does not occur, that is, an AlGaN layer is formed while coherently growing first unit layers and second unit layers, and an AlGaN layer having an in-plane lattice constant substantially the same as that of the surface layer and a surface that is substantially flat at the atomic level can be obtained.

[0014] For example, Patent Document 3 discloses a deep-ultraviolet light-emitting device structure of a group III nitride semiconductor having an emission wavelength of 220 to 280 nm, the deep-ultraviolet light-emitting device comprising an AlGaN / GaN short-period superlattice layer composed of an AlGaN barrier layer and a GaN well layer, and an n-type AlGaN functional layer and a p-type AlGaN contact layer arranged to sandwich the AlGaN / GaN short-period superlattice layer from above and below, wherein the Al composition of the AlGaN barrier layer, the Al composition of the n-type AlGaN layer, and the Al composition of the p-type AlGaN layer are 70% or more, and the thickness of the GaN well layer is 0.75 nm or less. Patent Document 3 describes that the high luminous efficiency can be achieved because the AlGaN / GaN short-period superlattice layer grows coherently epitaxially, no defects such as misfit dislocations occur, and large compressive strain is inherent in the GaN layer.

[0015] For example, Patent Document 4 discloses a method for producing an efficient ultraviolet LED, which includes a substrate or a template, an AlN or AlGaN functional layer epitaxially formed on the substrate or the template, the AlN or AlGaN functional layer having a calculated in-plane compressive strain of 1% or more applied to the AlN or AlGaN functional layer by the substrate or the template, and a highly doped epitaxial AlN or AlGaN intermediate layer inserted between the epitaxial AlN or AlGaN functional layer and the substrate or the template, the highly doped epitaxial AlN or AlGaN intermediate layer having a thickness of 40 to 400 nm and a density of 5×10 １９ ~5 x 10 ２０ cm －３ Heteroepitaxy strain management structures are disclosed that are doped in the range of

[0016] Patent No. 4681684 Patent No. 5274785 Patent No. 5400001 Patent No. 6353133

[0017] Y. Nagasawa and A. Hirano, Appl. Sci., 8, 1264 (2018).Z. Ren et al., Applied Physics Letters 91, 051116 (2007).JR Grandusky et al., Journal of Crystal Growth 311, 2864 (2009).V. ADIVARAHAN et al., Jpn. J. Appl. Phys., 46, L877 (2007).X. Li et al., Optical Materials Express, 5, 380 (2015)J. Enslin et al., Journal of Crystal Growth 464, 185 (2017).T. Matsumoto et al., J. Phys. et al., J. Mater. Chem. C, 7, 143, (2019).MA Moram, et al., Rep. Prog. Phys. 72, 036502 (2009).

[0018] For example, the luminous efficiency (external quantum efficiency) of conventional UV LEDs using AlGaN is less than 10%. The external quantum efficiency is determined by the product of the luminous efficiency (internal quantum efficiency) in the functional layers constituting the LED, the electron / hole injection efficiency, and the light extraction efficiency, and the dislocation density present in the crystal affects any or all of these. In particular, ９ cm －２ It is known that when a dislocation density exceeding 1000 kJ / cm is present, the internal quantum efficiency is 40% or less. Therefore, to realize a high-efficiency LED, it is necessary to improve the internal quantum efficiency, electron / hole injection efficiency, and light extraction efficiency. This requires a reduction in the dislocation density. Furthermore, in the case of an FET using AlGaN, for example, the interface between the functional layer and the active layer must be flat at the atomic level.

[0019] To improve the device characteristics of devices such as LEDs and FETs, it is important that the functional layer has a thickness of about 2000 to 4000 nm. However, as described in Non-Patent Documents 2 to 8, in the case of non-coherent growth in which the in-plane lattice constants of Group III semiconductor crystals are not lattice-matched, if the functional layer is to have a thickness of this magnitude, misfit dislocations will occur due to lattice relaxation, and the dislocation density of the semiconductor crystal will exceed 2×10 ９ cm －２ Furthermore, lattice relaxation significantly deteriorates the surface flatness of the semiconductor crystal, making it more difficult to ensure in-plane uniformity in crystal quality and sheet resistance, particularly when using a large substrate such as a 6-inch substrate.

[0020] Patent Documents 1 to 3 state that it is ideal to achieve a pseudomorphic state in which the in-plane lattice constants of the substrate and the group III semiconductor crystal match, resulting in coherent growth, and that the structure is designed to intentionally avoid incoherent growth in which the in-plane lattice constants do not match.

[0021] Patent Document 4 describes a structure in which a highly doped intermediate layer is used for strain management, resulting in an in-plane compressive strain of 1% or more. However, it does not disclose whether doping improves the surface condition of the semiconductor substrate or the dislocation density of the functional layer. Furthermore, when the purpose is a device such as a FET, the doped intermediate layer can be a source of leakage current, drift current, etc., so its application is limited to only specific applications.

[0022] The object of the present invention is to provide a compound semiconductor substrate in which a functional layer has a dominant region that is lattice-relaxed from the crystal lattice of the underlying layer, has a good surface condition, and simultaneously has a low dislocation density, thereby satisfying the characteristics required for devices such as efficiency and ensuring in-plane uniformity of physical properties such as sheet resistance. Note that, as will be described in detail later, the underlying layer here refers to a substrate underlying layer or an intermediate layer disposed on the surface of the substrate or underlying layer.

[0023] In order to solve the above problems, a first aspect of the present invention provides a semiconductor device comprising an underlayer having an in-plane lattice constant of a, a stress relaxation layer that relaxes strain received from the underlayer, and a functional layer having an in-plane lattice constant of b (a≠b), wherein the underlayer, the stress relaxation layer, and the functional layer are arranged in this order, a region of the functional layer that is lattice-relaxed from the crystal lattice of the underlayer is dominant, and a dislocation density of the functional layer is 2.0 × 10 ９ cm －２ A compound semiconductor substrate is provided, wherein the compound semiconductor substrate is less than

[0024] The underlayer may be perfectly lattice-matched to the substrate, pseudomorphic, partially relaxed, or completely relaxed, and may be a flat substrate covering the entire surface or a patterned substrate with a partially processed surface.

[0025] The stress relaxation layer may be formed so that a portion that is incoherent with the underlayer is dominant, and the in-plane lattice constant may be c that satisfies (a+c-2xb) / (2xb)≦±0.5%.

[0026] The lattice relaxation rate of the functional layer relative to the underlayer is preferably in the range of 60% or more, more preferably in the range of 75% or more, and particularly preferably in the range of 90% or more.

[0027] The dislocation density of the functional layer is 1.5×10 ９ cm －２ Preferably, it is 1.3 × 10 or less. ９ cm －２ It is more preferable that the dislocation density of the functional layer is smaller, so there is no particular lower limit. The dislocation density of the functional layer is, for example, 1.0 × 10 ２ cm －２ or more, or 1.0 x 10 ３ cm －２ It can be more than that.

[0028] The semiconductor crystal layer may further include an intermediate layer located between the underlayer and the stress relaxation layer and in contact with the underlayer. The semiconductor crystal layer may have a thickness of 1000 nm or more and 16000 nm or less.

[0029] The thickness of the substrate may be 200 μm or more, the diameter of the substrate may be 25 mm or more, the thickness of the underlayer may be 50 nm or more and 5000 nm or less, and the surface of the functional layer may be a mirror finish.

[0030] In a second aspect of the present invention, a semiconductor device includes an underlayer having an in-plane lattice constant of a, a stress relaxation layer that relaxes strain received from the underlayer, and a functional layer having an in-plane lattice constant of b (a≠b), wherein the underlayer, the stress relaxation layer, and the functional layer are arranged in this order, a region of the functional layer that is lattice-relaxed from the crystal lattice of the underlayer is dominant, and the dislocation density of the functional layer is 2.0 × 10 ９ cm －２ The present invention provides a method for inspecting a compound semiconductor substrate, the method determining that the substrate is acceptable if the lattice relaxation rate of the functional layer relative to the underlayer measured by X-ray reciprocal lattice mapping on an asymmetric plane of the semiconductor crystal layer is 60% or more and the full width at half maximum of the X-ray rocking curve on a diffraction plane (102) of the functional layer is less than 550 arcsec. Here, the asymmetric plane, for example, in the case of a diffraction plane (-1-14), is an X-ray diffraction plane expressed in Miller indices, where h = -1, k = -1, and l = 4 in the plane (hkl) notation according to Miller indices. The index -1 may also be expressed as a symbol (bar 1) with a horizontal line drawn through it.

[0031] In a third aspect of the present invention, there is provided a compound semiconductor substrate comprising: an underlayer having an in-plane lattice constant a; a stress relief layer that relieves strain from the underlayer; and a functional layer having an in-plane lattice constant b (a≠b), wherein the underlayer, stress relief layer, and functional layer are arranged in this order: underlayer, stress relief layer, functional layer; and the stress relief layer comprises: a first crystal layer located in contact with the underlayer and having an in-plane lattice constant c1 between a and b; and a second crystal layer located in contact with the functional layer side of the first crystal layer and having an in-plane lattice constant c2 that satisfies (c1 + c2 - 2 × b) / (2 × b) ≦ ±0.5%. The compound semiconductor substrate may further comprise additional components, as in the first aspect. Note that in the third aspect, b in the formula represents the in-plane lattice constant of the functional layer.

[0032] The thickness of the first crystal layer is preferably 6 nm to 125 nm, more preferably 10 nm to 100 nm, and particularly preferably 20 nm to 75 nm. If the thickness is 6 nm to 125 nm, the surface condition is further improved.

[0033] The thickness of the second crystal layer is preferably 6 nm to 125 nm, more preferably 10 nm to 100 nm, and particularly preferably 20 nm to 75 nm. If the thickness is 6 nm to 125 nm, the surface condition is further improved.

[0034] It is preferable that the stress relaxation layer has a laminate structure consisting of the first crystal layer and the second crystal layer repeated two or more times, and that the thickness of the stress relaxation layer is 500 nm or more and 10,000 nm or less.

[0035] In the stress relaxation layer, the chemical composition of the first crystal layer is Al ｘ Ga １－ｘ N (0<x≦1.0), and the chemical composition of the second crystal layer is Al ｙ Ga １－ｙ N (0≦y<1.0), and y<x may be satisfied.

[0036] The stress relaxation layer may have a plurality of stacked structures each consisting of the first crystal layer and the second crystal layer. The stress relaxation layer may further include a third crystal layer located in contact with the functional layer side of the second crystal layer, and having an in-plane lattice constant c3 that satisfies (c1 + c2 + c3 - 3 × b) / (3 × b) ≦ ±0.5%. The stress relaxation layer may further include an nth crystal layer located in contact with the functional layer side of an nth crystal layer located closer to the functional layer than the third crystal layer, and having an in-plane lattice constant cn that satisfies {c1 + c2 + ... + c(n-1) + cn - n × b} / (n × b) ≦ ±0.5%. Here, n in the formula is an integer of 4 or greater.

[0037] In a fourth aspect of the present invention, there is provided an optical waveguide device comprising an underlayer having an in-plane lattice constant of a, a stress relaxation layer for relieving strain received from the underlayer, a functional layer having an in-plane lattice constant of b (a≠b), and an active layer having an in-plane lattice constant that pseudomorphically matches the in-plane lattice constant b of the functional layer, wherein the underlayer, stress relaxation layer, functional layer, and active layer are arranged in this order, a region of the functional layer that is lattice-relaxed from the crystal lattice of the underlayer is dominant, and the dislocation density of the functional layer is 2.0×10 ９ cm －２ The compound semiconductor substrate may further include an additional component, as in the third aspect.

[0038] The stress relaxation layer may reflect 50% or more of the light generated from the active layer.

[0039] In a fifth aspect of the present invention, a semiconductor device includes an underlayer having an in-plane lattice constant of a, a stress relaxation layer that relaxes strain received from the underlayer, a functional layer having an in-plane lattice constant of b (a≠b), an active layer whose in-plane lattice constant is pseudomorphic to the in-plane lattice constant b of the functional layer, and a contact layer, wherein the underlayer, stress relaxation layer, functional layer, active layer, and contact layer are arranged in this order from the substrate side, the underlayer, stress relaxation layer, functional layer, active layer, and contact layer, a region of the functional layer that is lattice-relaxed from the crystal lattice of the underlayer is dominant, and the dislocation density of the functional layer is 2.0 × 10 ９cm －２ The compound semiconductor substrate may further include an additional component, as in the third aspect.

[0040] The contact layer may have a larger bandgap than the active layer.

[0041] A compound semiconductor substrate may include a substrate and a semiconductor crystal layer on the substrate. The semiconductor crystal layer may include at least any layer selected from an underlayer having an in-plane lattice constant of a, a stress relaxation layer that relieves strain from the underlayer, and a functional layer having an in-plane lattice constant of b (a≠b). In one example, the semiconductor crystal layer may include all of the underlayer, the stress relaxation layer, and the functional layer. In another example, the semiconductor crystal layer may include the stress relaxation layer and the functional layer. However, in this case, the substrate is considered to be the underlayer in terms of the positional relationship of each layer. Therefore, if the semiconductor crystal layer does not include an underlayer, the substrate may be considered to be the underlayer in this invention, and the in-plane lattice constant of the substrate may be considered to be a. In yet another example, the semiconductor crystal layer may include the underlayer and the stress relaxation layer.

[0042] The underlayer, the stress relaxation layer, and the functional layer may be arranged in this order: underlayer, stress relaxation layer, functional layer. The stress relaxation layer may include at least one of a first crystal layer located in contact with the underlayer and having an in-plane lattice constant c1 between a and b, and a second crystal layer located in contact with the functional layer side of the first crystal layer and having an in-plane lattice constant c2 that satisfies (c1 + c2 - 2 × b) / (2 × b) ≦ ±0.5%. In one example, the stress relaxation layer may include both the first crystal layer and the second crystal layer.

[0043] The thickness of the first crystal layer may be 6 nm or more and 125 nm or less. The thickness of the second crystal layer may be 6 nm or more and 125 nm or less. The stress relaxation layer may have two or more repeated cycles of stacked layers made of the first crystal layer and the second crystal layer. The thickness of the stress relaxation layer may be 500 nm or more and 10,000 nm or less. The first crystal layer may be Al ｘ Ga １－ｘN (0<x≦1.0), the second crystal layer is AlGa １－ｙ N (0.1≦y≦1.0), (where y<x). The stress relaxation layer may be located in contact with the functional layer side of the second crystal layer, and may include a third crystal layer having an in-plane lattice constant c3 that satisfies (c1 + c2 + c3 - 3×b) / (3×b)≦±0.5%. The stress relaxation layer may be located in contact with the functional layer side of an nth crystal layer located closer to the functional layer than the third crystal layer, and may include an nth crystal layer having an in-plane lattice constant cn that satisfies {c1 + c2 + ... + c(n-1) + cn - n×b} / (n×b)≦±0.5%. Here, n is an integer of 4 or greater.

[0044] The functional layer may have a lattice relaxation rate of 60% or more relative to the underlayer. The dislocation density of the functional layer may be 2.0×10 ９ cm －２ The semiconductor crystal layer may have a thickness of less than 1000 nm. The semiconductor crystal layer may have an intermediate layer located between the underlayer and the stress relaxation layer in contact with the underlayer, the intermediate layer having an in-plane lattice constant different from that of the underlayer. The semiconductor crystal layer may have an active layer located on the functional layer, the active layer having an in-plane lattice constant b that is pseudomorphic to the in-plane lattice constant b of the functional layer. The stress relaxation layer may reflect 50% or more of the light generated from the active layer. The semiconductor crystal layer may have a thickness of 1000 nm or more and 16000 nm or less. The underlayer may have a thickness of 50 nm or more and 5000 nm or less. The substrate may have a thickness of 200 μm or more. The substrate may have a diameter of 25 mm or more. The surface of the functional layer may be a mirror finish.

[0045] In the above-described compound semiconductor substrate inspection method, the substrate may be determined to be acceptable if, in addition to the lattice relaxation rate of the functional layer relative to the underlayer determined by X-ray reciprocal lattice mapping of the semiconductor crystal layer being 60% or more, the full width at half maximum of the X-ray rocking curve on the diffraction plane (102) of the functional layer is less than 550 arcsec.

[0046] According to the above-described aspect of the present invention, in the functional layer, the region that is lattice-relaxed from the crystal lattice of the lower layer is dominant, the surface condition is good, and a low dislocation density is simultaneously achieved, thereby satisfying the characteristics required for the device, such as efficiency, and ensuring in-plane uniformity of physical properties such as sheet resistance.

[0047] 1 is a cross-sectional view of a compound semiconductor substrate 100 according to a first embodiment of the present invention. 2 is a cross-sectional view showing a modified example of the compound semiconductor substrate 100 according to the first embodiment. 3 is a cross-sectional view showing a modified example of the compound semiconductor substrate 100 according to the first embodiment. 4 is a cross-sectional view showing a modified example of the compound semiconductor substrate 100 according to the first embodiment. 5 is a cross-sectional view of a compound semiconductor substrate 200 according to a second embodiment of the present invention. 6 is a cross-sectional view of a compound semiconductor substrate 300 according to a third embodiment of the present invention. 7 is a cross-sectional view of a compound semiconductor substrate 400 according to a fourth embodiment of the present invention. 8 is an X-ray reciprocal lattice mapping image of the diffraction plane (-1-14), which is an asymmetric plane, of Experimental Example 4. 9 is an atomic force microscope image obtained by scanning the surface of Experimental Example 4 within a 20 μm square field of view. 10 is a graph plotting X-ray rocking curves of the diffraction planes (002) and (102) of the functional layer 108 of Experimental Example 4. 11 is a graph plotting the lattice relaxation rates of Experimental Examples 1 to 5, 12, and 13. 12 is a graph plotting the surface roughness of Experimental Examples 1 to 5, 12, and 13. 1 is a graph plotting the dislocation densities of Experimental Examples 1 to 5, 12, and 13. FIG. 1 is a graph plotting the lattice relaxation rates of Experimental Examples 3 and 6 to 10. FIG. 1 is a graph plotting the surface roughness of Experimental Examples 3 and 6 to 10. FIG. 1 is a graph plotting the dislocation densities of Experimental Examples 3 and 6 to 10. FIG. 1 is an X-ray reciprocal lattice mapping image of the diffraction plane (-1-14), which is the asymmetric surface of Experimental Example 11. FIG. 1 is an atomic force microscope image obtained by scanning the surface of Experimental Example 11 within a 20 μm square field of view. FIG. 1 is a graph plotting X-ray rocking curves of the diffraction plane (002) and the diffraction plane (102) of the functional layer 108 of Experimental Example 11. FIG. 1 is a graph plotting the lattice relaxation rates of Experimental Examples 19 to 26. FIG. 1 is a graph plotting the surface roughness of Experimental Examples 19 to 26. FIG. 1 is a graph plotting the dislocation densities of Experimental Examples 19 to 26. FIG. 1 is a graph plotting the PL intensities of Experimental Examples 19 to 26. 1 is a graph plotting the in-plane distribution of sheet resistance for Experimental Examples 19 to 26. FIG. 2 is a graph plotting the reflectance spectrum for Experimental Example 29. FIG. 3 is a graph plotting the reflectance for Experimental Examples 27 to 30. FIG. 4 is a graph plotting the X-ray diffraction pattern for Experimental Example 31.

[0048] (Embodiment 1) FIG. 1 is a cross-sectional view of a compound semiconductor substrate 100 according to a first embodiment of the present invention. The compound semiconductor substrate 100 includes a substrate 102 and a semiconductor crystal layer on the substrate 102. The substrate 102 is a support substrate that supports the semiconductor crystal layer. The substrate 102 may be made of sapphire, silicon, gallium arsenide, gallium antimony, indium arsenide, gallium oxide, silicon carbide, gallium nitride, or aluminum nitride. By using a large substrate with a diameter of, for example, 150 mm as the substrate 102, material costs can be reduced, resulting in lower costs and increased industrial cost competitiveness. Therefore, the diameter of the substrate 102 is preferably 150 mm or greater.

[0049] The semiconductor crystal layer has an underlayer 104, a stress relaxation layer 106, and a functional layer 108, and the underlayer 104, the stress relaxation layer 106, and the functional layer 108 are arranged in this order from the substrate 102 side: underlayer 104, stress relaxation layer 106, functional layer 108.

[0050] The underlayer 104 has an in-plane lattice constant of a, and the chemical composition of the underlayer 104 is, for example, Al ｘ１ Ga １－ｘ１ GaN (0.8≦x1≦1.0), and a typical example is AlN (x1=1). The underlayer 104 allows an initial nucleus to be formed on the substrate 102, thereby improving the flatness of the semiconductor crystal layer.

[0051] In the compound semiconductor substrate 100 according to this embodiment, the first semiconductor layer of the semiconductor crystal layer on the substrate 102 is the base layer 104, and the crystalline properties of this base layer 104 have a significant effect on the crystalline properties of the semiconductor crystal layer grown thereon.

[0052] The stress relaxation layer 106 is made of, for example, Al ｘ３ Ga １－ｘ３N, and the Al composition ratio x3 may be determined so that the in-plane lattice constant c of the stress relaxation layer 106 satisfies (a + c - 2 × b) / (2 × b) ≦ ±0.5%. The stress relaxation layer 106 is formed so that the incoherent portion with the underlayer 104 is dominant, and serves to relieve strain received from the underlayer 104, thereby improving the crystallinity of the functional layer 108, which is a nitride semiconductor layer formed on the stress relaxation layer 106, and improving the electrical, optical, mechanical, and chemical properties of the functional layer 108. In other words, the dislocation density of the stress-relaxed functional layer 108 is reduced, thereby improving the crystal quality.

[0053] Generally, to improve the crystal quality of a nitride semiconductor layer, the nitride semiconductor layer is formed so that the heterojunction surface is coherent with the underlying crystal lattice. However, when the underlying layer 104 and the stress relaxation layer 106 are formed so that incoherent regions are dominant, as in the present invention, the in-plane lattice constants of the crystals are different from each other. As the thickness increases, stress strain accumulates within the film. When the growth thickness exceeds a critical thickness, numerous defects occur due to strain relaxation. Continuing growth after the occurrence of numerous defects results in three-dimensional growth, which may ultimately result in a cloudy compound semiconductor substrate rather than a mirror-like surface. In this case, the crystal quality of the functional layer 108 formed on the stress relaxation layer 106 is significantly impaired.

[0054] As a result of investigations by the present inventors, it was found that even if misfit dislocations are generated by an interface formed incoherently, it is possible to obtain a low dislocation density and sufficient crystal quality depending on the conditions for forming the stress relaxation layer 106. Although the details of this mechanism are unknown, the present inventors speculate that this is because dislocations do not propagate to the functional layer 108 formed above the stress relaxation layer 106 due to annihilation of dislocation pairs within the stress relaxation layer 106.

[0055] It is known that lattice relaxation varies depending on the stacking structure (lattice constant difference, thickness) and crystal quality (dislocation density) of the semiconductor crystal layer, or the growth conditions. However, according to this embodiment, it is possible to control the lattice relaxation rate by forming the stress relaxation layer 106 described above.

[0056] By sufficiently alleviating stress with the stress relaxation layer 106, the lattice relaxation rate of the functional layer 108 relative to the underlayer 104 is high, and excellent surface flatness and a low dislocation density can be achieved. Furthermore, by alleviating stress throughout the wafer, it is possible to reduce in-plane variations in physical properties such as sheet resistance. In other words, it is possible to improve the uniformity of the semiconductor crystal layer formed on the substrate 102.

[0057] The functional layer 108 is made of, for example, Al ｘ４ Ga １－ｘ４ N (0≦x4<1), typically satisfying (0.3≦x4≦0.7). The functional layer 108 is a layer on which an optoelectronic device will later be formed. The functional layer 108 is dominated by a region that is lattice-relaxed from the crystal lattice of the underlayer 104. For example, in the functional layer 108, it is preferable that the lattice relaxation rate of the functional layer 108 relative to the underlayer 104 be 60% or more as determined by X-ray reciprocal lattice mapping in an asymmetric diffraction plane. The functional layer 108 can be divided into two or more layers depending on its purpose. For example, if the functional layer 108 is an n-type carrier injection layer to control electrical conduction, the side of the functional layer 108 in contact with the stress relaxation layer 106 can be made a layer with increased flatness to reduce carrier scattering, and the upper layer can be made an electrical conductive layer with a minimum concentration of impurities such as carbon that provide n-type carrier compensation, thereby reducing the sheet resistance of the entire device. Alternatively, in order to use the functional layer 108 as an electron transport layer, the side of the functional layer 108 in contact with the stress relaxation layer 106 can be made a high-resistance layer with increased voltage resistance, and the layer above that can be made a high-purity layer with an impurity concentration as low as possible, thereby reducing carrier scattering and increasing electron mobility.

[0058] The thickness of the semiconductor crystal layer, in other words, the total thickness of the underlayer 104, the stress relief layer 106, and the functional layer 108, is preferably 500 nm or more and 16,000 nm or less. By setting the thickness of the semiconductor crystal layer within this range, the amount of warping of the compound semiconductor substrate 100 can be reduced. When the thickness of the substrate 102 is 200 μm or more and the diameter of the substrate 102 is 25 mm or more, the thickness of the underlayer 104 is preferably 50 nm or more and 5,000 nm or less. By setting the thickness of the substrate 102 and the underlayer 104 within this range, the amount of warping of the compound semiconductor substrate 100 can be reduced. The thickness of the functional layer 108 is more preferably 2,000 nm or more and 4,000 nm or less. Setting the thickness of the functional layer 108 within this range can further improve device characteristics. Note that when the semiconductor crystal layer does not have the underlayer 104, the thickness of the semiconductor crystal layer is the total thickness of the stress relief layer 106 and the functional layer 108.

[0059] When the temperatures of the semiconductor crystal layer and the substrate 102 drop from the high temperature during epitaxial growth to room temperature due to the difference in thermal expansion coefficient between them and the substrate 102, the semiconductor crystal layer generates stress relative to the substrate 102. However, in the compound semiconductor substrate 100 of this embodiment, the stress is relieved by the stress relief layer 106, so that warping of the compound semiconductor substrate 100 can be suppressed.

[0060] Any layer may be disposed at least in any of the following positions: between the underlayer 104 and the stress relief layer 106, between the stress relief layer 106 and the functional layer 108, and on top of the functional layer 108. For example, as shown in FIG. 2 , an intermediate layer 110 may be formed between the underlayer 104 and the stress relief layer 106. For example, as shown in FIG. 3 , an active layer 112 may be formed on the functional layer 108. For example, as shown in FIG. 4 , the active layer 112 and the contact layer 114 may be formed on the functional layer 108. The intermediate layer 110, the active layer 112, and the contact layer 114 are layers that constitute the semiconductor crystal layer, similar to the underlayer 104, the stress relief layer 106, and the functional layer 108. Therefore, when the semiconductor crystal layer includes these layers, the thickness of the semiconductor crystal layer is the total thickness including the thicknesses of these layers.

[0061] 2, the intermediate layer 110 is located between the underlayer 104 and the stress relaxation layer 106 and in contact with the underlayer 104. The chemical composition of the intermediate layer 110 is, for example, Al ｘ２ Ga １－ｘ２ N (0.6≦x2≦0.9). The intermediate layer 110 expands the initial nuclei formed in the underlayer 104 and forms the underlying surface of the stress relaxation layer 106 to be formed thereon. The heterointerface between the intermediate layer 110 and the underlayer 104 may be coherently continuous, or may be dominated by a region grown incoherently.

[0062] In the configuration of FIG. 3, the active layer 112 has a chemical composition of, for example, Al. ｘ５ Ga １－ｘ５ The active layer 112 may be a Schottky layer containing N. Specifically, a two-dimensional electron gas (2DEG) is generated at the heterointerface between the active layer 112 and the functional layer 108, and the active layer 112 may be a Schottky layer that functions as an electron supply layer for the transistor. The Al composition ratio x5 of the active layer 112 may be higher than the Al composition ratio x3 of the functional layer 108, and the thickness may be determined within a range that pseudomorphically matches the in-plane lattice constant b of the functional layer 108, and may be changed appropriately depending on the structure of the transistor to be formed.

[0063] In the configuration of FIG. 4, the active layer 112 is made of, for example, Al ｘ６ Ga １－ｘ６ N / Al ｘ７ Ga １－ｘ７ N can be used as a multi-quantum well (MQW) layer that serves as a light-emitting region. The Al compositions x6 and x7 and the thickness of the MQW layer may be determined within a range that achieves pseudomorphic matching with the in-plane lattice constant b of the functional layer 108, and can be changed as appropriate depending on the structure of the diode to be formed.

[0064] The contact layer 114 is, for example, Mg-doped Al ｘ８ Ga １－ｘ８ The Al composition x8 and thickness can be changed as appropriate depending on the structure of the diode to be formed. The contact layer 114 may also be made of boron nitride (BN), which has a large band gap.

[0065] Second Embodiment FIG. 5 is a cross-sectional view of a compound semiconductor substrate 200 according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view showing a modified example of the compound semiconductor substrate 200. As shown in FIG. 5 , the compound semiconductor substrate 200 has a semiconductor crystal layer on a substrate 102, similar to the compound semiconductor substrate 100. The semiconductor crystal layer has an underlayer 104, a stress relief layer 106, and a functional layer 108. However, as shown in FIGS. 5 and 6 , the stress relief layer 106 of the compound semiconductor substrate 200 has one or more stacked structures 106 c. The stacked structure 106 c has a first crystal layer 106 a and a second crystal layer 106 b. The other configuration of the compound semiconductor substrate 200 is similar to that of the compound semiconductor substrate 100.

[0066] The first crystal layer 106a preferably has an in-plane lattice constant c1 between a and b and a thickness of 6 nm to 125 nm. The second crystal layer 106b preferably has an in-plane lattice constant c2 that satisfies (c1 + c2 - 2 × b) / (2 × b) ≦ ±0.5% and a thickness of 6 nm to 125 nm. The first crystal layer 106a and the second crystal layer 106b are disposed in this order from the substrate 102 side.

[0067] The first crystal layer 106a is made of, for example, Al ｘ Ga １－ｘ N (0<x≦1.0), typically 0.6<x≦0.9. By making the thickness of the first crystal layer 106a 6 nm or more, the flatness of the stress relaxation layer 106 can be maintained. Note that if the thickness of the first crystal layer 106a is too small, the surface flatness tends to be impaired, and if the thickness of the first crystal layer 106a is too large, the effect of stress relaxation tends to be impaired. Therefore, the thickness of the first crystal layer 106a is preferably 6 nm or more and 125 nm or less, more preferably 10 nm or more and 100 nm or less, and particularly preferably 20 nm or more and 75 nm or less.

[0068] The second crystal layer 106b is made of, for example, Al ｙ Ga １－ｙN (0≦y<1.0), typically (0.1≦y≦0.6). Note that y is a value smaller than the Al composition ratio x of the first crystal layer 106a. The thickness of the second crystal layer 106b can be 6 nm or more and 125 nm or less. If the thickness of the second crystal layer 106b is too small, the stress relaxation effect is impaired, and if the thickness of the second crystal layer 106b is too large, the surface flatness tends to be impaired. Therefore, the thickness of the second crystal layer 106b is preferably 6 nm or more and 125 nm or less, more preferably 10 nm or more and 100 nm or less, and particularly preferably 20 nm or more and 75 nm or less. The second crystal layer 106b is intentionally formed so that the crystal lattice at the heterojunction surface with the first crystal layer 106a is incoherent with respect to the crystal lattice of the first crystal layer 106a. As described above, since the in-plane lattice constant c2 of the second crystal layer 106b in a bulk state is different from the in-plane lattice constant c1 of the first crystal layer 106a in a bulk state, if the second crystal layer 106b is incoherent with respect to the first crystal layer 106a, the stress applied to the first crystal layer 106a is released in the second crystal layer 106b, thereby facilitating stress relaxation.

[0069] The plurality of laminated structures 106c may form a multi-layer laminated structure, a so-called superlattice structure, as shown in FIG. 6. The number of repetition periods of the laminated structure 106c (the number of layers in the laminated structure 106c) may be, for example, 1 to 100. By forming the stress relief layer 106 into a laminated structure with a large number of repetition periods, the effect of the stress relief layer 106 in alleviating stress can be enhanced. Furthermore, the lattice relaxation rate of the stress relief layer 106 can be easily controlled by the number of layers in the laminated structure 106c.

[0070] For this reason, the heterointerface between the first crystal layer 106a and the second crystal layer 106b is not an ideal coherent interface, but is thought to be an interface that actively has some defects, and that is lattice-relaxed by these defects. It is thought that by stacking the heterointerface between the first crystal layer 106a and the second crystal layer 106b, the incoherent portion becomes more dominant.

[0071] The thicker the stress relaxation layer 106, particularly the second crystal layer 106b, and the greater the number of repetition periods of the first crystal layer 106a and the second crystal layer 106b, the more strain is relaxed. In other words, the lattice relaxation rate of the functional layer 108 relative to the underlayer 104 is expected to increase. In this embodiment, the increased lattice relaxation rate simultaneously improves the full width at half maximum of the X-ray rocking curve in the diffraction plane (102) of the functional layer 108, and also provides the effect of a mirror-finished surface. Here, "mirror-finished surface" refers to a surface that is free of opacity under normal fluorescent lighting (1000 to 5000 lux). While the mechanism by which these characteristic parameters are improved in a balanced manner is unknown, the inventors speculate that conditions such as the dislocation density of the underlayer 104 and the growth temperatures of the stress relaxation layer 106 and the functional layer 108 have an effect.

[0072] As long as the stress relaxation layer 106 includes the stacked structure 106c made up of the first crystal layer 106a and the second crystal layer 106b, the other layer configuration of the stress relaxation layer 106 is arbitrary. For example, the crystal layer constituting the stress relaxation layer 106 may be a so-called grated crystal layer in which the composition continuously changes in the depth direction.

[0073] 7 is a cross-sectional view of a compound semiconductor substrate 300 according to a third embodiment. Similar to the compound semiconductor substrate 100, the compound semiconductor substrate 300 includes a semiconductor crystal layer on a substrate 102. The semiconductor crystal layer includes an underlayer 104, a stress relief layer 106, and a functional layer 108. However, the stress relief layer 106 of the compound semiconductor substrate 300 further includes a third crystal layer 106d, which has an in-plane lattice constant c3 that satisfies (c1 + c2 + c3 - 3 × b) / (3 × b) ≦ ±0.5%, in addition to the stress relief layer 106 of the second embodiment. The first crystal layer 106a, the second crystal layer 106b, and the third crystal layer 106d are disposed in this order from the substrate 102 side. The other configuration of the compound semiconductor substrate 300 is the same as that of the compound semiconductor substrate 100. 7 shows an embodiment in which a plurality of stacked structures 106c are stacked, the compound semiconductor substrate 300 may have a single stacked structure 106c. In other words, the number of repetition periods of the stacked structure 106c in the compound semiconductor substrate 300 may be one.

[0074] The third crystal layer 106d is made of, for example, Al ｚ１ Ga １－ｚ１ N (0≦z1≠1), typically satisfying 0.0≦z1≦0.5. The thickness of the third crystal layer 106d is arbitrary. However, the in-plane lattice constant of the third crystal layer 106d in a bulk state is c3 that satisfies (c1+c2+c3-3×b) / (3×b)≦±0.5%. The third crystal layer 106d is formed so that the crystal lattice is coherently or non-coherently continuous with the crystal lattice of the second crystal layer 106b at the heterojunction surface with the second crystal layer 106b. Furthermore, when a plurality of stacked structures 106c are arranged, the third crystal layer 106d is formed so that the crystal lattice is coherently or non-coherently continuous with the crystal lattice of the first crystal layer 106a at the heterojunction surface with the first crystal layer 106a. Therefore, the stress is relaxed by the first crystal layer 106a, the second crystal layer 106b, and the third crystal layer 106d.

[0075] The heterointerface between the third crystal layer 106d and the second crystal layer 106b, and the heterointerface between the third crystal layer 106d and the first crystal layer 106a being coherently or non-coherently continuous means that lattice relaxation due to pseudomorphism or defects or the like has occurred, and coherently and non-coherently grown regions may be mixed.

[0076] 8 is a cross-sectional view of a compound semiconductor wafer 400 according to a fourth embodiment. Similar to the compound semiconductor wafer 100, the compound semiconductor wafer 400 includes a semiconductor crystal layer on a substrate 102. The semiconductor crystal layer includes an underlayer 104, a stress relief layer 106, and a functional layer 108. However, the stacked structure 106c of the stress relief layer 106 of the compound semiconductor wafer 400 may include one or more crystal layers located closer to the functional layer 108 than the third crystal layer 106d. The nth crystal layer 106n, which is the crystal layer in the stacked structure 106c closest to the functional layer 108, has an in-plane lattice constant cn that satisfies {c1 + c2 + ... c(n-1) + cn - n × b} / (n × b) ≤ ±0.5%. In other words, cn is the in-plane lattice constant of the nth crystal layer (nth crystal layer 106n) counting from the first crystal layer 106a. Here, n is an integer equal to or greater than 4. The other configurations of the compound semiconductor substrate 400 are the same as those of the compound semiconductor substrate 300. When there is only one crystal layer located closer to the functional layer 108 than the third crystal layer 106d, in other words, when only the fourth crystal layer 106e is disposed in contact with the third crystal layer 106d in the compound semiconductor substrate 300, the compound semiconductor substrate 400 has a configuration in which the first crystal layer 106a, the second crystal layer 106b, the third crystal layer 106d, and the fourth crystal layer 106n are sequentially stacked. While FIG. 8 shows an embodiment in which a plurality of stacked structures 106c are stacked, the compound semiconductor substrate 400 may have a single stacked structure 106c. In other words, the number of repetition periods of the stacked structure 106c in the compound semiconductor substrate 400 may be one.

[0077] The n-th crystal layer 106n is made of, for example, Al ｚ２ Ga １－ｚ２N (0≦z2≠1), typically satisfying 0.0≦z2≦0.5. The thickness of the nth crystal layer 106n is arbitrary. However, the in-plane lattice constant of the nth crystal layer 106n is set to cn satisfying {c1 + c2 + ... + c(n-1) + cn - n × b} / (n × b) ≦ ±0.5%. The nth crystal layer 106n is formed so that the crystal lattice is coherently or non-coherently continuous with the crystal lattice of the n-1th crystal layer 106(n-1) at the heterojunction surface with the n-1th crystal layer 106(n-1). Therefore, stress is relieved by the first crystal layer 106a, the second crystal layer 106b, the third crystal layer 106d, the n-1th crystal layer 106(n-1), and the nth crystal layer 106n.

[0078] The heterointerface between the nth crystal layer 106n and the (n-1)th crystal layer 106(n-1) being coherently or non-coherently continuous means that lattice relaxation due to pseudomorphism or defects or the like has occurred, and coherently and non-coherently grown regions may be mixed.

[0079] The configurations of the layers described in the first to fourth embodiments can be arbitrarily combined as long as the combination does not contradict the spirit of the invention. Furthermore, the composition and distribution within each crystal layer described in the first to fourth embodiments can be arbitrary as long as the specified conditions are met. For example, the composition distribution in the thickness direction of each crystal layer can be uniform or can vary in a grating pattern. Furthermore, the thickness of each crystal layer described in the first to fourth embodiments can be arbitrary as long as the specified conditions are met. The combination of the composition distribution and thickness of each crystal layer can also be arbitrary as long as the specified conditions are met. Furthermore, as in the first embodiment, the second to fourth embodiments may further include at least one of the intermediate layer 110, the active layer 112, and the contact layer 114.

[0080] Each of the semiconductor crystal layers described in the first to fourth embodiments can be formed by a general epitaxial growth method, such as MOCVD (Metal Organic Chemical Vapor Deposition) or HVPE (Hydride Vapor Phase Epitaxy). For example, well-known materials, equipment, and conditions can be applied to the manufacturing conditions, such as the source gas, manufacturing equipment, and film formation temperature, used in the MOCVD method. However, in the manufacturing method of the compound semiconductor substrates 100 to 400, the thickness D of the stress relaxation layer 106 can be determined according to the following formula (1), and the stress relaxation layer 106 can be formed to the determined thickness D. 500≦D=(d1+d2+ ... +d(n-1)+dn)×P≦10000 nm (nm) ... formula (1) where d1, d2, ..., d(n-1), and dn are the thickness of the first crystal layer 106a, the thickness of the second crystal layer 106b, ..., the thickness of the (n-1)th crystal layer 106(n-1), and the thickness of the nth crystal layer 106n, respectively, and P is the number of repetition periods. According to this method, compound semiconductor substrates 100 to 400 having a large lattice relaxation rate, good surface roughness, and low dislocation density can be manufactured.

[0081] In the above-described first to fourth embodiments, at the heterojunction surface between the stress relaxation layer 106 (or the first crystal layer 106a when the stress relaxation layer 106 has the stacked structure 106c) and the stress relaxation layer 106 or the first crystal layer 106a, the crystal lattice of the stress relaxation layer 106 or the first crystal layer 106a is not coherently continuous with the crystal lattice of the lower crystal layer, and while coherent regions and lattice-relaxed regions coexist at the interface, it is preferable that the lattice-relaxed regions are dominant. The lower crystal layer referred to here refers to a crystal layer disposed on the substrate side of the stress relaxation layer 106 or the first crystal layer 106a and in contact with the stress relaxation layer 106 or the first crystal layer 106a. Specifically, it refers to the underlayer 104, the intermediate layer 110 (see FIG. 2), the second crystal layer 106b (see FIG. 6), the third crystal layer 106d (see FIG. 7), or the n-th crystal layer 106n (see FIG. 8) that contacts the stress relaxation layer 106 or the first crystal layer 106a. Furthermore, when the underlayer 104 and the intermediate layer 110 are not provided, the substrate 102 that contacts the stress relaxation layer 106 or the first crystal layer 106a corresponds to the underlayer crystal layer.

[0082] In the above-described first to fourth embodiments, for example, Al ｘ Ga １－ｘ The in-plane lattice constant of each crystal layer constituting the semiconductor crystal layer, expressed as N (0<x<1), can be controlled by the Al composition ratio x. In addition, non-coherent growth at the heterojunction surface can be controlled by process conditions such as growth temperature.

[0083] (Embodiment 5) In Embodiments 1 to 4, the features of the present invention have been grasped as compound semiconductor substrates 100 to 400. However, the features of the present invention can also be grasped as an inspection method. That is, a compound semiconductor substrate inspection method includes a substrate 102 and a semiconductor crystal layer on the substrate 102, the semiconductor crystal layer having an underlayer 104, a stress relaxation layer 106 that relieves stress, and a functional layer 108 that controls carriers, the underlayer 104, the stress relaxation layer 106, and the functional layer 108 being arranged in this order from the substrate 102 side, the underlayer 104, the stress relaxation layer 106, and the functional layer 108, in this order from the substrate 102 side, can be judged as passing if the lattice relaxation rate of the functional layer 108 relative to the underlayer 104, as determined by X-ray reciprocal lattice mapping in the asymmetric diffraction plane of the semiconductor crystal layer, is 60% or more, and if the full width at half maximum of the X-ray rocking curve in the diffraction plane (102) of the functional layer is less than 550 arcsec. This can be understood as an inspection method for a compound semiconductor substrate that is judged as passing. The compound semiconductor substrate to be inspected may have an intermediate layer 110, an active layer 112, and a contact layer 114. In the inspection method according to this embodiment, the threshold value of the lattice relaxation rate used for pass / fail judgment is not limited to 60% and may be changed.

[0084] Next, examples of the present invention will be shown, but the conditions in the examples are merely examples adopted to confirm the feasibility and effects of the present invention, and the present invention is not limited to the conditions used in the following examples. Various conditions can be adopted in the present invention as long as they do not deviate from the gist of the present invention and the object of the present invention is achieved.

[0085] (Example 1) An AlN template was prepared by forming an AlN layer with a thickness of 300 to 400 nm on a sapphire substrate (size: diameter 50 mm) as a base layer, and a stress relaxation layer and a functional layer were sequentially formed thereon by MOCVD. The laminated structure of the stress relaxation layer consisted of an AlN layer with a thickness of 6 to 100 nm as a first crystalline layer. ０．８ Ga ０．２ The N layer is then formed as a second crystal layer with a thickness of 6 to 125 nm. ０．５ Ga ０．５The second crystal layer was formed on the surface of the first crystal layer opposite to the surface on the underlayer side. The above layered structure was repeated 1.5 to 50 times, and the thickness of each layer and the number of repetitions were adjusted so that the total thickness of the stress relaxation layer was approximately 600 nm. A 2500 nm thick Si-doped n-type Al layer was used as the functional layer. ０．６２ Ga ０．３８ A layer of N was formed. The growth temperature was changed in the range of 1000 to 1150° C. In this manner, the compound semiconductor substrates of Experimental Examples 1 to 10 were fabricated.

[0086] (Comparative Example 1A) An AlN template was prepared by forming an AlN base layer with a thickness of 300 to 400 nm on a sapphire substrate (size: diameter 50 mm), and functional layers were sequentially formed thereon by MOCVD. ０．６２ Ga ０．３８ A N layer was formed. The growth temperature was changed in the range of 1000 to 1150° C. In this manner, a compound semiconductor substrate of Experimental Example 11 was fabricated. The conditions were the same as those of Example 1, except that the stress relaxation layer was not formed.

[0087] (Comparative Example 1B) An AlN template was prepared by forming an AlN layer with a thickness of 300 to 400 nm on a sapphire substrate (size: diameter 50 mm) as a base layer, and a stress relaxation layer and a functional layer were sequentially formed thereon by MOCVD. ０．８ Ga ０．２ The N layer is used as the second crystal layer. ０．５ Ga ０．５ The number of repetitions of the laminated structure was adjusted so that the total thickness of the stress relaxation layer was about 600 nm. A Si-doped n-type AlN layer having a thickness of 2500 nm was formed as a functional layer on the surface of the stress relaxation layer. ０．６２ Ga ０．３８ A N layer was formed. The growth temperature was changed in the range of 1000 to 1150°C. The compound semiconductor substrates of Experimental Examples 12 and 13 were fabricated using combinations of (first crystal layer / second crystal layer / number of repetitions of stacked structure) of (3 nm / 3 nm / 100) and (200 nm / 200 nm / 1.5).

[0088] Here, the compound semiconductor substrate of Experimental Example 4 (the first crystal layer had a thickness of 50 nm, the second crystal layer had a thickness of 50 nm, and the number of repetition periods was 6) will be used as an example to describe methods for evaluating the lattice relaxation rate, the surface roughness, and the half-width of the X-ray rocking curve on the diffraction planes (002) and (102) with reference to FIGS. 9 to 11 .

[0089] The graph in Figure 9 is an X-ray reciprocal lattice mapping image of the diffraction plane (-1-14), which is the asymmetric plane of the semiconductor substrate. The positional relationship of each peak in the X-ray reciprocal lattice plane (Qx-Qz plane) of the underlayer and functional layer can be seen from Figure 9. Qz corresponds to the reciprocal of the lattice constant perpendicular to the growth surface, and Qx corresponds to the reciprocal of the lattice constant parallel to the growth surface. Note that a smaller Qx value and Qz value means a larger lattice constant. The in-plane lattice constant a of the underlayer can be calculated from the Qx value of the underlayer: a = 0.30964 nm. The in-plane lattice constant b of the functional layer can be calculated from the Qx value of the functional layer: b = 0.3132 nm. The Al composition ratio of 0.62 can be calculated from the Qx value and Qz value. From this Al composition ratio, the in-plane lattice constant r for complete relaxation is calculated as 0.3132 nm. The lattice relaxation rate R is calculated according to the formula R = |(b-a) / (r-a)| x 100, resulting in a lattice relaxation rate of 100%. In other words, in Experimental Example 4, the functional layer was completely lattice-relaxed relative to the underlayer. The Qx value, Qz value, Al composition, and lattice relaxation rate can be determined using the analysis software Epitaxy (version 4.5a) manufactured by PANalytical Corporation.

[0090] 10 is an atomic force microscope (AFM) image of the surface of the compound semiconductor substrate of Experimental Example 4, in other words, the surface of the functional layer, scanned over a 20 μm square field of view. The surface roughness was calculated using the RMS (roughness of root mean square) value, and this figure shows that the surface roughness was good at 5.8 nm, with no large holes or steps observed.

[0091] The graph in Figure 11 shows X-ray rocking curves for the diffraction planes (002) and (102) of the functional layer of the compound semiconductor substrate of Experimental Example 4. From Figure 11, the half-widths can be estimated to be 250 arcsec and 458 arcsec, respectively. The screw dislocation density and edge dislocation density were calculated according to the following formulas described in Non-Patent Document 9 (MA Moram, et al., Rep. Prog. Phys. 72, 036502 (2009)), and the dislocation density of the functional layer (the sum of the screw dislocation density and edge dislocation density) was found to be 1.3 x 10 ９ cm －２ Hereinafter, the total dislocation density of screw dislocation density and edge dislocation density may be simply referred to as the dislocation density. Screw dislocation density = (β （００２） ２ / 3600×2π / 360) / (4.35×(0.5080 / 10 ７ ) ２ ) (cm －２ ) ... (2) Edge dislocation density = (β （１０２） ２ / 3600×2π / 360) / (4.35×(0.3132 / 10 ７ ) ２ ) (cm －２ ) ... (3) Dislocation density = screw dislocation density + edge dislocation density (cm －２ In the above formula (2), β （００２） is the half-width (arcsec) of the X-ray rocking curve in the diffraction plane (002), and in the above formula (3), β （１０２） is the half-width (arcsec) of the X-ray rocking curve in the diffraction plane (102). According to this calculation, in Experimental Example 4, the screw dislocation density and edge dislocation density were each 0.1 × 10 ９ cm －２ , 1.1 × 10 ９ cm －２ , and the dislocation density is 1.3 × 10 ９ cm －２ It was estimated that:

[0092] The compound semiconductor substrates of Experimental Examples 1 to 13 were evaluated for lattice relaxation rate, surface roughness, half-width of X-ray rocking curves on the diffraction planes (002) and (102), and dislocation density as described above. The results are shown in Table 1. A substrate was evaluated as pass (A) when the lattice relaxation rate was 60% or more and the half-width of X-ray rocking curve on the diffraction plane (102) of the functional layer was less than 550 arcsec, while a substrate was evaluated as fail (B) when at least one of the lattice relaxation rate of 60% or more and the half-width of less than 550 arcsec was not satisfied.

[0093]

[0094] 12 to 14 are graphs plotting the lattice relaxation rate, surface roughness RMS, and dislocation density versus the thickness of the first crystal layer and the second crystal layer for Experimental Examples 1 to 5 and Experimental Examples 12 and 13. Experimental Examples 1 to 5, 12, and 13 are examples in which the ratio of the thicknesses of the first crystal layer and the second crystal layer of the stress relaxation layer was 1:1, the total thickness of the stress relaxation layer was fixed at approximately 600 nm, and the number of repetition periods was changed.

[0095] As can be seen from the graph in FIG. 12, the lattice relaxation rate exceeded 60% in all experimental examples, and when the thickness of the first crystal layer and the second crystal layer exceeded 10 nm, the lattice relaxation rate exceeded 80%, when the thickness exceeded 25 nm, the lattice relaxation rate exceeded 90%, and when the thickness reached 50 nm, the lattice relaxation rate reached 100%.

[0096] 13, the surface roughness decreased as the thickness of the first crystal layer and the second crystal layer increased. When the thickness of the first crystal layer and the second crystal layer was 6 nm or more, the RMS was 15.0 nm or less, and good flatness was achieved.

[0097] In Experimental Examples 1 to 5, the half-width of the X-ray rocking curve in the diffraction plane (102) was less than 550 arcsec, and as shown in the graph of FIG. 14, the dislocation density was 2.0 × 10 ９ cm －２ It was less than.

[0098] 15 to 17 are graphs plotting the lattice relaxation rate, surface roughness RMS, and dislocation density versus the thickness of the second crystal layer for Experimental Examples 3, and 6 to 10. Experimental Examples 3, and 6 to 10 are examples in which the thickness of the first crystal layer of the stress relaxation layer was fixed at 25 nm, the thickness of the second crystal layer was changed so that the thickness ratio to the second crystal layer was 1:0.5 to 5.0, and the number of repetition periods was changed, thereby making the total thickness of the stress relaxation layer approximately 600 or 625 nm.

[0099] 15 shows that the lattice relaxation rate exceeded 60% in Experimental Examples 3 and 6 to 10, exceeded 90% when the thickness of the second crystal layer exceeded 25 nm, and reached 97% when the thickness increased to 50 nm. With further increases in thickness, the lattice relaxation rate decreased but remained at 90%.

[0100] From the graph of FIG. 16, it can be seen that when the thickness of the second crystal layer was 12 nm, the surface roughness was 21.0 nm, but when the thickness was greater than this, the surface roughness was 10.0 nm or less, and good flatness was obtained.

[0101] From the graph in FIG. 17, in Experimental Examples 3, 6 to 10, the half-width of the X-ray rocking curve in the diffraction plane (102) was 550 arcsec or less, and the dislocation density was 2.0×10 ９ cm －２ It was less than.

[0102] When the compound semiconductor substrates of Experimental Examples 1 to 10 were inspected with the naked eye under fluorescent lighting with an illuminance of 2000 lux, the surfaces of all the compound semiconductor substrates were mirror-finished with no cloudiness.

[0103] For this reason, in the present invention, the thickness of the first crystal layer is set to 6 nm or more and 125 nm or less, preferably 10 nm or more and 100 nm or less, and more preferably 20 nm or more and 75 nm or less, and the thickness of the second crystal layer is set to 6 nm or more and 125 nm or less, preferably 10 nm or more and 100 nm or less, and more preferably 20 nm or more and 75 nm or less.

[0104] The compound semiconductor substrate of Experimental Example 11, in which no stress relaxation layer was formed, was also evaluated for lattice relaxation rate, surface roughness, and half-width of X-ray rocking curves in the diffraction planes (002) and (102) in the same manner as in Examples 1 to 10.

[0105] The graph in Figure 18 is an X-ray reciprocal lattice mapping image of the diffraction plane (-1-14), which is the asymmetric plane of the semiconductor substrate of Experimental Example 11. The lattice relaxation rate was calculated to be 17%, which means that the functional layer was not completely lattice relaxed relative to the underlayer.

[0106] 19 is an atomic force microscope (AFM) image obtained by scanning a 20 μm square field of view of the surface of the semiconductor substrate of Experimental Example 11. The surface roughness was 22.0 nm, which was attributed to the large number of large steps observed on the surface.

[0107] The graph in Figure 20 shows the X-ray rocking curve of the diffraction plane (102) of the functional layer of the compound semiconductor substrate of Experimental Example 11. From Figure 20, the half-width can be estimated to be 919 arcsec. When the dislocation density is calculated according to Non-Patent Document 9, the dislocation density is 7.3 x 10 ９ cm －２ It was.

[0108] 12, 13, and 14, the lattice relaxation rates of the compound semiconductor substrates of Experimental Examples 12 and 13 were 75% or more, but the surface roughness in an atomic force microscope (AFM) image scanned within a 20 μm square field of view exceeded 15.0 nm, the half-width of the X-ray rocking curve in the diffraction plane (102) exceeded 550 arcsec, and the dislocation density was 2.0×10 ９ cm －２ It exceeded that.

[0109] When the compound semiconductor substrates of Experimental Examples 11 to 13 were inspected with the naked eye under fluorescent lighting with an illuminance of 2000 lux, the surfaces of the compound semiconductor substrates were found to be cloudy.

[0110] Example 2 An AlN template was prepared on a sapphire substrate (size: diameter 50 mm) by forming AlN as an underlayer to a thickness of 300 to 400 nm, and a stress relaxation layer and a functional layer were sequentially formed thereon by MOCVD. A 25 nm thick AlGaN layer was formed as the first crystalline layer of the stress relaxation layer, and a 125 nm thick AlGaN layer was formed as the second crystalline layer, with the composition ratios shown in Table 2. The stacked structure of the first crystalline layer and the second crystalline layer was repeated four times, and the thicknesses and number of repetitions were adjusted so that the total thickness of the stress relaxation layer was approximately 600 nm. A 2500 nm thick Si-doped n-type AlGaN layer was formed as the functional layer. ０．６２ Ga ０．３８ A N layer was formed. The growth temperature was changed in the range of 1000 to 1150°C. The compound semiconductor substrates of Experimental Examples 14 to 17 were fabricated using combinations of (Al composition ratio of the first crystal layer / Al composition ratio of the second crystal layer) of (0.8 / 0.5), (0.8 / 0.35), (0.9 / 0.65), and (0.7 / 0.2).

[0111] (Comparative Example 2) An AlN template was prepared on a sapphire substrate (size: diameter 50 mm) by forming AlN as an underlayer to a thickness of 300 to 400 nm, and a stress relaxation layer and a functional layer were sequentially formed thereon by MOCVD. A 25 nm thick AlGaN layer was formed as the first crystalline layer of the stress relaxation layer, and a 125 nm thick AlGaN layer was formed as the second crystalline layer, with the composition ratios shown in Table 2. The stacked structure of the first crystalline layer and the second crystalline layer was repeated four times, and the thickness of each layer and the number of repetitions were adjusted so that the total thickness of the stress relaxation layer was approximately 600 nm. A 2500 nm thick Si-doped n-type AlGaN layer was formed as the functional layer. ０．６２ Ga ０．３８ A N layer was formed. The growth temperature was changed in the range of 1000 to 1150° C. The compound semiconductor substrate of Experimental Example 18 was fabricated with a combination of (Al composition ratio of the first crystal layer / Al composition ratio of the second crystal layer) of (0.7 / 0.1).

[0112] The compound semiconductor substrates of Experimental Examples 14 to 18 were evaluated for the lattice relaxation rate, surface roughness, half-width of the X-ray rocking curve on the diffraction planes (002) and (102), and dislocation density in the same manner as in Example 1, in addition to the relationship (c1 + c2 - 2 × b) / (2 × b). The results are shown in Table 2. For b (the in-plane lattice constant b of the functional layer) in the relationship (c1 + c2 - 2 × b) / (2 × b), 0.3132 nm was used as the in-plane lattice constant with an Al composition ratio of 0.62. A substrate with a lattice relaxation rate of 60% or more and an X-ray rocking curve half-width of less than 550 arcsec was evaluated as pass (A), while a substrate that did not satisfy at least one of the requirements of a lattice relaxation rate of 60% or more and an X-ray rocking curve half-width of less than 550 arcsec was evaluated as fail (B).

[0113]

[0114] From Table 2, it can be seen that the lattice relaxation rates of the compound semiconductor substrates of Experimental Examples 14 to 17 all exceeded 60%, the surface roughness measured in atomic force microscope (AFM) images scanned within a 20 μm square field of view was 7.0 nm or less, the half-width of the X-ray rocking curve in the diffraction plane (102) was 550 arcsec or less, and the dislocation density was 2.0 × 10 ９ cm －２ On the other hand, although the lattice relaxation rate of the compound semiconductor substrate of Experimental Example 18 was 100%, the surface roughness was 20.0 nm, the half-width of the X-ray rocking curve in the diffraction plane (102) was 628 arcsec, and the dislocation density was 2.4 × 10 ９ cm －２ It was.

[0115] (Example 3) An AlN template was prepared by forming an AlN layer with a thickness of 300 to 400 nm on a sapphire substrate (size: diameter 50 mm) as an underlayer, and a stress relaxation layer, a functional layer, and an active layer were sequentially formed thereon by MOCVD. ０．８ Ga ０．２ The N layer was then covered with a 30 nm thick Al layer as the second crystalline layer. ０．５ Ga ０．５The layer structure in which the first crystal layer and the second crystal layer are stacked is repeatedly stacked 30 times, so that the total thickness of the stress relaxation layer becomes 1800 nm. ０．６３ Ga ０．３７ The active layer was a 7.0 nm thick AlN layer as the first active crystal layer. ０．６０ Ga ０．４０ The N layer was then covered with a 3.5 nm thick AlN layer as the second active crystal layer. ０．４５ Ga ０．５５ An N layer was formed, and an active stack structure in which a first active crystal layer and a second active crystal layer were stacked was repeated five times. The composition of each layer was changed by changing the ratio of Al source gas to Ga source gas. The growth temperature was changed in the range of 1000 to 1150°C. In this manner, the compound semiconductor substrates of Experimental Examples 19 to 23 were fabricated.

[0116] The relationship between the in-plane lattice constants of the stress relaxation layer (first crystal layer, second crystal layer) and the functional layer is set to (c1 + c2 - 2 × b) / (2 × b) ≦ ±0.5%, where c1 is the in-plane lattice constant of the first crystal layer, c2 is the in-plane lattice constant of the second crystal layer, and b is the in-plane lattice constant of the functional layer.

[0117] (Comparative Example 3) An AlN template was prepared by forming an AlN base layer with a thickness of 300 to 400 nm on a sapphire substrate (size: diameter 50 mm), and a functional layer and an active layer were sequentially formed thereon by MOCVD. ０．６２ Ga ０．３８ The active layer was a 7.0 nm thick AlN layer as the first active crystal layer. ０．６０ Ga ０．４０ The N layer was then covered with a 3.5 nm thick AlN layer as the second active crystal layer. ０．４５ Ga ０．５５A layer of N was formed, and an active stack structure consisting of a first active crystal layer and a second active crystal layer was repeatedly stacked five times. The composition of each layer was changed by changing the ratio of Al source gas to Ga source gas. The growth temperature was changed in the range of 1000 to 1150°C. In this manner, the compound semiconductor substrates of Experimental Examples 24 to 26 were fabricated. The conditions were the same as those of Example 2, except that no stress relaxation layer was formed.

[0118] The compound semiconductor substrates of Experimental Examples 19 to 26 were evaluated for surface roughness, lattice relaxation rate, half-width of X-ray rocking curves on the diffraction planes (002) and (102), and photoluminescence (PL) emission intensity. Surface roughness was evaluated using the root mean square (RMS) in a 2 μm square field of view of an AFM (Atomic Force Microscope). Lattice relaxation rate was evaluated from the peak position relationship between the underlayer and the functional layer on the diffraction plane (-1-14), and the half-width of the X-ray rocking curve was measured using an X-ray diffraction method using ω / 2θ. PL was evaluated by evaluating the peak intensity of the spectrum emitted at 275 to 290 nm using a 266 nm laser as excitation light.

[0119] The compound semiconductor substrates of Experimental Examples 19 to 26 were evaluated for lattice relaxation rate, surface roughness, half-width of X-ray rocking curves on the diffraction planes (002) and (102), dislocation density, photoluminescence intensity in photoluminescence (PL), and in-plane distribution of sheet resistance, and the results are shown in Table 3 and Figures 21 to 24. A substrate in which the lattice relaxation rate was 60% or more and the half-width of the X-ray rocking curve on the diffraction plane (102) of the functional layer was less than 550 arcsec was rated as pass (A), and a substrate in which at least one of the lattice relaxation rate of 60% or more and the half-width of less than 550 arcsec was not satisfied was rated as fail (B).

[0120]

[0121] 21, the compound semiconductor substrates of Experimental Examples 19 to 23 (Example 3) all had lattice relaxation rates exceeding 70%, and when the functional layer thickness was 2000 nm or more, the relaxation rate exceeded 90%. On the other hand, the compound semiconductor substrates of Experimental Examples 24 to 26 (Comparative Example 3) all had lattice relaxation rates less than 60%.

[0122] From the graph of FIG. 22, the compound semiconductor substrates of Experimental Examples 19 to 23 all had an RMS of less than 6.0 nm, while the compound semiconductor substrates of Experimental Examples 24 to 26 all had an RMS of more than 6.0 nm.

[0123] The compound semiconductor substrates of Experimental Examples 19 to 23 all had a half-width of less than 550 arcsec on the (102) plane, while the compound semiconductor substrates of Experimental Examples 24 to 26 had a half-width of 450 arcsec on the (102) plane when the functional layer thickness was 1000 nm, but exceeded 550 arcsec when the functional layer thickness was 2000 nm or more. As shown in FIG. 23 , the dislocation density in Experimental Examples 19 to 23 was 2.0 × 10 ９ cm －２ In Experimental Examples 24 to 26, the dislocation density was less than 2.0 × 10 ９ cm －２ That was all.

[0124] 24 shows that the PL intensity was 8000 when the functional layer thickness was 1000 nm (Experimental Example 20), and 30000 when the thickness was 2000 nm (Experimental Example 21). On the other hand, in the compound semiconductor substrates of Experimental Examples 24 to 26, the PL intensity was all less than 7000, regardless of the thickness of the functional layer.

[0125] 25, the compound semiconductor substrates of Experimental Examples 19 to 23 all showed an in-plane distribution of sheet resistance of 12% or less. On the other hand, the compound semiconductor substrates of Experimental Examples 24 to 26 showed an in-plane distribution of 10% when the functional layer thickness was 500 nm, but increased to 40% and 80% when the thickness was 2000 nm and 4000 nm.

[0126] When the compound semiconductor substrates of Experimental Examples 19 to 23 were inspected with the naked eye under fluorescent lighting with an illuminance of 2000 lux, the surfaces of all the compound semiconductor substrates were mirror-finished with no cloudiness. On the other hand, when the compound semiconductor substrates of Experimental Examples 24 to 26 were inspected with the naked eye under fluorescent lighting with an illuminance of 2000 lux, the surfaces of the compound semiconductor substrates were inspected with the naked eye under fluorescent lighting with an illuminance of 2000 lux.

[0127] Example 4 An AlN template was prepared by forming an AlN layer with a thickness of 300 to 400 nm on a sapphire substrate (size: diameter 50 mm) as an underlayer, and a stress relaxation layer was sequentially formed thereon by MOCVD. ０．８ Ga ０．２ The N layer was then covered with a 30 nm thick Al layer as the second crystalline layer. ０．５ Ga ０．５ A layer of N was formed, and a stacked structure in which a first crystal layer and a second crystal layer were stacked was repeatedly stacked 10 to 40 times, so that the total thickness of the stress relaxation layer was 600 nm to 2400 nm. The composition of each layer was changed by changing the ratio of Al source gas to Ga source gas. The growth temperature was changed in the range of 1000 to 1150°C. Compound semiconductor substrates of Experimental Examples 27 to 30 were fabricated in the above manner. Experimental Example 27 is an example in which the number of repetition periods of the stacked structure in the stress relaxation layer was 10, and the total thickness of the stress relaxation layer was 600 nm. Experimental Example 28 is an example in which the number of repetition periods of the stacked structure in the stress relaxation layer was 20, and the total thickness of the stress relaxation layer was 1200 nm. Experimental Example 29 is an example in which the number of repetition periods of the stacked structure in the stress relaxation layer was 30, and the total thickness of the stress relaxation layer was 1800 nm. Experimental example 30 is an example in which the number of repetition periods of the laminated structure in the stress relaxation layer is 40, and the total thickness of the stress relaxation layer is 2400 nm.

[0128] Optical reflectance spectroscopy was performed on the compound semiconductor substrates of Experimental Examples 27 to 30. Specifically, a reflectance spectroscopy device manufactured by Ocean Insight was used to irradiate the compound semiconductor substrates of Experimental Examples 27 to 30 with a xenon lamp and a halogen lamp, and the reflection intensity in the range of 240 to 320 nm was evaluated.

[0129] FIG. 26 is a graph plotting the reflectance spectrum of Experimental Example 29 as an example of the results of optical reflectance spectroscopy. In FIG. 26, the solid line indicates measured values, and the dashed line indicates calculated values. As shown in the graph of FIG. 26, Experimental Example 29 had a reflectance peak at a wavelength of 280 nm, with a maximum reflectance of 0.8. FIG. 27 is a graph plotting the reflectances of Experimental Examples 27 to 30, with the DBR pair shown on the horizontal axis indicating the number of repetition periods of the stacked structure in the stress relaxation layer. Furthermore, the graph of FIG. 27 reveals that increasing the number of repetition periods of the stress relaxation layer from 10 to 40 increases the reflectance from 0.53 to 0.84.

[0130] (Example 5) An AlN template was prepared by forming an AlN layer with a thickness of 300 to 400 nm on a sapphire substrate (size: diameter 50 mm) as an underlayer, and a stress relaxation layer, a functional layer, an active layer, and a contact layer were sequentially formed thereon by MOCVD. ０．８ Ga ０．２ The N layer was then covered with a 30 nm thick Al layer as the second crystalline layer. ０．５ Ga ０．５ This laminated structure was repeatedly stacked 30 times to form a total thickness of the stress relaxation layer of 1800 nm. A Si-doped n-type AlGaN layer (Si-doped AlGaN) having a thickness of 2500 nm was formed as a functional layer. ０．６３ Ga ０．３７ The active layer was a 7.0 nm thick AlN layer as a first active crystal layer. ０．６０ Ga ０．４０ The N layer was then covered with a 3.5 nm thick AlN layer as the second active crystal layer. ０．４５ Ga ０．５５ A N layer was formed, and an active stack structure consisting of a first active crystal layer and a second active crystal layer was repeatedly stacked five times. A 120 nm Mg-doped p-type BN contact layer was formed as a contact layer. The composition of each layer was changed by changing the ratio of Al source gas to Ga source gas and B source gas. The growth temperature was changed in the range of 1000 to 1350°C. The compound semiconductor substrate of Experimental Example 31 was fabricated in the above manner.

[0131] The compound semiconductor substrate of Experimental Example 31 was subjected to X-ray diffraction measurement in a ω / 2θ measurement mode over a 2θ range of 25 to 40 degrees.

[0132] 28, the peaks at 2θ=26.72 degrees, 35.31 degrees, 35.39 degrees, and 35.99 degrees represent the hexagonal BN contact layer, stress relaxation layer, AlGaN functional layer, and AlN underlayer, respectively. Because the AlGaN active layer was thin, its X-ray diffraction peak was not observed. It was confirmed that high-temperature growth of the hexagonal BN contact layer did not cause crystal destruction in the AlGaN functional layer, stress relaxation layer, or AlN underlayer.

[0133] 100, 200, 300, 400 Compound semiconductor substrate 102 Substrate 104 Underlayer 106 Stress relaxation layer 106a First crystal layer 106b Second crystal layer 106c Laminated structure 106d Third crystal layer 106n Nth crystal layer 108 Functional layer 110 Intermediate layer 112 Active layer 114 Contact layer

Claims

1. A semiconductor device comprising: an underlayer having an in-plane lattice constant a; a stress relaxation layer for relieving strain received from the underlayer; and a functional layer having an in-plane lattice constant b (a ≠ b), wherein the underlayer, the stress relaxation layer, and the functional layer are arranged in this order: underlayer, stress relaxation layer, functional layer; a region of the functional layer that is lattice-relaxed from the crystal lattice of the underlayer is dominant; and a dislocation density of the functional layer is 2.0×10 ９ cm －２ A compound semiconductor substrate.

2. The compound semiconductor substrate according to claim 1, wherein the stress relieving layer has an in-plane lattice constant c that satisfies (a+c-2×b) / (2×b)≦±0.5%.

3. The compound semiconductor substrate according to claim 1, wherein the stress relaxation layer has a laminated structure, the stress relaxation layer having: a first crystal layer located in contact with the underlayer side and having an in-plane lattice constant c1 between a and b; and a second crystal layer located in contact with the functional layer side of the first crystal layer and having an in-plane lattice constant c2 that satisfies (c1 + c2 - 2 × b) / (2 × b) ≦ ±0.5%.

4. The compound semiconductor substrate according to claim 3, wherein the thickness of said first crystal layer of said stress relieving layer is not less than 6 nm and not more than 125 nm.

5. The compound semiconductor substrate according to claim 3 or 4, wherein the second crystal layer of the stress relieving layer has a thickness of 6 nm or more and 125 nm or less.

6. A compound semiconductor substrate according to any one of claims 3 to 5, wherein the stress relaxation layer has a repetition number of stacked layers consisting of the first crystal layer and the second crystal layer of two or more periods, and the thickness of the stress relaxation layer is 500 nm or more and 10,000 nm or less.

7. In the stress relaxation layer, the chemical composition of the first crystal layer is Al ｘ G １－ｘ N (0<x≦1.0), and the chemical composition of the second crystal layer is Al ｙ G １－ｙ 7. The compound semiconductor substrate according to claim 3, wherein N (0≦y<1.0) and y<x.

8. The compound semiconductor substrate according to any one of claims 3 to 7, further comprising: a third crystal layer, the stress relaxation layer being located in contact with the functional layer side of the second crystal layer, and having an in-plane lattice constant c3 that satisfies (c1 + c2 + c3 - 3 × b) / (3 × b) ≦ ±0.5%.

9. The compound semiconductor substrate according to claim 8, further comprising an n-th crystal layer, the stress relaxation layer being located in contact with the functional layer side of the n-th crystal layer located closer to the functional layer than the third crystal layer, and having an in-plane lattice constant cn that satisfies {c1+c2+...+c(n-1)+cn-nxb} / (nxb) ≤ ±0.5%, where n is an integer of 4 or more.

10. The compound semiconductor substrate according to any one of claims 3 to 9, wherein the lattice relaxation rate of said functional layer with respect to said underlayer is 60% or more.

11. The compound semiconductor substrate according to claim 3, further comprising an intermediate layer located between said underlayer and said stress relieving layer and in contact with said underlayer.

12. The compound semiconductor substrate according to claim 1, further comprising an active layer located on said functional layer and having an in-plane lattice constant b of said functional layer that pseudomorphically matches said in-plane lattice constant b.

13. The compound semiconductor substrate according to any one of claims 1 to 11, further comprising: an active layer located on the functional layer and having a pseudomorphic lattice match with the in-plane lattice constant b of the functional layer; and a contact layer located on the active layer.

14. The compound semiconductor substrate according to claim 13, wherein said contact layer has a larger band gap than said active layer.

15. The compound semiconductor substrate according to any one of claims 12 to 14, characterized in that the stress relieving layer reflects 50% or more of the light generated from the active layer.

16. The compound semiconductor substrate according to any one of claims 1 to 15, wherein the surface of said compound semiconductor substrate is a mirror surface.

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