DEVICE AND METHOD FOR ACTIVE INDUCTOR MODULATION

Abstract

An active inductor modulator circuit is provided. The active inductor modulator circuit can include a circuit to receive an input signal and provide an output signal at an output terminal of the circuit based on a clock signal. A modulated active inductor is coupled to the circuit to improve the time delay between the input signal and the provided output signal. A modulation clock circuit can also be included to generate a delayed clock signal to activate the modulated active inductor before the output signal transitions from a first logic state to a second logic state.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 319,156, filed March 11, 2022, and U.S. Patent Application No. 17 / 939,782, filed September 7, 2022, which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] The present disclosure relates generally to the use of active inductors to control the time delay between an input signal and an output signal, and more particularly to the use of active inductor modulation to control the time delay between an input signal and an output signal. BACKGROUND

[0003] In high-bandwidth applications with high capacitive loads, such as a clock distribution network, timing control can be improved by using an active inductor—that is, an inductorless circuit whose impedance increases with frequency over a frequency range of interest. However, the use of active inductors can increase power consumption and the required voltage headroom. As the active inductor thickness increases, both power and voltage headroom increase. Furthermore, while the use of active inductors can reduce the time delay between the input signal and the output voltage, the active inductor can limit the voltage swing of the output voltage. Therefore, there is a need to control the time delay between the input signal and the output signal without using excessive power and without degrading the voltage swing of the output voltage. SUMMARY

[0004] According to one aspect of one or more examples, an active inductor modulator circuit is provided, including a circuit for receiving an input signal and providing an output signal at an output terminal of the circuit based on a clock signal, wherein a modulated active inductor is coupled to the circuit to improve a time delay between the input signal and the provided output signal, and a modulation clock circuit is provided to generate a delayed clock signal to activate the modulated active inductor prior to a transition of the output signal from a first logic state to a second logic state. The modulation clock circuit may receive the clock signal and generate the delayed clock signal that is delayed relative to the clock signal.

[0005] The modulated active inductor may include an inverter, a resistor coupled in parallel with the inverter, and a resistor coupled in series with the inverter and a capacitor coupled in series with the inverter, wherein the resistor and the inverter are coupled to an output terminal of the circuit that provides the output signal. The modulated active inductor may include an inverter, a resistor coupled in parallel with the inverter, a capacitor coupled in series with the resistor, a first switch coupled to a voltage supply, and a second switch coupled to ground, wherein the first switch and the second switch are coupled to the inverter. The modulation clock circuit may generate a complementary delayed clock signal that is 180 degrees out of phase with the generated delayed clock signal.The complementary delayed clock signal and the delayed clock signal are intended to turn on the first switch and the second switch, respectively.

[0006] The modulation clock circuit may deactivate the modulated active inductor after the output voltage transitions from the first logic state to the second logic state.

[0007] The first logic state may be a logic low state, and the second logic state may be a logic high state.

[0008] The modulated active inductor may include an inverter including a first and a second p-channel MOSFET coupled in series, a resistor coupled between the gate and drain terminals of the first p-channel MOSFET, and a capacitor coupled between the gate terminal of the first p-channel MOSFET and ground. The second p-channel MOSFET includes a gate terminal for receiving the delayed clock signal, a source terminal coupled to a voltage supply, and a drain terminal coupled to a source terminal of the first p-channel MOSFET. The output signal may be provided at the drain terminal of the first p-channel MOSFET.

[0009] The modulated active inductor may include an inverter including first and second p-channel MOSFETs coupled in series to selectively couple the output terminal of the circuit to a voltage supply based on the delayed clock signal. A gate terminal of the second p-channel MOSFET is to receive the delayed clock signal, and a gate terminal of the first p-channel MOSFET is coupled to a capacitor and to the output terminal of the circuit via a resistor. The first and second p-channel MOSFETs are to couple the output terminal of the circuit to the voltage supply before a rising edge of the output signal.

[0010] The modulated active inductor may include an inverter including a first and a second n-channel MOSFET coupled in series, a resistor coupled between gate and drain terminals of the second n-channel MOSFET, and a capacitor coupled between the gate terminal of the second n-channel MOSFET and ground. The first n-channel MOSFET may include a gate terminal coupled to the modulation clock circuit to receive the delayed clock signal, a source terminal coupled to ground, and a drain terminal coupled to a source terminal of the second n-channel MOSFET. The output signal may be provided at the drain terminal of the second n-channel MOSFET.

[0011] The modulated active inductor may include an inverter including first and second n-channel MOSFETs coupled in series to selectively couple the output terminal of the circuit to ground based on the delayed clock signal. A gate terminal of the first n-channel MOSFET is to receive the delayed clock signal, and a gate terminal of the second n-channel MOSFET is coupled to a capacitor and to the output terminal of the circuit via a resistor. The first and second n-channel MOSFETs are to couple the output terminal of the circuit to ground before a falling edge of the output signal.

[0012] According to one aspect of one or more examples, a method for improving a time delay between an input signal and an output signal of a circuit is provided. The method may include receiving the input signal based on a clock signal, generating a delayed clock signal based on the clock signal, activating a modulated active inductor coupled to the circuit prior to a transition of the output signal from a first logic state to a second logic state based on the delayed clock signal, and outputting the output signal delayed in time relative to the input signal by the time delay. The delayed clock signal may be generated such that the delayed clock signal is delayed relative to the clock signal.

[0013] The method may include generating a complementary delayed clock signal that is 180 degrees out of phase with the delayed clock signal. Activating the modulated active inductor may include turning on the first and second switches of the modulated active inductor based on the complementary delayed clock signal and the delayed clock signal, respectively. The modulated active inductor may be deactivated after the output signal transitions from the first logic state to the second logic state. The first logic state may be a logic low state, and the second logic state may be a logic high state. The first logic state may be a logic high state, and the second logic state may be a logic low state.

[0014] Activating the modulated active inductor may include coupling an output terminal of the circuit to a voltage supply based on the delayed clock signal before a rising edge of the output signal. Activating the modulated active inductor may include coupling an output terminal of the circuit to ground based on the delayed clock signal before a falling edge of the output signal. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A illustrates a modulated active inductor topology according to one or more examples. Fig. Figure 1B illustrates waveform diagrams of the input signal, output signal, and current of an active inductor modulation circuit according to various examples. Fig. 1C illustrates another example inductor topology according to one or more examples. Fig. 1D illustrates a rising edge detector according to one or more examples. Fig. 1E illustrates a falling edge detector according to one or more examples. Fig. 2 illustrates a block diagram of a modulated active inductor according to various examples. Fig. 3A illustrates a circuit diagram of a selectively modulated active inductor according to various examples. Fig. 3B shows waveform diagrams of the input signal, the output signal, the current, and the modulated clock signal of a circuit with active inductor modulation based on the falling edge of the output signal according to various examples. Fig. 4A illustrates a circuit diagram of a selectively modulated active inductor according to various examples. Fig. 4B shows waveform diagrams of the input signal, the output signal, the current, and the modulated clock signal of a circuit with active inductor modulation based on the rising edge of the output signal according to various examples. DETAILED DESCRIPTION OF VARIOUS EXAMPLES

[0015] Reference will now be made in detail to the following various examples, illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The various examples may be embodied in forms without being limited to the various examples set forth herein. Descriptions of well-known parts have been omitted for clarity.

[0016] Fig. 1A is a circuit diagram according to one or more examples. Referring to Fig. 1A, the circuit may include circuit 110, which may include a first latch 111, a first inverter 112, and a second inverter 113. The first latch 111 may include an input signal Vin that varies between a logic high state and a logic low state based on a received clock signal CLK. According to various examples, the input signal Vin is latched on the rising edge of the clock signal CLK and output from the first latch 111 to the first inverter 112, and the first inverter 112 inverts the received signal and outputs the inverted received signal to the second inverter 113, wherein the second inverter 113 generates an output signal Vout at an output terminal of the circuit 110. The output signal Vout may be provided as an input to various other components, such as a time-sensitive component included in the Fig. 1A as a second latch 114 coupled to the output terminal of circuit 110, but is not limited thereto. Each of the first inverter 112 and the second inverter 113 may cause a delay in the output signal Vout relative to the input signal Vin. For example, each of the first inverter 112 and the second inverter 113 may delay the output signal Vout by 10 ps relative to the input signal Vin. Although the Fig. While the circuit 110 shown in Figure 1A includes the first inverter 112 and the second inverter 113, the first and second inverters 112, 113 may instead be buffers or other circuitry to delay the output signal Vout relative to the input signal Vin. The output signal Vout may be input to the second latch 114, which may latch the output signal Vout based on a rising edge of a second clock CLK2. However, if the output signal Vout is delayed relative to the rising edge of the second clock CLK2, the second latch 114 may not latch the correct signal at the input of the second latch 114.

[0017] A modulated active inductor 130 may be coupled to the input terminal of the second latch 114 to control the delay between the input signal Vin and the output signal Vout. For example, the modulated active inductor 130 may include an inverter 131, which may be a tri-state inverter 131, a resistor 132 coupled in parallel with the tri-state inverter 131, and a capacitor 133 coupled in series with the tri-state inverter 131 and the resistor 132. That is, the capacitor 133 is coupled between an input of the tri-state inverter 131 and ground or another common potential, and the output of the tri-state inverter 131 is coupled to the output of the second inverter 113.When modulated active inductor 130 is enabled, modulated active inductor 130 uses a positive feedback loop across resistor 132 to generate a zero that resonates with the pole on the line of output signal Vout, thereby improving bandwidth. In one example, when output signal Vout is in a logic high state and can transition to a logic low state in response to clock signal CLK, the positive feedback loop generated across resistor 132 provides the logic high signal to the input of tri-state inverter 131, which drives output signal Vout to a logic low state, thereby improving bandwidth by improving, i.e., shortening, the fall time to improve the time delay experienced by Vout.When the output signal Vout is in a logic low state and can transition to a high-low state in response to the clock signal CLK, the positive feedback loop created across resistor 132 provides the logic high-low signal to the input of tri-state inverter 131, which drives the output signal Vout to a logic high state, thereby improving the bandwidth by improving, i.e., shortening, the rise time to thereby improve the time delay experienced by Vout.

[0018] In the absence of modulation, the output signal Vout can be a large signal that alternates between a logic high and a logic low. When the output signal Vout is in a logic high state, the tri-state inverter 131 drives the output signal Vout to a logic low state, effectively creating a short circuit from the power supply to ground or common potential, resulting in high current consumption and electromagnetic radiation problems.

[0019] A modulation clock circuit 120 may be coupled to the modulated active inductor 130 to modulate the modulated active inductor 130, which may mitigate these problems. In particular, the modulation clock circuit 120 may include a third inverter 121 and a fourth inverter 122 and receive the clock signal CLK. The third inverter 121 and the fourth inverter 122 are coupled in series and may each delay the clock signal to generate a delayed clock signal CLK_MOD, which is input to the tri-state inverter 131 of the modulated active inductor 130. The modulation clock circuit 120 may be configured to approximate the delay of the first inverter 112 and the second inverter 113 based on the delay introduced by the circuit 110.For example, the third and fourth inverters 121, 122 of the modulation clock circuit 120 may each delay the clock signal CLK by 10 ps or slightly less than 10 ps based on the respective 10 ps delay caused by the first and second inverters 112, 113 of the circuit 110, so that the delayed clock signal CLK_MOD is delayed with respect to the clock signal CLK by the sum of the delays, ie, by about 20 ps.

[0020] The delayed clock signal CLK_MOD is input to an enable input of the tri-state inverter 131 of the modulated active inductor 130 to enable the modulated active inductor 130 before the output signal Vout transitions from a first logic state to a second logic state. The delayed clock signal CLK_MOD may be a differential clock signal including a complementary delayed clock signal CLK_MODB that is 180 degrees out of phase with the delayed clock signal CLK_MOD, as described in more detail below. The modulation clock circuit 120 may, as shown, enable the modulated active inductor 130 before a rising edge and before a falling edge or unchanged state of the output signal Vout in response to a logic high state of CLK_MOD.In another example, the delayed clock signal CLK_MOD may activate the modulated active inductor 130 before a rising edge of the output signal Vout. Alternatively, the delayed clock signal CLK_MOD may activate the modulated active inductor 130 before a falling edge of the output signal Vout. By activating the modulated active inductor 130 before the rising edge or the falling edge of the output signal Vout, the delay associated with the output signal Vout with respect to the input signal Vin may be controlled such that the output signal Vout is ready to be latched at the second latch 114 based on the second clock CLK2.

[0021] Fig. 1B shows example waveform diagrams for the input signal Vin, the output signal Vout, the current, and the modulated clock signal CLK_MOD (which may be a differential clock signal including a complementary delayed clock signal CLK_MODB that is 180 degrees out of phase with the delayed clock signal CLK_MOD) based on the method described in conjunction with Fig. 1A described active inductor modulation scheme. As in Fig. As shown in Figure 1B, the delay between the input signal Vin and the output voltage Vout is approximately 9ps, while the voltage swing of the output signal Vout is approximately 960 mA and the average current is approximately 740 µA.

[0022] Fig. 1C is a circuit diagram according to one or more examples. The circuit of Fig. 1C is similar to Fig. 1A, so no description of the same components is repeated here to avoid redundancy. With reference to Fig. 1C closes the circuit of Fig. 1C instead of the modulation clock circuit 120 of Fig. 1A includes an edge detector 115, which can be implemented in many ways, as discussed below. The edge detector 115 serves to detect an edge of the output signal L_OUT of the first latch 111 and output the delayed clock signal CLK_MOD upon detecting the edge of the output signal L_OUT. Fig. For example, FIG. 1D shows a rising edge detector 115A according to one or more examples, including three series-connected inverters 116A and a NAND gate 117A. The output signal L_OUT of the first latch 111 is input to a first input A1 of the NAND gate 117A and is also input to the first inverter of the three inverters 116A. The output of the third inverter of the three inverters 116A is coupled to a second input B1 of the NAND gate 117A. As shown in the timing diagram of Fig. As shown in Figure 1D, when the output signal L_OUT of the first latch 111 is logic low, the first input A1 receives a logic low signal, the second input B1 receives a logic high signal, and the NAND gate 117A outputs a logic high-delayed clock signal CLK_MOD. When the output signal L_OUT of the first latch 111 changes to logic high, the NAND gate 117A outputs a logic low-delayed clock signal CLK_MOD, since the second input B1 of the NAND gate 117A still receives a logic high signal, as the change in the output signal L_OUT is delayed by the three inverters 116A. By changing the delayed clock signal CLK_MOD from logic high to logic low based on the change of the output signal L_OUT, the rising edge detector 115A is able to detect the rising edge of the output signal L_OUT and output the delayed clock signal CLK_MOD to activate the inverter 131.The three inverters 116A each invert the output signal L_OUT, resulting in a logic low signal received at the second input B1, which causes the delayed clock signal CLK_MOD to become logic high again.

[0023] Fig. 1E illustrates a falling edge detector 115B according to one or more examples. Similar to the falling edge detector 115A of Fig. 1D includes the Fig. 1E includes three series-connected inverters 116B and an OR gate 117B. The output signal L_OUT of the first latch 111 is input to a first input A2 of the OR gate 117B and is also input to the first inverter of the three inverters 116B. The output of the third inverter of the three inverters 116B is coupled to a second input B2 of the OR gate 117B. As shown in the timing diagram of Fig. As shown in Figure 1E (reading from right to left), when the output signal L_OUT of the first latch 111 is logic high, the first input A2 receives a logic high signal, the second input B2 receives a logic low signal, and the OR gate 117A outputs a logic high-delayed clock signal CLK_MOD. When the output signal L_OUT of the first latch 111 changes to logic low, the OR gate 117B outputs a logic low-delayed clock signal CLK_MOD, because the second input B2 of the OR gate 117B still receives a logic low signal, as the change in the output signal L_OUT is delayed by the three inverters 116A. By changing the delayed clock signal CLK_MOD from logic high to logic low based on the change of the output signal L_OUT, the falling edge detector 115B is able to detect the falling edge of the output signal L_OUT and output the delayed clock signal CLK_MOD to activate the inverter 131.After the output signal L_OUT has changed from logic high to logic low, each of the three inverters 116B inverts the output signal L_OUT, resulting in a logic high signal received at the second input B2, which causes the delayed clock signal CLK_MOD to become logic high again.

[0024] According to various examples, the edge detector could also be implemented using an XOR gate (not shown) instead of the NAND gate 117A and the OR gate 117B. By using an XOR gate, the edge detector 115 could detect both rising and falling edges of the output signal L_OUT.

[0025] Fig. 2 shows a modulated active inductor 130 according to various examples. The active inductor 130 may include a first switch 134 and a second switch 135, which may be p-channel and n-channel MOSFETs, each of which is coupled to respective power and feedback inputs of the inverter 131. The source terminal of the first switch 134 is coupled to a voltage supply VDD, and the source terminal of the second switch 135 is coupled to ground or a common potential. Furthermore, the resistor 132 and the capacitor 133 are provided as described above with respect to Fig. 1A. According to the Fig. In the example shown in Figure 2, the delayed clock signal CLK_MOD may be a differential clock signal that also includes a complementary delayed clock signal CLK_MODB that is 180 degrees out of phase with the delayed clock signal CLK_MOD. The delayed clock signal CLK_MOD and the complementary delayed clock signal CLK_MODB may each turn on the second switch 135 and the first switch 134 to activate the active inductor 130. For example, when the delayed clock signal CLK_MOD is in a logic high state and the complementary delayed clock signal CLK_MODB is in a logic low state, the first switch 134 and the second switch 135 are turned on, thereby activating the inverter 131.When the delayed clock signal CLK_MOD is in a logic low state and the complementary delayed clock signal CLK_MODB is in a logic high state, the first switch 134 and the second switch 135 are turned off, thereby disabling the inverter 131. As explained above, when the inverter 131 is enabled, the output signal Vout is fed back to the input of the inverter 131 via the resistor 132, which inverts the output signal Vout to improve the delay of the output signal Vout relative to the input signal Vin. When the delayed clock signal CLK_MOD and the complementary delayed clock signal CLK_MODB are in logic low and logic high states, the inverter 131 is disabled to reduce power dissipation.

[0026] According to various examples, the modulated active inductor 130 may be configured to improve the time delay of a rising edge or a falling edge of the output signal Vout. Fig. Figure 3a shows a circuit diagram of the modulated active inductor 130 according to various examples in which the time delay during the falling edge of the output signal Vout can be improved. According to the Fig. 3A, the inverter 131 may include first and second n-channel MOSFETs 131a, 131b connected in series, with the gate of the second MOSFET 131b coupled between a first end of the resistor 132 and a first end of the capacitor 133. In this example, the gate of the second n-channel MOSFET 131b is the input to the inverter 131, and the drain of the second n-channel MOSFET 131b is the output of the inverter 131. The gate of the first n-channel MOSFET 131a is coupled to the delayed clock signal CLK_MOD, the source of the first n-channel MOSFET 131a is coupled to ground or a common potential, and the drain of the second n-channel MOSFET 131b is coupled to a second end of the resistor 132 and provides the output signal Vout, as mentioned above. A second end of the capacitor 133 is coupled to ground or a common potential.In this configuration, capacitor 133 charges in the direction indicated by the arrow in . Fig. 3A, through resistor 132 when Vout is at a high level, turning on the second n-channel MOSFET 131b after the charge across capacitor 133 reaches a predetermined level. The modulated active inductor 130 can improve the time delay during a falling edge of the output voltage Vout relative to the input signal Vin. When the modulated clock signal CLK_MOD goes high, preceding the falling edge of the output voltage Vout, the modulated clock signal CLK_MOD turns on the first n-channel MOSFET 131a, opening a path to ground through the inverter 131 because the capacitor 133 is charged to the voltage of the logic high state. When the second inverter 113 of the circuit 110 starts driving the output signal Vout low, it is assisted by the inverter 131, resulting in a fast pulldown.Capacitor 133 discharges through resistor 132 until it turns off second n-channel MOSFET 131b to deactivate modulated active inductor 130 after the transition of the output signal. By not activating modulated active inductor 130 during the rising edge of output signal Vout, since second n-channel MOSFET 131b is off due to the discharge condition of capacitor 133, power consumption can be reduced while still improving the time delay of output signal Vout relative to input signal Vin during the falling edge of output signal Vout. Inverter 131 is connected in parallel with second inverter 113 (Fig. Fig. 1A) and may consequently be dimensioned such that in the case where there is no transition, i.e. Vin was at a logic high during a previous period of the clock signal CLK and remains high during a current period of the clock signal CLK, the inverter 131 does not have sufficient pull-down drive to override the pull-up drive of the second inverter 113 and thereby inappropriately change the logic state of Vout.

[0027] Fig. Figure 3B shows example waveforms for the input signal Vin, the output signal Vout, the current, the delayed clock signal CLK_MOD and the complementary delayed clock signal CLK_MODB based on the above-described method in connection with Fig. 3A described selective modulation scheme with respect to the falling edge of the output signal Vout. As in Fig. 3B, the delay between the input signal Vin and the output voltage Vout remains for approximately 9ps, and the voltage swing of the output voltage Vout remains for approximately 960 m, but the average current is reduced compared to the waveforms of Fig. 1B reduced to approximately 590 µA.

[0028] Alternatively, the modulated active inductor 130 may be configured to improve the time delay during the rising edge of the output signal Vout, as shown in Fig. 4A. According to the Fig. 4A, the inverter 131 may include first and second p-channel MOSFETs 141a, 141b connected in series, wherein the gate of the first p-channel MOSFET 141a is coupled between a first end of the resistor 132 and a first end of the capacitor 133 and may represent the input of the inverter 131. The gate of the second p-channel MOSFET 141b is coupled to the delayed clock signal CLK_MOD, and the drain of the first p-channel MOSFET 141a, which represents the output of the inverter 131, is coupled to a second end of the resistor 132 and provides the output signal Vout. A second end of the capacitor 133 is coupled to ground or a common potential. The source of the second p-channel MOSFET 141b is connected to a voltage source, e.g., a power supply. B. Vdd, and the drain of the second p-channel MOSFET 141b is coupled to the source of the first p-channel MOSFET 141a.In this configuration, capacitor 133 discharges when the output signal Vout is low, turning on the first p-channel MOSFET 141a. When the delayed clock signal CLK_MOD goes low, the delayed clock signal CLK_MOD turns on the second p-channel MOSFET 141b, opening a path to the positive voltage Vdd through inverter 131 to the output terminal of circuit 110. When the second inverter 113 of circuit 110 begins driving the output signal Vout high, it is assisted by inverter 131, resulting in a fast pull-up. Capacitor 133 charges through resistor 132 in the direction indicated by the arrow in . Fig. 4A until it turns off the first p-channel MOSFET 131a to deactivate the modulated active inductor 130 after the transition of the output signal. The modulated active inductor 130 can improve the time delay during a rising edge of the output signal Vout relative to the input signal Vin. By not activating the active inductor circuit 130 during the falling edge of the output voltage Vout, the power consumption can be reduced while still reducing the time delay of the output voltage Vout. The inverter 131 is connected in parallel to the second inverter 113 ( Fig. 1A) and may consequently be dimensioned such that in the case where there is no transition, i.e. Vin was at a logic low during a previous period of the clock signal CLK and remains low during a current period of the clock signal CLK, the inverter 131 does not have sufficient pull-up drive to override the pull-down drive of the second inverter 113 and thereby inappropriately change the logic state of Vout.

[0029] Fig. Figure 4B shows waveform diagrams of the input signal Vin, the output signal Vout, current, the delayed clock signal CLK_MOD, and the complementary delayed clock signal CLK_MODB of a circuit with active inductor modulation based on the rising edge of the output voltage according to various examples. As shown in Fig. 4B, the delay between the input signal Vin and the output signal Vout remains for approximately 9ps, and the voltage swing of the output signal Vout remains for approximately 960 m, but the average current is reduced compared to the waveforms of Fig. 1B reduced to approximately 610 µA.

[0030] Various examples have been disclosed herein in conjunction with the foregoing description and drawings. It is understood that it would be unreasonable to describe and illustrate verbatim every combination and subcombination of these examples. Accordingly, all examples may be combined in any manner and / or combination, and this specification, including the drawings, is to be construed as a complete written description of all combinations and subcombinations of the examples described herein and the manner and process of making and using them, and is to support claims to any such combination or subcombination.

[0031] It will be understood by those skilled in the art that the examples described herein are not limited to what has been specifically shown and described above. Furthermore, unless otherwise stated above, all accompanying drawings are not to scale. Numerous modifications and variations are possible in light of the above teachings. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 319,156

[0001] US 17 / 939,782

[0001]

Claims

[1] Active inductor modulator circuit comprising: a circuit for receiving an input signal and providing an output signal at an output terminal of the circuit based on a clock signal; a modulated active inductor coupled to the circuit to improve a time delay between the input signal and the provided output signal; and a modulation clock circuit for generating a delayed clock signal to activate the modulated active inductor prior to a transition of the output signal from a first logic state to a second logic state. [2] The active inductor modulator circuit of claim 1, wherein the modulation clock circuit is to receive the clock signal and generate the delayed clock signal, the delayed clock signal being delayed relative to the clock signal. [3] The active inductor modulator circuit of claim 1, wherein the modulated active inductor comprises an inverter, a resistor coupled in parallel to the inverter, and a capacitor coupled in series to the resistor and the inverter; and wherein the resistor and the inverter are coupled to an output terminal of the circuit that provides the output signal. [4] The active inductor modulator circuit of claim 1, wherein the modulated active inductor comprises: an inverter, a resistor coupled in parallel to the inverter, a capacitor coupled in series with the resistor, a first switch coupled to a voltage supply, and a second switch coupled to ground, the first switch and the second switch coupled to the inverter; wherein the modulation clock circuit is arranged to generate a complementary delayed clock signal that is 180 degrees out of phase with the generated delayed clock signal; and where the complementary delayed clock signal and the delayed clock signal are intended to turn on the first switch and the second switch, respectively. [5] The active inductor modulator circuit of claim 1, wherein the modulation clock circuit is to deactivate the modulated active inductor after the transition of the output signal from the first logic state to the second logic state. [6] The active inductor modulator circuit of claim 1, wherein the first logic state is a logic low state and the second logic state is a logic high state. [7] The active inductor modulator circuit of claim 6, wherein the modulated active inductor comprises an inverter including a first and a second p-channel MOSFET coupled in series, a resistor coupled between gate and drain terminals of the first p-channel MOSFET, and a capacitor coupled between the gate terminal of the first p-channel MOSFET and ground; and wherein the second p-channel MOSFET includes a gate terminal for receiving the delayed clock signal, a source terminal coupled to a voltage supply, and a drain terminal coupled to a source terminal of the first p-channel MOSFET; wherein the output signal is provided at the drain terminal of the first p-channel MOSFET. [8] The active inductor modulator circuit of claim 6, wherein the modulated active inductor comprises an inverter including first and second p-channel MOSFETs coupled in series to selectively couple the output terminal of the circuit to a voltage supply based on the delayed clock signal; wherein a gate terminal of the second p-channel MOSFET is to receive the delayed clock signal and a gate terminal of the first p-channel MOSFET is coupled via a resistor to a capacitor and to the output terminal of the circuit; wherein the first and second p-channel MOSFETs are intended to couple the output terminal of the circuit to the voltage supply before a rising edge of the output signal. [9] The active inductor modulator circuit of claim 1, wherein the first logic state is a logic high state and the second logic state is a logic low state. [10] The active inductor modulator circuit of claim 9, wherein the modulated active inductor comprises an inverter including a first and a second n-channel MOSFET coupled in series, a resistor coupled between gate and drain terminals of the second n-channel MOSFET, and a capacitor coupled between the gate terminal of the second n-channel MOSFET and ground; and wherein the first n-channel MOSFET includes a gate terminal coupled to the modulation clock circuit to receive the delayed clock signal, a source terminal coupled to ground, and a drain terminal coupled to a source terminal of the second n-channel MOSFET; wherein the output signal is provided at the drain terminal of the second n-channel MOSFET. [11] The active inductor modulator circuit of claim 9, wherein the modulated active inductor comprises an inverter including first and second n-channel MOSFETs coupled in series to selectively couple the output terminal of the circuit to ground based on the delayed clock signal; wherein a gate terminal of the first n-channel MOSFET is to receive the delayed clock signal and a gate terminal of the second n-channel MOSFET is coupled via a resistor to a capacitor and to the output terminal of the circuit; wherein the first and second n-channel MOSFETs are intended to couple the output terminal of the circuit to ground before a falling edge of the output signal. [12] A method for improving a time delay between an input signal and an output signal of a circuit, the method comprising: Receiving the input signal based on a clock signal; generating a delayed clock signal based on the clock signal; activating a modulated active inductor coupled to the circuit prior to a transition of the output signal from a first logic state to a second logic state based on the delayed clock signal; and Output the output signal which is delayed relative to the input voltage by the time delay. [13] The method of claim 12, wherein generating the delayed clock signal comprises generating the delayed clock signal such that the delayed clock signal is delayed relative to the clock signal. [14] The method of claim 12, comprising generating a complementary delayed clock signal that is 180 degrees out of phase with the delayed clock signal; and wherein activating the modulated active inductor comprises turning on the first and second switches of the modulated active inductor based on the complementary delayed clock signal and the delayed clock signal, respectively. [15] The method of claim 12, comprising deactivating the modulated active inductor circuit after the transition of the output signal from the first logic state to the second logic state. [16] The method of claim 12, wherein the first logic state is a logic low state and the second logic state is a logic high state. [17] The method of claim 16, wherein activating the modulated active inductor comprises coupling an output terminal of the circuit to a voltage supply based on the delayed clock signal prior to a rising edge of the output signal. [18] The method of claim 12, wherein the first logic state is a logic high state and the second logic state is a logic low state. [19] The method of claim 18, wherein activating the modulated active inductor comprises coupling an output terminal of the circuit to ground based on the delayed clock signal prior to a falling edge of the output signal.

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