GATE DRIVER SWITCH

Abstract

A gate driver circuit (100) for controlling a main switching element (101) connected in series with a main switching element (102) comprises: a controller (15) that outputs to a gate terminal of the main switching element (101) in a high-impedance state for a predetermined period when a drain-source voltage (Vds1) of the main switching element (101) fluctuates during a turn-on process, wherein the turn-on process period is the period from a state change of the main switching element (101) until the turn-on of the main switching element (101) is completed, wherein the state change is a change from a state in which the main switching element (101) is kept off to a state in which the main switching element (101) is in a turn-on state, and wherein the controller (15) reverses the output to the gate terminal of the main switching element (101) back to a turn-on state.after the specified period ends, wherein the switch-on process state is a state that is detected before the start of the specified period and continues a switch-on process until the switch-on of the main switching element (101) is completed; and a detector (6) that detects a time indication which serves as a trigger to start the specified period.

Description

Area

[0001] The present disclosure relates to a gate driver circuit. background

[0002] Conventionally, semiconductor elements such as insulated-gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) are used as switching elements for use in power conversion devices and the like. These switching elements each perform a switching operation by receiving an output voltage from a driver circuit. Furthermore, these switching elements cause switching loss when they are turned on and off.

[0003] It is known that in an inverter, converter, or the like including switching elements with a totem-pole configuration, when one of a pair of switching elements is turned on while current flows through a diode of the other switching element, reverse recovery occurs in the diode of the other switching element, causing a high surge voltage. This high surge voltage may exceed the withstand voltage of the switching element, destroying the switching element. Furthermore, this high surge voltage may serve as noise, causing malfunction of other devices. It is possible to suppress the occurrence of such a surge voltage by reducing the switching speed of the switching element.

[0004] It is possible to change the switching speed of a switching element by, for example, adjusting a resistance value of a gate resistor connected to a gate terminal of the switching element or adjusting a gate voltage to be applied to the gate terminal. For the switching element, it is desirable to minimize an increase in switching loss while selecting a resistance value of the gate resistor such that a surge voltage falls within a specific range where no problem is caused. For example, Patent Literature 1 discloses a technique for reducing switching noise by switching gate resistors in a transient period when switching a switching element. List of citationsPatent literature

[0005] Patent Literature 1: Japanese Patent Application Laid-Open No. 10-32976 Brief description of the inventionProblem to be solved by the invention

[0006] However, the conventional technique described above has a problem in that an additional switch and gate resistor are required to switch gate resistors, and thus a circuit increases in size.

[0007] The present disclosure has been made in view of the foregoing, and an object of the present disclosure is to obtain a gate drive circuit capable of suppressing occurrence of a surge voltage and suppressing an increase in a switching loss while suppressing an increase in the circuit size. Ways to solve the problem

[0008] To solve the problems described above and achieve the object, the present disclosure relates to a gate drive circuit in which a first main switching element and a second main switching element are connected in series, and the gate drive circuit makes the first main switching element a target to be driven. The gate drive circuit includes a controller configured to output to a gate terminal of the first main switching element in a high-resistance state for a predetermined period of time when a drain-source voltage of the first main switching element fluctuates during a turn-on period, that is, a period from a state change of the first main switching element to completion of turn-on of the first main switching element.The state change is a change from a state in which the first main switching element is kept off to a state in which the first main switching element is in an on-state, wherein the drain-source voltage of the first main switching element is completely lowered when the turning-on of the first main switching element is completed. And the controller reverses the output to the gate terminal of the first main switching element back to a turn-on operation state after the predetermined period ends. The turn-on operation state is a state detected before a start of the predetermined period, and the controller continues the turn-on operation until the turning-on of the first main switching element is completed. The gate drive circuit further includes a detector configured to detect a timing indicator that serves as a trigger for starting the predetermined period. Effects of the invention

[0009] The gate drive circuit of the present disclosure has an effect of suppressing occurrence of a surge voltage and suppressing an increase in a switching loss while suppressing an increase in the circuit size. Short description of the drawings Fig. 1 is a diagram illustrating an exemplary configuration of a gate drive circuit according to a first embodiment. Fig. 2 is a diagram illustrating an exemplary configuration of a power conversion system including the gate drive circuit according to the first embodiment. Fig. 3 is a timing chart illustrating operating states of the gate drive circuit according to the first embodiment. Fig. 4 is a timing chart illustrating an operation of the gate driving circuit according to the first embodiment. Fig. 5 is a diagram illustrating an example of a configuration of a processing circuit implementing the gate driving circuit according to the first embodiment, in a case where the processing circuit includes a processor and a memory. Fig. 6 is a diagram illustrating an example of a configuration of a processing circuit implementing the gate drive circuit according to the first embodiment, in a case where the processing circuit includes dedicated hardware. Fig. 7 is a diagram illustrating an exemplary configuration of a gate drive circuit according to a second embodiment. Fig. 8 is a diagram illustrating an exemplary configuration of a gate drive circuit according to a third embodiment. Description of embodiments

[0010] Gate driver circuits according to embodiments of the present disclosure will be described in more detail below with reference to the drawings. First embodiment.

[0011] Fig. 1 is a diagram illustrating an exemplary configuration of a gate driver circuit 100 according to a first embodiment. In a system in which the main switching element 101 and a main switching element 102 are connected in a totem pole configuration, that is, connected in series, as shown in Fig. 1; the gate driver circuit 100 makes a main switching element 101 a target to be driven. In the following description, the main switching element 101 may be referred to as a first main switching element, and the main switching element 102 may be referred to as a second main switching element. Although this is Fig. 1, another gate driver circuit 100 (not illustrated) makes the main switching element 102 a target to be driven.

[0012] Fig. 2 is a diagram illustrating an exemplary configuration of a power conversion system 200 including the gate drive circuit 100 according to the first embodiment. Fig. 2, gate driver circuits 100a to 100f have the same configuration as those in Fig. 1. In addition, main switching elements 101a to 101c have the same configuration as the gate driver circuit 100 shown in Fig. 1, and main switching elements 102a to 102c have the same configuration as that shown in Fig. 1. The power conversion system 200 is a three-phase inverter system that converts DC power supplied from a DC power supply 150 into AC power to be output to a load, such as an electric motor 160. Note that the DC power supply 150 may be composed of: a system power supply that outputs AC power; a rectifier circuit that rectifies the AC power; and the like.

[0013] The main switching elements 101 and 102 to be driven by the gate driver circuit 100 are power semiconductor elements, such as IGBTs, but may be other voltage-driven switching elements, such as MOSFETs. When each of the main switching elements 101 and 102 is formed from an IGBT, a diode is connected in antiparallel to a semiconductor that performs switching. When each of the main switching elements 101 and 102 is formed from a MOSFET, the diode to be connected in antiparallel to the semiconductor that performs switching can be replaced by a body diode of the MOSFET.

[0014] Next, a configuration of the gate drive circuit 100 that makes the main switching element 101 the target to be driven will be described with reference to Fig. 1. As an example, in the present embodiment, a general constant voltage drive circuit is used as the gate drive circuit 100. As shown in Fig. 1, the gate driver circuit 100 includes: switching elements 1 and 2; gate resistors 3 and 4; a detector 6; DC power supplies 12 and 13; and a controller 15. The controller 15 includes a control circuit 5.

[0015] The switching element 1 is a first switching element having one end connected to the DC power supply 12, i.e., a first DC power supply. The switching element 1 is capable of outputting a voltage from the other end to a gate terminal of the main switching element 101 via the gate resistor 3.

[0016] The switching element 2 is a second switching element having one end connected to the DC power supply 13, i.e., a second DC power supply. The switching element 2 is capable of outputting a voltage from the other end to the gate terminal of the main switching element 101 via the gate resistor 4.

[0017] The gate resistor 3 is a gate resistor for adjusting the switching speed of the main switching element 101.

[0018] The gate resistor 4 is a gate resistor for adjusting the switching speed of the main switching element 101.

[0019] The DC power supply 12 is the first DC power supply for applying a positive voltage to the gate terminal of the main switching element 101. The DC power supply 12 is connected to the gate terminal of the main switching element 101 via the switching element 1 and the gate resistor 3.

[0020] The DC power supply 13 is the second DC power supply for applying a negative voltage to the gate terminal of the main switching element 101. The DC power supply 13 is connected to the gate terminal of the main switching element 101 via the switching element 2 and the gate resistor 4.

[0021] In the present embodiment, switching elements 1 and 2 are, for example, MOSFETs. Here, when a first voltage V1 is defined as the positive voltage to be applied from the DC power supply 12 to the gate terminal of the main switching element 101, and a second voltage V2 is defined as the negative voltage to be applied from the DC power supply 13 to the gate terminal of the main switching element 101, the following relationship is established, as shown in Formula (1) below. V1>Mirror voltage of the main switching element101>V2

[0022] When the main switching element 101 is turned on, a gate voltage Vgs of the main switching element 101 temporarily becomes flat at a specific voltage referred to as the mirror voltage of the main switching element 101.

[0023] In the controller 15, the control circuit 5 controls the operation of the switching elements 1 and 2 to control the voltages to be applied from the gate drive circuit 100 to the gate terminal of the main switching element 101.

[0024] The controller 15 outputs an output to the gate terminal of the main switching element 101 in a high-impedance state once, that is, for a predetermined period of time, when a drain-source voltage Vds1 of the main switching element 101 fluctuates during a turn-on period. The turn-on period is a period from a state change of the main switching element 101 until the completion of turning on the main switching element 101. The state change is a change from a state in which the main switching element 101 is kept off to a state in which the main switching element 101 is in an on state. The drain-source voltage Vds1 of the main switching element 101 is completely lowered when the turning on of the main switching element 101 is completed.After the end of the predetermined period of time, the controller 15 reverses the output to the gate terminal of the main switching element 101 from the high-impedance state back to a turn-on state detected before the start of the predetermined period of time, and continues the turn-on operation until the turn-on of the main switching element 101 is completed.

[0025] In the present embodiment, by individually controlling the on / off state of switching element 1 and switching element 2, control circuit 5 of controller 15 controls the voltages to be output to the gate terminal of main switching element 101; or sets the output to the gate terminal of main switching element 101 to the high-impedance state. The operation of control circuit 5 of controller 15 will be described in detail below.

[0026] The detector 6 detects a timing signal that serves as a trigger for starting the predetermined period during which the controller 15 outputs the output to the gate terminal of the main switching element 101 in the high-impedance state. In the present embodiment, the detector 6 includes a circuit that generates a signal corresponding to a single pulse when the current flowing through the main switching element 101 enters a predetermined state by determining the state of the current flowing through the main switching element 101 based on a voltage generated in a reactor 7. This signal is an example of a reference signal for generating a timing signal for switching gate drive states of the main switching element 101.It should be noted that a timing to be detected by the detector 6 does not have to coincide with a timing of the start of the predetermined period for which the controller 15 makes the output to the gate terminal of the main switching element 101 in the high-impedance state. In fact, there is a delay time between these two timings. The delay time includes, for example, a processing time from the time the detector 6 detects a timing that serves as a trigger for starting the predetermined period until the time the detector 6 outputs a signal; and a processing time from the time the controller 15 receives the signal from the detector 6 until the time the controller 15 actually makes the output to the gate terminal of the main switching element 101 in the high-impedance state.

[0027] Outside the gate drive circuit 100, the reactor 7 may be mounted as an external component on a substrate or the like on which the main switching element 101 is mounted. Alternatively, a parasitic inductance component located on a wiring portion of the substrate on which the main switching element 101 is mounted may be used as the reactor 7.

[0028] Next, the operation of the gate driver circuit 100 will be described with reference to a timing chart of Fig. 3 described. Fig. 3 is a timing chart illustrating operating states of the gate drive circuit 100 according to the first embodiment. Fig. 3 illustrates, in order from the top: the gate voltage Vgs, which is a voltage between the gate and the source of the main switching element 101; a drive signal Vg1 with which the controller 15 turns the switching element 1 on and off; a drive signal Vg2 with which the controller 15 turns the switching element 2 on and off; a drain current Id1 of the main switching element 101; the drain-source voltage Vds1 of the main switching element 101; a drain-source voltage Vds2 of the main switching element 102; and a gate current Ig1 of the main switching element 101. Note that the horizontal axis in Fig. 3 represents the time. Fig. 4 is a timing chart illustrating an operation of the gate driving circuit 100 according to the first embodiment.

[0029] The control circuit 5 sets the drive signal Vg1 for the switching element 1 to high (H) at a time t0 to turn on the switching element 1 (step S1). As a result, the first voltage V1 is applied as the gate voltage Vgs to the gate terminal of the main switching element 101 via the gate resistor 3. Thus, the main switching element 101 is turned on at a normal switching speed. Here, the normal switching speed refers to a switching speed at which the main switching element 101 is turned on when the main switching element 101 is turned on, and the first voltage V1 is to be applied in an ON state.

[0030] When the gate voltage Vgs of the main switching element 101 reaches the mirror voltage at a time t1, the main switching element 101 changes the conduction characteristic in a state in which the gate voltage Vgs does not increase while injection of charges into the gate terminal continues.

[0031] At this time, the drain current Id1 of the main switching element 101 gradually increases. Then, at time t2, the drain current Id1 reaches a drain current Id2 that has flowed through the main switching element 102 of a counter arm. After that, the drain current Id1 of the main switching element 101 temporarily overshoots, and the current commutation is completed while accompanying oscillation damping. At this time, the detector 6 detects the timing information from the driving state of the main switching element 101, which serves as a trigger for starting the predetermined period for which the output to the gate terminal of the main switching element 101 is maintained in the high-resistance state (step S2).In the present embodiment, the detector 6 detects a change that occurs when the drain current Id1 overshoots and oscillation damping occurs, and outputs a signal to the control circuit 5 of the controller 15 indicating that the timing information serving as a trigger for starting the predetermined period has been detected only once. In practice, it is assumed that a delay time is included in a period from the time at which the detector 6 detects the change in oscillation damping of the drain current Id1 to the time at which the detector 6 outputs the signal. Furthermore, the drain-source voltage Vds1 of the main switching element 101 begins to decrease at time t2.

[0032] At a time t3, at which a response delay until the detector 6 once outputs a signal after a detection delay and a response delay of the control circuit 5 at time t2 have been added, the control circuit 5 lowers the drive signal Vg1 once, that is, for the predetermined period, to low (Low - L) and turns off the switching element 1 to perform the output from the gate drive circuit 100 to the gate terminal of the main switching element 101 in the high-resistance state (step S3). As a result, the injection of charges from the gate drive circuit 100 into the gate terminal of the main switching element 101 or a discharge from the gate terminal of the main switching element 101 to the gate drive circuit 100 is temporarily stopped. Thus, the gate current Ig1 becomes zero, as shown in Fig. 3. At this time, the conduction characteristics of the main switching element 101 temporarily stop changing. Thus, the drain-source voltage Vds1 of the main switching element 101 and the drain-source voltage Vds2 of the main switching element 102 also temporarily stop changing.

[0033] As described above, in the present embodiment, the detector 6 detects a time as the time serving as a trigger for starting the predetermined period; the detected time is a time at which the drain current Id1 reaches a peak and begins to decrease so that it converges; the peak exceeds the drain current Id2, the drain current Id1 is a first current value of a current flowing through the main switching element 101; and the drain current Id2 is a second current value of a current flowing through the main switching element 102 when the main switching element 101 is in the state where the main switching element 101 is kept off. The detector 6 outputs a signal indicating that the time serving as a trigger for starting the predetermined period has been detected to the control circuit 5 of the controller 15.At this time, upon detecting the timing that serves as a trigger for starting the predetermined period, the detector 6 outputs a pulse signal as the above-described signal for a predetermined period to the control circuit 5 of the controller 15, the pulse signal being in a state different from a state detected before the timing is detected. Note that the predetermined period for which the detector 6 outputs the pulse signal may be the same as or different from the predetermined period for which the gate drive circuit 100 outputs to the gate terminal of the main switching element 101 in the high-impedance state. The control circuit 5 of the controller 15 outputs to the gate terminal of the main switching element 101 in the high-impedance state for the predetermined period after a predetermined delay time has elapsed after receiving the signal from the detector 6.

[0034] Thereafter, when the control circuit 5 returns the drive signal Vg1 to H at a time t4, the gate drive circuit 100 resumes driving, and charge injection into the gate terminal of the main switching element 101 also resumes. Thus, the switching of the main switching element 101 is resumed. That is, after the end of the predetermined period, the control circuit 5 returns a turn-on state of the main switching element 101 to a turn-on state established before the start of the predetermined period (step S4).

[0035] Thereafter, the drain-source voltage Vds1 of the main switching element 101 further decreases. Then, at time t5, the drain-source voltage Vds1 of the main switching element 101 completely decreases to 0 to several volts, which corresponds to the turn-on voltage of the main switching element 101, and the drain-source voltage Vds2 of the main switching element 102 coupled to the main switching element 101 is maximized. At this time, a surge voltage, a ringing voltage, and the like of the drain-source voltage Vds2 of the main switching element 102 are low, and the convergence of the voltage oscillation proceeds quickly, unlike a general switching method.

[0036] Note that in the present embodiment, since a switching operation of the main switching element 101 is temporarily stopped halfway through the switching operation, an increase in the switching loss of the main switching element 101 is caused. However, a period from time t3 to time t4 is from tens of nanoseconds to several hundred nanoseconds or less. Thus, the impact on the loss is small.

[0037] In addition, since the gate drive circuit 100 does not extract gate charges by outputting a negative voltage as a turn-off pulse, the conduction characteristics of the main switching element 101 do not deteriorate and an increase in loss is small.

[0038] Furthermore, it is possible to minimize deterioration of the switching loss of the main switching element 102 by setting a timing at which a step of the drain-source voltage Vds2 of the main switching element 102 occurs to a timing near time t5, that is, near a timing at which the drain-source voltage Vds1 of the main switching element 101 becomes 0 V.

[0039] Moreover, since the speed of charge injection into the gate terminal of the main switching element 101 in a period other than the period from time t3 to time t4 is the same as that in the normal switching operation, the switching loss of the main switching element 101 in the period other than the period from time t3 to time t4 does not deteriorate.

[0040] As described above, the gate drive circuit 100 can suppress an increase in switching loss in the main switching element 101 and the main switching element 102 while suppressing the occurrence of a ringing voltage in the main switching element 102 without requiring a switching device that switches gate resistors.

[0041] Next, a hardware configuration of the gate drive circuit 100 according to the first embodiment will be described. In the gate drive circuit 100, switching elements 1 and 2 are semiconductor elements such as MOSFETs as described above. Gate resistors 3 and 4 are resistors with desired resistance values. DC power supplies 12 and 13 are power supply circuits capable of outputting DC power. The detector 6 and the control circuit 5 are implemented by a processing circuit. The processing circuit may be a memory in which programs are stored and a processor that executes the programs stored in the memory. Alternatively, the processing circuit may be dedicated hardware.

[0042] Fig. Fig. 5 is a diagram illustrating an example of a configuration of a processing circuit 90 implementing the gate drive circuit 100 according to the first embodiment in a case where the processing circuit 90 includes a processor 91 and a memory 92. Fig. The processing circuit 90 illustrated in FIG. 5 includes the processor 91 and the memory 92. In a case where the processing circuit 90 includes the processor 91 and the memory 92, each function of the processing circuit 90 is implemented by software, firmware, or a combination of software and firmware. The software or firmware is written as a program and stored in the memory 92. In the processing circuit 90, the processor 91 reads the program stored in the memory 92 and executes it to implement each function. That is, the processing circuit 90 includes the memory 92 for storing a program that consequently causes the processing to be performed in the gate drive circuit 100. It can also be said that this program is a program for causing the gate drive circuit 100 to execute each function to be implemented by the processing circuit 90.This program may be provided by means of a storage medium on which the program has been stored, or may be provided by other means, such as a communications medium.

[0043] Here, the processor 91 is, for example, a central processing unit (CPU), a processing device, a computing device, a microprocessor, a microcomputer, or a digital signal processor (DSP). Further, examples of the memory 92 include non-volatile or volatile semiconductor memories such as random access memory (RAM), read-only memory (ROM), flash memory, erasable programmable ROM (EPROM), and electrical EPROM (EEPROM (registered trademark)), a magnetic disk, a floppy disk, an optical disk, a compact disc, a mini disc, and a digital versatile disc (DVD).

[0044] Fig. 6 is a diagram illustrating an example of a configuration of a processing circuit 93 implementing the gate drive circuit 100 according to the first embodiment in a case where the processing circuit 93 is implemented by dedicated hardware. Fig. Processing circuitry 93 illustrated in Figure 6 corresponds, for example, to a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a combination thereof. Part of processing circuitry 93 may be implemented by dedicated hardware, and another part of processing circuitry 93 may be implemented by software or firmware. Thus, processing circuitry 93 may implement any of the functions described above using dedicated hardware, software, firmware, or a combination thereof.

[0045] As described above, the gate drive circuit 100 according to the present embodiment outputs to the gate terminal of the main switching element 101 for a predetermined period in a high-resistance state when the drain-source voltage Vds1 of the main switching element 101 fluctuates during the turn-on period. The turn-on period is a period from a state change of the main switching element 101 until the completion of turning on the main switching element 101. The state change is a change from a state in which the main switching element 101 is kept off to a state in which the main switching element 101 is in an on state. The drain-source voltage Vds1 of the main switching element 101 is completely lowered when the turning on of the main switching element 101 is completed.After the end of the predetermined period, the gate drive circuit 100 returns the output to the gate terminal of the main switching element 101 to a turn-on state established before the start of the predetermined period and continues the turn-on operation until the turn-on of the main switching element 101 is completed. As a result, the gate drive circuit 100 can suppress the occurrence of a surge voltage of the main switching element 102 and suppress an increase in the switching loss of the main switching elements 101 and 102, while suppressing an increase in size in the system in which the main switching elements 101 and 102 are connected in series.

[0046] In the present embodiment, while attempting to achieve a switching loss equivalent to that in the case of a general driving method by first using the normal first voltage V1, the gate drive circuit 100 brings the output to the gate terminal of the main switching element 101 into a high-impedance state during a change in the drain-source voltage Vds1 of the main switching element 101 after the gate voltage Vgs of the main switching element 101 reaches a mirror voltage. As a result, a change in the drain-source voltage Vds2 caused in the main switching element 102 coupled to the main switching element 101 temporarily stops while the voltage increases. Thereafter, the gate drive circuit 100 returns the output to the gate terminal of the main switching element 101 to a driving state established before the output to the gate terminal was brought into the high-impedance state.As a result, compared with a general driving method, it is possible to suppress an increase in switching loss in the main switching elements 101 and 102 while suppressing the occurrence of a ringing voltage in the main switching element 102. Second embodiment.

[0047] In a second embodiment, a case is described in which a controller includes a buffer in a gate driver circuit.

[0048] Fig. 7 is a diagram illustrating an exemplary configuration of a gate driver circuit 110 according to the second embodiment. The gate driver circuit 110 drives the main switching element 101 in a system in which the main switching elements 101 and 102 are connected in a totem pole configuration, that is, connected in series, as shown in Fig. 7. It should be noted that, although not illustrated, the gate driver circuit 110, like the gate driver circuit 100 of the first embodiment, is based on the Fig. 2 illustrated power conversion system 200 can be applied.

[0049] The controller 15 in the gate driver circuit 100 of the first embodiment was replaced by a controller 15a to implement the gate driver circuit 110 of the second embodiment. The controller 15a includes a control circuit 5a and a buffer 9.

[0050] The control circuit 5a outputs control signals for controlling the on / off state of the switching elements 1 and 2. Unlike the control circuit 5 of the first embodiment, the control circuit 5a controls the operation of the switching elements 1 and 2 via the buffer 9. In general, the control circuit 5a often does not output the current and voltage necessary to drive the switching elements 1 and 2. Therefore, the controller 15a amplifies the control signals input from the control circuit 5a via the buffer 9 and controls the operation of the switching elements 1 and 2.

[0051] Buffer 9 amplifies the control signals input from control circuit 5a to turn switching elements 1 and 2 on and off. Buffer 9 is, for example, a buffer circuit including a half-bridge driver integrated circuit (IC) or the like. Furthermore, in the present embodiment, buffer 9 includes a control terminal, referred to as an enable terminal or reset terminal. Buffer 9 can lower both outputs from buffer 9 to switching elements 1 and 2 to L due to the logical operation of the control terminal. Note that Fig. 7 illustrates an example in which the buffer 9 includes an enable terminal.

[0052] The detector 6 performs the same operation as in the first embodiment. Meanwhile, the detector 6 outputs a signal indicating that a timer serving as a trigger for starting a predetermined period has been detected, not to the control circuit 5a, but to the enable terminal of the buffer 9.

[0053] The buffer 9 has a function of controlling the operation of the switching elements 1 and 2 and bringing an output to the gate terminal of the main switching element 101 into a high-impedance state based on the signal obtained from the detector 6, the signal indicating that the time information serving as a trigger for starting the predetermined period has been detected. The enable terminal included in the buffer 9 is originally a control terminal to be used when, for example, an abnormality occurs or control power is lost. However, in the present embodiment, the signal output from the detector 6 is intentionally directed to the enable terminal of the buffer 9. As a result, the buffer 9 can provide both outputs on a high side and a low side, that is,, both outputs to the switching elements 1 and 2, to L and can bring the output from the gate driver circuit 110 to the gate terminal of the main switching element 101 into the high-impedance state.

[0054] The other components operate in the same manner as in the first embodiment. Furthermore, the controller 15a of the second embodiment operates in the same manner as the controller 15 of the first embodiment. Therefore, the description of the specific operation of each component is omitted.

[0055] As described above, the gate drive circuit 110 according to the present embodiment is configured such that the controller 15a includes the control circuit 5a and the buffer 9. In this case, too, the same effects as those of the gate drive circuit 100 of the first embodiment can be achieved. Furthermore, the gate drive circuit 110 is configured such that the buffer 9 receives a signal from the detector 6. As a result, an existing control circuit can be used as the control circuit 5a. Moreover, since there is no response delay, a high-speed response can be achieved. Thus, the switching of the high-resistance state can also be accelerated. Third embodiment.

[0056] In the first and second embodiments, the gate drive circuits of a constant-voltage drive system were described. In a third embodiment, a gate drive circuit using a constant-current circuit is described.

[0057] Fig. Fig. 8 is a diagram illustrating an exemplary configuration of a gate driver circuit 120 according to the third embodiment. The gate driver circuit 120 drives the main switching element 101 in a system in which the main switching elements 101 and 102 are connected in a totem pole configuration, that is, connected in series, as shown in Fig. 8. It should be noted that, although not illustrated, the gate driver circuit 120, like the gate driver circuit 100 of the first embodiment, is based on the Fig. 2 illustrated power conversion system 200 can be applied.

[0058] The gate drive circuit 120 of the third embodiment includes the detector 6, constant current circuits 10 and 11, DC power supplies 12 and 13, and a controller 15b. The controller 15b includes a control circuit 5b.

[0059] The constant current circuit 10 is a first constant current circuit having one end connected to the DC power supply 12 and capable of outputting a current from another end to the gate terminal of the main switching element 101.

[0060] The constant current circuit 11 is a second constant current circuit having one end connected to the DC power supply 13 and capable of outputting a current from another end to the gate terminal of the main switching element 101.

[0061] The control circuit 5b of the controller 15b controls currents to be output to the gate terminal of the main switching element 101 or outputs to the gate terminal of the main switching element 101 in a high-impedance state by individually controlling the constant current circuits 10 and 11. Specifically, the control circuit 5b controls a current to be output from the constant current circuit 10 to the gate terminal of the main switching element 101 using a current command value Ig10 for the constant current circuit 10. Furthermore, the control circuit 5b controls a current to be output from the constant current circuit 11 to the gate terminal of the main switching element 101 using a current command value Ig11 for the constant current circuit 11.At this time, the control circuit 5b sets the current command value Ig10 for the constant current circuit 10 and the current command value Ig11 for the constant current circuit 11 such that both the current command value Ig10 and the current command value Ig11 are 0 A (zero amperes). As a result, the injection of charges into or discharge from the gate terminal of the main switching element 101 is temporarily stopped, allowing the output to the gate terminal of the main switching element 101 to be brought into the high-impedance state. As with the control circuit 5 of the first embodiment, the control circuit 5b brings the output to the gate terminal of the main switching element 101 into the high-impedance state based on a signal from the detector 6.Note that, with respect to the current command value Ig10 for the constant current circuit 10 and the current command value Ig11 for the constant current circuit 11, the control circuit 5b may output signals to instruct the constant current circuit 10 and the constant current circuit 11 to stop outputting currents, instead of instructing each of the constant current circuit 10 and the constant current circuit 11 to output a current of 0 A (zero amperes).

[0062] The gate drive circuit 120 differs from the gate drive circuit 100 of the first embodiment in that the gate drive circuit 120 controls the output of currents to the gate terminal of the main switching element 101, while the gate drive circuit 100 of the first embodiment controls the output of voltages to the gate terminal of the main switching element 101. Meanwhile, the gate drive circuit 120 is similar in operation to the gate drive circuit 100 of the first embodiment. Therefore, the description of the specific operation of each component is omitted.

[0063] As described above, the gate drive circuit 120 in the present embodiment brings the output to the gate terminal of the main switching element 101 into the high-impedance state by using the constant current circuits 10 and 11 to control the output of currents to the gate terminal of the main switching element 101. Also in this case, the gate drive circuit 120 can achieve the same effects as those of the gate drive circuit 100 of the first embodiment. Fourth embodiment.

[0064] In a fourth embodiment, another detection method is described in which the detector 6 detects a timer that serves as a trigger for starting a predetermined period based on the drive state of the main switching element 101. Here, the gate drive circuit 100 of the first embodiment is described as an example, but the present embodiment is also applicable to the gate drive circuit 110 of the second embodiment and the gate drive circuit 120 of the third embodiment.

[0065] For example, the detector 6 detects the timing for entering a mirror region based on a change in the gate voltage Vgs of the main switching element 101. Furthermore, the control circuit 5 estimates a timing at which the drain-source voltage Vds1 of the main switching element 101 changes later than the detected timing, outputs a single-pulse signal, and sets the output to the gate terminal of the main switching element 101 in a high-impedance state. Thus, the same effects as in the first embodiment can be achieved.

[0066] That is, the detector 6 can detect a time as the time serving as a trigger for starting the predetermined period, and can output to the control circuit 5 of the controller 15 a signal indicating that the time serving as a trigger for starting the predetermined period has been detected, the detected time being a time at which a change amount of the gate voltage Vgs has decreased to enter the mirror region, the gate voltage Vgs being applied to the main switching element 101, the gate voltage Vgs being a mirror voltage in the mirror region.At this time, upon detecting the timing that serves as a trigger for starting the predetermined period, the detector 6 outputs a pulse signal as the above-described signal to the control circuit 5 of the controller 15 for a predetermined period of time, the pulse signal being in a state different from a state detected before detecting the timing. In this case, the control circuit 5 of the controller 15 assumes that the drain-source voltage Vds1 of the main switching element 101 has started to decrease upon receiving the signal from the detector 6, and outputs to the gate terminal of the main switching element 101 in the high-impedance state for the predetermined period of time after a predetermined delay time has elapsed after receiving the signal from the detector 6.

[0067] It should be noted that the operation of assuming that the drain-source voltage Vds1 of the main switching element 101 has started to decrease may be performed not by the control circuit 5 of the controller 15 but by the detector 6.

[0068] Furthermore, the detector 6 detects the drain-source voltage Vds1 of the main switching element 101 to determine a time at which the drain-source voltage Vds1 has changed, and causes the control circuit 5 to output a single-pulse signal according to the change to bring the output to the gate terminal of the main switching element 101 into a high-impedance state. Thus, the same effects as in the first embodiment can be achieved.

[0069] That is, the detector 6 can detect a timing at which the drain-source voltage Vds1 applied to the main switching element 101 has started to decrease as the timing serving as a trigger for starting the predetermined period, and can output a signal indicating that the timing serving as a trigger for starting the predetermined period has been detected to the control circuit 5 of the controller 15. At this time, the detector 6, upon detecting the timing serving as a trigger for starting the predetermined period, outputs a pulse signal as the above-described signal for a predetermined period to the control circuit 5 of the controller 15, the pulse signal being in a state different from a state established before the timing was detected.In this case, the control circuit 5 of the controller 15 outputs to the gate terminal of the main switching element 101 in the high-resistance state for the predetermined period of time after a predetermined delay time has elapsed after receiving the signal from the detector 6.

[0070] Note that the circuit configurations of the gate drive circuits described in the first to fourth embodiments are not limited to those described above. The gate drive circuit may have any circuit configuration as long as it is possible to bring a gate-source path of the main switching element 101 to be driven into a high-impedance state for only a single moment.

[0071] The configurations set forth in the above embodiments are examples, and it is possible to combine the configurations with other known techniques or to combine the embodiments with each other, and it is also possible to partially omit or change the configurations without departing from the scope of the present disclosure. List of reference symbols

[0072] 1, 2 switching element; 3, 4 gate resistor; 5, 5a, 5b control circuit; 6 detector; 7 reactor; 9 buffer; 10, 11 constant current circuit; 12, 13, 150 DC power supply; 15, 15a, 15b controller; 90, 93 processing circuit; 91 processor; 92 memory; 100, 100a to 100f, 110, 120 gate drive circuit; 101, 101a to 101c, 102, 102a to 102c main switching element; 160 electric motor; 200 power conversion system. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 10-32976

[0005]

Claims

[1] A gate driving circuit configured to make a first main switching element a target to be driven, the first main switching element and a second main switching element being connected in series, the gate driving circuit comprising: a controller configured to: Making an output to a gate terminal of the first main switching element for a predetermined period in a high-resistance state when a drain-source voltage of the first main switching element fluctuates during a turn-on period, ie, a period from a state change of the first main switching element to completion of turning on the first main switching element, wherein the change of state is a change from a state in which the first main switching element is kept off to a state in which the main switching element is in an on state, the drain-source voltage of the first main switching element is completely lowered when the switching-on of the first main switching element is completed: and reversing the output to the gate terminal of the first main switching element back to a turn-on state after the predetermined period of time ends, the turn-on state being a state detected before a start of the predetermined period of time, and continuing a turn-on operation until the turn-on of the first main switching element is completed; and a detector configured to detect a time cue that serves as a trigger to start the specified period. [2] The gate driver circuit of claim 1, further comprising: a first switching element having one end connected to a first DC power supply, the first switching element being capable of outputting a voltage from another end to the gate terminal of the first main switching element; and a second switching element, one end of which is connected to a second DC power supply, the second switching element being capable of outputting a voltage from another end to the gate terminal of the first main switching element, wherein by individually controlling the on / off state of the first switching element and the second switching element, the controller is configured to: Controlling the voltages to be output to the gate terminal of the first main switching element; or Making the output to the gate terminal of the first main switching element in the high resistance state. [3] A gate driver circuit according to claim 2, wherein the controller includes: a control circuit configured to output control signals for controlling the on-off state of the first switching element and the second switching element; and a buffer configured to turn the first switching element and the second switching element on and off by amplifying the control signals, and the buffer has a function of controlling an operation of the first switching element and the second switching element and outputting to the gate terminal of the first main switching element in the high-impedance state based on a signal obtained from the detector, the signal indicating that the time information serving as a trigger for starting the predetermined period has been detected. [4] The gate driver circuit of claim 1, further comprising: a first constant current circuit having one end connected to a first DC power supply, the first constant current circuit capable of outputting a current from another end to the gate terminal of the first main switching element; and a second constant current circuit having one end connected to a second DC power supply, the second constant current circuit being capable of outputting a current from another end to the gate terminal of the first main switching element, wherein by individually controlling the first constant current circuit and the second constant current circuit, the controller is configured to: Controlling the currents to be output to the gate terminal of the first main switching element; or Making the output to the gate terminal of the first main switching element in the high resistance state. [5] A gate driver circuit according to any one of claims 1 to 4, wherein the detector is configured to: Capturing a time specification as the time specification that serves as the trigger for starting the specified period; and Outputting, to the controller, a signal indicating that the timing serving as the trigger for starting the predetermined period of time has been detected, wherein the detected timing is a timing at which a first current value reaches a peak and begins to decrease so as to converge, the peak exceeding a second current value, wherein the first current value is a current value of a current flowing through the first main switching element, wherein the second current value is a current value of a current flowing through the second main switching element when the first main switching element is in the state in which the first main switching element is kept off, and the controller is configured to output to the gate terminal of the first main switching element in the high-impedance state for the predetermined period of time after a predetermined delay time has elapsed after receiving the signal. [6] A gate driver circuit according to any one of claims 1 to 4, wherein the detector is configured to: Capturing a time specification as the time specification that serves as the trigger for starting the specified period; and Outputting, to the controller, a signal indicating that the timing serving as the trigger for starting the predetermined period of time has been detected, wherein the detected timing is a timing at which the drain-source voltage starts to decrease, the drain-source voltage being applied to the first main switching element, and the controller is configured to output to the gate terminal of the first main switching element in the high-impedance state for the predetermined period of time after a predetermined delay time has elapsed after receiving the signal. [7] A gate driver circuit according to any one of claims 1 to 4, wherein the detector is configured to: Capturing a time specification as the time specification that serves as the trigger for starting the specified period; and Outputting, to the controller, a signal indicating that the time serving as the trigger for starting the predetermined period of time has been detected, wherein the detected time is a time at which a change amount of the gate voltage has decreased to enter a mirror region, wherein the gate voltage is applied to the first main switching element, wherein the gate voltage is a mirror voltage in the mirror region, and upon receiving the signal, the controller is configured to: Assume that the drain-source voltage of the first main switching element has started to decrease; and Making the output to the gate terminal of the first main switching element in the high-impedance state for the predetermined period of time after a predetermined delay time has elapsed after receiving the signal. [8] The gate drive circuit according to any one of claims 5 to 7, wherein the detector, when the timing serving as the trigger for starting the predetermined period of time is detected, is configured to output a pulse signal as the signal to the controller for a predetermined period of time, the pulse signal being in a state different from a state detected before the timing is detected.

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