OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING AN OPTOELECTRONIC DEVICE

Abstract

The invention relates to an optoelectronic device comprising an epitaxially grown functional layer stack and an electrically conductive contact layer arranged on the functional layer stack. The functional layer stack comprises a first layer doped with a first conductivity type; an active region arranged on the first layer; a second layer doped with a second conductivity type, arranged on the active region; and a third layer doped with the second conductivity type, arranged on the second layer, wherein the third layer has a higher concentration of the second conductivity type dopant than the second layer. The functional layer stack is laterally bounded by side faces of the functional layer stack and comprises a central region along a centerline of the functional layer stack, the central region being spaced apart from the side faces.A current path from the electrically conductive contact layer through the third layer to the second layer is limited to the central area.

Description

[0001] The present invention relates to an optoelectronic device and a method for producing an optoelectronic device. background

[0002] Optoelectronic devices, also known as light-emitting diodes (LEDs), require a power supply for illumination. Charge carriers introduced into an active zone of the optoelectronic device recombine, emitting light.

[0003] A well-known problem for light-emitting diodes, especially for very small LEDs such as µ-LEDs, whose size is in the range of less than 1000 µm 2 and up to about 10 µm 2However, the efficient generation and extraction of light is a major challenge. On the one hand, manufacturing-related impurities on the side surfaces of optoelectronic devices can lead to (efficiency) losses due to non-radiative recombination of charge carriers. On the other hand, a large portion of the internally generated light can be trapped in the LED structure, since only a small portion of the internally generated light can be extracted from the LED via direct emission from the active zone or internal reflections. The trapped light must then be extracted from the LED, for example, using suitable extraction structures.

[0004] The object of the invention is therefore to counteract at least one of the aforementioned problems and to provide a correspondingly improved optoelectronic device. It is also an object of the invention to provide a method for producing a correspondingly improved device. Summary

[0005] These and other requirements are met by an optoelectronic device having the features of independent claim 1 and a method for producing an optoelectronic device having the features of independent claim 14. Embodiments and further developments of the invention are described in the dependent claims.

[0006] The inventors' concept is to implement a current confinement for an epitaxially grown functional semiconductor layer stack such that a charge carrier flow within the layer stack is centered on a central region of the functional layer stack. This reduces the charge carrier density along the side surfaces of the layer stack, and impurities along the side surfaces have no or less significant influence on (efficiency) losses due to non-radiative recombination of the charge carriers. The functional layer stack and / or an electrically conductive contact layer arranged on the functional layer stack is therefore modified / configured such that a current path from the electrically conductive contact layer through the layer stack is formed only in a central region of the layer stack.In order to additionally achieve an improved coupling out of light generated in the layer stack, several possibilities of coupling-out structures on a surface of the layer stack facing the conductive contact layer are proposed.

[0007] According to one aspect, an epitaxially grown functional layer stack is provided with an electrically conductive contact layer, which is arranged on the functional layer stack and together forms an optoelectronic device. The functional layer stack comprises a first layer doped with a first conductivity type, an active region, a second layer doped with a second conductivity type, and a third layer doped with the second conductivity type. The functional layer stack is laterally bounded by side surfaces of the functional layer stack, and the functional layer stack comprises a central region along a center line of the functional layer stack, wherein the center line extends in a growth direction of the functional layer stack.The central region is defined such that it is spaced apart from the side surfaces of the functional layer stack, forming a "true" central region of the functional layer stack that only forms a partial region of the functional layer stack. The third layer has a higher doping concentration of the second conductivity type than the second layer and acts as a current spreading layer, but its current spreading function is limited to the central region of the functional layer stack. This is because the functional layer stack is modified / configured such that a current path extending from the electrically conductive contact layer through the third layer to the second layer is limited to the central region.

[0008] The functional layer stack comprises, in particular, a layer stack of epitaxially grown layers with an active region arranged between the first and second layers. The first layer can, for example, be a p-doped layer, and the second layer can be an n-doped layer. In this case, the third layer can be a highly n-doped cap layer of the functional layer stack in order to establish electrical contact with the electrically conductive contact layer (metal, TCO, etc.) applied to the functional layer stack. High doping of the third layer generally results in good lateral current propagation into the functional layer stack. To achieve current limitation to the central region of the layer stack, structuring the electrically conductive contact layer may not be sufficient, since lateral current propagation can also occur within the third layer.Therefore, the highly doped n-epi cap layer must be a) removed in a region outside the central region, or b) discontinuously separated to form an electrically isolated central region to suppress lateral current propagation within the third layer.

[0009] The optoelectronic device is, for example, a radiation-emitting optoelectronic semiconductor chip. The semiconductor chip can be, for example, a light-emitting diode (LED) or a laser chip. The optoelectronic semiconductor chip can generate light during operation. In particular, it is possible for the optoelectronic semiconductor chip to generate light in the spectral range from UV radiation to light in the infrared range, in particular visible light. Alternatively, it is possible for the optoelectronic semiconductor chip to be a radiation-detecting semiconductor chip, for example, a photodiode.

[0010] The optoelectronic device can, for example, have edge lengths of less than 100 µm, or less than 40 µm, in particular less than 10 µm. The optoelectronic semiconductor chip can therefore be, for example, a µLED (LED for light-emitting device, µLED for micro-LED) or a µLED chip. For such small optoelectronic devices, current limitation to reduce (efficiency) losses due to non-radiative recombination of charge carriers caused by impurities along the side surfaces of the device is not yet known. However, the proposed principle offers a solution to this problem.

[0011] In some cases, the third layer is confined to the central region to limit the current to the central region of the layer stack. The third layer can be removed, particularly in a region outside the central region, to suppress lateral current propagation into the remote region of the third layer compared to a full third layer.

[0012] In some aspects, the third layer comprises at least one interruption, wherein the at least one interruption divides the third layer into at least a first and a second region that are separated from one another. The first and second regions are, in particular, electrically isolated from one another within the third region. The first region is limited to the central region, thereby current-limiting the central region of the layer stack.

[0013] In some aspects, the electrically conductive contact layer electrically contacts the third layer only in the central region. The electrically conductive contact layer can, for example, be limited to the central region of the functional layer stack or extend beyond the central region but only electrically contact the third layer in the central region. In some aspects, the electrically conductive contact layer is arranged only in the central region on the third layer and is thus limited to the central region of the functional layer stack.

[0014] In some aspects, the optoelectronic device, and in particular the functional layer stack, further comprises a p-type dopant, such as Zn (zinc), deposited in an edge region of the active region, in particular in a region outside the central region, thereby creating quantum well intermixing (QWI). The efficiency of, for example, very small optoelectronic InGaAlP devices can thereby be further improved. Such a QWI is particularly preferred outside the central region to further enhance the effect already created by confinement. The QWI increases the band gap of the quantum wells in this outer region near the side surfaces of the layer stack, so that the charge carriers in the quantum wells can no longer reach the side surfaces near the quantum wells, which further increases the efficiency of such very small LEDs.

[0015] To further achieve improved coupling of the light generated in the layer stack, various options for coupling-out structures are proposed on a surface of the layer stack facing the conductive contact layer. By using a coupling-out structure as proposed below, improved coupling of the light generated in the active zone can also be achieved for small optoelectronic devices such as LEDs, in particular p-LEDs, whose size is in the range of less than 1000 µm. 2 and up to about 10 µm 2 can go down.

[0016] In some aspects, the third layer or the third layer and the second layer comprise a first surface structuring on a surface facing the electrically conductive contact layer, having a plurality of protrusions and trenches, wherein the first surface structuring serves as an outcoupling structure on the third layer to improve the outcoupling efficiency of light generated within the optoelectronic device. The protrusions and trenches of the first surface structuring can be homogeneously distributed, but can also have an inhomogeneous / random distribution. The protrusions of the first surface structuring can all have the same height, or their height can vary for all or only some of the protrusions.

[0017] In some aspects, the elevations of the first surface structuring in the central region are higher than the elevations of the first surface structuring outside the central region. As a result, the electrically conductive contact layer, which extends, for example, over the entire third layer, can contact the third layer and, in particular, the elevations of the first surface structuring of the third layer only in the central region. "Higher" in this context can be understood, in particular, to mean that the upper level of the projections outside the central region is higher than the upper level of the projections within the central region.

[0018] In some aspects, the protrusions of the first surface structuring have, at least in the central region, a planarized surface facing the electrically conductive contact layer. In particular, protrusions that contact the electrically conductive contact layer have a planarized surface facing the electrically conductive contact layer. Such a planarized surface can result, for example, from planarizing the protrusions to create a contact surface for the electrically conductive contact layer.

[0019] In some aspects, the projections of the first surface structuring contact the electrically conductive contact layer at least in the central region.

[0020] In some aspects, the second layer comprises a second surface structuring on a surface facing the electrically conductive contact layer, having a plurality of protrusions and trenches, in particular in a region outside the central region. The second surface structuring can be arranged, in particular, in a region outside the central region in which the third layer is removed, and can serve as an outcoupling structure on the second layer to improve the outcoupling efficiency of the light generated in the optoelectronic device. The protrusions and trenches of the second surface structuring can be homogeneously distributed, but can also have an inhomogeneous / random distribution. The protrusions of the second surface structuring can all have the same height, or their height can vary for all or only some of the protrusions.

[0021] The first and / or second surface structuring may correspond to a roughening of the third and / or second layer and may be selected / generated with regard to the desired requirement and the desired coupling-out properties.

[0022] In some aspects, the optoelectronic device further comprises a planarization layer arranged on the third and / or second layer. The planarization layer, in particular, fills the at least one interruption and / or the trenches of the first and / or second surface structuring and / or covers the first and / or second surface structuring at least in a region outside the central region. The planarization layer is, in particular, made of a transparent material in order to allow light generated in the optoelectronic device to pass through the planarization layer. In the event that the planarization layer covers the first and / or second surface structuring, the planarization layer additionally has a low refractive index in order to further improve, or at least not counteract, the outcoupling efficiency improved by the first and / or second surface structuring.

[0023] In some aspects, the planarization layer consists of an electrically insulating material. This allows a region of the third and optionally second layer outside the central region to be electrically insulated from the electrically conductive contact layer, particularly if the electrically conductive contact layer extends across the entire functional layer stack.

[0024] In some aspects, the planarization layer covers the entire functional layer stack, while in some aspects, the planarization layer covers the functional layer stack only in the central region. In the latter case, the planarization layer may also be made of a transparent conductive material such as indium tin oxide (ITO).

[0025] In some aspects, the central region is limited to half the distance between two opposite side surfaces of the functional layer stack. The central region may, in particular, be a partial region of the functional layer stack that extends along a center line of the functional layer stack, wherein the central region is smaller than the rest of the functional layer stack and, in particular, amounts to less than half of the functional layer stack.

[0026] In some aspects, the distance between the central region and an adjacent side surface is on the order of the mean free path of the mobile charge carriers of the functional layer stack. This can suppress recombination of charge carriers near the side surfaces. In some aspects, the distance between the central region and an adjacent side surface is between 500 nm and 2500 nm, between 500 nm and 2000 nm, or between 500 nm and 1500 nm.

[0027] In some aspects, the first layer and / or the second layer and / or the third layer comprises a base material selected from the group consisting of: - GaN; - AlGaN; - AlGaInP; - AlGaInN; and - AlGaP.

[0028] Other materials can also be used. The first layer and / or the second layer consist, in particular, of epitaxially grown layers.

[0029] Some other aspects relate to a method for producing at least one optoelectronic device. In a first step, a functional layer stack is provided, comprising a first layer with a doping of a first conductivity type, an active region arranged on the first layer, a second layer with a doping of a second conductivity type arranged on the active region, and a third layer with the doping of the second conductivity type arranged on the second layer, wherein the third layer has a higher concentration of the doping of the second conductivity type than the second layer.The functional layer stack is laterally delimited by side surfaces of the functional layer stack and comprises a central region along a centerline of the functional layer stack, wherein the central region is spaced from the side surfaces and forms a sub-region of the functional layer stack. An electrically conductive contact layer is then provided on the third layer, so that a current path from the electrically conductive contact layer through the third layer to the second layer is confined to the central region.

[0030] In some aspects, the method further comprises removing or thinning the third layer in a region outside the central region, or the method further comprises creating at least one discontinuity in the third layer such that the at least one discontinuity divides the third layer into at least a first and a second, separate region, wherein the first region is limited to the central region. The removal or creation of the discontinuity may occur after the functional layer stack has been grown, for example, on a wafer and after the functional layer stack has been removed from the wafer and transported to a final destination. The removal or creation of the discontinuity may comprise an etching process and / or photolithographic processes.

[0031] In some aspects, the method further comprises roughening a surface of the third layer facing the electrically conductive contact layer to create a first surface structuring having a plurality of protrusions and trenches.

[0032] In some aspects, the method further comprises roughening a surface of the second layer facing the electrically conductive contact layer, in particular in a region outside the central region in which the third layer was removed, in order to create a second surface structuring having a plurality of projections and trenches.

[0033] The steps of removing or thinning the third layer, creating at least one discontinuity in the third layer, roughening a surface of the third layer, and / or roughening a surface of the second layer can, for example, be performed in one and the same process. This can be achieved, for example, by exploiting loading effects in dry etching processes. Large structures are etched faster / deeper than small structures, so that the creation of a roughening and the creation of, for example, at least one discontinuity can occur at the same time, resulting in the respective structures.

[0034] The roughening of the second and / or third layer can be achieved by etching and / or photolithographic processes. The roughening can, for example, be applied over the entire surface of the third layer facing the electrically conductive contact layer, or only in the central region, or only in the vicinity of the central region.

[0035] Roughening can be achieved, for example, by "pufferfishing / natural lithography" of OSRAM thin-film products or by photolithographic processes followed by etching processes. To avoid far-field features due to regular surface patterns (photonic grating), it can be advantageous to arrange the structures / protrusions randomly. Etching can be performed through "holes" in the surface of the third and / or second layer or through residual areas (etching all but certain areas). Etching resulting in shaped / angled sidewalls (e.g., pyramids vs. pillars) has been found to be advantageous, as has etching all but certain areas. Furthermore, feature sizes with a CD (critical dimension, e.g., top surface diameter) below 1 µm have been found to be advantageous.

[0036] The roughening of the third layer can, for example, occur after at least a portion of the electrically conductive contact layer has been applied to the third layer, particularly to the third layer in the central region. For example, AuGe can be deposited on the third layer in the central region prior to roughening using photolithographic and etching processes. The roughening process can be carried out in such a way that portions of the metal remain on the resulting protrusions in the third layer (AuGe is only present on the tips of the remaining pyramids and contacts the third layer). In a further step and to complete the electrically conductive contact layer, the AuGe portions can be connected by subsequent deposition of a conductive material, such as a transparent conductive oxide (TCO).

[0037] The step of providing the electrically conductive contact layer may comprise applying thin metal layers and / or a layer of a TCO to the third layer and in particular to projections of the first surface structuring.

[0038] In some aspects, the method further comprises filling the at least one interruption and / or the trenches of the first and / or second surface structuring with a filler material, for example an electrically insulating filler material. The filling may, for example, comprise applying the filler material to the third and / or second layer. The filler material may form a planarization layer that covers the functional layer stack over the entire functional layer stack or that covers the functional layer stack only in the central region. The planarization layer may, for example, also consist of a transparent conductive material such as indium tin oxide (ITO).

[0039] The filling can be made of any transparent material, for example. When choosing the material, the following aspects can be considered: - low refractive index; the higher the refractive index, the less effective the roughening is in increasing the outcoupling efficiency. - Electrical insulating materials electrically insulate the electrically conductive contact layer and the third layer in desired areas. - conductive materials can have the following advantages: 1) The electrical contact is easy to establish and requires no further processing steps. 2) When a picking method with electrostatic forces is used, a polarizable surface is advantageous for the picking process and conductive materials are always well polarizable.

[0040] In some aspects, the method further comprises planarizing protrusions of the first surface structuring at least in the central region, as well as planarizing the filler material, if present. The planarization can contribute to creating a flat surface on which the electrically conductive contact layer is applied.

[0041] Advantages of an optoelectronic device according to some aspects of the invention include a higher internal efficiency (IQE) due to lower losses at the side surfaces of the optoelectronic device. Furthermore, the light extraction efficiency (LEE) can be increased by appropriate removal of the third layer or by shaping the emission surface, e.g., by creating a surface pattern on the emission surface of the optoelectronic device. Shaping the emission surface can not only increase the light yield but also lead to a higher Lambertian far-field distribution. At the same time, the optoelectronic device according to some aspects of the invention can still be equipped with good assembly capability. Short description of the drawings

[0042] In the following, embodiments of the invention are explained in more detail with reference to the accompanying drawings. It is shown schematically in Fig. 1 is a cross-sectional view of an optoelectronic device, Fig. 2A and Fig. 2B each show a cross-sectional view of an optoelectronic device according to some aspects of the invention, and Fig. 3A to 7C each show a cross-sectional view of another embodiment of an optoelectronic device according to some aspects of the invention. Detailed description

[0043] The present disclosure will now be described in more detail with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are illustrated. However, the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are presented for the sake of thoroughness and completeness. Like reference characters refer to like elements throughout the specification. The drawings are not necessarily to scale, and certain features may be exaggerated to better illustrate and explain exemplary embodiments of the present disclosure.

[0044] Fig. 1 shows a cross-sectional view of an optoelectronic device, comprising a layer stack 2 with a first layer 3 with a doping of a first conductivity type, an active region 4 arranged on the first layer 3, a second layer 5 with a doping of a second conductivity type arranged on the active region 4 and a third layer 6 with the doping of the second conductivity type arranged on the second layer 5, wherein the third layer 6 has a higher concentration of the doping of the second conductivity type than the second layer 5. In addition, an electrically conductive contact layer 7 is arranged on the third layer 6.Due to the electrical connection of the optoelectronic device, charge carriers (indicated by the tree arrows) are distributed across the entire third layer due to the high doping of the third layer 6 and introduced into the active region 4 of the optoelectronic device, where they recombine with light emission. However, charge carriers recombining along the side surfaces of the functional layer stack can recombine without light emission due to impurities in the material, resulting in non-radiative losses (indicated by the two flashes). These non-radiative losses reduce the internal efficiency (IQE) of the optoelectronic device and are therefore undesirable, especially when the optoelectronic device is particularly small.

[0045] However, the inventors found that implementing a current confinement for the functional layer stack, such that the charge carrier flow within the layer stack is centered on a central region of the functional layer stack, can contribute to reducing these non-radiative losses. Current confinement reduces the charge carrier density along the side surfaces 8 of the layer stack, and impurities along the side surfaces have no or a lesser influence on the (efficiency) losses due to non-radiative recombination of the charge carriers. The functional layer stack and / or an electrically conductive contact layer arranged on the functional layer stack is therefore modified / configured such that a current path from the electrically conductive contact layer through the layer stack is formed only in a central region of the layer stack, as described in several embodiments in the Fig. 2A to 7C. Some of the embodiments shown in the figures additionally provide for improved coupling-out of light generated in the layer stack by providing an outcoupling structure on a surface of the layer stack facing the conductive contact layer.

[0046] Fig. 2A shows an optoelectronic device 1 in a cross-sectional view. The optoelectronic device 1 comprises a layer stack 2 with a first layer 3 doped with a first conductivity type, an active region 4 arranged on the first layer 3, a second layer 5 doped with a second conductivity type arranged on the active region 4, and a third layer 6 doped with the second conductivity type arranged on the second layer 5, wherein the third layer 6 has a higher concentration of the doped with the second conductivity type than the second layer 5. Furthermore, an electrically conductive contact layer 7 is arranged on the third layer 6. The functional layer stack 2 is laterally delimited by side surfaces 8 of the functional layer stack 2 and comprises a central region 9 along a center line 10 of the functional layer stack 2.The central region 9 is spaced from the side surfaces 8 and forms a partial region of the layer stack that extends through the entire layer stack along the center line 10 of the functional layer stack. To achieve current limitation, the third layer 6 is modified such that a current path from the electrically conductive contact layer 7 through the third layer 6 to the second layer 5 is limited to the central region 9. For this purpose, a region of the third layer 6 outside the central region was removed or its height was reduced in a region outside the central region in order to guide a current introduced into the electrically conductive contact layer 7 into the central region and not distribute it over an entire third layer that extends over the entire functional layer stack 2.Furthermore, the removal of a region of the third layer 6 outside the central region can also lead to an at least partial removal of the second layer 5 by reducing its height in a region outside the central region.

[0047] Fig. 2B shows an alternative embodiment of the optoelectronic device 1. In order to achieve current limitation, the third layer 6 was not completely removed in the regions outside the central region, but rather overlaps 11 were introduced to divide the third layer 6 into a first region 6a and a second region 6b. The first region 6a is limited to the central region 9, and the electrically conductive contact layer 7 contacts the third layer only in the first region / central region. A current path from the electrically conductive contact layer 7 through the third layer 6 to the second layer 5 is thus limited to the central region 9 in order to conduct a current introduced into the electrically conductive contact layer 7 into the central region and not distribute it over the entire third layer 6.

[0048] The Fig. 3A to 3C show embodiments in which the region of the third layer 6 outside the central region 9 has been removed to create a current limitation. Furthermore, a first surface structuring 12 comprising a plurality of projections and trenches is provided on the third layer 6 on a surface facing the electrically conductive contact layer 7. The first surface structuring can serve to improve the coupling-out efficiency of the optoelectronic device 1.

[0049] As in Fig. 3A and Fig. As shown in Figure 3B, a planarization layer 14 is arranged on the layer stack 2, which replaces regions that were removed by the third layer 6 outside the central region and provides the first surface structuring 12. The planarization layer 14 consists in particular of a transparent material, which in the case of Fig. 3A and Fig. 3B can additionally be an electrically insulating material in order not to counteract the current restriction caused by the removal of the third layer outside the central region. The electrically conductive contact layer 7 contacts the protrusions of the first surface structuring, while the trenches are filled by the planarization layer. For better contacting, the protrusions can be planarized to create a good contact surface for the electrically conductive contact layer 7.

[0050] The electrically conductive contact layer 7 can extend over the entire functional layer stack (see Fig. 3A) or be limited to the central area 9 (see Fig. 3B). In particular, if the electrically conductive contact layer 7 extends over the entire functional layer stack, it may consist of a transparent conductive material so that the light generated in the functional layer stack can exit the optoelectronic device 1.

[0051] As in Fig. As shown in Figure 3C, the planarization layer may also cover only the first surface pattern and fill the trenches of the first pattern 12. In this case, the planarization layer may also consist of an electrically conductive material such as a TCO to ensure good current propagation into the third layer within the central region 9.

[0052] Fig. 4A and Fig. 4B show embodiments of the optoelectronic device 1 without a planarization layer. The optoelectronic device of Fig. 4A and in particular the third layer 6 of the optoelectronic device 1 comprises, in addition to the Fig. 2B, a first surface structuring is provided on the second region 6b of the third layer 6 on a surface facing the electrically conductive contact layer 7. The first surface structuring comprises a plurality of protrusions and trenches and can serve to improve the coupling-out efficiency of the optoelectronic device 1.

[0053] The optoelectronic device of Fig. 4B and in particular the second layer 6 of the optoelectronic device 1 outside the central region comprises, in addition to the layer shown in Fig. 2A, a second surface structuring on a surface facing the electrically conductive contact layer 7. The second surface structuring comprises a plurality of elevations and depressions and can serve to improve the coupling-out efficiency of the optoelectronic device 1.

[0054] In an embodiment not shown, the third layer 6 of the optoelectronic device 1 comprises, for example, Fig. 4A, a first surface structuring on the second region 6b of the third layer 6 on a surface facing the electrically conductive contact layer 7, wherein the first surface structuring also extends into the second layer 5. The first surface structuring thus comprises a plurality of projections and trenches, wherein the trenches can be arranged at least partially in the second layer 5 and can serve to improve the coupling-out efficiency of the optoelectronic device 1.

[0055] Fig. 5A to 5C show embodiments of the optoelectronic device 1 which, in addition to the Fig. 4A, a planarization layer 14 and in which the first surface structuring 12 also extends on a surface of the third layer 6 in the central region 9. The projections of the first surface structuring 12 are higher in the central region 9 than in a region outside the central region in order to provide a contact surface for the electrically conductive contact layer 7 and to provide current limitation for the central region 9 when the third layer is arranged with an electrically conductive contact layer 7 that extends over the entire functional layer stack, as in Fig. 5A shown.

[0056] In addition, the third layer may have at least one interruption for current limitation, which divides the third layer into at least a first and a second region, wherein the first region is in contact with the electrically conductive contact layer 7 and forms the current path from the electrically conductive contact layer 7 to the second layer.

[0057] As in Fig. 5A and Fig. 5B, the planarization layer 14 is arranged on the layer stack 2 to replace areas that were removed from the third layer 6 outside the central area and to provide the first surface structuring 12. The planarization layer 14 is in particular made of a transparent material, which in the case of Fig. 5A and Fig. 5B should additionally be an electrically insulating material in order not to counteract the current restriction caused by the removal of the third layer outside the central region. The electrically conductive contact layer 7 contacts the protrusions of the first surface structuring, while the trenches are filled by the planarization layer. For better contact, the protrusions can be planarized to create a good contact surface for the electrically conductive contact layer 7.

[0058] The electrically conductive contact layer 7 can extend over the entire functional layer stack (see Fig. 5A) or be limited to the central area 9 (see Fig. 5B). In particular, if the electrically conductive contact layer 7 extends over the entire functional layer stack, it may consist of a transparent conductive material so that the light generated in the functional layer stack can exit the optoelectronic device 1.

[0059] As in Fig. As shown in Figure 5C, the planarization layer 14 may also cover only the first surface pattern 12 and fill the trenches of the first pattern 12 in the central region 9. In this case, the planarization layer may also consist of an electrically conductive material such as a TCO to ensure good current propagation into the third layer within the central region 9.

[0060] Fig. 6A and Fig. 6B show embodiments of the optoelectronic device 1 in which, compared to the one in Fig. 5A and Fig. 5B, the projections of the first surface structuring 12 have substantially the same height over the entire first surface structuring 12. To create a current limitation for the central region 9, the third layer comprises interruptions 11 that divide the third layer into a first region 6a and a second region 6b, wherein the first region is limited to the central region and contacts the electrically conductive contact layer 7, which is also limited to the central region 9.

[0061] As in Fig. As shown in Figure 6A, the planarization layer 14 is arranged on the layer stack 2 and replaces regions that were removed by the third layer 6 in the interruption regions and in the trenches of the first surface structuring. The planarization layer 14 can, as shown in Fig. 6B, only cover the first surface structuring 12 and fill the trenches of the first structuring 12 in the central region 9. In this case, the planarization layer can also consist of an electrically conductive material, such as a TCO, to ensure good current propagation into the third layer within the central region 9.

[0062] The Fig. 7A to 7C show a further development of the embodiment of the Fig. 4B, according to which not only the second layer has the second surface structuring 13, but the third layer 6 also has a first surface structuring, which is provided on the third layer 6 on a surface facing the electrically conductive contact layer 7 and comprises a plurality of projections and trenches. The first surface structuring can serve to improve the coupling-out efficiency of the optoelectronic device 1.

[0063] As in Fig. 7A and Fig. As shown in Figure 7B, a planarization layer 14 is arranged on the layer stack 2, which replaces regions that were removed from the third layer 6 outside the central region and form the first surface structuring 12 and the trenches of the second surface structuring 13. The planarization layer 14 consists in particular of a transparent material, which in the case of Fig. 3A and Fig. 3B should additionally be an electrically insulating material in order not to counteract the current restriction caused by the removal of the third layer outside the central region. The electrically conductive contact layer 7 contacts the protrusions of the first surface structuring, while the trenches are filled by the planarization layer. For better contact, the protrusions can be planarized to create a good contact surface for the electrically conductive contact layer 7.

[0064] The electrically conductive contact layer 7 can extend over the entire functional layer stack (see Fig. 7A) or be limited to the central area 9 (see Fig. 7B). In particular, if the electrically conductive contact layer 7 extends over the entire functional layer stack, it may consist of a transparent conductive material so that the light generated in the functional layer stack can exit the optoelectronic device 1.

[0065] As in Fig. As shown in Figure 7C, the planarization layer may also cover only the first surface pattern and fill the trenches of the first pattern 12. In this case, the planarization layer may also consist of an electrically conductive material such as a TCO to ensure good current propagation into the third layer within the central region 9. List of reference symbols 1 optoelectronic device 2 functional layer stacks 3 first layer 4 active regions 5 second layer 6 third layer 6a first area 6b second area 7 electrically conductive contact layer 8 side surface 9 central area 10 Center line 11 Interruption 12 first surface structuring 13 second surface structuring 14 Planarization layer

Claims

[1] An optoelectronic device (1) comprising: - an epitaxially grown functional layer stack (2) comprising: - a first layer (3) doped with a first conductivity type; - an active region (4) arranged on the first layer (3); - a second layer (5) with a doping of a second conductivity type, which is arranged on the active region (4); and - a third layer (6) with the doping of the second conductivity type, which is arranged on the second layer (5), wherein the third layer (6) has a higher concentration of the doping of the second conductivity type than the second layer (5); and - an electrically conductive contact layer (7) arranged on the third layer (6); wherein the functional layer stack (2) is laterally delimited by side surfaces (8) of the functional layer stack (2); wherein the functional layer stack (2) comprises a central region (9) along a center line (10) of the functional layer stack (2); wherein the central region (9) is spaced from the side surfaces (8); and wherein a current path from the electrically conductive contact layer (7) through the third layer (6) to the second layer (5) is limited to the central region (9). [2] The optoelectronic device according to claim 1, wherein the third layer (6) is confined to the central region (9). [3] The optoelectronic device according to claim 1 or 2, wherein the third layer (6) has at least one interruption (11) and the at least one interruption (11) divides the third layer (6) into at least a first and a second region (6a, 6b) which are separated from each other, the first region (6a) being limited to the central region (9). [4] The optoelectronic device according to one of the preceding claims, wherein the electrically conductive contact layer (7) electrically contacts the third layer (6) only in the central region (9) and / or is arranged on the third layer (6) only in the central region (9). [5] The optoelectronic device according to one of the preceding claims, wherein the third layer (6) or the third layer (6) and the second layer (5) has a first surface structuring (12) with a plurality of projections and trenches on a surface facing the electrically conductive contact layer (7). [6] The optoelectronic device according to claim 5, wherein the projections of the first surface structuring (12) in the central region (9) are higher than the projections of the first surface structuring (12) outside the central region (9). [7] The optoelectronic device according to claim 5 or 6, wherein projections of the first surface structuring (12) have a planarized surface at least in the central region (9) which faces the electrically conductive contact layer (7). [8] The optoelectronic device according to one of claims 5 to 7, wherein projections of the first surface structuring (12) electrically contact the electrically conductive contact layer (7) in the central region (9). [9] The optoelectronic device according to one of the preceding claims, wherein the second layer (5) has, on a surface facing the electrically conductive contact layer (7), a second surface structuring (13) with a plurality of elevations and depressions, in particular in a region outside the central region (9). [10] The optoelectronic device according to one of the preceding claims, further comprising a planarization layer (14) arranged on the third and / or second layer (5, 6), wherein the planarization layer (14) in particular fills the at least one interruption (11) and / or the trenches of the first and / or second surface structuring (12, 13). [11] The optoelectronic device of claim 9, wherein the planarization layer (14) is formed of an electrically insulating material. [12] The optoelectronic device according to one of the preceding claims, wherein the central region (9) is limited to half the distance between two opposite side surfaces (8) of the functional layer stack (2). [13] The optoelectronic device according to any one of the preceding claims, wherein the first layer (3) and / or the second layer (5) and / or the third layer (6) comprises a base material selected from the group consisting of: - GaN; - AlGaN; - AlGaInP; - AlGaInN; and - AlGaP. [14] Method for producing at least one optoelectronic device (1), comprising the steps: - Providing a functional layer stack (2) comprising: - a first layer (3) doped with a first conductivity type; - an active region (4) arranged on the first layer (3); - a second layer (5) with a doping of a second conductivity type, which is arranged on the active region (4); and - a third layer (6) with the doping of the second conductivity type, which is arranged on the second layer (5), wherein the third layer (6) has a higher concentration of the doping of the second conductivity type than the second layer (5); wherein the functional layer stack (2) is laterally delimited by side surfaces (8) of the functional layer stack (2); wherein the functional layer stack (2) comprises a central region (9) along a center line (10) of the functional layer stack (2); and wherein the central region (9) is spaced from the side surfaces (8); and - Providing an electrically conductive contact layer (7) on the third layer (6) such that a current path from the electrically conductive contact layer (7) through the third layer (6) to the second layer (5) is limited to the central region (9). [15] The method of claim 14, further comprising removing the third layer (6) in a region outside the central region (9). [16] The method of claim 14, further comprising creating at least one interruption (11) in the third layer (6) such that the at least one interruption (11) divides the third layer (6) into at least a first and a second region (6a, 6b) which are separated from each other, the first region (6a) being limited to the central region (9). [17] The method according to any one of claims 14 to 16, further comprising roughening a surface of the third layer (6) facing the electrically conductive contact layer (7) to produce a first surface structuring (12) having a plurality of projections and trenches. [18] The method according to one of claims 14 to 17, further comprising roughening a surface of the second layer (5) facing the electrically conductive contact layer (7), in particular in a region outside the central region (9), in order to produce a second surface structuring (13) with a plurality of elevations and trenches. [19] The method according to one of claims 14 to 18, further comprising filling the at least one interruption (11) and / or the trenches of the first and / or second surface structuring (12, 13) with a filling material, in particular an electrically insulating filling material. [20] The method according to one of claims 17 to 19, further comprising a planarization of projections of the first surface structuring (12) at least in the central region (9).

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