CURRENT MEASURING DEVICE AND CURRENT MEASURING METHOD
Patent Information
- Application Number
- DE112022007411
- Authority / Receiving Office
- DE · DE
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-06-23
- Publication Date
- 2025-04-10
AI Technical Summary
Conventional current detection devices for multi-phase inverters require separate reset output circuits for each Rogowski coil, leading to complex configurations.
A current detection device that uses multiple Rogowski coils and integrating circuits with shared reset signals, where the reset signals are generated based on the conducting states of switching elements, allowing for simultaneous resetting of multiple integrating circuits during non-conducting periods of the switching elements.
This configuration simplifies the device setup by sharing reset signals across multiple integrating circuits, improving detection accuracy and reducing complexity.
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Abstract
Description
Current detection device and current detection method
[0001] The present invention relates to a current detection device and a current detection method.
[0002] In recent years, a technique using a Rogowski coil has become known as a technique for detecting current in motor drive control, etc. (See, for example, Patent Document 1.) In this conventional technique, the output of the Rogowski coil is integrated using an integrator with a reset function to detect the current.
[0003] International Publication No. 2021 / 066153
[0004] However, in the above-mentioned conventional technology, for example, when detecting the current flowing through a three-phase drive inverter unit, it is necessary to provide one reset output circuit for each Rogowski coil, which poses a problem of complex configuration.
[0005] The present invention has been made to solve the above problems, and an object of the present invention is to provide a current detection device and a current detection method that can be simplified in configuration.
[0006] In order to solve the above problem, one aspect of the present invention is a current detection device that has a plurality of pairs of first switching elements and second switching elements connected in series and detects a current flowing in an inverter unit that generates a multi-phase AC signal, the current detection device comprising a plurality of first Rogowski coils, each of which corresponds one-to-one to the first switching elements and detects a current flowing in the first switching elements, a plurality of second Rogowski coils, each of which corresponds one-to-one to the second switching elements and detects a current flowing in the second switching elements, and a plurality of second Rogowski coils, each of which corresponds one-to-one to the first Rogowski coils, has a reset function, integrates an output of the first Rogowski coils, and outputs a first detection signal. a plurality of first integrating circuits each having a reset function and integrating the output of the second Rogowski coil to output a second detection signal; a detection processing unit that detects a current flowing in the inverter unit based on the first detection signal and the second detection signal; a first reset output unit that outputs a first reset signal to reset the plurality of first integrating circuits during a first period in which all of the first switching elements are in a non-conductive state; and a second reset output unit that outputs a second reset signal to reset the plurality of second integrating circuits during a second period in which all of the second switching elements are in a non-conductive state.
[0007] In addition, one aspect of the present invention is that, in the above-mentioned current detection device, the first reset output unit outputs the first reset signal during a portion of the first period so that all of the plurality of first integration circuits are in a reset state, and the second reset output unit outputs the second reset signal during a portion of the second period so that all of the plurality of second integration circuits are in a reset state.
[0008] Furthermore, one aspect of the present invention is that, in the above-mentioned current detection device, a timing generation unit is provided that generates a reset timing for the first integrator circuit and a reset timing for the second integrator circuit, and the first reset output unit outputs the first reset signal based on the reset timing for the first integrator circuit generated by the timing generation unit so that all of the plurality of first integrator circuits are in a reset state, and the second reset output unit outputs the second reset signal based on the reset timing for the second integrator circuit generated by the timing generation unit so that all of the plurality of second integrator circuits are in a reset state.
[0009] In addition, one aspect of the present invention may be such that the current detection device further includes a control unit that controls switching of the first switching element and the second switching element, and the control unit further includes the timing generation unit.
[0010] In addition, one aspect of the present invention is that in the above-mentioned current detection device, the timing generation unit may include a logic circuit that generates reset timing for the first integrator circuit based on a control signal for the first switching element corresponding to the multiple phases, and generates reset timing for the second integrator circuit based on a control signal for the second switching element corresponding to the multiple phases.
[0011] Another aspect of the present invention is a current detection method for detecting a current flowing in an inverter unit that has a plurality of pairs of first switching elements and second switching elements connected in series and generates a multi-phase AC signal, the method including a first integration step in which each of a plurality of first integrating circuits integrates an output of a first Rogowski coil that detects a current flowing in the first switching element corresponding to each of the plurality of phases and outputs a first detection signal; and a second integration step in which each of a plurality of second integrating circuits integrates an output of a second Rogowski coil that detects a current flowing in the second switching element corresponding to each of the plurality of phases and outputs a second detection signal. The current detection method includes a second integration step of outputting a detection signal, a detection processing step in which a detection processing unit detects a current flowing in the inverter unit based on the first detection signal and the second detection signal, a first reset output step in which a first reset output unit outputs a first reset signal that resets the plurality of first integration circuits during a first period in which all of the first switching elements are in a non-conductive state, and a second reset output step in which a second reset output unit outputs a second reset signal that resets the plurality of second integration circuits during a second period in which all of the second switching elements are in a non-conductive state.
[0012] According to the present invention, the current detection device outputs a first reset signal to reset a plurality of first integrating circuits corresponding to a plurality of first Rogowski coils during a first period in which all of the first switching elements are in a non-conductive state, and outputs a second reset signal to reset a plurality of second integrating circuits corresponding to a plurality of second Rogowski coils during a second period in which all of the second switching elements are in a non-conductive state. Therefore, the current detection device can share a reset signal for a plurality of first integrating circuits and a plurality of second integrating circuits. Since the reset signal can be shared between two systems in this way, the current detection device can have a simplified configuration.
[0013] 1 is a block diagram showing an example of a motor control device according to the present embodiment; FIG. 2 is a block diagram showing an example of a current detection unit according to the present embodiment; FIG. 3 is a circuit diagram showing an example of an integrating circuit according to the present embodiment; FIG. 4 is a diagram explaining a process for generating a composite signal according to the present embodiment; FIG. 5 is a flowchart showing an example of a process for detecting an output current of a current detection device according to the present embodiment; FIG. 6 is a diagram showing an example of a process for generating a reset signal of a first integrating circuit according to the present embodiment; FIG. 7 is a flowchart showing an example of a timing generation of a reset signal of a first integrating circuit according to the present embodiment; FIG. 8 is a diagram showing an example of a process for generating a reset signal of a second integrating circuit according to the present embodiment; FIG. 9 is a flowchart showing an example of a timing generation of a reset signal of a second integrating circuit according to the present embodiment;
[0014] A current detection device and a current detection method according to an embodiment of the present invention will now be described with reference to the drawings.
[0015] Fig. 1 is a block diagram showing an example of a motor control device 1 according to this embodiment. As shown in Fig. 1, the motor control device 1 includes a DC power supply 2, a smoothing capacitor 4, a current detection device 10, an inverter unit 20, and a motor control unit 30. The motor control device 1 is also connected to a motor 3.
[0016] The DC power supply 2 is, for example, a battery, and supplies DC power to the motor control device 1. The motor 3 is, for example, a three-phase brushless motor driven by a sine wave, and is driven by AC signals (U-phase signal, V-phase signal, and W-phase signal) supplied as drive signals from an inverter unit 20 of the motor control device 1.
[0017] The smoothing capacitor 4 is connected between a power supply line L1 connected to the positive terminal of the DC power supply 2 and a ground line L2 connected to the negative terminal of the DC power supply 2, and smoothes the DC voltage supplied from the DC power supply 2.
[0018] The inverter unit 20 generates AC signals (U-phase signal, V-phase signal, and W-phase signal) that drive the motor 3 under the control of the motor control unit 30. The inverter unit 20 includes switching elements 21-1 to 21-3 and switching elements 22-1 to 22-3. The inverter unit 20 generates, for example, three-phase sinusoidal wave current signals with a phase shift of 120 degrees as drive signals by switching the switching elements 21-1 to 21-3 and the switching elements 22-1 to 22-3.
[0019] In this embodiment, the switching elements 21-1 to 21-3 correspond to the high arm, which is the upper switching element (first switching element), and when referring to any upper switching element provided in the inverter unit 20, or when no particular distinction is made, they will be described as switching element 21.
[0020] In addition, switching elements 22-1 to 22-3 correspond to the low arm, which is the lower switching element (second switching element), and when referring to any lower switching element provided in the inverter unit 20, or when no particular distinction is made, they will be described as switching elements 22.
[0021] The switching elements 21 and 22 are connected in series between the power supply line L1 and the ground line L2 to form a full-bridge circuit. The switching elements 21 (21-1 to 21-3) and the switching elements 22 (22-1 to 22-3) are, for example, N-type metal-oxide-semiconductor field-effect transistors (MOSFETs). The switching elements 21 and 22 are turned on (conductive) when their gate terminals (control terminals) are high, and turned off (non-conductive) when their gate terminals (control terminals) are low.
[0022] The switching elements 21-1 and 22-1 are connected in series between the power supply line L1 and the ground line L2 to form a full bridge circuit that generates a U-phase signal that is a drive signal for the U-phase. The switching elements 21-1 and 22-1 are switched based on control signals (S1, S2) output from the motor control unit 30, and output the U-phase signal from a node N1 between the switching elements 21-1 and 22-1 that are connected in series.
[0023] The switching elements 21-2 and 22-2 are connected in series between the power supply line L1 and the ground line L2, and form a full-bridge circuit that generates a V-phase signal that is a drive signal for the V-phase. The switching elements 21-2 and 22-2 are switched based on control signals (S3, S4) output from the motor control unit 30, and output the V-phase signal from a node N2 between the switching elements 21-2 and 22-2 that are connected in series.
[0024] The switching elements 21-3 and 22-3 are connected in series between the power supply line L1 and the ground line L2, and form a full bridge circuit that generates a W-phase signal that is a drive signal for the W-phase. The switching elements 21-3 and 22-3 are switched based on control signals (S5, S6) output from the motor control unit 30, and output the W-phase signal from a node N3 between the switching elements 21-3 and 22-3 that are connected in series.
[0025] In this way, the inverter unit 20 has multiple (e.g., three) pairs of switching elements 21 and switching elements 22 connected in series, and generates multiple-phase (e.g., three-phase) AC signals (U-phase signal, V-phase signal, W-phase signal) of different phases corresponding to each of the multiple pairs of switching elements 21 and switching elements 22.
[0026] The current detection device 10 detects the current flowing through the inverter unit 20. The current detection device 10 detects, for example, the output current of the drive signal (AC signal) of each phase generated by the inverter unit 20. The current detection device 10 also detects the input current from the DC power supply 2 (the input current of the inverter unit 20). The current detection device 10 includes Rogowski coils 11-1 to 11-3, Rogowski coils 12-1 to 12-3, and a current detection unit 13.
[0027] In this embodiment, the Rogowski coils 11-1 to 11-3 are air-core coils that detect the current flowing through the switching elements 21 (21-1 to 21-3), and when referring to a Rogowski coil (first Rogowski coil) for any switching element 21 provided in the current detection device 10, or when no particular distinction is made, they will be described as Rogowski coils 11.
[0028] In addition, the Rogowski coils 12-1 to 12-3 are air-core coils that detect the current flowing through the switching elements 22 (22-1 to 22-3), and when referring to a Rogowski coil (second Rogowski coil) for any switching element 22 provided in the current detection device 10, or when no particular distinction is made, they will be described as Rogowski coils 12.
[0029] The Rogowski coil 11 (first Rogowski coil) detects the current flowing through the switching element 21. For example, the Rogowski coil 11-1 is arranged on a signal line connecting the drain terminal of the switching element 21-1 and the power supply line L1, and detects the current flowing through the switching element 21-1. The Rogowski coil 11-2 is arranged on a signal line connecting the drain terminal of the switching element 21-2 and the power supply line L1, and detects the current flowing through the switching element 21-2. The Rogowski coil 11-3 is arranged on a signal line connecting the drain terminal of the switching element 21-3 and the power supply line L1, and detects the current flowing through the switching element 21-3.
[0030] For example, the Rogowski coil 12-1 is disposed on a signal line connecting the source terminal of the switching element 22-1 and the ground line L2, and detects the current flowing through the switching element 22-1. The Rogowski coil 12-2 is disposed on a signal line connecting the source terminal of the switching element 22-2 and the ground line L2, and detects the current flowing through the switching element 22-2. The Rogowski coil 12-3 is disposed on a signal line connecting the source terminal of the switching element 22-3 and the ground line L2, and detects the current flowing through the switching element 22-3.
[0031] As described above, the current detection device 10 includes a Rogowski coil 11 and a Rogowski coil 12 corresponding to each of a plurality of pairs of switching elements 21 and 22. That is, the plurality (three) of Rogowski coils 11 each correspond one-to-one to the switching elements 21 and detect the current flowing through the switching elements 21. The plurality (three) of Rogowski coils 12 each correspond one-to-one to the switching elements 22 and detect the current flowing through the switching elements 22.
[0032] The current detection unit 13 executes a process of detecting the current flowing through the inverter unit 20. For example, the current detection unit 13 generates a composite signal by adding a first detection signal obtained by integrating the output of the Rogowski coil 11 and a second detection signal obtained by integrating the output of the Rogowski coil 12, and detects the output current of the AC signal based on the composite signal. The current detection unit 13 generates composite signals corresponding to each of the multiple pairs and detects the output current of each AC signal with a different phase based on the composite signals. Specifically, the current detection unit 13 outputs the generated composite signals as current signals indicating the output currents of the drive signals (U-phase signal, V-phase signal, and W-phase signal) of the motor 3. Note that the detailed configuration of the current detection unit 13 will be described later with reference to FIG. 2 .
[0033] The motor control unit 30 is, for example, a processor including a CPU (Central Processing Unit), and performs overall control of the current detection device 10 and the motor control device 1. The motor control unit 30 performs various processes, for example, by causing the CPU to execute programs stored in a storage unit (not shown).
[0034] The motor control unit 30 acquires, for example, via an ADC, current signals indicating the output currents of the drive signals (U-phase signal, V-phase signal, W-phase signal) output by the current detection unit 13, and detects the current values of the current signals. The motor control unit 30 controls the switching of the switching elements 21 and 22 based on the detected current values of the drive signals (U-phase signal, V-phase signal, W-phase signal). The motor control unit 30 also includes a timing generation unit 31.
[0035] The timing generation unit 31 generates reset timings for the integrating circuits 41 and 42 of the current detection unit 13, which will be described later, and supplies the reset timings to the current detection unit 13. The configuration of the timing generation unit 31 will be described in detail later with reference to FIG.
[0036] Next, the configuration of the above-mentioned current detection unit 13 will be described in detail with reference to Fig. 2. Fig. 2 is a block diagram showing an example of the current detection unit 13 in this embodiment. As shown in Fig. 2, the current detection unit 13 includes integrating circuits 41-1 to 41-3 and integrating circuits 42-1 to 42-3, a detection processing unit 131, a first reset output unit 132, and a second reset output unit 133.
[0037] In this embodiment, the integrating circuits 41-1 to 41-3 have the same configuration, and any integrating circuit corresponding to the Rogowski coil 11 will be described as the integrating circuit 41. In this embodiment, the integrating circuit 41 is an example of a first integrating circuit.
[0038] In addition, in this embodiment, the integrating circuits 42-1 to 42-3 have the same configuration, and any integrating circuit corresponding to the Rogowski coil 12 will be described as the integrating circuit 42. In this embodiment, the integrating circuit 42 is an example of a second integrating circuit.
[0039] The plurality of (three) integrating circuits 41 each correspond one-to-one to the Rogowski coil 11, have a reset function, and integrate the output of the Rogowski coil 11 to output first detection signals (detection signal UH, detection signal VH, detection signal WH). Here, the detection signal UH, detection signal VH, and detection signal WH correspond to the first detection signals.
[0040] The plurality of (three) integrating circuits 42 each correspond one-to-one to the Rogowski coil 12, have a reset function, and integrate the output of the Rogowski coil 12 to output second detection signals (detection signal UL, detection signal VL, detection signal WL). Here, the detection signal UL, detection signal VL, and detection signal WL correspond to the second detection signals.
[0041] Specifically, the integrating circuit 41-1 is connected to the Rogowski coil 11-1 and outputs a detection signal UH obtained by integrating the output of the Rogowski coil 11-1, while the integrating circuit 42-1 is connected to the Rogowski coil 12-1 and outputs a detection signal UL obtained by integrating the output of the Rogowski coil 12-1.
[0042] The integrating circuit 41-2 is connected to the Rogowski coil 11-2 and outputs a detection signal VH obtained by integrating the output of the Rogowski coil 11-2. The integrating circuit 42-2 is connected to the Rogowski coil 12-2 and outputs a detection signal VL obtained by integrating the output of the Rogowski coil 12-2.
[0043] The integrating circuit 41-3 is connected to the Rogowski coil 11-3 and outputs a detection signal WH obtained by integrating the output of the Rogowski coil 11-3. The integrating circuit 42-3 is connected to the Rogowski coil 12-3 and outputs a detection signal WL obtained by integrating the output of the Rogowski coil 12-3.
[0044] The integrating circuits 41 (41-1 to 41-3) and 42 (42-1 to 42-3) have a reset function and integrate the outputs of the Rogowski coils (11, 12). Here, the detailed configuration of the integrating circuit 41 (42) will be described with reference to Fig. 3. Fig. 3 is a circuit diagram showing an example of the integrating circuit 41 (42) in this embodiment.
[0045] 3, the integrator circuit 41 (42) includes a resistor 43, an operational amplifier 44, a capacitor 45, and a reset switch 46. The resistor 43 is connected between one end of the Rogowski coil 11 (12) and the inverting input terminal of the operational amplifier 44. The capacitor 45 is connected between the inverting input terminal (node N5) of the operational amplifier 44 and the output terminal (node N5) of the operational amplifier 44.
[0046] The operational amplifier 44 functions as an integrating circuit by being connected to a resistor 43 and a capacitor 45. One end of the Rogowski coil 11 (12) is connected to the inverting input terminal of the operational amplifier 44 via the resistor 43, and the other end of the Rogowski coil 11 (12) is connected to the non-inverting input terminal. The operational amplifier 44 receives the output of the Rogowski coil 11 (12) as an input signal (IN), and outputs an output signal (OUT) obtained by integrating the output of the Rogowski coil 11 (12).
[0047] The reset switch 46 is connected in parallel with the capacitor 45 between the inverting input terminal (node N4) of the operational amplifier 44 and the output terminal (node N5) of the operational amplifier 44. The reset switch 46 is a switch that resets the output potential of the integrating circuit 41 (42), and its conductive state is controlled by, for example, a pulse signal that is a control signal S. The reset switch 46 is controlled to a conductive state (ON state) when resetting the integrating circuit 41 (42).
[0048] Here, the control signal S of the integrating circuit 41 is supplied with a reset signal RST1 (first reset signal) output by the first reset output unit 132. The control signal S of the integrating circuit 42 is supplied with a reset signal RST2 (second reset signal) output by the second reset output unit 133. Note that when the control signal S controls the reset switch 46 to a non-conductive state (off state), the integrating circuit 41 (42) functions as an integrating circuit.
[0049] 2, the detection processing unit 131 detects the current flowing through the inverter unit 20 based on the first detection signals (detection signals UH, VH, and WH) and the second detection signals (detection signals UL, VL, and WL). The detection processing unit 131 includes adders 50-1 to 50-3.
[0050] The adders 50-1 to 50-3 have the same configuration, and will be described as the adder 50 when referring to any adder included in the detection processing unit 131 or when no particular distinction is made.
[0051] The adder 50 is a two-input analog adder, and is realized by an adder circuit using, for example, an operational amplifier. The adder 50 outputs a composite signal obtained by adding two input signals.
[0052] For example, the adder 50-1 receives the detection signal UH and the detection signal UL as two input signals, and outputs a composite signal obtained by adding the detection signal UH and the detection signal UL as the U-phase current signal UC.
[0053] The adder 50-2 also receives the detection signal VH and the detection signal VL as two input signals, and outputs a composite signal obtained by adding the detection signal VH and the detection signal VL as a V-phase current signal VC.
[0054] The adder 50-3 also receives the detection signal WH and the detection signal WL as two input signals, and outputs a composite signal obtained by adding the detection signal WH and the detection signal WL as a W-phase current signal WC.
[0055] In this way, the detection processing unit 131 generates composite signals (U-phase current signal UC, V-phase current signal VC, W-phase current signal WC) corresponding to each of the multiple pairs of switching elements 21 and 22, and detects the output current for each drive signal (AC signal) of a different phase based on the composite signals. That is, the detection processing unit 131 outputs the generated composite signals (U-phase current signal UC, V-phase current signal VC, W-phase current signal WC) as current signals indicating the output current for each drive signal (U-phase signal, V-phase signal, W-phase signal).
[0056] The first reset output unit 132 outputs a reset signal RST1 that resets a plurality of (e.g., three) integrating circuits 41 during a first period TRrst1 in which all of the switching elements 21 are in an off state. That is, the first reset output unit 132 defines the period in which all of the switching elements 21-1 to 21-3 are in an off state as the first period TRrst1, and outputs the reset signal RST1 during this first period TRrst1. Furthermore, the first reset output unit 132 outputs the reset signal RST1 during a portion (e.g., the central portion) of the first period TRrst1 so that all of the plurality of (e.g., three) integrating circuits 41 are in a reset state.
[0057] The first reset output unit 132 is, for example, a conversion circuit that converts a logic signal output by the timing generation unit 31 of the motor control unit 30 into a signal for controlling the reset switch 46. The first reset output unit 132 outputs a reset signal RST1 so that all of the multiple (e.g., three) integrating circuits 41 are in a reset state, based on the reset timing of the integrating circuits 41 generated by the timing generation unit 31. That is, the first reset output unit 132 outputs the reset signal RST1 to the integrating circuits 41-1 to 41-3 based on the reset timing signal RT1 that indicates the reset timing.
[0058] Furthermore, the second reset output unit 133 outputs a reset signal RST2 that resets a plurality of (e.g., three) integrating circuits 42 during a second period TRrst2 in which all of the switching elements 22 are in the off state. That is, the second reset output unit 133 defines the period in which all of the switching elements 22-1 to 22-3 are in the off state as the second period TRrst2, and outputs the reset signal RST2 during this second period TRrst2. Furthermore, the second reset output unit 133 outputs the reset signal RST2 during a portion (e.g., the center portion) of the second period TRrst2 so that all of the plurality of (e.g., three) integrating circuits 42 are in the reset state.
[0059] The second reset output unit 133 is, for example, a conversion circuit that converts a logic signal output by the timing generation unit 31 of the motor control unit 30 into a signal for controlling the reset switch 46. The second reset output unit 133 outputs a reset signal RST2 so that all of the multiple (e.g., three) integrating circuits 42 are in a reset state, based on the reset timing of the integrating circuits 42 generated by the timing generation unit 31. That is, the second reset output unit 133 outputs the reset signal RST2 to the integrating circuits 41-1 to 41-3 based on the reset timing signal RT2 that indicates the reset timing.
[0060] The timing generation unit 31 generates the reset timing of the integration circuit 41 and the reset timing of the integration circuit 42. The timing generation unit 31 outputs a reset timing signal RT1 to the first reset output unit 132, using, for example, the central timing of the first period TRrst1 in which all of the high arm switching elements 21-1 to 21-3 are in the OFF state as the reset timing of the integration circuit 41.
[0061] In addition, the timing generation unit 31 outputs the reset timing signal RT2 to the second reset output unit 133, using, for example, the central timing of the second period TRrst2 when all of the row arm switching elements 22-1 to 22-3 are in the off state as the reset timing for the integration circuit 42.
[0062] Next, the operation of the current detection device 10 according to this embodiment will be described with reference to the drawings. First, the process of generating a current signal by the detection processing unit 131 of the current detection device 10 will be described with reference to Fig. 4. Fig. 4 is a diagram illustrating the process of generating a composite signal according to this embodiment.
[0063] 4, waveform W1 indicates the voltage waveform of detection signal UH, waveform W2 indicates the voltage waveform of detection signal UL, and waveform W3 indicates the voltage waveform of U-phase current signal UC.
[0064] 4, the integration circuit 41-1 of the detection processing unit 131 integrates the output of the Rogowski coil 11-1 and outputs a detection signal UH as shown in waveform W1. Note that each of the timings Tr11 to Tr15 indicates the reset timing of the integration circuit 41 generated by the timing generation unit 31, and at these timings, the first reset output unit 132 outputs a reset signal RST1 to the integration circuit 41.
[0065] The integration circuit 42-1 of the detection processing unit 131 integrates the output of the Rogowski coil 12-1 and outputs a detection signal UL as shown in waveform W2. Note that each of the timings Tr21 to Tr25 indicates the reset timing of the integration circuit 42 generated by the timing generation unit 31, and at these timings, the second reset output unit 133 outputs a reset signal RST2 to the integration circuit 42.
[0066] Next, adder 50-1 adds detection signal UH as shown in waveform W1 and detection signal UL as shown in waveform W2, and outputs a composite signal, U-phase current signal UC as shown in waveform W3. This U-phase current signal UC is a signal obtained by converting the output current (positive current) of the U-phase drive signal into a voltage.
[0067] The detection processing unit 131 also generates and outputs the V-phase current signal VC and the W-phase current signal WC in the same manner as the U-phase current signal UC. That is, the detection processing unit 131 generates the U-phase current signal UC, the V-phase current signal VC, and the W-phase current signal WC according to the following equations (1) to (3).
[0068] U-phase current signal UC=detection signal UH+detection signal UL (1) V-phase current signal VC=detection signal VH+detection signal VL (2) W-phase current signal WC=detection signal WH+detection signal WL (3)
[0069] The motor control unit 30 acquires the U-phase current signal UC, the V-phase current signal VC, and the W-phase current signal WC generated by the detection processing unit 131 via an ADC (not shown) and uses them to detect zero-crossing points of the output current of each phase. The motor control unit 30 performs switching control of the switching elements 21-1 to 21-3 and the switching elements 22-1 to 22-3 based on the detected zero-crossing points.
[0070] Next, a current detection method of the current detection device 10 according to this embodiment will be described with reference to Figures 5 to 7. Figure 5 is a flowchart showing an example of a detection process of the output current of the current detection device 10 according to this embodiment.
[0071] 5, when detecting the output current (positive current) of each phase of the inverter unit 20, the current detection device 10 first integrates the output of the upper Rogowski coil 11 to generate a first detection signal (step S101). For example, in the current detection unit 13 of the current detection device 10, the integrating circuit 41-1 integrates the output of the Rogowski coil 11-1 to generate a detection signal UH, the integrating circuit 41-2 integrates the output of the Rogowski coil 11-2 to generate a detection signal VH, and the integrating circuit 41-3 integrates the output of the Rogowski coil 11-3 to generate a detection signal WH.
[0072] Next, the current detection device 10 integrates the output of the lower Rogowski coil 12 to generate a second detection signal (step S102). For example, in the current detection unit 13, the integration circuit 42-1 integrates the output of the Rogowski coil 12-1 to generate a detection signal UL, the integration circuit 42-2 integrates the output of the Rogowski coil 12-2 to generate a detection signal VL, and the integration circuit 42-3 integrates the output of the Rogowski coil 12-3 to generate a detection signal WL.
[0073] The current detection unit 13 may execute the process of step S101 and the process of step S102 in the reverse order, or may execute them in parallel using the configuration shown in FIG. 2, for example.
[0074] Next, the current detection device 10 adds the first detection signal and the second detection signal to generate a composite signal (step S103). For example, in the detection processing unit 131 of the current detection unit 13, the adder 50-1 adds the detection signal UH and the detection signal UL to generate a U-phase current signal UC as a composite signal. The adder 50-2 adds the detection signal VH and the detection signal VL to generate a V-phase current signal VC as a composite signal. The adder 50-3 adds the detection signal WH and the detection signal WL to generate a W-phase current signal WC as a composite signal.
[0075] Next, the current detection device 10 detects the output current based on the composite signal (step S104). For example, the detection processing unit 131 of the current detection unit 13 outputs a U-phase current signal UC, a V-phase current signal VC, and a W-phase current signal WC as current signals indicating the output currents of the respective phases to the motor control unit 30. After processing in step S104, the current detection device 10 ends the output current detection process.
[0076] Next, a process for generating a reset signal for the integrating circuit 41 (42) in this embodiment will be described with reference to Fig. 6 to Fig. 9. Fig. 6 is a diagram showing an example of a process for generating a reset signal RST1 for the first integrating circuit (integrating circuit 41) in this embodiment.
[0077] 6, waveform W4 represents the waveform of the control signal S1 for the U phase of the switching element 21, waveform W5 represents the waveform of the control signal S3 for the V phase of the switching element 21, waveform W6 represents the waveform of the control signal S5 for the W phase of the switching element 21, and waveform W7 represents the waveform of the reset signal RST1. The horizontal axis represents time.
[0078] The timing generation unit 31 generates a first period TRrst1 in which all of the switching elements 21 are in the off state, based on the U-phase control signal S1 (waveform W4), the V-phase control signal S3 (waveform W5), and the W-phase control signal S5 (waveform W6) for the high-arm switching elements 21, and generates reset timing in the center period of the first period TRrst1. Based on the reset timing generated by the timing generation unit 31, the first reset output unit 132 outputs a reset signal RST1, as shown in waveform W7, to the integration circuits 41 (41-1 to 41-3).
[0079] FIG. 7 is a flowchart showing an example of timing generation of the reset signal RST1 of the first integrating circuit (integrating circuit 41) according to this embodiment.
[0080] 7, the timing generation unit 31 first determines whether all of the switching elements 21 (21-1 to 21-3) are in the OFF state (step S201). If all of the switching elements 21 (21-1 to 21-3) are in the OFF state (step S201: YES), the timing generation unit 31 proceeds to step S202. If any of the switching elements 21 (21-1 to 21-3) is in the ON state (step S201: NO), the timing generation unit 31 returns to step S201.
[0081] In step S202, the timing generation unit 31 generates reset timing for the integration circuits 41 (41-1 to 41-3). The timing generation unit 31 outputs a reset timing signal RT1 so that the integration circuits 41 (41-1 to 41-3) are reset, for example, in the center of the first period TRrst1 in which all of the switching elements 21 (21-1 to 21-3) are in the OFF state.
[0082] Next, the first reset output unit 132 outputs the reset signal RST1 based on the reset timing (step S203). The first reset output unit 132 converts the reset timing signal RT1 into a signal for controlling the reset switch 46 of the integration circuit 41 and outputs the reset signal RST1. After the process of step S203, the timing generation unit 31 returns the process to step S201.
[0083] FIG. 8 is a diagram showing an example of a process for generating the reset signal RST2 of the second integrating circuit (integrating circuit 42) in this embodiment.
[0084] 8, waveform W8 indicates the waveform of the control signal S2 of the U-phase of the switching element 22, waveform W9 indicates the waveform of the control signal S4 of the V-phase of the switching element 22, waveform W10 indicates the waveform of the control signal S6 of the W-phase of the switching element 22, and waveform W11 indicates the waveform of the reset signal RST2. The horizontal axis indicates time.
[0085] The timing generation unit 31 generates a second period TRrst2 in which all of the switching elements 22 are in the off state, based on the U-phase control signal S2 (waveform W8), the V-phase control signal S4 (waveform W9), and the W-phase control signal S6 (waveform W10) for the low-arm switching elements 22, and generates reset timing in the center period of the second period TRrst2. The second reset output unit 133 outputs a reset signal RST2, as shown in waveform W11, to the integration circuits 42 (42-1 to 42-3), based on the reset timing generated by the timing generation unit 31.
[0086] FIG. 9 is a flowchart showing an example of timing generation of the reset signal RST2 of the second integrating circuit (integrating circuit 42) according to this embodiment.
[0087] 9, the timing generation unit 31 first determines whether all of the switching elements 22 (22-1 to 22-3) are in the OFF state (step S211). If all of the switching elements 22 (22-1 to 22-3) are in the OFF state (step S211: YES), the timing generation unit 31 proceeds to step S212. If any of the switching elements 22 (22-1 to 22-3) is in the ON state (step S211: NO), the timing generation unit 31 returns to step S211.
[0088] In step S212, the timing generation unit 31 generates reset timing for the integration circuits 42 (42-1 to 42-3). The timing generation unit 31 outputs a reset timing signal RT2 so that the integration circuits 42 (42-1 to 42-3) are reset, for example, in the center of the second period TRrst2 in which all of the switching elements 22 (22-1 to 22-3) are in the OFF state.
[0089] Next, the second reset output unit 133 outputs the reset signal RST2 based on the reset timing (step S213). The second reset output unit 133 converts the reset timing signal RT2 into a signal for controlling the reset switch 46 of the integration circuit 42, and outputs the reset signal RST2. After the process of step S213, the timing generation unit 31 returns the process to step S211.
[0090] As described above, the current detection device 10 according to this embodiment is a current detection device that detects currents flowing through an inverter unit 20 and includes a plurality of Rogowski coils 11 (first Rogowski coils), a plurality of Rogowski coils 12 (second Rogowski coils), a plurality of integrating circuits 41 (first integrating circuits), a plurality of integrating circuits 42 (second integrating circuits), a detection processing unit 131, a first reset output unit 132, and a second reset output unit 133. The inverter unit 20 has a plurality (e.g., three) pairs of switching elements 21 (first switching elements) and switching elements 22 (second switching elements) connected in series, and generates multi-phase (e.g., three-phase) AC signals (U-phase signal, V-phase signal, and W-phase signal). Each of the plurality of Rogowski coils 11 corresponds one-to-one to a switching element 21 and detects currents flowing through the switching elements 21. Each of the plurality of Rogowski coils 12 corresponds one-to-one to a switching element 22 and detects currents flowing through the switching elements 22. The plurality of integrating circuits 41 each correspond one-to-one to the Rogowski coils 11, have a reset function, and integrate the output of the Rogowski coils 11 to output first detection signals (detection signals UH, VH, and WH). The plurality of integrating circuits 42 each correspond one-to-one to the Rogowski coils 12, have a reset function, and integrate the output of the Rogowski coils 12 to output second detection signals (detection signals UL, VL, and WL). The detection processing unit 131 detects the current flowing through the inverter unit 20 based on the first and second detection signals. The first reset output unit 132 outputs a reset signal RST1 (first reset signal) that resets the plurality of integrating circuits 41 during a first period TRrst1 in which all switching elements 21 are in the off state (non-conducting state). The second reset output unit 133 outputs a reset signal RST2 (second reset signal) that resets the plurality of integrating circuits 42 during a second period TRrst2 in which all the switching elements 22 are in the OFF state (non-conducting state).
[0091] As a result, the current detection device 10 according to this embodiment outputs a reset signal RST1 that resets the multiple integrating circuits 41 corresponding to the multiple Rogowski coils 11 during a first period TRrst1 in which all switching elements 21 are in the off state (non-conducting state). Furthermore, the current detection device 10 according to this embodiment outputs a reset signal RST2 that resets the multiple integrating circuits 42 corresponding to the multiple Rogowski coils 12 during a second period TRrst2 in which all switching elements 22 are in the off state (non-conducting state). Therefore, the current detection device 10 according to this embodiment can share a reset signal for the multiple integrating circuits 41 and can also share a reset signal for the multiple integrating circuits 42. Because the reset signal can be shared between two systems in this way, the current detection device 10 according to this embodiment can have a simplified configuration.
[0092] In this embodiment, the first reset output unit 132 outputs a reset signal RST1 during a part of the first period TRrst1 so that all of the plurality of integration circuits 41 are in the reset state. The second reset output unit 133 outputs a reset signal RST2 during a part of the second period TRrst2 so that all of the plurality of integration circuits 42 are in the reset state.
[0093] As a result, the current detection device 10 according to this embodiment outputs the reset signals RST1 and RST2 during a portion of the first period TRrst1 (for example, the central period) and a portion of the second period TRrst2 (for example, the central period), and therefore can reliably and appropriately reset (initialize) the plurality of integrating circuits 41 and the plurality of integrating circuits 42 with a common reset signal. Therefore, the current detection device 10 according to this embodiment can improve detection accuracy.
[0094] The current detection device 10 according to this embodiment also includes a timing generation unit 31 that generates reset timing for the integrating circuit 41 and reset timing for the integrating circuit 42. The first reset output unit 132 outputs a reset signal RST1 based on the reset timing for the integrating circuit 41 generated by the timing generation unit 31 so that all of the plurality of integrating circuits 41 are in a reset state. The second reset output unit 133 outputs a reset signal RST2 based on the reset timing for the integrating circuit 42 generated by the timing generation unit 31 so that all of the plurality of integrating circuits 42 are in a reset state.
[0095] As a result, the current detection device 10 according to this embodiment is equipped with a timing generation unit 31, and by generating reset timing, it is possible to appropriately reset (initialize) the multiple integrating circuits 41 and the multiple integrating circuits 42 with a simple configuration.
[0096] The current detection device 10 according to this embodiment also includes a motor control unit 30 that controls the switching of the switching elements 21 and 22. The motor control unit 30 includes a timing generation unit 31.
[0097] As a result, the current detection device 10 according to this embodiment can generate reset timing through software processing by the CPU of the motor control unit 30, and can therefore appropriately reset (initialize) the multiple integrating circuits 41 and the multiple integrating circuits 42 with an even simpler configuration.
[0098] The current detection method according to this embodiment detects a current flowing through an inverter unit 20 that has a plurality of pairs of serially connected switching elements 21 and 22 and generates a multi-phase AC signal, and includes a first integration step, a second integration step, a detection processing step, a first reset output step, and a second reset output step. In the first integration step, each of a plurality of (e.g., three) integrating circuits 41 integrates the output of a Rogowski coil 11 that detects a current flowing through a corresponding switching element 21 of a plurality of phases (e.g., three phases) to output a first detection signal. In the second integration step, each of a plurality of integrating circuits 42 integrates the output of a Rogowski coil 12 that detects a current flowing through a corresponding switching element 22 of a plurality of phases to output a second detection signal. In the detection processing step, a detection processing unit 131 detects a current flowing through the inverter unit 20 based on the first detection signal and the second detection signal. In the first reset output step, the first reset output unit 32 outputs a reset signal RST1 (first reset signal) that resets the plurality of integrating circuits 41 during a first period TRrst1 in which all switching elements 21 are in the off state (non-conducting state). In the second reset output step, the second reset output unit 33 outputs a reset signal RST2 (second reset signal) that resets the plurality of integrating circuits 42 during a second period TRrst2 in which all switching elements 22 are in the off state (non-conducting state).
[0099] As a result, the current detection method according to this embodiment has the same effects as the current detection device 10 described above, and can simplify the configuration of the current detection device 10.
[0100] The present invention is not limited to the above-described embodiments and can be modified without departing from the spirit of the present invention. For example, in each of the above-described embodiments, the current detection device 10 is included in the motor control device 1 and is applied to current detection for controlling the drive of the motor 3, but the present invention is not limited to this. For example, the current detection device 10 may be applied to current detection in an inverter unit used in a power supply device or the like other than the motor control device 1.
[0101] In addition, in the above embodiment, an example was described in which the motor control unit 30 is equipped with a timing generation unit 31, but this is not limited to this, and the timing generation unit 31 may be provided outside the motor control unit 30 and realized by a logic circuit.
[0102] 10 is a diagram showing a modification of the timing generation unit 31 in this embodiment. The timing generation unit 31a shown in FIG. 10 is a modification realized by a logic circuit.
[0103] As shown in FIG. 10, the timing generation unit 31a includes NOR circuits (311-1, 311-2), delay circuits (312-1, 312-2, 313-1, 313-2), inverter circuits (314-1, 314-2), and AND circuits (315-1, 315-2).
[0104] The NOR circuit 311-1 and the NOR circuit 311-2 are three-input NOR circuits. The NOR circuit 311-1 outputs an output signal that is the NOR of the U-phase control signal S1 (waveform W4), the V-phase control signal S3 (waveform W5), and the W-phase control signal S5 (waveform W6) for the switching element 21.
[0105] The delay circuit 312-1 delays the output of the NOR circuit 311-1 by a predetermined period and outputs the delayed output to the next-stage delay circuit 313-1 and AND circuit 315-1.
[0106] Furthermore, the delay circuit 312-2 delays the output of the NOR circuit 311-2 by a predetermined period and outputs the delayed output to the next-stage delay circuit 313-2 and AND circuit 315-2.
[0107] The delay circuit 313-1 and the delay circuit 313-2 are delay circuits. The delay circuit 313-1 delays the output of the delay circuit 312-1 by a predetermined period and outputs the delayed output to the inverter circuit 314-1. The delay circuit 313-2 delays the output of the delay circuit 312-2 by a predetermined period and outputs the delayed output to the inverter circuit 314-2.
[0108] The inverter circuit 314-1 and the inverter circuit 314-2 are logic inversion circuits. The inverter circuit 314-1 logically inverts the output of the delay circuit 313-1 and outputs the result to the AND circuit 315-1. The inverter circuit 314-2 logically inverts the output of the delay circuit 313-2 and outputs the result to the AND circuit 315-2.
[0109] The AND circuit 315-1 and the AND circuit 315-2 are AND circuits. The AND circuit 315-1 outputs an output signal obtained by ANDing the output of the delay circuit 312-1 and the output of the inverter circuit 314-1 as the reset timing signal RT1. The AND circuit 315-2 outputs an output signal obtained by ANDing the output of the delay circuit 312-2 and the output of the inverter circuit 314-2 as the reset timing signal RT2.
[0110] 10, a logic circuit formed by a NOR circuit 311-1, delay circuits (312-1, 313-1), an inverter circuit 314-1, and an AND circuit 315-1 generates a reset timing signal RT1 for the integrating circuit 41.
[0111] Furthermore, a logic circuit formed by a NOR circuit 311-2, delay circuits (312-2, 313-2), an inverter circuit 314-2, and an AND circuit 315-2 generates a reset timing signal RT2 for the integrating circuit .
[0112] Thus, in this embodiment, the timing generation unit 31a may include a logic circuit that generates the reset timing of the integrating circuit 41 based on the control signals (S1, S3, S5) of the switching elements 21 corresponding to the multiple phases, and generates the reset timing of the integrating circuit 42 based on the control signals (S2, S4, S6) of the switching elements 22 corresponding to the multiple phases.
[0113] As a result, the current detection device 10 according to this embodiment can appropriately reset (initialize) the plurality of integrating circuits 41 and the plurality of integrating circuits 42 using a logic circuit with a simple configuration.
[0114] In the above embodiment, the current detection unit 13 (detection processing unit 131) outputs a signal obtained by converting a current waveform into a voltage, and the motor control unit 30 acquires the current value via an ADC (not shown). However, this is not limiting. The current detection unit 13 (detection processing unit 131) may include, for example, an ADC. That is, the current detection unit 13 (detection processing unit 131) may have some of the functions of the motor control unit 30. Furthermore, the motor control unit 30 may have some or all of the functions of the current detection unit 13 (detection processing unit 131).
[0115] In addition, in the above embodiment, an example has been described in which the current detection device 10 detects a current corresponding to a three-phase AC signal, but this is not limited to this and the current detection device 10 may be applied to applications with less than three phases or four or more phases.
[0116] Each component of the motor control device 1 and current detection device 10 described above has an internal computer system. A program for realizing the functions of each component of the motor control device 1 and current detection device 10 described above may be recorded on a computer-readable recording medium, and the program recorded on the recording medium may be read into a computer system and executed to perform processing in each component of the motor control device 1 and current detection device 10 described above. Here, "reading a program recorded on a recording medium into a computer system and executing it" includes installing the program into a computer system. The "computer system" referred to here includes hardware such as an OS and peripheral devices.
[0117] Furthermore, a "computer system" may include multiple computer devices connected via a network, including communication lines such as the Internet, WAN, LAN, and dedicated lines. Furthermore, a "computer-readable recording medium" refers to portable media such as flexible disks, optical magnetic disks, ROMs, and CD-ROMs, as well as storage devices such as hard disks built into a computer system. Thus, the recording medium storing the program may be a non-transitory recording medium such as a CD-ROM.
[0118] REFERENCE SIGNS LIST 1 Motor control device 2 DC power supply 3 Motor 4 Smoothing capacitor 10 Current detection device 11, 11-1, 11-2, 11-3, 12, 12-1, 12-2, 12-3 Rogowski coil 13 Current detection unit 20 Inverter unit 21, 21-1, 21-2, 21-3, 22, 22-1, 22-2, 22-3 Switching element 30 Motor control unit 31, 31a Timing generation unit 41, 41-1, 41-2, 41-3, 42, 42-1, 42-2, 42-3 Integration circuit 43 Resistor 44 Operational amplifier 45 Capacitor 46 Reset switch 50, 50-1, 50-2, 50-3 Adder 131 Detection processing unit 132 First reset output unit 133 Second reset output unit 311-1, 311-2 NOR circuits 312-1, 312-2, 313-1, 313-2 Delay circuits 314-1, 314-2 Inverter circuits 315-1, 315-2 AND circuits
Claims
1. A current detection device having a plurality of sets of first switching elements and second switching elements connected in series, and detecting a current flowing in an inverter unit that generates a multi-phase AC signal, comprising: a plurality of first Rogowski coils, each corresponding one-to-one to the first switching elements and detecting a current flowing in the first switching elements; a plurality of second Rogowski coils, each corresponding one-to-one to the second switching elements and detecting a current flowing in the second switching elements; a plurality of first integrating circuits, each corresponding one-to-one to the first Rogowski coils, having a reset function, and integrating the output of the first Rogowski coils to output a first detection signal; a plurality of second integrating circuits, each corresponding one-to-one to the second Rogowski coils, having a reset function, and integrating the output of the second Rogowski coils to output a second detection signal; and a detection processing unit that detects the current flowing in the inverter unit based on the first detection signal and the second detection signal. a first reset output unit that outputs a first reset signal to reset the plurality of first integrating circuits during a first period in which all of the first switching elements are in a non-conductive state; and a second reset output unit that outputs a second reset signal to reset the plurality of second integrating circuits during a second period in which all of the second switching elements are in a non-conductive state.
2. The current detection device according to claim 1, wherein the first reset output unit outputs the first reset signal during a portion of the first period so that all of the plurality of first integration circuits are in a reset state, and the second reset output unit outputs the second reset signal during a portion of the second period so that all of the plurality of second integration circuits are in a reset state.
3. A current detection device as described in claim 1 or claim 2, further comprising a timing generation unit that generates reset timing for the first integrating circuit and reset timing for the second integrating circuit, wherein the first reset output unit outputs the first reset signal based on the reset timing for the first integrating circuit generated by the timing generation unit so that all of the plurality of first integrating circuits are in a reset state, and the second reset output unit outputs the second reset signal based on the reset timing for the second integrating circuit generated by the timing generation unit so that all of the plurality of second integrating circuits are in a reset state.
4. The current detection device according to claim 3, further comprising a control unit that controls switching of the first switching element and the second switching element, the control unit comprising the timing generation unit.
5. The current detection device according to claim 3, wherein the timing generation unit comprises a logic circuit that generates reset timing for the first integrating circuit based on a control signal for the first switching element corresponding to the multiple phases, and generates reset timing for the second integrating circuit based on a control signal for the second switching element corresponding to the multiple phases.
6. A current detection method for detecting a current flowing in an inverter unit having a plurality of sets of first switching elements and second switching elements connected in series and generating a plurality of phase AC signals, comprising: a first integration step in which each of a plurality of first integrating circuits integrates an output of a first Rogowski coil that detects a current flowing in the first switching element corresponding to each of the plurality of phases and outputs a first detection signal; a second integration step in which each of a plurality of second integrating circuits integrates an output of a second Rogowski coil that detects a current flowing in the second switching element corresponding to each of the plurality of phases and outputs a second detection signal; a detection processing step in which a detection processing unit detects a current flowing in the inverter unit based on the first detection signal and the second detection signal; and a first reset output step in which a first reset output unit outputs a first reset signal that resets the plurality of first integrating circuits during a first period in which all of the first switching elements are in a non-conducting state. a second reset output step in which a second reset output unit outputs a second reset signal that resets the plurality of second integrating circuits during a second period in which all of the second switching elements are in a non-conductive state.