Silicon carbide semiconductor device, power module device, power conversion device and mobile body

Abstract

An object of the present invention is to provide a technique for increasing the overvoltage capability in a silicon carbide semiconductor device in which an SBD is embedded. The silicon carbide semiconductor device comprises a semiconductor layer of a first conductivity type provided with an active region including a unit cell region containing a Schottky barrier diode region and a MOSFET region, and an overvoltage excitation region. The overvoltage excitation region includes a Schottky barrier diode replacement region in which the first conductivity type of the Schottky barrier diode region is replaced by a second conductivity type.The area ratio of the Schottky barrier diode replacement region in the active region is not lower than 0.01% and lower than the area ratio of the Schottky barrier diode region in the active region in a case where the Schottky barrier diode region is not replaced by the Schottky barrier diode replacement region.

Description

TECHNICAL FIELDThe present disclosure relates to a silicon carbide semiconductor device, a power module device, a power converter, and a mobile body.BACKGROUND ARTThere is known a problem that a crystal defect such as a stacking fault or the like occurs in a crystal and thereby a forward voltage is shifted when a forward current, i.e., a bipolar current, is continuously conducted in a pn diode disposed in a semiconductor layer formed of silicon carbide (SiC). This is considered to be because the crystal defect such as the stacking fault or the like, which is a planar defect, expands with a basal plane dislocation or the like present in the semiconductor layer formed of silicon carbide as a starting point due to recombination energy generated when minority carriers injected through the pn diode are recombined with majority carriers. Since this crystal defect inhibits a flow of currents, when the crystal defect expands, currents are reduced and the forward voltage increases, and this causes reliability deterioration of a silicon carbide semiconductor device.Such an increase in forward voltage also occurs in a vertical MOSFET (metal oxide semiconductor field effect transistor) using silicon carbide. The vertical MOSFET includes a body diode which is a parasitic pn diode between a source and a drain, and when the forward current flows in the body diode, this causes deterioration in reliability of the vertical MOSFET as in the pn diode. For this reason, when the body diode of a SiC MOSFET is used as a free wheeling diode of the MOSFET, deterioration of the MOSFET characteristics sometimes occurs.As a structure for solving the above-described problem of reliability due to excitation of the forward current to the parasitic pn diode, a structure in which a unipolar diode is embedded as the free-wheeling diode in the silicon carbide semiconductor device, which is a unipolar transistor such as the MOSFET or the like, is proposed. For example, in Patent Documents 1 and 2, a structure is proposed in which a Schottky barrier diode (SBD) which is a unipolar diode is embedded in a unit cell of the MOSFET.In the silicon carbide semiconductor device formed of a unipolar transistor in which a unipolar diode is embedded, since the bipolar current of the body diode, i.e., the parasitic pn diode, can be reduced during a reflux operation, it is possible to suppress degradation of characteristics of the transistor.PRIOR ART DOCUMENTSPATENT DOCUMENT (E)[Patent Document 1] Japanese Patent Application Laid-Open No. 2003-017701[Patent Document 2] WO 2014 / .038110SUMMARYPROBLEM TO BE SOLVED BY THE INVENTIONHowever, the pn diode, which is a bipolar diode, becomes low resistance due to conductivity modulation by bipolar operation; however, the SBD, which is the unipolar diode, has a relatively high resistance. For this reason, the generated energy during excitation of the SBD is higher than that during excitation of the body diode which is the pn diode.As a result, in the silicon carbide semiconductor device in which the above-described SBD is embedded, the generated energy density is high when the SBD is excited by a surge current (overcurrent) such as a leakage current or the like, and strong heat generation occurs in the SBD. For this reason, a problem arises that a surge capability (surge capability), which is a breakdown tolerance for the overcurrent, becomes lower.The present disclosure is then intended to solve the above-described problem, and it is an object of the present disclosure to provide a technique for enabling to increase overvoltage capability in a silicon carbide semiconductor device in which an SBD is embedded.MEANS FOR SOLVING THE PROBLEMThe present disclosure is intended for a silicon carbide semiconductor device, and the silicon carbide semiconductor device includes a semiconductor layer of a first conductivity type provided with an active region including a unit cell region including a Schottky barrier diode region and a MOSFET region and a surge energy region (UV) and, in the silicon carbide semiconductor device, the surge energy region includes a Schottky barrier diode replacement region in which the first conductivity type of the Schottky barrier diode region is replaced with a second conductivity type, and an area ratio of the Schottky barrier diode replacement region in the active region is not lower than 0.01 % and lower than an area ratio of the Schottky barrier diode region in the active region in a case where the Schottky barrier diode region is not replaced with the Schottky barrier diode replacement region.EFFECTS OF THE INVENTIONAccording to the present disclosure, during a long reflux operation by an overcurrent such as a leakage current or the like in a chain reaction with an operation of a pn diode formed in the Schottky barrier diode replacement region, the body diode is operated earlier in a plane of the active region compared to a case where it is not replaced with the Schottky barrier diode replacement region and the generated energy density is reduced, and therefore it is possible to increase the overvoltage capability.These and other objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when taken in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a plan view illustrating a structure of a silicon carbide semiconductor device according to a first preferred embodiment; FIG. 2 is a plan view illustrating the structure of the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 3 is a schematic cross-sectional view illustrating the structure of the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 4 is a schematic plan view illustrating the structure of the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 5 is a schematic plan view illustrating the structure of the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 6 is a schematic cross-sectional view illustrating the structure of the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 7 is a plan view illustrating the structure of the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 8 is a schematic cross-sectional view illustrating the structure of the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 9 is a schematic cross-sectional view illustrating the structure of the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 10 is a schematic cross-sectional view for explaining a method of manufacturing the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 11 is a schematic cross-sectional view for explaining the method of manufacturing the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 12 is a schematic cross-sectional view for explaining the method of manufacturing the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 13 is a schematic cross-sectional view for explaining the method of manufacturing the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 14 is a schematic cross-sectional view for explaining the method of manufacturing the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 15 is a schematic cross-sectional view for explaining the method of manufacturing the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 16 is a schematic cross-sectional view for explaining the method of manufacturing the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 17 is a schematic cross-sectional view for explaining the method of manufacturing the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 18 is a view illustrating a simulation result of the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 19 is a diagram for explaining a switching operation of energization in the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 20 is a diagram for explaining a switching operation of energization in the silicon carbide semiconductor device according to the first preferred embodiment; FIG. 21 is a schematic cross-sectional view illustrating a structure of a silicon carbide semiconductor device according to a second preferred embodiment; FIG. 22 is a plan view illustrating a structure of a silicon carbide semiconductor device according to a third preferred embodiment; FIG. 23 is a plan view illustrating the structure of the silicon carbide semiconductor device according to the third preferred embodiment; FIG. 24 is a schematic cross-sectional view illustrating the structure of the silicon carbide semiconductor device according to the third preferred embodiment; FIG. 25 is a schematic cross-sectional view illustrating the structure of the silicon carbide semiconductor device according to the third preferred embodiment; FIG. 26 is a schematic cross-sectional view for explaining a method of manufacturing the silicon carbide semiconductor device according to the third preferred embodiment; FIG. 27 is a schematic cross-sectional view for explaining the method of manufacturing the silicon carbide semiconductor device according to the third preferred embodiment; FIG. 28 is a schematic cross-sectional view for explaining the method of manufacturing the silicon carbide semiconductor device according to the third preferred embodiment; FIG. 29 is a schematic cross-sectional view for explaining the method of manufacturing the silicon carbide semiconductor device according to the third preferred embodiment; FIG. 30 is a schematic cross-sectional view for explaining the method of manufacturing the silicon carbide semiconductor device according to the third preferred embodiment; FIG. 31 is a schematic cross-sectional view for explaining the method of manufacturing the silicon carbide semiconductor device according to the third preferred embodiment; FIG. 32 is a block diagram illustrating a structure of a power module device according to a fourth preferred embodiment; FIG. 33 is a block diagram illustrating a structure of a power converter according to a fifth preferred embodiment; and FIG. 34 is a view illustrating a structure of a mobile body according to a sixth preferred embodiment.DESCRIPTION OF THE EMBODIMENT(S)In the following description, "n" and "p" each represent a conductivity type of a semiconductor. In the present disclosure, description is made on the assumption that a first conductivity type is an n-type and a second conductivity type is a p-type; however, it may be assumed that the first conductivity type is a p-type and the second conductivity type is an n-type.Hereinafter, preferred embodiments of the present disclosure will be described with reference to accompanying drawings. Further, figures are schematically illustrated, and the correlation of the size and position of respective images illustrated in the various figures is not always accurately illustrated, but may be appropriately changed as appropriate. Moreover, in the following description, identical constituent elements are represented by the same reference numerals and each have the same or similar designation and function. Therefore, the description thereof is sometimes omitted.Hereinafter, a case where a silicon carbide semiconductor device is an SBD-embedded SiC MOSFET (SBD-embedded SiC MOSFET) will be described. The silicon carbide semiconductor device can perform stable operation under a high temperature and a high voltage and increase the switching speed, as compared with a silicon semiconductor device.<Die First Preferred Embodiment>FIG. 1 is a plan view illustrating a structure of a silicon carbide semiconductor device 100 according to the first preferred embodiment as viewed from an upper surface. The silicon carbide semiconductor device 100 according to the first preferred embodiment is a planar-type silicon carbide semiconductor device. In FIG. 1, a gate pad 81 is formed on a part of the upper surface of the silicon carbide semiconductor device 100, and a source electrode 80 is formed adjacent thereto. Further, a gate wiring 82 extending from the gate pad 81 is formed.(1) Planar Strip StructureFIG. 2 is a plan view illustrating a silicon carbide layer of the silicon carbide semiconductor device 100 according to the first preferred embodiment as viewed from the upper surface. This FIG. 2 corresponds to a plan view of FIG. 1 except for the source electrode 80, the gate pad 81, and the gate wiring 82. In FIG. 2, the unit cell regions each including an SBD region (Schottky barrier diode region) and MOSFET regions disposed on both sides of the SBD region sandwiching the SBD region are arranged while being aligned in stripes. The structure of the silicon carbide semiconductor device 100 in which such unit cell regions are arranged is referred to as a "stripe" structure.In FIG. 2, the unit cell regions each including an n-type first separation region 21 substantially corresponding to the SBD region and a p-type first well region 30 substantially corresponding to the MOSFET region are repeatedly arranged in one direction in plan view. A region including the unit cell region in which such an SBD embedded MOSFET is formed and an overvoltage excitation region described later is referred to as an active region. A region that is an outer peripheral region of the active region including a gate pad formation region 81, on which a second p-type well region 31 and the like are formed, is referred to as a terminal region (terminal region).FIG. 3 is a schematic cross-sectional view illustrating, as viewed from a longitudinal direction of the strip-shaped unit cell regions, a schematic structure from the source electrode 80 of FIG. 1 to the gate wiring 82 in an outer peripheral portion of the silicon carbide semiconductor device 100.In the silicon carbide semiconductor device 100 illustrated in FIG. 3, a drift layer 20 formed of n-type silicon carbide is formed on a surface of a semiconductor substrate 10 formed of n-type low-resistance silicon carbide. In the present first preferred embodiment, a semiconductor layer on which an active region is disposed may be the drift layer 20 on the semiconductor substrate 10, but may be the semiconductor substrate 10. In a surface layer portion of the drift layer 20 positioned substantially corresponding to the region where the gate wiring 82 is disposed as described with reference to FIG. 1, as illustrated in the cross-sectional view of FIG. 3, the second well region 31 formed of p-type silicon carbide is disposed.In the surface layer portion of the drift layer 20 in the active region, which is a region below the source electrode 80 described with reference to FIG. 1, the first well region 30 formed of p-type silicon carbide is disposed. As illustrated in FIG. 2, the first well regions 30 are formed into stripes in plan view. A well region obtained by connecting a plurality of the first well regions 30 to each other may be provided, or a plurality of separate first well regions 30 may be provided.As illustrated in FIG. 3, in the surface layer portion of the first well region 30, a source region 40 formed of n-type silicon carbide is formed at a position a certain distance inward from an outer periphery of the first well region 30.On one end side of the source region 40 in the surface layer portion of the first well region 30, a contact region 35 formed of low-resistance p-type silicon carbide is formed. Between the adjacent contact regions 35, the first separation region 21 formed of silicon carbide penetrating the first well region 30 is formed. As illustrated in FIG. 2, the first separation regions 21 are formed into stripes. The conductivity type of the first separation region 21 is an n-type which is the same as that of the drift layer 20, and the concentration of n-type impurities of the first separation region 21 may be the same as that of the drift layer 20 or may be higher or lower than that of the drift layer 20.As illustrated in FIG. 3, on a surface side of the first separation region 21, stripe-shaped Schottky electrodes 71 each of which is Schottky-connected to the first separation region 21 via a Schottky contact are formed in plan view. It is preferable that the Schottky electrode 71 is formed in a region including the first separation region 21 accordingly in plan view.On a surface of the source region 40, an ohmic electrode 70 is formed. On top of this, the source electrode 80 connected to the ohmic electrode 70, the Schottky electrode 71 and the contact region 35 is formed. The first well region 30 can easily emit electrons or positive holes to and receive electrons or positive holes from the ohmic electrode 70 via the low-resistance contact region 35.In a region other than the first separation region 21, a second separation region 22 formed of n-type silicon carbide is formed in the region between the adjacent first well regions 30. The conductivity type of the second separation region 22 is an n-type that is the same as that of the drift layer 20, and the concentration of n-type impurities of the second separation region 22 may be the same as that of the drift layer 20 or may be higher or lower than that of the drift layer 20.On surfaces of the adjacent first well regions 30, the second separation region 22 therebetween, and the respective source regions 40 within these first well regions 30, a gate insulating film 50 formed of, for example, silicon oxide is selectively formed. On at least the gate insulating film 50 on an upper surface of the first well region 30, a gate electrode 60 formed of, for example, polycrystalline silicon is formed. A surface layer portion of the first well region 30 that faces the gate electrode 60 with the gate insulating film 50 interposed therebetween is referred to as a "channel region".On an outer side of the first well region 30 in an outermost periphery of the silicon carbide semiconductor device 100, the second well region 31 is formed, and between the first well region 30 and the second well region 31, a third separation region 23 formed of silicon carbide is formed. The conductivity type of the third separation region 23 is an n-type that is the same as that of the drift layer 20, and the n-type impurity concentration of the third separation region 23 may be the same as that of the drift layer 20 or may be higher or lower than that of the drift layer 20.The gate insulating film 50 is selectively formed on the second well region 31 as on the first well region 30, and on the gate insulating film 50, the gate electrode 60 electrically connected to the gate electrode 60 formed on the first well region 30 is formed.In a region having a certain proportion of an upper layer portion of the second well region 31, a conductive silicon carbide layer 45 formed of silicon carbide having a higher n-type impurity concentration than that of the drift layer 20 and a low resistance is formed. The conductive silicon carbide layer 45 has a lower sheet resistance than that of the second well region 31, and forms a pn junction with the second p-type well region 31. The conductive silicon carbide layer 45 is formed over the width that is half or more of the width toward a (transverse) cross section of the second well region 31, for example. A portion in which the conductive silicon carbide layer 45 is formed in the width that is half or more of the width in the cross-sectional direction of the second well portion 31 does not necessarily need to be arranged in all the cross-sections, but may be arranged in some of the cross-sections.Between the gate electrode 60 and the source electrode 80, an interlayer insulating film 55 formed of, for example, silicon oxide is formed. The gate electrode 60 and the gate wiring 82 above the second well region 31 are connected to each other through a gate contact hole 95 formed in the interlayer insulating film 55. Further, on an outer peripheral side of the second well region 31, that is, on the side opposite to the first well region 30, a JTE region 38 formed of p-type silicon carbide is formed. The impurity concentration of the JTE region 38 is lower than that of the second well region 31. In addition, a combination of the JTE region 38 and the FLR may be formed.On the second well region 31 and the silicon carbide conductive layer 45, a field insulating film 51 having a film thickness larger than that of the gate insulating film 50 or the gate insulating film 50 is formed. In a part of the gate insulating film 50 or the field insulating film 51 on a surface of the silicon carbide conductive layer 45, an opening, i.e., a terminal region contact hole 91, is formed. The conductive silicon carbide layer 45 and the source electrode 80 are connected via an ohmic contact via an ohmic electrode 72 positioned at a terminal portion on the lower side of the terminal portion contact hole 91.The terminal region contact hole 91 penetrates through the gate insulating film 50 or the field insulating film 51 and the interlayer insulating film 55, thereby forming ohmic connection between the silicon carbide conductive layer 45 and the source electrode 80, but not connecting the second well region 31 and the source electrode 80. Further, the width of the conductive silicon carbide layer 45 is larger than the diameter or the width of the terminal region contact hole 91. in the present first preferred embodiment, the second well region 31 is not directly connected to the source electrode 80 via an ohmic contact.In the active region, the ohmic electrode 70, the Schottky electrode 71, and the contact region 35 are connected to the source electrode 80 on the interlayer insulating film 55 through an active region contact hole 90 penetrating through the interlayer insulating film 55 and the gate insulating film 50.On a back surface side of the semiconductor substrate 10, a drain electrode 84 is formed.In a case where the plane orientation of a first main surface of the semiconductor substrate 10 is a (0001) plane having an off angle (<11-20> direction, an extending direction of the stripe-shaped first well regions 30 may be parallel to the <11-20> direction, which is an off direction (off direction), or parallel to an orthogonal direction of the off direction.FIG. 4 is a schematic plan view schematically illustrating the structure of the silicon carbide layer illustrated in FIG. 2. The active region 15 includes an overvoltage excitation region 301 and the above-described unit cell region.The overvoltage excitation region 301 does not include the first separation region 21 in contact with the Schottky electrode 71, and is defined as, for example, a region whose periphery is surrounded by the first separation region 21. Herein, "surrounded" is not necessarily limited to "surrounded by a continuous first separation region 21", but includes "adjacent to a plurality of first separation regions 21 that are periodically arranged being separated at end portions in the extending direction of the stripes", as illustrated in the plan view of FIG. 2. In other words, the overvoltage excitation region 301 is a region whose circumference is adjacent to and preferably surrounded by the first separation region 21 connected to the Schottky electrode 71 in plan view in the active region 15 covered with the source electrode 80.The area of the overvoltage excitation region 301 is sufficiently smaller than that of the entire active region 15, and the overvoltage excitation region 301 is disposed in the active region 15. Further, like the unit cell region, the overvoltage excitation region 301 is covered with the source electrode 80. From these points, the overvoltage excitation region 301 is clearly different from the second well region 31 formed below the gate pad 81 around the active region 15 and having a relatively large area.The overvoltage excitation portion 301 is formed within at least one unit cell portion in one chip. If the overvoltage excitation region 301 is formed within two or more unit cell regions, it is preferable that the overvoltage excitation region 301 is formed dispersedly in the chip in plan view.As described later, the overvoltage excitation region 301 includes a Schottky barrier diode replacement region 302 in which the n-type of the SBD region in the unit cell region is replaced with the p-type, and the p-type Schottky barrier diode replacement region 302 cooperates with the n-type drift layer 20, thereby performing a function of the pn diode. In the silicon carbide semiconductor device 100, during a reflux operation in which a current is conducted over an energization time sufficiently long, i.e., 1 to 10 ms or the like, a body diode of the unit cell region is operated in a chain reaction with the operation of the pn diode. The body diode here includes a parasitic pn diode which is a free wheeling diode of the MOSFET.In the present first preferred embodiment, the area ratio of the p-type Schottky barrier diode replacement region 302 in the active region 15 in plan view is not less than 0.01 % and less than the area ratio of the SBD region not replaced by the Schottky barrier diode replacement region 302 in the active region 15, and more preferably not less than 0.01 % and not more than 5 %.If the area ratio of the Schottky barrier diode replacement region 302 is equal to that of the SBD region not replaced by the Schottky barrier diode replacement region 302, there is no SBD in the plane of the active region 15 and the function as the SBD-embedded MOSFET is lost.Further, as the in-plane ratio of the Schottky barrier diode replacement region 302 becomes smaller, an effect on original electrical characteristics becomes smaller, and then the efficiency of power conversion is expected to increase (loss is reduced).In the silicon carbide semiconductor device 100 according to the present first preferred embodiment, during the reflux operation described above, the area ratio of a region 16 for a body diode chain operation, which is a region where the body diode operates in a chain reaction, in the active region 15 increases as the energization time becomes longer, and finally the body diode operates entirely in the active region 15. FIG. 5 is a view illustrating an example of such a region 16 for a body diode chain operation. The speed at which the body diode chain operation region 16 fully spreads in the active region 15 during the above-described reflux operation is adjusted by adjusting the size of each overvoltage excitation region 301 and the number of overvoltage excitation regions 301.FIG. 6 is a schematic cross-sectional view illustrating a schematic structure of the overvoltage excitation region 301 and the active region contact hole 90 when viewed from the longitudinal direction of the unit cell striped regions.On an inner side of the overvoltage excitation region 301, one or more Schottky barrier diode replacement regions 302 formed of p-type silicon carbide are formed in the surface layer portion of the drift layer 20. The Schottky barrier diode replacement region 302 is disposed between the Schottky electrode 71 and the drift layer 20, and the pn junction is thus disposed at a certain midpoint of a conduction path between the source electrode 80 and the drain electrode 84. In other words, the Schottky electrode 71 is not connected to an n-type silicon carbide layer such as the first n-type separation region 21 or the like having the same n-type as the drift layer 20, and the Schottky electrode 71 and the drift layer 20 are separated by the Schottky barrier diode replacement region 302. Further, herein, "connected" refers to a state in which the Schottky current can flow in a cross-sectional direction of a chip without the pn junction being interposed at a certain midpoint therebetween.In the present first preferred embodiment, the Schottky barrier diode replacement region 302 is the p-type region in which the first separation region 21 sandwiched between the adjacent first well regions 30 is replaced. The Schottky barrier diode replacement region 302 is formed below each of the periodically formed Schottky electrodes 71. At this time, the first well region 30 adjacent to the Schottky barrier diode replacement region 302 is a p-type region. In such a layout, the width of the Schottky barrier diode replacement region 302 and the first well region 30 adjacent thereto inevitably becomes larger than the width of the first well region 30. two merits (advantages) of this layout will be exemplified below.The first advantage (advantage) is that the gate electrode 60 and the active region contact hole 90 can be formed within the overvoltage excitation region 301 at the same center-to-center distance as that in a surrounding region. Since the gate electrode 60 and the active region contact hole 90 can thereby be completely arranged within the chip at regular intervals, it is possible to increase the uniformity of processing. Since it is not necessary to interrupt or branch the gate electrode 60 and the active region contact hole 90 at an end portion of the overvoltage excitation region 301 in the extension direction of the stripe, it is possible to further increase the uniformity of processing.The second advantage (advantage) is that the gate electrode 60 can be formed to penetrate the overvoltage excitation region 301 in plan view. This results in the effect of preventing interruption of propagation of the gate potential through the overvoltage excitation region 301. Particularly in the stripe structure, when the gate potential is interrupted by the overvoltage excitation region 301, the gate potential cannot propagate any further therefrom and thereby a region without the function of the MOSFET is generated, and this leads to a weakness (a disadvantage) that the chip area cannot be used efficiently. Since the propagation of the gate potential through the overvoltage excitation region 301 is not interrupted, this weakness (disadvantage) can be reduced. Further, since a delay in the propagation of the gate potential in the present structure is smaller than that in a structure in which the gate electrode structure is formed so as to bypass the overvoltage excitation region 301, it is possible to produce effects that a switching operation achieves at high speed and a local concentration of the switching current is suppressed.The active region contact hole 90 formed above the Schottky barrier diode replacement region 302 is referred to herein as the second active region contact hole 90B, and the active region contact hole 90, other than the above-described contact hole, is referred to as the first active region contact hole 90A. The source electrode 80 is in contact with both the source region 40 and the first separation region 21 through the first active region contact hole 90A, while the source electrode 80 is in contact with the p-type Schottky barrier diode replacement region 302 through the second active region contact hole 90B. For this reason, a pn diode, which is formed by the pn junction between the Schottky barrier diode replacement region 302 and the drift layer 20 and conducts a current in a thickness direction of the chip, is formed at a position separated from the SBD.In the present first preferred embodiment, within the overvoltage excitation region 301, the second separation region 22 is disposed between the adjacent two Schottky barrier diode replacement regions 302 or between the Schottky barrier diode replacement region 302 and the first well region 30. The source region 40 is formed at a certain distance inward away from the end portion in the surface layer of the Schottky barrier diode replacement region 302, and the gate insulating film 50 and the gate electrode 60 are formed in a region from the second separation region 22 to the source region 40. In the present first preferred embodiment, a channel structure such as the MOSFET region of the active region 15 is formed on an inner side of the Schottky barrier diode replacement region 302, and the overvoltage excitation region 301 also performs the function of the MOSFET.In the channel structure, a separation distance between the source region 40 and the second separation region 22 is referred to as a channel length. It is preferable that the channel length formed in the overvoltage excitation region 301 be equal to or longer than that formed in the MOSFET region of the active region 15. Further, when the channel length formed in the overvoltage excitation region 301 is made too short, a current at a low gate voltage flows by a short channel effect in the overvoltage excitation region 301, and as a result, a threshold voltage of the entire chip is reduced, and this facilitates initiation of a malfunction of the device. On the other hand, if the channel length formed in the overvoltage excitation region 301 is set too long, a channel current in the overvoltage excitation region 301 is reduced, and generation of the effect to be generated by the channel current described later is made difficult. For these reasons, it is preferable that the channel length formed in the overvoltage excitation region 301 be equal to that formed in the MOSFET region of the active region 15.For the same reasons, it is preferable that the impurity concentration of the channel formed in the overvoltage excitation region 301 be the same as that formed in the MOSFET region of the active region 15. In addition, it is preferable that the film thickness of the gate insulating film 50 in the overvoltage excitation region 301 is equal to that of the gate insulating film 50 in the MOSFET region of the active region 15. With such a structure, it is possible to prevent a reduction in a gate breakdown voltage of the Schottky barrier diode replacement region 302 and prevent a reduction in the channel current with respect to the MOSFET region.(2) Planar grid structureFIG. 7 is a plan view illustrating another structure of the silicon carbide semiconductor device 100 according to the first preferred embodiment when viewed from the upper surface, and corresponds to the plan view of FIG. 2. in the silicon carbide semiconductor device 100 illustrated in FIG. 7, the unit cell regions each including the SBD region and the MOSFET region surrounding the SBD region are repeatedly arranged in both a longitudinal direction and a transverse direction in plan view. The structure of the silicon carbide semiconductor device 100 in which such unit cell regions are arranged is referred to as a "lattice" structure.In FIG. 7, the unit cell regions each including the first n-type separation region 21 substantially corresponding to the SBD region and the first p-type well region 30 substantially corresponding to the MOSFET region are repeatedly arranged in both the longitudinal direction and the transverse direction in plan view. A region including the unit cell region in which such an SBD embedded MOSFET is formed and the overvoltage excitation region is referred to as the active region. A region that is an outer peripheral region of the active region including the gate pad formation region 81 on which the second p-type well region 31 and the like are formed is referred to as the terminal region.FIG. 8 is a schematic cross-sectional view illustrating a schematic structure from the source electrode 80 of FIG. 1 to the gate wiring 82 in the outer peripheral portion of the silicon carbide semiconductor device 100.In the silicon carbide semiconductor device 100 illustrated in FIG. 8, the drift layer 20 formed of n-type silicon carbide is formed on the surface of the semiconductor substrate 10 formed of low-resistance n-type silicon carbide. In the surface layer portion of the drift layer 20 substantially corresponding to the region where the gate wiring 82 is disposed as described with reference to FIG. 1, as illustrated in the cross-sectional view of FIG. 8, the second well region 31 formed of p-type silicon carbide is disposed.In the surface layer portion of the drift layer 20 in the active region, which is a region below the source electrode 80 described with reference to FIG. 1, a plurality of first well regions 30 each formed of p-type silicon carbide are disposed.In the surface layer portion of the first well region 30, the source region 40 formed of n-type silicon carbide is formed at a position a certain distance inward from the outer periphery of the first well region 30.On one end side of the source region 40 in the surface layer portion of the first well region 30, the contact region 35 formed of low-resistance p-type silicon carbide is formed. Between the adjacent contact regions 35, the first separation region 21 formed of silicon carbide is formed, which penetrates the first well region 30. The conductivity type of the first separation region 21 is the n-type which is the same as that of the drift layer 20, and the n-type impurity concentration of the first separation region 21 may be the same as that of the drift layer 20 or may be higher or lower than that of the drift layer 20.On the surface side of the first separation region 21, the Schottky electrode 71 is formed, which is connected to the first separation region 21 via a Schottky contact. It is preferable that the Schottky electrode 71 is formed in the region including the first separation region 21 corresponding thereto in plan view.On the surface of the source region 40, the ohmic electrode 70 is formed. The source electrode 80 connected to the ohmic electrode 70, the Schottky electrode 71 and the contact region 35 is formed thereon. The first well region 30 can easily emit electrons or positive holes to and receive electrons or positive holes from the ohmic electrode 70 via the low-resistance contact region 35.In a region other than the first separation region 21, in the region between the adjacent first well regions 30, the second separation region 22 formed of n-type silicon carbide is formed. The conductivity type of the second separation region 22 is the n-type which is the same as that of the drift layer 20, and the n-type impurity concentration of the second separation region 22 may be the same as that of the drift layer 20 or may be higher or lower than that of the drift layer 20.On surfaces of the adjacent first well regions 30, the second separation region 22 therebetween, and the respective source regions 40 within these first well regions 30, the gate insulating film 50 formed of, for example, silicon oxide is selectively formed. On at least the gate insulating film 50 on the upper surface of the first well region 30, the gate electrode 60 formed of, for example, polycrystalline silicon is formed. The surface layer portion of the first well region 30 that faces the gate electrode 60 with the gate insulating film 50 interposed therebetween is referred to as the "channel region".On the outer side of the first well region 30 in the outermost periphery of the silicon carbide semiconductor layer 100, the second well region 31 is formed, and between the first well region 30 and the second well region 31, the third separation region 23 formed of silicon carbide is formed. The conductivity type of the third separation region 23 is the n-type which is the same as that of the drift layer 20, and the concentration of n-type impurities of the third separation region 23 may be the same as that of the drift layer 20 or may be higher or lower than that of the drift layer 20.The gate insulating film 50 is selectively formed on the second well region 31 as on the first well region 30, and the gate electrode 60 electrically connected to the gate electrode 60 formed on the first well region 30 is formed on the gate insulating film 50.In a region having a certain portion of the upper layer portion of the second well region 31, the conductive silicon carbide layer 45 formed of silicon carbide is formed, which has a higher concentration of n-type impurities than those of the drift layer 20 and a low resistance. The conductive silicon carbide layer 45 has a lower sheet resistance than that of the second well region 31, and forms the pn junction with the p-type second well region 31. The conductive silicon carbide layer 45 is formed over the width, which is half or more of the width in the (transverse) cross-sectional direction of the second well region 31, for example. A portion where the conductive silicon carbide layer 45 is formed with the width that is half or more of the width in the cross-sectional direction of the second well portion 31 does not necessarily need to be arranged in all the cross-sections, but may be arranged in some of the cross-sections.Between the gate electrode 60 and the source electrode 80, the interlayer insulating film 55 formed of, for example, silicon oxide is formed. The gate electrode 60 and the gate wiring 82 above the second well region 31 are connected through the gate contact hole 95 formed in the interlayer insulating film 55. On the outer peripheral side of the second well region 31, i.e., on the side opposite to the first well region 30, the JTE region 38 formed of p-type silicon carbide is further formed. The impurity concentration of the JTE region 38 is lower than that of the second well region 31. Moreover, the combination of the JTE region 38 and the FLR may be formed.On the second well region 31 and the silicon carbide conductive layer 45, the field insulating film 51 is formed with a film thickness larger than that of the gate insulating film 50 or the gate insulating film 50. In a part of the gate insulating film 50 or the field insulating film 51 on the surface of the silicon carbide conductive layer 45, an opening, i.e., a terminal region contact hole 91, is formed. The conductive silicon carbide layer 45 and the source electrode 80 are connected to each other through ohmic contact by the ohmic electrode 72 positioned on the lower side of the terminal portion contact hole 91 at the terminal portion.The terminal region contact hole 91 penetrates through the gate insulating film 50 or the field insulating film 51 and the interlayer insulating film 55, thereby establishing ohmic connection between the silicon carbide conductive layer 45 and the source electrode 80 but not connecting the second well region 31 and the source electrode 80. Further, the width of the conductive silicon carbide layer 45 is larger than the diameter or the width of the land contact hole 91.In the present first preferred embodiment, the second well region 31 is not directly connected to the source electrode 80 via an ohmic contact.In the active region, the ohmic electrode 70, the Schottky electrode 71, and the contact region 35 are connected to the source electrode 80 on the interlayer insulating film 55 through the active region contact hole 90 penetrating through the interlayer insulating film 55 and the gate insulating film 50.On the back surface side of the semiconductor substrate 10, the drain electrode 84 is formed.FIG. 9 is a schematic cross-sectional view illustrating a schematic structure of the overvoltage excitation region 301 and the active region contact hole 90. In this cross section, since the structure of the overvoltage excitation region 301 and the Schottky barrier diode replacement region 302 is the same as that illustrated in FIG. 6, detailed description is omitted. Further, the area ratio of the Schottky barrier diode replacement region 302 in the active region 15 in plan view is also the same as that described with reference to FIGS. 4 and 5.(3) Supplemental Explanation Common to Stripe and Lattice StructuresIn a region of the active region closest to the terminal region, an SBD structure having a high surface density such as a folded structure or the like may be formed. Further, in a region of the terminal region closest to the active region, a high surface density structure of a terminal portion including a JBS (Junction Barrier Schottky) in which many SBDs are formed may be formed. Moreover, a measuring cell for detecting a current can be arranged within the active region.The concentration of n-type impurities of the second separation region 22 may be higher than that of the drift layer 20. If the drift layer 20 and the second separation region 22 are thus formed, an ON resistance can be made lower.(4) Method of Making a Planar StructureNext, with reference to the schematic cross-sectional views of FIGS. 10 to 17, a method of manufacturing the planar-type silicon carbide semiconductor device 100 according to the first preferred embodiment will be described. Although a method of manufacturing the stripe-type silicon carbide semiconductor device 100 will be described, the same applies hereinafter to a method of manufacturing the lattice-type silicon carbide semiconductor device 100.First, the semiconductor substrate 10 formed of n-type low resistance silicon carbide and having a 4H polytype in which the plane orientation of the first main surface is the (0001) plane with a dislocation angle is prepared. On the semiconductor substrate 10, the drift layer 20 made of silicon carbide is epitaxially grown by the chemical vapor deposition (CVD) method, has an n-type impurity concentration of, for example, 1×10 15 to 1×10 17 cm -3 and a thickness of, for example, 5 to 50 μm.Subsequently, an implantation mask made of a photoresist or the like is formed in a predetermined region of a surface of the drift layer 20, and ions of Al (aluminum), which is a p-type impurity, are implanted. At this time, the depth of ion implantation of Al does not exceed the thickness of the drift layer 20, and is, for example, about 0.5 to 3 μm. Further, the impurity concentration of Al from which ions are implanted is in a range of, for example, 1×10 17 to 1×10 19 cm -3, which is higher than the impurity concentration of the drift layer 20. Thereafter, the implantation mask is removed. The region into which ions of Al are implanted in this process step becomes the first well region 30 in the active region and becomes the second well region 31 in the terminal region.Next, in a predetermined region of the surface of the drift layer 20, the implantation mask is formed of a photoresist or the like, and ions of Al which is a p-type impurity are implanted. At this time, the depth of ion implantation of Al does not exceed the thickness of the drift layer 20, and is, for example, about 0.5 to 3 μm. Further, the impurity concentration of Al from which ions are implanted is in a range of, for example, 1×10 17 to 1×10 19 cm -3, which is higher than the impurity concentration of the drift layer 20. Thereafter, the implantation mask is removed. The region into which ions of Al are implanted in this process step becomes the Schottky barrier diode replacement region 302.A part of the surfaces of the first well regions 30 adjacent to the Schottky barrier diode replacement region 302 becomes the channel region. In order to set a threshold voltage of the first well regions 30 adjacent to the Schottky barrier diode replacement region 302 to be not lower than or preferably equal to that of the MOSFET region, the concentration of p-type impurities of the surface of the Schottky barrier diode replacement region 302 and the adjacent first well regions 30 may be not lower than or preferably equal to that of the surface of the first well region 30 in the MOSFET region. As a method for achieving this, the implantation process for the Schottky barrier diode replacement region 302 and the adjacent first well regions 30 and that for the first well region 30 in the MOSFET region are performed as the same process step. By such a method, the concentrations of p-type impurities of the surfaces of the Schottky barrier diode replacement region 302 and the first well region 30 can be made equal to each other, and the number of process steps can be reduced.Next, in a predetermined region of the surface of the drift layer 20 in the terminal region, the implantation mask is formed of a photoresist or the like, and ions of Al which is a p-type impurity are implanted. At this time, the depth of ion implantation of Al does not exceed the thickness of the drift layer 20, and is, for example, about 0.5 to 3 μm. Further, the impurity concentration of Al from which ions are implanted is in a range of, for example, 1×10 16 to 1×10 18 cm -3, which is higher than the impurity concentration of the drift layer 20 and lower than the impurity concentrations of the first well region 30 and the Schottky barrier diode replacement region 302. Thereafter, the implantation mask is removed. The region into which ions of Al are implanted in this process step becomes the JTE region 38. Similarly, in a predetermined region of the surface layer portions of the first well region 30 and the Schottky barrier diode replacement region 302, the contact region 35 is formed by performing ion implantation of Al having an impurity concentration of, for example, 1×10 16 to 1×10 18 cm -3, which is higher than those of these regions.Subsequently, the implantation mask is formed of a photoresist or the like so that a predetermined portion is exposed within the surface layer portions of the first well region 30 and the Schottky barrier diode replacement region 302, and ions of N (nitrogen) which is an n-type impurity are implanted. The depth of ion implantation of N is set shallower than the thickness of the first well region 30. Further, the impurity concentration of N from which ions are implanted is in a range of, for example, 1×10 18 to 1×10 21 cm -3, which is higher than the concentration of p-type impurities of the first well region 30 and the Schottky barrier diode replacement region 302. An n-type region in the region into which ions of N are implanted in this process step becomes the source region 40.Similarly, the implantation mask is formed of a photoresist or the like so that a predetermined portion within the second well region 31 is exposed in the terminal region, and ions of N which is an n-type impurity are implanted. The depth of ion implantation of N is set shallower than the thickness of the second well region 31. Further, the impurity concentration of N from which ions are implanted is in a range of, for example, 1×10 18 to 1×10 21 cm -3, which is higher than the concentration of p-type impurities of the second well region 31. An n-type region in the region where ions of N are implanted in this process step becomes the conductive silicon carbide layer 45.The conductive silicon carbide layer 45 and the source region 40 may be formed in the same process step, with the same thickness and with the same concentration, or may be formed in different process steps, with different thicknesses and with different impurity concentrations.Next, in an inert gas atmosphere of an argon gas (Ar) or the like, annealing is performed on the drift layer 20 using a heat treatment device at a temperature of 1300 to 1900° C., for example, for 30 seconds to one hour. By this annealing, the N and Al implanted as ions are electrically activated. FIGS. 10 and 11 are cross-sectional views illustrating the same region as shown in FIGS. 3 and 4 where the process steps up to this stage are completed.Subsequently, using the CVD method, the photolithography technique, or the like, the field insulating film 51 formed of silicon oxide is formed in a region other than the active region in which the first well region 30 and the overvoltage excitation region 301 are formed, i.e., on the terminal region. The film thickness of the field insulating film 51 is, for example, 0.5 to 2 μm and is larger than that of the gate insulating film 50.Next, a surface of the silicon carbide layer not covered with the field insulating film 51 is thermally oxidized to thereby form a silicon oxide film having a desired thickness as the gate insulating film 50. Subsequently, a polycrystalline silicon film having conductivity is formed on the gate insulating film 50 and the field insulating film 51 by the low pressure CVD method, for example, and then patterned to thereby form the gate electrode 60. Next, by the low pressure CVD method, the interlayer insulating film 55 having a film thickness larger than that of the gate insulating film 50 and made of, for example, silicon oxide is formed. FIGS. 12 and 13 are cross-sectional views illustrating the same region as shown in FIGS. 3 and 6 where the process steps up to this stage are completed.Subsequently, a part of the active region contact hole 90 that penetrates the interlayer insulating film 55 and the gate insulating film 50 and reaches the contact region 35 and the source region 40 within the active region and the terminal region contact hole 91 that reaches the silicon carbide conductive layer 45 in the terminal region are formed. However, in a remaining part of the active region contact hole 90, i.e., a portion where the Schottky electrode 71 is to be formed, the interlayer insulating film 55 and the gate insulating film 50 are left.Next, on a surface of the silicon carbide layer exposed from a part of the active region contact hole 90 and the terminal region contact hole 91, a metal film mainly made of Ni (nickel) is formed by, for example, the sputtering method or the like, and then the heat treatment is performed at a temperature of 600 to 1100° C. By this operation, the metal film mainly made of Ni and the silicon carbide layer react with each other to thereby form a silicide layer between the metal film and the silicon carbide layer. Then, the remaining metal film that does not form the silicide layer is removed by wet etching. By this process, the remaining silicide layer becomes the ohmic electrode 70 and the ohmic electrode 72 in the terminal portion. FIGS. 14 and 15 are cross-sectional views illustrating the same region shown in FIGS. 3 and 6 where the process steps up to this stage are completed.Then, by forming a metal film mainly made of Ni on the back surface (second main surface) of the semiconductor substrate 10 and performing heat treatment thereon, the drain electrode 84, which is a back ohmic electrode, is formed on the back surface of the semiconductor substrate 10.Next, a resist mask 99 is formed, and the interlayer insulating film 55 and the gate insulating film 50 are removed on the first separation region 21 and the Schottky barrier diode replacement region 302 and the interlayer insulating film 55 to become the gate contact hole 95. As a method for removing the insulating films, a wet etching method that does not damage the surface of the silicon carbide layer serving as a Schottky interface is used. FIGS. 16 and 17 are cross-sectional views illustrating the same region shown in FIGS. 3 and 6 where the process steps up to this stage are completed.Subsequently, after removing the resist mask 99 by the sputtering method or the like, a metal film to be a Schottky electrode is deposited. Then, by using patterning using a photoresist or the like, the Schottky electrode 71 is formed on the first separation region 21 and the Schottky barrier diode replacement region 302 within the active region contact hole 90. The material of the Schottky electrode 71 is, for example, Ti (titanium), Mo (molybdenum), or the like.Next, a wiring layer of Al or the like is formed on the surface of the substrate subjected to these treatments (process steps) up to this stage by the sputtering method or the vapor deposition method and processed into a predetermined shape by the photolithography technique, thereby forming the source electrode 80 in contact with the source-side ohmic electrode 70, the ohmic electrode 72 at the terminal portion, and the Schottky electrode 71, and the gate pad 81 and the gate wiring 82 in contact with the gate electrode 60. By the above-described process, the silicon carbide semiconductor device 100 according to the present first preferred embodiment illustrated in FIGS. 3 and 6 is manufactured.(Explanation of Operation)Next, an operation of the silicon carbide semiconductor device 100 according to the present first preferred embodiment will be described. Herein, description will be made taking the silicon carbide semiconductor device whose semiconductor material is 4H-type silicon carbide as an example. The diffusion potential of the pn junction in this case is about 2 V.The operation of the silicon carbide semiconductor device 100 according to the present first preferred embodiment is divided into four normal operation states and an abnormal state for ease of description.The first normal operation state is a state in a case where a voltage applied to the drain electrode 84 is higher than that applied to the source electrode 80 and a positive voltage not lower than the threshold voltage is applied to the gate electrode 60, and this state is hereinafter referred to as an "ON state". In this ON state, an inversion channel is formed in the channel region, and a path in which electrons are carried is formed between the n-type source region 40 and the second n-type separation region 22. On the other hand, in a Schottky junction formed in a contact portion between the first separation region 21 and the Schottky electrode 71, since an electric field (reverse bias) is applied in a direction in which hardly current flows for the Schottky connection, i.e., in a reverse direction, no current is conducted.The electrons flowing from the source electrode 80 into the drain electrode 84 follow the electric field formed by the positive voltage applied to the drain electrode 84. For this reason, the electrons from the source electrode 80 reach the drain electrode 84 via the ohmic electrode 70, the source region 40, the channel region, the second separation region 22, the drift layer 20, and the semiconductor substrate 10. A voltage applied between the source electrode 80 and the drain electrode 84 is referred to as an ON voltage, and a value obtained by dividing the ON voltage by the density of the ON current is referred to as an "ON resistance". The ON resistance is equal to the sum of resistances in the path in which the above-described electrons are transported. Since the product of the ON resistance and the square of the ON current corresponds to the excitation loss that the MOSFET consumes during excitation, it is preferable that the ON resistance is low. In the present first preferred embodiment, the channel region is also formed within the overvoltage excitation region 301. Therefore, the overvoltage excitation region 301 can also contribute to a reduction in the ON resistance.The second normal operation state is a state in a case where a voltage applied to the drain electrode 84 is higher than that applied to the source electrode 80 and a voltage lower than the threshold voltage is applied to the gate electrode 60, and hereinafter referred to as an "OFF state". In this OFF state, since there is no inverted carrier, the ON current does not flow and a high voltage applied to a load in the ON state is applied between the source electrode 80 and the drain electrode 84 in the MOSFET.Since the electric field is applied to the Schottky junction formed in the contact portion between the first separation region 21 and the Schottky electrode 71 in the same direction as that in the "ON state", ideally, no current is conducted. However, since an electric field much higher than that in the "ON state" is applied, a leakage current can be generated. When the leakage current is large, there is a possibility that heat generation of the MOSFET may increase, thereby causing thermal destruction of the MOSFET and a module using the MOSFET. For this reason, in order to reduce the leakage current, it is preferable that the electric field applied to the Schottky junction is suppressed to be low.The third normal operation state is a state in a case where a voltage applied to the drain electrode 84 is lower than that applied to the source electrode 80, i.e., a counter electromotive voltage is applied to the MOSFET, and a voltage lower than the threshold voltage is applied to the gate electrode 60. In this state, a circulating current is conducted from the source electrode 80 toward the drain electrode 84. Hereinafter, this state is referred to as "asynchronous rectification state". In the asynchronous rectification state, in the active region other than the overvoltage excitation region 301, an electric field (forward bias) in a forward direction is applied to the Schottky junction formed in the contact portion between the first separation region 21 and the Schottky electrode 71. For this reason, a unipolar current containing an electronic current is conducted from the Schottky electrode 71 toward the first n-type separation region 21. In other words, the unipolar current is conducted in the SBD including the Schottky electrode 71 and the first separation region 21. A circulating current component of the free-wheeling diode is mainly this unipolar component.Further, the source electrode 80 and the first well region 30 have the same potential with the ohmic electrode 70 interposed therebetween on the source side. As a result, the forward bias voltage is also applied to the pn junction between the first p-type well region 30 and the drift layer 20. However, the pn junction is formed in parallel with the above-described Schottky junction, and when the OFF state is changed to the asynchronous rectification state, since the Schottky junction in which the threshold voltage is lower turns on before the pn junction, almost all the circulating current is conducted into the Schottky junction and no circulating current is conducted into the pn junction.Also, in a case where the voltage applied between the source and the drain exceeds the diffusion potential of the pn junction, a voltage obtained by subtracting a voltage drop caused by the unipolar current of the SBD in the drift layer 20 from the source-drain voltage is applied to the pn junction. For this reason, a high source-drain voltage may be applied while the pn junction does not turn on, and as a result, a high current may be conducted by means of the unipolar current alone.Thus, by embedding the SBD therein, in the asynchronous rectification state, it is possible to suppress conduction of a forward current, which is a bipolar current, to the pn junction, i.e., the body diode, which is the parasitic pn diode. When a start point of basal plane dislocation or the like is present in the pn junction in which the bipolar current is conducted, there is a possibility that a crystal defect such as a stacking fault or the like is expanded by repeating the asynchronous rectification state. Since the crystal defect such as the stacking fault or the like blocks a current flowing in a thickness direction of the chip, there is a possibility that the ON resistance may increase, thereby causing element failure by thermal runaway. Since the SBD is embedded in the silicon carbide semiconductor device 100 according to the present first preferred embodiment, it is possible to suppress the bipolar current from flowing into the pn junction during reflux and to increase the reliability of the silicon carbide semiconductor device 100.On the other hand, in the overvoltage excitation region 301, since the first separation region 21 connected to the Schottky electrode 71 is not present, the unipolar current hardly flows in the asynchronous rectification state. The unipolar current flowing in the contact portion between the Schottky electrode 71 and the first separation portion 21 formed around the overvoltage excitation portion 301 is diffused in the drift layer 20 in a chip-plane direction, and the unipolar current is thereby more or less conducted also in the drift layer 20 within the overvoltage excitation portion 301. However, since its current density is small also for the active region except for the overvoltage excitation region 301, the bipolar current flows more easily in the pn junction of the overvoltage excitation region 301 by the low source-drain voltage than in the active region except for the overvoltage excitation region 301.When the bipolar current flows in the pn junction, there is a possibility that the crystal defect such as a stacking fault or the like may expand; however, since a sequence time of the asynchronous rectification state is assumed to be short, ranging from several hundreds ns to several μs, expansion of the crystal defect such as a stacking fault or the like hardly occurs. Further, in the present first preferred embodiment, the area ratio of the Schottky barrier diode replacement region 302 in the active region is not lower than 0.01 % and lower than the area ratio of the SBD region not replaced by the Schottky barrier diode replacement region 302 in the active region 15, and more preferably is not lower than 0.01 % and not higher than 5 %, which is relatively low. For this reason, it is possible to reduce the possibility of deterioration in reliability due to expansion of the crystal defect such as stacking fault or the like. Further, when the area ratio is not higher than 5%, since the effect on electrical characteristics of a chip in a normal operation can be almost ignored, it is possible to suppress deterioration in electrical characteristics such as conduction loss or the like by the overvoltage energization portion 301.The fourth normal operation state is a state in a case where a voltage applied to the drain electrode 84 is lower than that applied to the source electrode 80, that is, a counter electromotive voltage is applied to the MOSFET, and a voltage not lower than the threshold voltage is applied to the gate electrode 60. In this state, the circulating current is conducted from the source electrode 80 to the drain electrode 84. This state is referred to as "synchronous rectification state" hereinafter. In the synchronous rectification state, the unipolar current flowing in the channel is conducted as well as the unipolar current flowing in the Schottky electrode 71. In the present first preferred embodiment, the channel is formed not only in the MOSFET region but also in the overvoltage excitation region 301. Therefore, in the overvoltage excitation region 301, although there is no junction between the Schottky electrode 71 and the first separation region 21, the channel current becomes a carrier of the unipolar current, and it is possible to suppress the turn-on of the pn junction. Thereby, it is possible to suppress concentration of heat generation to the overvoltage excitation region 301 in the synchronous rectification state.In an inverter operation, for example, the sequence in the synchronous rectification state takes about half of a carrier cycle, and it is assumed that its time is relatively long, ranging from about several tens μs to several ms. This time is much longer than that in the asynchronous rectification state in which the time is assumed to be short, ranging from several ns to several μs. If current continues to flow in the pn diode for such a long time, heat is generated locally. The reason for this will be described hereinafter.First, as compared with the unipolar current, the bipolar current has the properties of causing conductivity modulation and reducing drift resistance. In a region where the bipolar current is conducted, the resistance is reduced and a larger amount of current than that in the region where only the unipolar current is conducted is conducted. In the local area where the bipolar current is conducted, positive feedback starts with the temperature thereby rising, and further the modulation of conductivity becomes stronger and current concentration starts to occur. As a result, there is a possibility that local heat generation may occur in the overvoltage energization region 301 and the like, and reliability deterioration such as a crack of a portion of an electrode junction, a breakage of the gate insulating film, and the like may be caused. In contrast, in the present first preferred embodiment, the channel current is conducted during the synchronous rectification state in the overvoltage excitation region 301. For this reason, since the operation of the pn diode in the overvoltage excitation region 301 can be suppressed and local heat generation can be avoided, it is possible to achieve high reliability.Finally, as the abnormal state, a state in which an overcurrent flows between the source and the drain will be described. In this state, due to inverter failure or the like, current exceeding a rated current momentarily flows from the source toward the drain. In these many cases, a case is assumed in which an OFF signal is applied to the gate and the channel is not energized. At this time, the chip is required not to be broken due to heat generation. An allowable current that does not cause a failure is referred to as overvoltage capability. In order to increase the allowable current, it is important that the overcurrent is conducted at a low resistance, thereby reducing heat generation of the chip. Further, the abnormal state occurs only in very rare cases such as an accident (failure) and / or the like occurring, and since the occurrence frequency is low, it is said that it is generally not necessary to think of reliability deterioration caused by the excitation of the pn diode such as extension of the crystal defect such as stacking fault or the like.However, overvoltage capability should be increased. From the viewpoint of enhancing overvoltage capability, the bipolar current that brings about the modulation of conductivity easier than the unipolar current is suitable for conducting the overcurrent at low resistance. In the overvoltage excitation region 301 according to the present first preferred embodiment, since the first separation region 21 connected to the Schottky electrode 71 is not present, the unipolar current hardly flows. For this reason, at the start of the overvoltage excitation in the overvoltage excitation region 301, the pn junction turns on while an excitation current in a region except the overvoltage excitation region 301 is low, and bipolar excitation starts. In this state, when the overcurrent temporarily increases and reaches a large current exceeding the rated current, the bipolar current flowing from the overvoltage excitation region 301 further increases and the holes in the drift layer 20 are diffused toward the active region around the overvoltage excitation region 301.In a region where the holes are diffused, the resistance of the drift layer 20 is reduced and the unipolar current density increases, and the parasitic pn diode (in other words, the body diode) or the like in the MOSFET turns on. The holes are then diffused to the drift layer 20 around the region, and further the body diode in the adjacent active region turns on. In other words, when the overcurrent is excited with the overvoltage excitation region 301 as a starting point, the body diodes carry out a chain reaction therearound and operate sequentially. Since the body diodes thus turn on over a wide range of the chip, the chip is brought into the bipolar excitation state and the generated energy is reduced by the lower resistance due to the modulation of the conductivity, and thereby it is possible to suppress heat generation in a case where a chip current is conducted. In other words, since an allowable overcurrent can be increased, it is possible to increase overvoltage capability.Thus, in the overvoltage excitation region 301, it is possible to not only increase a current that can be conducted in the overvoltage excitation region 301 but also change the characteristics over a wide range of the chip by a chain reaction. For this reason, the area ratio of the overvoltage excitation region 301 in the active region may be low.FIG. 18 is a view illustrating a result of verifying the string operation of the pn diode from the Schottky barrier diode replacement region 302 having a width of 20 μm by the TCAD (Technology Computer Aided Design) simulation. In FIG. 18, increasing density of dots in a dot hatching means that the hole concentration is higher. It is shown that, over time, the region for body diode chain operation corresponding to a region where the hole concentration is high spreads due to the modulation of the conductivity of the bipolar excitation. As described above, the region for a body diode string operation is a region in which, by a string reaction with the operation of the pn diode of the Schottky barrier diode replacement region 302 as a starting point, the body diode, which is the parasitic pn diode of the MOSFET in the unit cell region, is operated.After the pn diode in the overvoltage excitation region 301 is operated by the overvoltage excitation, it is confirmed that the hole density in an adjacent cell increases with time, the modulation of the conductivity propagates through the operation of the body diode which is the pn diode, and the region propagates for a body diode string operation. By detecting the propagation speed of the pn diode operation in the overcurrent energization, i.e., the chain speed, the area ratio of the region for body diode chain operation in the active region can be designed in a case where no overvoltage energization shorter than 1 ms occurs, which is generally assumed to be the abnormal state.According to the present first preferred embodiment, as described above, as compared with the case where the overvoltage excitation region 301 is not present, the SBD excitation is switched to the body diode excitation at an early stage. Since the body diode, which is the pn diode, becomes a low resistance due to the modulation of the conductivity by the bipolar operation, the generated energy density is reduced simultaneously with the start of the body diode excitation. As a result, it is possible to suppress heat generation in the overvoltage excitation and to increase the overvoltage capability.FIG. 19 is a graph illustrating a relationship between a maximum forward voltage VFmax and an applied current IFSM in an overvoltage energization test in an experimentally manufactured silicon carbide semiconductor device. In the silicon carbide semiconductor device manufactured experimentally, the area ratio of the p-type Schottky barrier diode replacement region 302 of the overvoltage excitation region 301 in the active region 15 is changed in plan view.As illustrated in FIG. 19, in a region where the current is relatively low, the SBD is excited, and when a certain amount of current or more is conducted, the SBD excitation is switched to the body diode excitation, and the gradient of V-I characteristics is changed due to the resistance change. At this time, since the switching to the body diode excitation is performed earlier, the generated energy is more reduced and this is advantageous for the overvoltage capability. In FIG. 19, evaluation is made by changing the area ratio of the Schottky barrier diode replacement region 302 in the active region 15 from about 0.0197% to 0.1967% in a plan view. As a result, it is confirmed that as the area ratio increases, a starting voltage of the body diode operation is reduced and the switching to the body diode energization is performed earlier.FIG. 20 is a graph illustrating a result of checking overvoltage capability on the basis of the above result. The overcurrent to be applied to the silicon carbide semiconductor device is gradually increased, and the measurement is performed until a breakage occurs in the silicon carbide semiconductor device. As a result, it is confirmed that, compared with the structure in which the Schottky barrier diode replacement region 302 is not present, the overvoltage capability is improved in the structure having the Schottky barrier diode replacement region 302.Further, in the present first preferred embodiment, at a position far from the junction portion between the Schottky electrode 71 and the first separation region 21, the Schottky barrier diode replacement region 302 is connected to the source electrode 80 through the second active region contact hole 90B. In other words, within the overvoltage excitation region 301, the pn diode penetrating between the source and the drain in the cross-sectional direction of the chip is formed. Since this pn diode does not need to conduct current within a p-type layer having a high sheet resistance in the chip plane direction, when the pn diode turns on by the overcurrent, the pn diode can conduct a large amount of bipolar current. For this reason, the Schottky barrier diode replacement region 302 can easily function as the start point of the pn diode operation.Moreover, in the present first preferred embodiment, since a unipolar transistor and a bipolar diode are adjacently present within the active region of the same chip, it is possible to reduce an effective area of the diode region as compared with a case where one of them is disposed outside.Further, in order to further increase overvoltage capability, it is preferable that a plurality of overvoltage excitation regions 301 be uniformly arranged over the entire active region so that regions in which the pn diodes are operated in a chain reaction by the overvoltage excitation region 301 are not unevenly distributed. With such a structure, it is possible to distribute portions having heat generation.<The Second Preferred Embodiment>FIG. 21 is a schematic cross-sectional view illustrating a schematic structure of the overvoltage excitation region 301 and the active region contact hole 90 according to the second preferred embodiment. As illustrated in FIG. 6, within the overvoltage excitation region 301 according to the first preferred embodiment, the second separation region 22 is formed. In contrast, within overvoltage excitation region 301 according to the present second preferred embodiment, as illustrated in FIG. 21, second separation region 22 is not formed. As an example of the layout method, within the overvoltage excitation region 301, a region including the first well region 30, the first separation region 21, and the second separation region 22 is replaced with the p-type.With such a structure, since there is no channel in the overvoltage excitation region 301, the overvoltage excitation region 301 does not perform a function of the MOSFET. For this reason, even in a case where the gate is turned on, since the pn diode turns on preferentially and the operation of the pn diode is concatenated with its surrounding region, it is possible to increase the overvoltage capability.<Variante of First and Second Preferred Embodiments>Although in the above description, the unit cell structure in which the SBD region and the MOSFET region are united in the active region is formed, the SBD and the MOSFET may be arranged in parallel within the unit cell formed in the active region.<Die Third Preferred Embodiment>The silicon carbide semiconductor device 100 according to the first or second preferred embodiment is a planar-type silicon carbide semiconductor device. In contrast, the silicon carbide semiconductor device 100 according to the third preferred embodiment is a trench-type silicon carbide semiconductor device.(1) Trench structureFIG. 22 is a plan view illustrating a silicon carbide layer of the silicon carbide semiconductor device 100 according to the third preferred embodiment as viewed from the upper surface, and corresponds to the plan view of FIG. 2. in the silicon carbide semiconductor device 100 illustrated in FIG. 22, in the active region, stripe-shaped gate trenches GT in each of which a transistor is formed and stripe-shaped Schottky trenches ST in each of which the Schottky electrode is embedded are alternately arranged in parallel with each other. In the connection region around the active region, the second well region 31 is formed.FIG. 23 is an enlarged plan view illustrating the active region of the silicon carbide semiconductor device 100 according to the third preferred embodiment. In the gate trench GT and the Schottky trench ST, first connection regions 36 and second connection regions 37, each of which is formed of p-type silicon carbide, are formed adjacent to each other at regular intervals along their extension direction. Further, within the overvoltage excitation region 301, the p-type Schottky barrier diode replacement region 302 is formed in the Schottky trench ST adjacent thereto. A region including the unit cell region including the Schottky trench ST substantially corresponding to the SBD region and the gate trench GT substantially corresponding to the MOSFET region and the overvoltage excitation region 301 is referred to as the active region.In the terminal portion of the silicon carbide semiconductor device 100 according to the third preferred embodiment, a structure like the planar type silicon carbide semiconductor device 100 described in the first preferred embodiment and the like may be formed or another structure corresponding to the trench type may be formed. Hereinafter, only the active region of the silicon carbide semiconductor device 100 according to the third preferred embodiment will be described.FIG. 24 is a schematic cross-sectional view schematically illustrating a portion in the active region including the overvoltage excitation region 301 illustrated in FIG. 23, in which neither the first connection region 36 nor the second connection region 37 are formed. FIG. 25 is a schematic cross-sectional view schematically illustrating a partial region in the active region including the overvoltage excitation region 301 illustrated in FIG. 23, in which the first connection region 36 and the second connection region 37 are formed.In the silicon carbide semiconductor device 100 illustrated in FIGS. 23 to 25, the drift layer 20 formed of n-type silicon carbide is formed on the surface of the semiconductor substrate 10 formed of low-resistance n-type silicon carbide. In the present third preferred embodiment, although the semiconductor layer in which the active region is disposed is the drift layer 20 on the semiconductor substrate 10, the semiconductor layer may be the semiconductor substrate 10. As illustrated in the cross-sectional views of FIGS. 24 and 25, in the surface layer portion of the drift layer 20, the first well region 30 formed of p-type silicon carbide is formed.In a part of the surface layer portion on the first well region 30, the source region 40 formed of n-type silicon carbide is formed. In the remaining surface layer portion on the first well region 30, the contact region 35 formed of low-resistance p-type silicon carbide is formed adjacent to the source region 40.In the active region, the gate trench GT is formed, which penetrates the source region 40 and the first well region 30 and reaches the drift layer 20. Further, in another portion, the Schottky trench ST is formed, which penetrates the source region 40 and the first well region 30 and reaches the drift layer 20.The gate trenches GT and the Schottky trenches ST are alternately arranged in parallel with each other. The gate trench GT and the Schottky trench ST have the same depth, but may have different depths. Further, the gate trench GT and the Schottky trench ST may be formed to have the same width or may be formed to have different widths.Within the gate trench GT, the gate electrode 60 is disposed with the gate insulating film 50 formed of, for example, silicon oxide interposed therebetween. The gate electrode 60 is formed of, for example, low-resistance polycrystalline silicon having a high impurity concentration. On the gate electrode 60, the interlayer insulating film 55 formed of, for example, silicon oxide is formed. Within the Schottky trench ST, the Schottky electrode 71 and the source electrode 80 are formed, and the Schottky electrode 71 is formed in contact with the drift layer 20 and connected to the drift layer 20 via a Schottky contact.Within the drift layer 20, the first p-type protection region 32 is formed at the bottom of the gate trench GT. Within the drift layer 20, the second p-type protection region 33 is formed at the bottom of the Schottky trench ST. It is preferable that the first protection region 32 and the second protection region 33 have the same depth and have the same impurity concentration.As illustrated in FIG. 25, the first protection region 32 and the first well region 30 are connected to each other via the first p-type connection region 36. Further, the second protection portion 33 and the first well portion 30 are connected to each other via the p-type second connection portion 37.On the surface of the source region 40, the ohmic electrode 70 is formed. The source electrode 80 to be connected to the ohmic electrode 70, the Schottky electrode 71 and the contact region 35 is formed thereon. The first well region 30 can easily emit electrons or positive holes to and receive electrons from the ohmic electrode 70 via the low-resistance contact region 35. The source electrode 80 is also connected to the Schottky electrode 71 inside the Schottky trench ST.A portion of the first well region 30 that faces the gate electrode 60 with the gate insulating film 50 interposed therebetween in a side surface of the gate trench GT in which the gate electrode 60 is formed is referred to as the channel region. On a portion in a side surface of the Schottky trench ST where the Schottky electrode 71 and the drift layer 20 are in contact with each other, the SBD is formed.On the back surface side of the semiconductor substrate 10, the drain electrode 84 is formed.Further, the second well region 31 in the terminal region may have the same depth and thickness as those of the first well region 30 in the active region. Moreover, the second well region 31 in the terminal region may be formed to have the same depth as those of the first protection region 32 and the second protection region 33 in the active region up to the depth of the bottom of each of the gate trench GT and the Schottky trench ST. Further, the low-resistance n-type conductive silicon carbide layer 45 may be formed in the surface layer portion of the second well region 31. Moreover, the second well region 31 may not be directly connected to the source electrode 80 via an ohmic contact.As illustrated in FIG. 24, in the present third preferred embodiment, the first separation region 21 corresponds to a region in contact with the side surface of the Schottky trench ST and sandwiched between the first well region 30 and the second protection region 33 in contact with the Schottky trench ST. Further, the second separation region 22 corresponds to a region in contact with the side surface of the gate trench GT and sandwiched between the first well region 30 and the first protection region 32 in contact with the gate trench GT.In the overvoltage excitation region 301, the first separation region 21 is replaced with the p-type Schottky barrier diode replacement region 302 in contact with the side surface of the Schottky trench ST. Further, in FIGS. 24 and 25, a boundary of the Schottky barrier diode replacement region 302 is indicated by the broken line for convenience. The Schottky electrode 71 is not connected to the n-type silicon carbide layer such as the first separation region 21 or the like having an n-type such as the drift layer 20, and the Schottky electrode 71 and the drift layer 20 are separated from each other by the p-type Schottky barrier diode replacement region 302.Further, in the present third preferred embodiment, as in the first preferred embodiment, the area ratio of the Schottky barrier diode replacement region 302 in the active region 15 in plan view is not less than 0.01 % and less than the area ratio of the SBD region not replaced by the Schottky barrier diode replacement region 302 in the active region 15, and more preferably is not less than 0.01 % and not more than 5 %.(2) Method for Manufacturing a Trench StructureNext, with reference to the schematic cross-sectional views of FIGS. 26 to 31 illustrating the active region, a method of manufacturing the trench-type silicon carbide semiconductor device 100 according to the third preferred embodiment will be described. Although a method of manufacturing a portion in which the first connection region 36, the second connection region 37, or the Schottky barrier diode replacement region 302 is not formed is described herein, a portion in which these regions are formed is substantially the same as below and thus will be described as appropriate without being illustrated.First, the semiconductor substrate 10 formed of n-type low resistance silicon carbide and having the 4H polytype in which the plane orientation of the first main surface is the (0001) plane having an off angle is prepared. On the semiconductor substrate 10, the drift layer 20 formed of silicon carbide has an n-type impurity concentration of, for example, 1×10 15 to 1×10 17 cm -3 and a thickness of, for example, 5 to 50 μm is epitaxially grown by the chemical vapor deposition (CVD) method.Subsequently, ions of Al which is a p-type impurity are implanted into the surface of the drift layer 20. At this time, the depth of ion implantation of Al does not exceed the thickness of the drift layer 20, and is, for example, about 0.5 to 3 μm. Further, the impurity concentration of Al from which ions are implanted is in a range of, for example, 1×10 17 to 1×10 19 cm -3, which is higher than the impurity concentration of the drift layer 20. The region into which ions of Al are implanted in this process step becomes the first well region 30 in the active region and becomes the second well region 31 in the terminal region. Moreover, the first well region 30 may be formed on the drift layer 20 by the epitaxial growth method instead of the ion implantation.Subsequently, in a predetermined region of the surface layer portion of the first well region 30, by performing ion implantation of Al having an impurity concentration of, for example, 1×10 16 to 1×10 18 cm -3, which is higher than that of the first well region 30, the contact region 35 is formed. Further, in a predetermined region of the surface layer portion of the first well region 30, ions of N which is an n-type impurity are implanted. The depth of ion implantation of N is set shallower than the thickness of the first well region 30. Further, the impurity concentration of N from which ions are implanted is in a range of, for example, 1×10 18 to 1×10 21 cm -3, which is higher than the concentration of p-type impurities of the first well region 30. An n-type region in the region into which ions of N are implanted in this process step becomes the source region 40. FIG. 26 is a cross-sectional view illustrating the active region at which the process steps are completed up to this stage.Next, in a source region 40 between the adjacent contact regions 35, one of the gate trench GT and the Schottky trench ST is formed. Further, the gate trenches GT and the Schottky trenches ST are alternately arranged. Ions of Al, which is a p-type impurity, are implanted into the bottom of both the gate trench GT and the Schottky trench ST. Thereby, the first protection region 32 is formed on the bottom of the gate trench GT, and thus the second protection region 33 is formed on the bottom of the Schottky trench ST. The impurity concentration of each of the first protection region 32 and the second protection region 33 is, for example, 1×10 17 to 1×10 19 cm -3.The first connection region 36 and the second connection region 37 formed in the gate trench GT and the Schottky trench ST, respectively, are formed by performing, for example, oblique (tilted) ion implantation of ions of a p-type impurity such as Al or the like from an orthogonal direction to an extending direction of each trench. The impurity concentration of each of the first connection region 36 and the second connection region 37 is, for example, 1×10 17 to 1×10 19 cm -3.Like the first connection region 36 and the second connection region 37, the Schottky barrier diode replacement region 302 is formed by performing oblique ion implantation of p-type impurity ions such as Al or the like from the direction orthogonal to the extending direction of the Schottky trench ST, for example. The impurity concentration of the Schottky barrier diode replacement region 302 is 1×10 17 to 1×10 19 cm -3. By forming the Schottky barrier diode replacement region 302 simultaneously with the formation of the first connection region 36 and / or the second connection region 37, it is possible to reduce the number of process steps.Herein, in a case where the plane orientation of the first main surface of the semiconductor substrate 10 is the (0001) plane having an offset angle in the <11-20> direction, the extension direction of each of the gate trench GT and the Schottky trench ST may be in the active region parallel to the <11-20> direction, which is an offset direction. With such a structure, since no effect is generated in the displacement direction of the semiconductor substrate 10 on the Schottky trench ST and trench side walls on both sides thereof, it is possible to reduce variation in the barrier height of the Schottky interface of the Schottky trench ST. Further, since no effect is generated in the displacement direction of the semiconductor substrate 10 on the threshold voltage of the MOSFET of the gate trench GT, it is possible to reduce variation in the threshold voltage of the MOSFET.Subsequently, in the inert gas atmosphere of an Ar gas or the like, annealing is performed on the drift layer 20 using the heat treatment device at a temperature of 1300 to 1900° C. for 30 seconds to one hour, for example. By this annealing, N and Al, ions of which have been implanted, are electrically activated. FIG. 27 is a cross-sectional view illustrating the active region where the process steps up to this stage are completed.Subsequently, as illustrated in FIG. 28, the inside of the Schottky trench ST is filled with a protective insulating film 52 formed of, for example, silicon oxide.Next, a surface of the silicon carbide layer not covered with the protective insulating film 52 is thermally oxidized to thereby form the gate insulating film 50 made of, for example, silicon oxide and having a desired thickness within the gate trench GT. Subsequently, on the gate insulating film 50, for example, the polycrystalline silicon film having conductivity is formed by the low pressure CVD method and then patterned to thereby form the gate electrode 60. Next, on the gate electrode 60, the interlayer insulating film 55 having a film thickness larger than that of the gate insulating film 50 and formed of, for example, silicon oxide is formed by the low pressure CVD method. Subsequently, the interlayer insulating film 55 and the gate insulating film 50 are selectively removed by wet etching to expose the contact region 35 and the source region 40 in the active region. FIG. 29 is a cross-sectional view illustrating the active region where the process steps up to this stage are completed.Subsequently, on the surfaces of the silicon carbide layers of the source region 40 and the contact region 35 that are exposed, a metal film mainly formed of Ni is formed by, for example, the sputtering method or the like, and then the heat treatment is performed at a temperature of 600 to 1100° C. By this operation, the metal film mainly formed of Ni and the silicon carbide layer react with each other to thereby form a silicide layer between the metal film and the silicon carbide layer. Then, the remaining metal film except for the silicide layer is removed by wet etching. By this process, the remaining silicide layer becomes ohmic electrode 70.Fig. 30 is a cross-sectional view illustrating the active region where the process steps up to this stage are completed.Next, the protective insulating film 52 within the Schottky trench ST is removed using hydrofluoric acid or the like, and then the Schottky electrode 71 is formed within the Schottky trench ST. The material of the Schottky electrode 71 is, for example, Ti, Mo, or the like.Subsequently, the source electrode 80 mainly formed of Al is formed to be in contact with the Schottky electrode 71 and the ohmic electrode 70. FIG. 31 is a cross-sectional view illustrating the active region where the process steps up to this stage are completed. The gate pad 81 and the gate wiring 82 are formed in the same manner as the source electrode 80 is formed. The gate pad 81 and the gate wiring 82 may be formed at the same time as the source electrode 80 is formed.Next, by forming a metal film mainly formed of Ni on the back surface of the semiconductor substrate 10 and performing heat treatment thereon, the drain electrode 84, which is a back ohmic electrode, is formed on the back surface of the semiconductor substrate 10. Thus, the silicon carbide semiconductor device 100 according to the third preferred embodiment illustrated in FIG. 24 is manufactured.(3) Explanation of OperationSince the operation and effect of the trench-type silicon carbide semiconductor device 100 according to the third preferred embodiment are the same as those of the planar-type silicon carbide semiconductor device 100 according to the first or second preferred embodiment, detailed description will be omitted.<Die Fourth Preferred Embodiment>FIG. 32 is a block diagram schematically illustrating a structure of a power module device 101 according to the fourth preferred embodiment. The power module device 101 includes a plurality of silicon carbide semiconductor devices 100, each of which is the silicon carbide semiconductor device 100 according to any one of the first to fourth preferred embodiments.With such a structure, it is possible to increase the overvoltage capability of the power module device 101 upon energization of the overcurrent. Further, since the time from the detection of the overcurrent to its shutdown can be secured longer, in the power module device 101, it is possible to increase the degree of freedom of design of an overvoltage protection circuit, not illustrated, that operates upon energization of the overcurrent.Further, in order to increase the current that the power module device 101 processes, the plurality of silicon carbide semiconductor devices serving as the switching element and the free wheel diode may be connected in parallel with each other. This plurality of silicon carbide semiconductor devices may include the silicon carbide semiconductor device 100 having the overvoltage excitation region 301, and a silicon carbide semiconductor device without the overvoltage excitation region 301. However, in order to prevent the phenomenon that the pn diode of a certain silicon carbide semiconductor device turns on when the overcurrent is conducted and the current is concentrated on the silicon carbide semiconductor device, the plurality of silicon carbide semiconductor devices may include only the silicon carbide semiconductor device 100.<Die Fifth Preferred Embodiment>FIG. 33 is a block diagram illustrating a power converter 501 according to the fifth preferred embodiment. The power converter 501 includes a control circuit 501 a, a drive circuit 501 b, and a main converter circuit 501 cprovided with the silicon carbide semiconductor device 100 according to any one of the first to fourth preferred embodiments. Further, the main converter circuit 501 cmay be provided with the power module device 101 according to the fourth preferred embodiment instead of the silicon carbide semiconductor device 100 according to any one of the first to fourth preferred embodiments.The drive circuit 501 bdrives the silicon carbide semiconductor device 100 of the main converter circuit 501 cbased on a control signal from the control circuit 501 a. The drive circuit 501 b, when the circulating current is supplied to the parasitic pn diode, which is the free wheeling diode of the silicon carbide semiconductor device 100, turns on the gate of the MOSFET of the silicon carbide semiconductor device 100 except for a short dead time. With such a structure, it is possible to pass the unipolar current through the channel and avoid concentration of heat generation in the overvoltage excitation region 301.The control circuit 501 cincluding the silicon carbide semiconductor device 100 converts electric power from a power supply 502 into the electric power usable in a load 503 by driving the silicon carbide semiconductor device 100 on the basis of the control signal.With the structure described above, it is possible to increase overvoltage capability in the power converter 501 when the overcurrent is energized. Further, in the power converter 501, since the time from the detection of the overcurrent to the shutdown thereof can be secured longer, it is possible to increase the degree of freedom of design of an unillustrated overvoltage protection circuit upon the excitation of the overcurrent.Further, in the present fifth preferred embodiment, since the silicon carbide semiconductor device 100 according to any one of the first to fourth preferred embodiments is used as the switching element of the main converter circuit 501 c, it is possible to achieve a power converter 501 in which the loss is low and the reliability of the high-speed switching operation is increased.<Die Sixth Preferred Embodiment>FIG. 34 is a view illustrating a mobile body 601 according to the sixth preferred embodiment. Although the mobile body 601 is a train in the exemplary case of FIG. 34, the mobile body 601 is not limited to this example. The mobile body 601 is provided with the power converter 501 according to the fifth preferred embodiment, and the power converter 501 generates electric power required by the mobile body 601. With such a structure, it is possible to produce the same effect as that of the power converter 501 according to the fifth preferred embodiment even on the power converter used in the mobile body 601.< Explanations of First to Sixth Preferred Embodiments>The p-type impurity described above may be boron (B) or gallium (Ga) instead of aluminum (Al). The above-described n-type impurity may be phosphorus (P) instead of nitrogen (N). The gate insulating film 50 described above need not necessarily be an oxide film such as SiO 2 or the like, but may be an insulating film other than the oxide film or a combination of the insulating film other than the oxide film and the oxide film. Further, the gate insulating film 50 may be an oxide film made of silicon formed by the CVD method instead of a silicon oxide obtained by thermal oxidation of silicon carbide. Moreover, in the above description, although the crystal structure, the plane orientation of the main surface, the off angle, the conditions of ion implantation, and the like are described using specific examples, these numerical ranges are only examples. Further, the silicon carbide semiconductor device 100 may have a structure in which the SBD is embedded in the MOSFET having a superjunction structure.Moreover, the preferred embodiments and variations can be freely combined as appropriate, or changed or omitted, respectively.The foregoing description is illustrative in all aspects and is not restrictive. It is therefore to be understood that numerous modifications and variations that are not illustrated may be devised.EXPLANATION OF THE REFERENCE NUMERALS15 Active region, 16 Region for body diode chain operation, 20 Drift layer, 100 Silicon carbide semiconductor device, 101 Power module device, 301 Overvoltage excitation region, 302 Schottky barrier diode replacement region, 501 Power converter, 551 Mobile bodyReferences included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedJP 2003-017701

[0005] WO 2014 / 038110

[0005]

Claims

A silicon carbide semiconductor device comprising: a semiconductor layer of a first conductivity type provided with an active region including a unit cell region including a Schottky barrier diode region and a MOSFET region and an overvoltage excitation region, wherein the overvoltage excitation region includes a Schottky barrier diode replacement region in which the first conductivity type of the Schottky barrier diode region is replaced with a second conductivity type, and an area ratio of the Schottky barrier diode replacement region in the active region is not lower than 0.01 % and lower than an area ratio of the Schottky barrier diode region in the active region in a case where the Schottky barrier diode region is not replaced with the Schottky barrier diode replacement region.The silicon carbide semiconductor device according to claim 1, wherein the overvoltage excitation region takes a function of the MOSFET.The silicon carbide semiconductor device according to claim 1, wherein the overvoltage excitation region does not function as the MOSFET.The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein an area ratio of the overvoltage excitation region in the active region is not lower than 0.01 % and not higher than 5%.A power module device, comprising: a plurality of silicon carbide semiconductor devices each of which is the silicon carbide semiconductor device according to any one of claims 1 to 4.A power converter for converting electric power using a power module device including the silicon carbide semiconductor device according to any one of claims 1 to 4.A mobile body provided with the power converter according to claim 6.

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