SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR DEVICE

Abstract

A semiconductor circuit according to one embodiment includes transistors PM10 to PM12 and NM10 and NM11, and a constant current source CS10. The transistor PM10 is coupled between a node VDD and a node ND10. A gate end of the transistor PM10 is coupled to the node ND10 via a resistor R10. The transistor PM11 is coupled between the node VDD and a node ND11. A gate end of the transistor PM11 is coupled to the node ND10. A node ND11 is coupled to an output node OUT. The transistor NM10 is coupled between the node ND10 and a node ND12. A gate of the transistor NM10 is coupled to an input node IN. The transistor NM11 is coupled between the nodes ND11 and ND12. A gate of the transistor NM11 is coupled to an input node / IN. One end and another end of the constant current source CS10 are coupled between the node ND12 and a node VSS.Transistor PM12 is coupled between node VDD and input node / IN. A gate of transistor PM12 is coupled to the gate of transistor PM10.

Description

AREA

[0001] The embodiments relate to a semiconductor circuit and a semiconductor device. BACKGROUND

[0002] Semiconductor circuits for the transmission of high-speed signals in integrated circuits are known. CITATION LISTPATENT LITERATURE

[0003] Patent Literature 1: US Patent Application Publication No. US 2021 / 0343328 A SUMMARYTECHNICAL PROBLEM

[0004] A semiconductor circuit is provided that can realize high-speed signal transmission. SOLUTION TO THE PROBLEM

[0005] A semiconductor circuit according to an embodiment includes first to third transistors of a first conductivity type, first and second transistors of a second conductivity type, and a constant current source. One end and the other end of the first transistor of the first conductivity type are respectively coupled to a first power supply node and a first node, and a gate end of the first transistor of the first conductivity type is coupled to the first node via a resistor. One end and the other end of the second transistor of the first conductivity type are respectively coupled to the first power supply node and a second node, the second node is coupled to an output node, and a gate end of the second transistor of the first conductivity type is coupled to the first node.One end and another end of the first second conductivity type transistor are coupled to the first node and a third node, respectively, and a gate end of the first second conductivity type transistor is coupled to a first input node. One end and another end of the second second conductivity type transistor are coupled to the second node and the third node, respectively, and a gate end of the second second conductivity type transistor is coupled to a second input node. One end and another end of the constant current source are coupled to the third node and a second power supply node, respectively. One end and another end of the third first conductivity type transistor are coupled to the first power supply node and the second input node, respectively, and a gate end of the third first conductivity type transistor is coupled to a gate end of the first first conductivity type transistor. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram illustrating an example of a circuit configuration of a semiconductor circuit according to a first embodiment. Fig. 2 is a circuit diagram illustrating an example of a circuit configuration of a semiconductor circuit according to a modification of the first embodiment. Fig. 3 is a schematic diagram illustrating an overview of the operation of the semiconductor circuit according to the first embodiment. Fig. 4 is a waveform diagram illustrating a simulation result of the operation of the semiconductor circuit according to the first embodiment. Fig. 5 is a waveform diagram illustrating a specific example of the operation of a semiconductor circuit according to a comparative example. Fig. 6 is a waveform diagram illustrating a specific example of the operation of the semiconductor circuit according to the first embodiment. Fig. 7 is a circuit diagram illustrating an example of a circuit configuration of a semiconductor circuit according to a second embodiment. Fig. 8 is a circuit diagram illustrating an example of a circuit configuration of a semiconductor circuit according to a modification of the second embodiment. Fig. 9 is a circuit diagram illustrating an example of a circuit configuration of a semiconductor circuit according to a third embodiment. Fig. 10 is a circuit diagram illustrating an example of a circuit configuration of a semiconductor circuit according to a modification of the third embodiment. Fig. 11 is a circuit diagram illustrating an example of a circuit configuration of a semiconductor circuit according to a first configuration example of a fourth embodiment. Fig. 12 is a circuit diagram illustrating an example of a circuit configuration of a semiconductor circuit according to a second configuration example of the fourth embodiment. Fig. 13 is a circuit diagram illustrating an example of a circuit configuration of a semiconductor circuit according to a third configuration example of the fourth embodiment. Fig. 14 is a circuit diagram illustrating an example of a circuit configuration of a semiconductor circuit according to a fourth configuration example of the fourth embodiment. Fig. 15 is a circuit diagram illustrating an example of a circuit configuration of a semiconductor circuit according to a fifth configuration example of the fourth embodiment. Fig. 16 is a circuit diagram illustrating an example of a circuit configuration of a semiconductor circuit according to a sixth configuration example of the fourth embodiment. Fig. 17 is a block diagram illustrating an example of a configuration of a semiconductor device according to a first configuration example of a fifth embodiment. Fig. 18 is a block diagram illustrating an example of a configuration of an input / output circuit included in the semiconductor device according to the first configuration example of the fifth embodiment. Fig. 19 is a block diagram illustrating an example of a configuration of a data input circuit in the semiconductor device according to the first configuration example of the fifth embodiment. Fig. 20 is a circuit diagram illustrating an example of a configuration of a C2C circuit included in a data input circuit in the semiconductor device according to the first configuration example of the fifth embodiment. Fig. 21 is a circuit diagram illustrating an example of a configuration of the C2C circuit included in the data input circuit in the semiconductor device according to the first configuration example of the fifth embodiment. Fig. 22 is a block diagram illustrating an example of a configuration of a semiconductor device according to a second configuration example of the fifth embodiment. Fig. 23 is a block diagram illustrating an example of a configuration of a semiconductor device according to a third configuration example of the fifth embodiment. Fig. 24 is a block diagram illustrating an example of a configuration of a semiconductor device according to a fourth configuration example of the fifth embodiment. Fig. 25 is a block diagram illustrating an example of a configuration of a semiconductor device according to a fifth configuration example of the fifth embodiment. Fig. 26 is a block diagram illustrating an example of a configuration of a semiconductor device according to a sixth configuration example of the fifth embodiment. Fig. 27 is a block diagram illustrating an example of a configuration of a semiconductor device according to a seventh configuration example of the fifth embodiment. Fig. 28 is a block diagram illustrating an example of a configuration of a semiconductor device according to an eighth configuration example of the fifth embodiment. Fig. 29 is a circuit diagram illustrating an example of a circuit configuration of a constant current source using an N-type transistor. Fig. 30 is a circuit diagram illustrating an example of a circuit configuration of a constant current source using a P-type transistor. DETAILED DESCRIPTION

[0006] Hereinafter, each embodiment will be described with reference to the drawings. Each embodiment illustrates an apparatus and a method for realizing the technical idea of the invention. The drawings are schematic or conceptual. The illustration of the configuration is omitted where appropriate. In this description, components having substantially the same function and configuration are denoted by the same reference numerals. Numerals, characters, and the like added to the reference numerals are denoted by the same reference numerals and are used to distinguish similar elements.

[0007] It should be noted that in the present specification, each of the N-type transistors NM and NT is, for example, an N-type MOS transistor. Each of the P-type transistors PM and PT is, for example, a P-type MOS transistor. A resistor R may be provided as an element or as wiring. The constant current source CS is a power supply circuit that regulates the output current to a constant value. A power supply voltage is applied to a power supply node VDD. A ground voltage is applied to a ground node VSS. The power supply voltage is higher than the ground voltage. An input signal is input to an input node. An output signal is output from an output node. The voltages of the input node and the output node are also referred to as "input voltage" and "output voltage," respectively.A character “ / ” added to the reference symbol indicates that an inverted signal of a signal input to the node of the combined reference symbol is input or output. <1> First embodiment

[0008] A semiconductor circuit 1 according to a first embodiment is a 2-in-1-out current mode logic (CML) to CMOS circuit (hereinafter referred to as a "C2C circuit") with an active inductor signal feedback configuration. Details of the semiconductor circuit 1 according to the first embodiment will be described below. <1-1> Configuration

[0009] Fig. 1 is a circuit diagram illustrating an example of a circuit configuration of the semiconductor circuit 1 according to the first embodiment. As shown in Fig. As illustrated in Figure 1, semiconductor circuit 1 is a C2C circuit that receives an analog small signal at input nodes IN and / IN and outputs a digital large signal at an output node OUT. Semiconductor circuit 1 includes, for example, P-type transistors PM10 to PM12, N-type transistors NM10 and NM11, a resistor R10, a constant current source CS10, and nodes ND10 to ND12.

[0010] A source end and a drain end of the P-type transistor PM10 are connected to the power supply node VDD and the node ND10, respectively. A gate end of the P-type transistor PM10 is connected to the node ND10 via the resistor R10. A drain end and a source end of the N-type transistor NM10 are coupled to the nodes ND10 and ND12, respectively. A gate end of the N-type transistor NM10 is coupled to the input node IN.

[0011] A source end and a drain end of the P-type transistor PM11 are coupled to the power supply node VDD and the node ND11, respectively. A gate end of the P-type transistor PM11 is coupled to the node ND10. The node ND11 is coupled to the output node OUT. A drain end and a source end of the N-type transistor NM11 are coupled to the nodes ND11 and ND12, respectively. A gate end of the N-type transistor NM11 is coupled to the input node / IN.

[0012] An input end and an output end of the constant current source CS10 are coupled to the node ND12 and a ground node VSS, respectively.

[0013] A source end and a drain end of the P-type transistor PM12 are coupled to the power supply node VDD and the input node / IN, respectively. A gate end of the P-type transistor PM12 is coupled to the gate end of the P-type transistor PM10. The P-type transistor PM12 can be smaller than the P-type transistor PM10. The ratio between the size of the P-type transistor PM12 and the size of the P-type transistor PM10 is, for example, 1:1, 2:7.

[0014] In the C2C circuit according to the first embodiment, the transistor that receives the input signal may be a P-type transistor. Hereinafter, as a C2C circuit according to a modification of the first embodiment, a semiconductor device 1A including a PMOS transistor that receives an input signal will be described.

[0015] Fig. 2 is a circuit diagram illustrating an example of a circuit configuration of the semiconductor circuit 1A according to the modification of the first embodiment. As shown in Fig. 2, the semiconductor circuit 1A includes, for example, P-type transistors PM13 and PM14, N-type transistors NM12 to NM14, a resistor R11, a constant current source CS11, and nodes ND13 to ND15.

[0016] An input end and an output end of the constant current source CS11 are coupled to the power supply node VDD and the node ND13, respectively.

[0017] A source end and a drain end of the P-type transistor PM13 are coupled to nodes ND13 and ND14, respectively. A gate end of the P-type transistor PM13 is coupled to the input node IN. A drain end and a source end of the N-type transistor NM12 are coupled to node ND14 and a ground node VSS, respectively. A gate end of the N-type transistor NM12 is coupled to node ND14 via resistor R11.

[0018] A source end and a drain end of the P-type transistor PM14 are coupled to nodes ND13 and ND15, respectively. A gate end of the P-type transistor PM14 is coupled to an input node / IN. Node ND15 is coupled to an output node OUT. A drain end and a source end of the N-type transistor NM13 are coupled to node ND15 and a ground node VSS, respectively. A gate end of the N-type transistor NM13 is coupled to node ND14.

[0019] A drain end and a source end of the N-type transistor NM14 are coupled to the input node / IN and a ground node VSS, respectively. A gate end of the N-type transistor NM14 is coupled to the gate end of the N-type transistor NM12. The N-type transistor NM14 can be smaller than the N-type transistor NM12. The ratio between the size of the N-type transistor NM14 and the size of the N-type transistor NM12 is, for example, 1:1, 2:7. <1-2> Operation

[0020] Fig. 3 is a schematic diagram illustrating an overview of the operation of the semiconductor circuit 1 according to the first embodiment. As shown in Fig. As illustrated in Figure 3, in semiconductor circuit 1, a parasitic capacitance PC is formed at the gate end of P-type transistor PM10. In semiconductor circuit 1, a set of parasitic capacitance PC and resistor R10 functions as an RC filter. Consequently, a set of P-type transistor PM10, parasitic capacitance PC, and resistor R10 functions as an active inductor. In semiconductor circuit 1, P-type transistor PM12 feeds the active inductor signal back to input node / IN.

[0021] Specifically, the on / off state of N-type transistors NM10 and NM11 changes according to the input signals IN and / IN. Then, the voltage of node ND10 changes according to the states of N-type transistors NM10 and NM11. When a high-frequency signal is input to input nodes IN and / IN, the parasitic capacitance PC is charged when N-type transistor NM10 is in the on state. As a result, the high-frequency signal is suppressed at the gate end of P-type transistor PM10 to be a DC signal. Then, in semiconductor circuit 1, the gate end of P-type transistor PM12 is coupled to the gate end of P-type transistor PM10, and P-type transistor PM12 is coupled between power supply node VDD and input node / IN.With this configuration, the P-type transistor PM12 can feed back a signal based on the gate end voltage of the P-type transistor PM10 to the node / IN and reduce the gain near the DC current of the semiconductor circuit 1.

[0022] Note that in the semiconductor circuit 1A, similar to the semiconductor circuit 1, the N-type transistor NM14 can feed back a signal based on the voltage of the gate end of the N-type transistor NM12 to the node / IN, and the gain of the semiconductor circuit 1A can be reduced near the DC current. <1-3> Effects of the first embodiment

[0023] According to the semiconductor circuits 1 and 1A of the first embodiment described above, high-speed signal transmission can be realized. The effects of the first embodiment will be described in detail below.

[0024] The frequency of a signal used for transmitting and receiving data between two devices tends to increase with increasing data transmission speed. Therefore, it is desirable for a circuit used for signal transmission to be capable of processing a high-frequency signal. However, in a case where the signal frequency increases, the receiving circuit may not be in a fully oscillating state (a rail-to-rail state), and skew may occur.

[0025] As a method for suppressing skew, it is conceivable to provide a plurality of CMLs in the path of the input node to reduce the gain near the DC current. In a case where the gain decreases near the DC current, the receiving circuit can be in a full-wave state (a rail-to-rail state), and high-speed operation becomes possible. However, providing a plurality of CMLs in the path of the input node requires a large circuit area and high power consumption, which may lead to an increase in the cost of the semiconductor circuit.

[0026] Therefore, semiconductor circuits 1 and 1A according to the first embodiment include a transistor that operates based on the voltage of the active inductor. With this configuration, semiconductor circuits 1 and 1A can feed the voltage back to the paired input node / IN based on the signal input to the input node IN.

[0027] Fig. 4 is a waveform diagram illustrating a simulation result of the operation of the semiconductor circuit 1 according to the first embodiment. Fig. Figure 4 illustrates a change in the voltage of the output node of the semiconductor circuit 1 in a case where the signal input to the input node changes from a DC signal to a high-frequency signal. A change in the voltage of the output node of the semiconductor circuit 1 according to the first embodiment is shown by a dashed line. In addition, Fig. 4, as a comparison example, a simulation result for the case where the P-type transistor PM12 is omitted in the semiconductor circuit 1 is indicated by a solid line.

[0028] As in Fig. 4, in the comparative example, the difference between the output voltage based on the DC signal and the peak of the output voltage at the time of the first swing when the DC signal transitions to the high-frequency signal is DX. On the other hand, in the first embodiment, the difference between the output voltage based on the DC signal and the voltage at the peak of the output voltage at the time of the first swing when the DC signal transitions to the high-frequency signal, DY, is smaller than DX. In other words, in the semiconductor circuit 1 according to the first embodiment, the gain near the DC current of the semiconductor circuit 1 (transmission circuit) is reduced by the P-type transistor PM12. Similar to the semiconductor circuit 1, the semiconductor circuit 1A can also reduce the gain near the DC current by the N-type transistor NM14.

[0029] Fig. 5 and Fig. 6 are waveform diagrams illustrating specific examples of the operation of the semiconductor circuit 1. Fig. 5 and Fig. 6 correspond to the comparative example and the first embodiment, respectively. In (A) the Fig. 5 and Fig. 6 illustrated waveforms indicate the timings at which a signal input to the semiconductor circuit 1 transitions between an “L” level and an “H” level. In (B) the Fig. 5 and Fig. 6 illustrates an output signal of the semiconductor circuit 1 based on the signal shown in (A). The waveforms shown in (B) of the Fig. 5 and Fig. The regions AR1 to AR3 illustrated in Figure 6 each extract one period corresponding to one pulse. Specifically, the AR1 region extracts the output voltage waveform when the "H" level signal corresponding to a pulse is input from the "L" level DC signal. The AR2 region extracts the output voltage waveform when the high-frequency signal is input. The AR3 region extracts the output voltage waveform when the "L" level signal corresponding to a pulse is input from the "H" level DC signal.

[0030] As in (B) of Fig. 5, the output voltage in each of the regions AR1 to AR3 of the comparative example cannot be completely switched. Specifically, in the comparative example, the difference (amplitude) between the output voltage based on the DC signal at the "L" level and the output voltage based on the DC signal at the "H" level is indicated as "A1." In the comparative example, the amount of change in the output voltage in each of the regions AR1 to AR3 is smaller than A1. (C) in Fig. Figure 5 shows the waveforms of regions AR1 and AR3 in the comparison example in an overlapping manner, so that the timing of the transition from the "L" level to the "H" level is aligned. As shown in (C) of Fig. As illustrated in Figure 5, the full sweep cannot be performed in each of the regions AR1 and AR3 of the comparative example, so the timing of crossing the thresholds used to determine the "H" level and the "L" level are different during the transition from the "L" level to the "H" level. In other words, a skew may occur in the comparative example.

[0031] On the other hand, as in (B) of Fig. 6, in each of the regions AR1 to AR3 of the first embodiment, the output voltage can be completely switched. Specifically, in the first embodiment, the difference (amplitude) between the output voltage based on the DC signal at the "L" level and the output voltage based on the DC signal at the "H" level is indicated as "A2." According to the first embodiment, the amount of change in the output voltage in each of the regions AR1 to AR3 is A2. (C) of Fig. Fig. 6 illustrates a state in which the waveforms of the regions AR1 and AR3 are superimposed in the first embodiment. As shown in (C) of Fig. As illustrated in Figure 6, in each of the regions AR1 and AR3 of the first embodiment, the timing of crossing the thresholds used for determining the "H" level and the "L" level at the time of transition from the "L" level to the "H" level are substantially the same, since full swing is possible. In other words, according to the first embodiment, the shift can be suppressed.

[0032] As described above, semiconductor circuits 1 and 1A according to the first embodiment can improve the output voltage to be close to the full-wave state, compared to a case where the active inductor voltage is not fed back. As a result, semiconductor circuits 1 and 1A can suppress drift and realize high-speed operation for high frequencies. In other words, semiconductor circuits 1 and 1A can realize high-speed signal transmission.

[0033] In semiconductor circuits 1 and 1A according to the first embodiment, a transistor is added to feed back the voltage of the active inductor. With such a transistor, a similar effect to that achieved when a plurality of CMLs are provided in the path of the input node is achieved. Therefore, semiconductor circuits 1 and 1A according to the first embodiment can realize a circuit with a smaller area than when a plurality of CMLs are provided in the path of the input node.

[0034] According to the first embodiment, the case where the number of transistors added for feedback of the active inductor voltage is one has been exemplified, but the present invention is not limited thereto. According to the layout of the circuit region around the semiconductor circuits 1 and 1A according to the first embodiment, the P-type transistor PM12 and the N-type transistor NM14 may include a plurality of transistors. Specifically, for example, in the semiconductor circuit 1, the gate ends of the plurality of P-type transistors PM12 are coupled to the gate ends of the P-type transistors PM10, and the plurality of P-type transistors PM12 are coupled between the power supply node VDD and the input node / IN. The total size of the plurality of P-type transistors PM12 may be smaller than that of the P-type transistor PM10.The ratio between the total size of the plurality of P-type transistors PM12 and the size of the P-type transistor PM10 is, for example, 1:1.2 to 7. Specifically, for example, in the semiconductor circuit 1A, the drain ends and the source ends of the plurality of N-type transistors NM14 are coupled to the input node / IN and the ground node VSS, respectively. The gate ends of the plurality of N-type transistors NM14 are coupled to the gate ends of the N-type transistors NM12. The total size of the plurality of N-type transistors NM14 may be smaller than that of the N-type transistor NM12. The ratio between the total size of the plurality of N-type transistors NM14 and the size of the N-type transistor NM12 is, for example, 1:1.2 to 7.

[0035] Note that the semiconductor circuits 1 and 1A according to the first embodiment are preferably used selectively according to an input signal (input circuit). By selectively using the NMOS-based semiconductor circuit 1 and the PMOS-based semiconductor circuit 1A according to the characteristics of the input signal, higher efficiency and high-speed signal transmission can be realized. <2> Second embodiment

[0036] A semiconductor circuit 2 according to a second embodiment is a 2-in-2-out differential amplifier circuit configured to feed back an active inductor signal. Details of the semiconductor circuit 2 according to the second embodiment will be described below. <2-1> Configuration

[0037] Fig. 7 is a circuit diagram illustrating an example of a circuit configuration of the semiconductor circuit 2 according to the second embodiment. As shown in Fig. As illustrated in Figure 7, semiconductor circuit 2 is a differential amplifier circuit that amplifies a difference between two input voltages input to input nodes IN and / IN and outputs the amplified difference to output nodes OUT and / OUT. Semiconductor circuit 2 includes, for example, P-type transistors PM20 to PM23, N-type transistors NM20 and NM21, resistors R20 and R21, a constant current source CS20, and nodes ND20 to ND22.

[0038] A source end and a drain end of the P-type transistor PM20 are coupled to a power supply node VDD and ND20, respectively. A gate end of the P-type transistor PM20 is coupled to the node ND20 via the resistor R20. The node ND20 is coupled to the output node OUT. A drain end and a source end of the N-type transistor NM20 are coupled to the nodes ND20 and ND22, respectively.

[0039] A source end and a drain end of the P-type transistor PM21 are connected to the power supply node VDD and ND21, respectively. A gate end of the P-type transistor PM21 is coupled to the node ND21 via the resistor R21. The node ND21 is coupled to the output node / OUT. A drain end and a source end of the N-type transistor NM21 are coupled to the nodes ND21 and ND22, respectively.

[0040] One input end and one output end of the constant current source CS20 are coupled to the node ND22 and the ground node VSS, respectively.

[0041] A source end and a drain end of P-type transistor PM22 are coupled to a power supply node VDD and the input node / IN, respectively. A gate end of P-type transistor PM12 is coupled to the gate end of P-type transistor PM20. P-type transistor PM22 can be smaller than P-type transistor PM20. The ratio between the size of P-type transistor PM22 and that of P-type transistor PM20 is, for example, 1:1.2 to 7.

[0042] A source end and a drain end of the P-type transistor PM23 are coupled to a power supply node VDD and the input node IN, respectively. A gate end of the P-type transistor PM23 is coupled to the gate end of the P-type transistor PM21. The P-type transistor PM23 can be smaller than the P-type transistor PM21. The ratio between the size of the P-type transistor PM23 and the size of the P-type transistor PM21 is, for example, 1:1, 2:7.

[0043] In the differential amplifier circuit according to the second embodiment, the transistor that receives the input signal may be a P-type transistor. Hereinafter, a semiconductor device 2A including a PMOS transistor that receives an input signal will be described as a differential amplifier circuit according to a modification of the second embodiment.

[0044] Fig. 8 is a circuit diagram illustrating an example of a circuit configuration of the semiconductor circuit 2A according to the modification of the second embodiment. As shown in Fig. 8, the semiconductor circuit 2A includes, for example, P-type transistors PM24 and PM25, N-type transistors NM22 to NM25, resistors R22 and R23, a constant current source CS21, and nodes ND23 to ND25.

[0045] An input end and an output end of the constant current source CS21 are coupled to a power supply node VDD and the node ND23, respectively.

[0046] A source end and a drain end of the P-type transistor PM24 are coupled to nodes ND23 and ND24, respectively. A gate end of the P-type transistor PM24 is coupled to an input node IN. Node ND24 is coupled to an output node OUT. A drain end and a source end of the N-type transistor NM22 are coupled to node ND24 and a ground node VSS, respectively. A gate end of the N-type transistor NM22 is coupled to node ND24 via resistor R22.

[0047] A source end and a drain end of the P-type transistor PM25 are coupled to nodes ND23 and ND25, respectively. A gate end of the P-type transistor PM25 is coupled to an input node / IN. Node ND25 is coupled to an output node / OUT. A drain end and a source end of the N-type transistor NM23 are coupled to node ND25 and a ground node VSS, respectively. A gate end of the N-type transistor NM23 is coupled to node ND25 via resistor R23.

[0048] A drain end and a source end of the N-type transistor NM24 are coupled to the input node / IN and a ground node VSS, respectively. A gate end of the N-type transistor NM24 is coupled to the gate end of the N-type transistor NM22. The N-type transistor NM24 can be smaller than the N-type transistor NM22. The ratio between the size of the N-type transistor NM24 and the size of the N-type transistor NM22 is, for example, 1:1.2 to 7.

[0049] A drain end and a source end of the N-type transistor NM25 are connected to the input node IN and a ground node VSS, respectively. A gate end of the N-type transistor NM25 is coupled to the gate end of the N-type transistor NM23. The N-type transistor NM25 can be smaller than the N-type transistor NM23. The ratio between the size of the N-type transistor NM25 and the size of the N-type transistor NM23 is, for example, 1:1, 2:7. <2-2> Effects of the second embodiment

[0050] In semiconductor circuit 2, P-type transistor PM22 returns a signal based on the gate voltage of P-type transistor PM20, which corresponds to the active inductance, to node / IN. In semiconductor circuit 2, P-type transistor PM23 returns a signal based on the gate voltage of P-type transistor PM21, which corresponds to the active inductance, to node IN. As a result, semiconductor circuit 2 can reduce the gain near the DC current.

[0051] Similarly, in semiconductor circuit 2A, N-type transistor NM24 returns a signal based on the gate voltage of N-type transistor NM22, which corresponds to the active inductance, to node / IN. In semiconductor circuit 2A, N-type transistor NM25 returns a signal based on the gate voltage of N-type transistor NM23, which corresponds to the active inductance, to node IN. As a result, semiconductor circuit 2 can reduce the gain near the DC current.

[0052] Therefore, the semiconductor circuits 2 and 2A according to the second embodiment can improve the output voltage to a state close to full scale, as in the first embodiment. As a result, the semiconductor circuits 2 and 2A can suppress skew and realize high-speed operation for high frequencies. Moreover, the semiconductor circuits 2 and 2A according to the second embodiment can be realized by a circuit having a small area, as in the first embodiment. Furthermore, the semiconductor circuits 2 and 2A according to the second embodiment are selectively used in accordance with an input signal, so it is possible to realize high-speed signal transmission with more desirable efficiency. <3> Third embodiment

[0053] Similar to the active inductor, a semiconductor circuit 3 according to a third embodiment is a 2-in-2-out time-linear equalizer (CTLE) configured to feed back a signal from an operating node to . Details of the semiconductor circuit 3 according to the third embodiment will be described below. <3-1> Configuration

[0054] Fig. 9 is a circuit diagram illustrating an example of a circuit configuration of the semiconductor circuit 3 according to the third embodiment. As shown in Fig. As illustrated in Figure 9, semiconductor circuit 3 is a CTLE that amplifies two input voltages at input nodes IN and / IN and outputs the two amplified input voltages at output nodes OUT and / OUT. Semiconductor circuit 3 can amplify a specific frequency band of a signal. Semiconductor circuit 3 includes, for example, P-type transistors PM30 and PM31, N-type transistors NM30 and NM31, resistors R30 to R32, a capacitance element (capacitor) CP30, constant current sources CS30 and CS31, and nodes ND30 to ND33.

[0055] Node ND30 is coupled to the output node OUT. Node ND30 is coupled to a power supply node VDD via resistor R30. A drain end and a source end of N-type transistor NM30 are coupled to nodes ND30 and ND32, respectively. An input end and an output end of constant current source CS30 are coupled to node ND32 and a ground node VSS, respectively.

[0056] Node ND31 is coupled to the output node / OUT. Node ND31 is coupled to a power supply node VDD via resistor R31. A drain end and a source end of N-type transistor NM31 are coupled to nodes ND31 and ND33, respectively. An input end and an output end of constant current source CS31 are coupled to node ND33 and a ground node VSS, respectively.

[0057] Resistor R32 and capacitance element CP30 are coupled in parallel between nodes ND32 and ND33. Resistor R32 and capacitance element CP30 function as an RC filter.

[0058] A source end and a drain end of the P-type transistor PM30 are connected to a power supply node VDD and the input node / IN, respectively. A gate end of the P-type transistor PM30 is connected to the node ND30.

[0059] A source end and a drain end of the P-type transistor PM31 are connected to a power supply node VDD and the input node IN, respectively. A gate end of the P-type transistor PM31 is connected to the node ND31.

[0060] In the CTLE of the third embodiment, the transistor that receives the input signal may be a P-type transistor. Hereinafter, a semiconductor device 3A including a PMOS transistor that receives an input signal will be described as a CTLE according to a modification of the third embodiment.

[0061] Fig. 10 is a circuit diagram illustrating an example of a circuit configuration of the semiconductor circuit 3A according to the modification of the third embodiment. As shown in Fig. 10, the semiconductor circuit 3A includes, for example, P-type transistors PM32 and PM33, N-type transistors NM32 and NM33, resistors R33 to R35, a capacitance element CP31, constant current sources CS32 and CS33, and nodes ND34 to ND37.

[0062] An input end and an output end of the constant current source CS32 are connected to a power supply node VDD and node ND34, respectively. A source end and a drain end of the P-type transistor PM32 are coupled to nodes ND34 and ND36, respectively. Node ND36 is coupled to an output node OUT. Node ND36 is connected to a ground node VSS via resistor R34.

[0063] An input end and an output end of the constant current source CS33 are connected to a power supply node VDD and node ND35, respectively. A source end and a drain end of the P-type transistor PM33 are coupled to nodes ND35 and ND37, respectively. Node ND37 is coupled to an output node / OUT. Node ND37 is coupled to a ground node VSS via resistor R35.

[0064] Resistor R33 and capacitance element CP31 are coupled in parallel between nodes ND34 and ND35. Resistor R33 and capacitance element CP31 act as an RC filter.

[0065] A drain end and a source end of the N-type transistor NM32 are coupled to an input node / IN and a ground node VSS, respectively. A gate end of the N-type transistor NM32 is coupled to the node ND36.

[0066] A drain end and a source end of the N-type transistor NM33 are coupled to an input node IN and a ground node VSS, respectively. A gate end of the N-type transistor NM33 is coupled to the node ND37.

[0067] Note that the resistance values of the resistors R32 and R33, the capacitance values of the capacitance elements CP30 and CP31, and the like included in the semiconductor circuits 3 and 3A can be configured to be adjustable based on a control signal input from the outside. <3-2> Effects of the third embodiment

[0068] In semiconductor circuit 3, P-type transistor PM30 returns a signal to node / IN based on the voltage of node ND30, which operates similarly to the active inductance. In semiconductor circuit 3, P-type transistor PM31 returns a signal to node IN based on the voltage of node ND31, which operates similarly to the active inductance. As a result, semiconductor circuit 3 can reduce the gain near the DC current.

[0069] Similarly, in semiconductor circuit 3A, N-type transistor NM32 returns a signal to node / IN based on the voltage of node ND36, which operates similarly to the active inductance. In semiconductor circuit 3A, N-type transistor NM33 returns a signal to node IN based on the voltage of node ND37, which operates similarly to the active inductance. As a result, semiconductor circuit 3 can reduce the gain near the DC current.

[0070] Therefore, the semiconductor circuits 3 and 3A according to the third embodiment can improve the output voltage to a state close to full scale, as in the first embodiment. As a result, the semiconductor circuits 3 and 3A can suppress drift and realize high-speed operation for high frequencies. Moreover, the semiconductor circuits 3 and 3A according to the third embodiment can be realized by a circuit having a small area, as in the first embodiment. Furthermore, the semiconductor circuits 3 and 3A according to the third embodiment are selectively used in accordance with an input signal, so it is possible to realize high-speed signal transmission with more desirable efficiency. <4> Fourth embodiment

[0071] A semiconductor circuit according to a fourth embodiment has a configuration in which a circuit capable of switching whether or not to use a transistor that feeds back a signal from an active inductor is added to each of the semiconductor circuits 1, 1A, 2, 2A, 3, and 3A of the first to third embodiments. Details of the semiconductor circuit according to the fourth embodiment will be described below. <4-1> Configuration

[0072] Hereinafter, the semiconductor circuit 1 to which the fourth embodiment is applied is referred to as semiconductor circuit 1B according to a first configuration example of the fourth embodiment. The semiconductor circuit 1A to which the fourth embodiment is applied is referred to as semiconductor circuit 1C according to a second configuration example of the fourth embodiment. The semiconductor circuit 2 to which the fourth embodiment is applied is referred to as semiconductor circuit 2B according to a third configuration example of the fourth embodiment. The semiconductor circuit 2A to which the fourth embodiment is applied is referred to as semiconductor circuit 2C according to a fourth configuration example of the fourth embodiment. The semiconductor circuit 3 to which the fourth embodiment is applied is referred to as semiconductor circuit 3B according to a fifth configuration example of the fourth embodiment.The semiconductor circuit 3A to which the fourth embodiment is applied is referred to as a semiconductor circuit 3C according to a sixth configuration example of the fourth embodiment. <Erstes Konfigurationsbeispiel: C2C-Schaltung (NMOS-Basis)>

[0073] Fig. 11 is a circuit diagram illustrating an example of a circuit configuration of the semiconductor circuit 1B according to the first configuration example of the fourth embodiment. As shown in Fig. 11, for example, the semiconductor circuit 1B has a configuration in which P-type transistors PM15 and PM16 and P-type transistors PT10 to PT12 are added to the semiconductor circuit 1.

[0074] In the semiconductor circuit 1B, a circuit similar to the semiconductor circuit 1 is formed by P-type transistors PM10 to PM12, N-type transistors NM10 and NM11, a resistor R10, a constant current source CS10, and nodes ND10 to ND12 corresponding to the semiconductor circuit 1.

[0075] The drain ends of P-type transistors PM15 and PM16 are connected to an input node / IN. The gate ends of P-type transistors PM15 and PM16 are coupled to a gate end of P-type transistor PM10.

[0076] P-type transistor PT10 is connected between a power supply node VDD and a source end of P-type transistor PM12. P-type transistor PT11 is connected between a power supply node VDD and a source end of P-type transistor PM15. P-type transistor PT12 is connected between a power supply node VDD and a source end of P-type transistor PM16.

[0077] In other words, the source ends of P-type transistors PT10 to PT12 are coupled to the power supply node VDD. A drain end of P-type transistor PT10 is coupled to the source end of P-type transistor PM12. A drain end of P-type transistor PT11 is coupled to the source end of P-type transistor PM15. A drain end of P-type transistor PT12 is coupled to the source end of P-type transistor PM16.

[0078] A control signal EN10 is input to the gate end of the P-type transistor PT10. A control signal EN11 is input to the gate end of the P-type transistor PT11. A control signal EN12 is input to the gate end of the P-type transistor PT12. The control signals EN10 to EN12 can be individually controlled by an external control circuit. The on / off state of each of the P-type transistors PT10 to PT12 can be controlled based on the control signals EN10 to EN12.

[0079] In the first configuration example of the fourth embodiment, the number of sets of P-type transistors PM and PT connected in series between the power supply node VDD and the input node / IN (e.g., P-type transistors PM12 and PT10) may be one or more. In the first configuration example of the fourth embodiment, the plurality of P-type transistors PT included in the plurality of sets of P-type transistors PM and PT connected in series between the power supply node VDD and the input node / IN may be configured to be individually capable of controlling the on / off state. <Zweites Konfigurationsbeispiel: C2C-Schaltung (PMOS-Basis)>

[0080] Fig. 12 is a circuit diagram illustrating an example of a circuit configuration of the semiconductor circuit 1C according to the second configuration example of the fourth embodiment. As shown in Fig. 12, for example, the semiconductor circuit 1C has a configuration in which N-type transistors NM15 and NM16 and N-type transistors NT10 to NT12 are added to the semiconductor circuit 1A.

[0081] In the semiconductor circuit 1C, a circuit similar to the semiconductor circuit 1A is formed by P-type transistors PM13 and PM14, N-type transistors NM12 to NM14, a resistor R11, a constant current source CS11, and nodes ND13 to ND15.

[0082] The drain ends of N-type transistors NM15 and NM16 are connected to an input node / IN. The gate ends of N-type transistors NM15 and NM16 are coupled to a gate end of N-type transistor NM12.

[0083] The N-type transistor NT10 is coupled between the N-type transistor NM14 and a ground node VSS. The N-type transistor NT11 is coupled between the N-type transistor NM15 and a ground node VSS. The N-type transistor NT12 is coupled between the N-type transistor NM16 and a ground node VSS. Specifically, a source end of each of the N-type transistors NT10 to NT12 is coupled to the ground node VSS. A drain end of the N-type transistor NT10 is coupled to a source end of the N-type transistor NM14. A drain end of the N-type transistor NT11 is coupled to a source end of the N-type transistor NM15. A drain end of the N-type transistor NT12 is coupled to a source end of the N-type transistor NM16.

[0084] A control signal EN10 is input to a gate end of the N-type transistor NT10. A control signal EN11 is input to a gate end of the N-type transistor NT11. A control signal EN12 is input to a gate end of the N-type transistor NT12. The on / off state of each of the N-type transistors NT10 to NT12 can be controlled based on the control signals EN10 to EN12.

[0085] In the second configuration example of the fourth embodiment, the number of sets of N-type transistors NM and NT (e.g., N-type transistors NM14 and NT10) connected in series between the input node / IN and the ground node VSS may be one or more. In the second configuration example of the fourth embodiment, a plurality of N-type transistors NT included in the plurality of sets of N-type transistors NM and NT connected in series between the input node / IN and the ground node VSS may be configured to be individually capable of controlling the on / off state. <Drittes Konfigurationsbeispiel: Differenzverstärkerschaltung (NMOS-Basis)>

[0086] Fig. 13 is a circuit diagram illustrating an example of a circuit configuration of the semiconductor circuit 2B according to the third configuration example of the fourth embodiment. As shown in Fig. 13, for example, the semiconductor circuit 2B has a configuration in which P-type transistors PM26 and PM27 and P-type transistors PT20 to PT23 are added to the semiconductor circuit 2.

[0087] In the semiconductor circuit 2B, a circuit similar to the semiconductor circuit 2 is formed by P-type transistors PM20 to PM23, N-type transistors NM20 and NM21, resistors R20 and R21, a constant current source CS20, and nodes ND20 to ND22.

[0088] A drain end of the P-type transistor PM26 is coupled to an input node / IN. A gate end of the P-type transistor PM26 is coupled to a gate end of the P-type transistor PM20. A drain end of the P-type transistor PM27 is coupled to an input node IN. A gate end of the P-type transistor PM27 is coupled to a gate end of the P-type transistor PM21.

[0089] The P-type transistor PT20 is coupled between a power supply node VDD and the P-type transistor PM22. The P-type transistor PT21 is coupled between a power supply node VDD and the P-type transistor PM26. The P-type transistor PT22 is coupled between a power supply node VDD and the P-type transistor PM23. The P-type transistor PT23 is coupled between a power supply node VDD and the P-type transistor PM27. Specifically, the source ends of the P-type transistors PT20 to PT23 are coupled to the power supply nodes VDD. A drain end of the P-type transistor PT20 is coupled to a source end of the P-type transistor PM22. A drain end of the P-type transistor PT21 is coupled to a source end of the P-type transistor PM26. A drain end of the P-type transistor PT22 is coupled to a source end of the P-type transistor PM23.A drain end of the P-type transistor PT23 is coupled to a source end of the P-type transistor PM27.

[0090] A control signal EN20 is input to a gate end of the P-type transistor PT20. A control signal EN21 is input to a gate end of the P-type transistor PT21. A control signal EN22 is input to a gate end of the P-type transistor PT22. A control signal EN23 is input to a gate end of the P-type transistor PT23. The control signals EN20 to EN23 can be individually controlled by an external control circuit. The on / off state of each of the P-type transistors PT20 to PT23 can be controlled based on the control signals EN20 to EN23.

[0091] In the third configuration example of the fourth embodiment, the number of sets of P-type transistors PM and PT (e.g., P-type transistors PM22 and PT20) connected in series between the power supply node VDD and the input node IN or / IN may be one or more. In the third configuration example of the fourth embodiment, the plurality of P-type transistors PT included in the plurality of sets of P-type transistors PM and PT connected in series between the power supply node VDD and the input node IN or / IN may be configured to be individually capable of controlling the on / off state. As a set of P-type transistors PM and PT, at least one of the transistors coupled to the input node IN and the transistors coupled to the input node / IN may be provided. <Viertes Konfigurationsbeispiel: Differenzverstärkerschaltung (PMOS-Basis)>

[0092] Fig. 14 is a circuit diagram illustrating an example of a circuit configuration of the semiconductor circuit 2C according to the fourth configuration example of the fourth embodiment. As shown in Fig. 14, for example, the semiconductor circuit 2C has a configuration in which N-type transistors NM26 and NM27 and N-type transistors NT20 to NT23 are added to the semiconductor circuit 2A.

[0093] In the semiconductor circuit 2C, a circuit similar to the semiconductor circuit 2A is formed by P-type transistors PM24 and PM25, N-type transistors NM22 to NM25, resistors R22 and R23, a constant current source CS21, and nodes ND23 to ND25.

[0094] A drain end of N-type transistor NM26 is connected to an input node / IN. A gate end of N-type transistor NM26 is coupled to a gate end of N-type transistor NM22. A drain end of N-type transistor NM27 is coupled to an input node IN. A gate end of N-type transistor NM27 is coupled to a gate end of N-type transistor NM23.

[0095] The N-type transistor NT20 is coupled between the N-type transistor NM24 and a ground node VSS. The N-type transistor NT21 is coupled between the N-type transistor NM26 and a ground node VSS. The N-type transistor NT22 is coupled between the N-type transistor NM25 and a ground node VSS. The N-type transistor NT23 is coupled between the N-type transistor NM27 and a ground node VSS. Specifically, the source end of each of the N-type transistors NT20 to NT23 is coupled to the ground node VSS. A drain end of the N-type transistor NT20 is coupled to a source end of the N-type transistor NM24. A drain end of N-type transistor NT21 is coupled to a source end of N-type transistor NM26. A drain end of N-type transistor NT22 is coupled to a source end of N-type transistor NM25. A drain end of N-type transistor NT23 is coupled to a source end of N-type transistor NM27.

[0096] A control signal EN20 is input to a gate end of the N-type transistor NT20. A control signal EN21 is input to a gate end of the N-type transistor NT21. A control signal EN22 is input to a gate end of the N-type transistor NT22. A control signal EN23 is input to a gate end of the N-type transistor NT23. The on / off state of each of the N-type transistors NT20 to NT23 can be controlled based on the control signals EN20 to EN23.

[0097] In the fourth configuration example of the fourth embodiment, the number of sets of N-type transistors NM and NT (e.g., N-type transistors NM24 and NT20) connected in series between the input node IN or / IN and the ground node VSS may be one or more. In the fourth configuration example of the fourth embodiment, the plurality of N-type transistors NT included in the plurality of sets of N-type transistors NM and NT coupled in series between the input node IN or / IN and the ground node VSS may be configured to be individually capable of controlling the on / off state. As a set of N-type transistors NM and NT, at least one of the transistors coupled to the input node IN and the transistors coupled to the input node / IN may be provided. <Fünftes Konfigurationsbeispiel: CTLE (NMOS-Basis)>

[0098] Fig. 15 is a circuit diagram illustrating an example of a circuit configuration of the semiconductor circuit 3B according to the fifth configuration example of the fourth embodiment. As shown in Fig. 15, for example, the semiconductor circuit 3B has a configuration in which P-type transistors PM34 and PM35 and P-type transistors PT30 to PT33 are added to the semiconductor circuit 3.

[0099] In the semiconductor circuit 3B, a circuit similar to the semiconductor circuit 3 is formed by P-type transistors PM30 and PM31, N-type transistors NM30 and NM31, resistors R30 to R32, a capacitance element CP30, constant current sources CS30 and CS31, and nodes ND30 to ND33.

[0100] A drain end of P-type transistor PM34 is coupled to an input node / IN. A gate end of P-type transistor PM34 is coupled to a gate end of P-type transistor PM30. A drain end of P-type transistor PM35 is coupled to an input node IN. A gate end of P-type transistor PM35 is coupled to a gate end of P-type transistor PM31.

[0101] The P-type transistor PT30 is coupled between a power supply node VDD and the P-type transistor PM30. The P-type transistor PT31 is coupled between a power supply node VDD and the P-type transistor PM34. The P-type transistor PT32 is coupled between a power supply node VDD and the P-type transistor PM31. The P-type transistor PT33 is coupled between a power supply node VDD and the P-type transistor PM35. Specifically, the source ends of the P-type transistors PT30 to PT33 are coupled to the power supply nodes VDD. A drain end of the P-type transistor PT30 is coupled to a source end of the P-type transistor PM30. A drain end of the P-type transistor PT31 is coupled to a source end of the P-type transistor PM34. A drain end of the P-type transistor PT32 is coupled to a source end of the P-type transistor PM31.A drain end of the P-type transistor PT33 is coupled to a source end of the P-type transistor PM35.

[0102] A control signal EN30 is input to a gate end of the P-type transistor PT30. A control signal EN31 is input to a gate end of the P-type transistor PT31. A control signal EN32 is input to a gate end of the P-type transistor PT32. A control signal EN33 is input to a gate end of the P-type transistor PT33. The control signals EN30 to EN33 can be individually controlled by an external control circuit. The on / off state of each of the P-type transistors PT30 to PT33 can be controlled based on the control signals EN30 to EN33.

[0103] In the fifth configuration example of the fourth embodiment, the number of sets of P-type transistors PM and PT (e.g., P-type transistors PM30 and PT30) coupled in series between the power supply node VDD and the input node IN or / IN may be one or more. In the fifth configuration example of the fourth embodiment, the plurality of P-type transistors PT included in the plurality of sets of P-type transistors PM and PT coupled in series between the power supply node VDD and the input node IN or / IN may be configured to be individually capable of controlling the on / off state. As a set of P-type transistors PM and PT, at least one of the transistors coupled to the input node IN and the transistors coupled to the input node / IN may be provided. <Sechstes Konfigurationsbeispiel: CTLE (PMOS-Basis)>

[0104] Fig. 16 is a circuit diagram illustrating an example of a circuit configuration of the semiconductor circuit 3C according to the sixth configuration example of the fourth embodiment. As shown in Fig. 16, for example, the semiconductor circuit 3C has a configuration in which N-type transistors NM34 and NM35 and N-type transistors NT30 to NT33 are added to the semiconductor circuit 3A.

[0105] In the semiconductor circuit 3C, a circuit similar to the semiconductor circuit 3A is formed by P-type transistors PM32 and PM33, N-type transistors NM32 and NM33, resistors R33 to R35, a capacitance element CP31, constant current sources CS32 and CS33, and nodes ND34 to ND37.

[0106] A drain end of N-type transistor NM34 is connected to the input node / IN. A gate end of N-type transistor NM34 is coupled to a gate end of N-type transistor NM32. A drain end of N-type transistor NM35 is coupled to the input node IN. A gate end of N-type transistor NM35 is coupled to a gate end of N-type transistor NM33.

[0107] The N-type transistor NT30 is coupled between the N-type transistor NM32 and a ground node VSS. The N-type transistor NT31 is coupled between the N-type transistor NM34 and a ground node VSS. The N-type transistor NT32 is coupled between the N-type transistor NM33 and a ground node VSS. The N-type transistor NT33 is coupled between the N-type transistor NM35 and a ground node VSS. Specifically, the source end of each of the N-type transistors NT30 to NT33 is coupled to the ground node VSS. A drain end of the N-type transistor NT30 is coupled to a source end of the N-type transistor NM32. A drain end of N-type transistor NT31 is coupled to a source end of N-type transistor NM34. A drain end of N-type transistor NT32 is coupled to a source end of N-type transistor NM33. A drain end of N-type transistor NT33 is coupled to a source end of N-type transistor NM35.

[0108] A control signal EN30 is input to a gate end of the N-type transistor NT30. A control signal EN31 is input to a gate end of the N-type transistor NT31. A control signal EN32 is input to a gate end of the N-type transistor NT32. A control signal EN33 is input to a gate end of the N-type transistor NT33. The on / off state of each of the N-type transistors NT30 to NT33 can be controlled based on the control signals EN30 to EN33.

[0109] In the sixth configuration example of the fourth embodiment, the number of sets of N-type transistors NM and NT (e.g., N-type transistors NM32 and NT30) connected in series between the input node IN or / IN and the ground node VSS may be one or more. In the sixth configuration example of the fourth embodiment, the plurality of N-type transistors NT included in the plurality of sets of N-type transistors NM and NT connected in series between the input node IN or / IN and the ground node VSS may be configured to be individually capable of controlling the on / off state. As a set of N-type transistors NM and NT, at least one of the transistors coupled to the input node IN and the transistors coupled to the input node / IN may be provided. <4-2> Effects of the fourth embodiment

[0110] In each configuration example of the fourth embodiment described above, the number of transistors that feed the active inductor voltage back to the input node can be changed by the control signal EN. In other words, in each configuration example of the fourth embodiment, the gain adjustment amount near the DC current can be changed according to the input signal. As the number of transistors that feed the active inductor voltage back to the input node increases, the gain near the DC current can be reduced.

[0111] Therefore, in the semiconductor circuits 1B, 1C, 2B, 2C, 3B and 3C according to the fourth embodiment, the gain near the DC is adjusted by adjustment according to the input signal, so that it is possible to suppress the shift by a preferential adjustment such as realizing the full swing while maintaining the amplitude width of the signal, and it is possible to realize the high-speed operation. <5> Fifth embodiment

[0112] A fifth embodiment relates to a specific example of a semiconductor device using at least one of the semiconductor devices 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments. Details of the semiconductor device according to the fifth embodiment will be described below. <5-1> Configuration

[0113] The first to eighth configuration examples of the fifth embodiment will be described sequentially below. <Erstes Konfigurationsbeispiel: NAND-Flash-Speicher>

[0114] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can be used for the NAND flash memory. A semiconductor device 100 according to a first configuration example of the fifth embodiment will be described below as an example of such a NAND flash memory. (Configuration of the semiconductor device 100)

[0115] Fig. 17 is a block diagram illustrating an example of a configuration of the semiconductor device 100 (a NAND flash memory) according to the first configuration example of the fifth embodiment. As shown in Fig. As illustrated in Figure 17, the semiconductor device 100 is configured to be controllable by a memory controller 110. The semiconductor device 100 includes, for example, a memory cell array 101, an input / output circuit 102, a logic controller 103, a register circuit 104, a sequencer 105, a driver circuit 106, a row decoder module 107, and a sense amplifier module 108.

[0116] The memory cell array 101 is composed of a plurality of memory cells (memory cell transistors) MC capable of storing data in a non-volatile manner. The memory cell array 101 is divided into a plurality of blocks BLK. The block BLK is used, for example, as a data erasing unit. The block BLK contains a plurality of pages. The page contains a plurality of memory cells MC and is used as a unit for writing and reading data. The memory cell array 101 is provided with a plurality of bit lines BL and a plurality of word lines WL. Each memory cell MC is connected to a bit line BL and a word line WL.In a case where a plurality of memory cells MC are connected to the same set of bit lines BL and word lines WL, these memory cells MC can be independently selected using a plurality of selection transistors connected between the bit line BL and each memory cell MC. Each memory cell MC is a field-effect transistor with a stacked-gate structure including a charge storage layer. The charge storage layer may be a floating gate electrode or a charge trap film. The plurality of memory cells MC are arranged in a two-dimensional or three-dimensional array.

[0117] The input / output circuit 102 is, for example, a semiconductor integrated circuit configured to send and receive an 8-bit wide signal DQ<7:0> and the signals DQS and / DQS to and from the memory controller 110. The signal DQ may contain data, status information, address information, a command, and the like. The signals DQS and / DQS are signals that specify the transmission / reception timing of the signal DQ. The signals DQS and / DQS are signal pairs whose phases are opposite to each other. The input / output circuit 102 may transmit the received address information and a command to the register circuit 104. The input / output circuit 102 may send and receive data DAT to or from the sense amplifier module 58.

[0118] The input / output circuit 102 may be referred to as a memory interface circuit of the semiconductor device 100. The plurality of pads PD included in the semiconductor device 100 are connected to an interface circuit of the memory controller 110. The plurality of pads PD are used for the input and output of the signals DQ<7:0>, DQS, and / DQS. Note that the signal DQ<7:0> may be referred to as a "data signal." The signals DQS and BDQS may be referred to as a "data strobe signal and its inverted signal." The signals DQS and / or BDQS may be referred to as "clock signals," "operation clock signals," "strobe signals," and "timing signals."

[0119] Note that the DQ signal, for example, is a pulse signal. Each pulse contained in the DQ signal corresponds to modulated data. Pulse amplitude modulation, for example, is used as a data modulation method. Pulse amplitude modulation is a modulation method in which data is transmitted using voltages (amplitudes) of pulses at regular intervals. When pulse amplitude modulation is used as the data modulation method, the voltage level of each pulse of the DQ signal corresponds to 1-bit data or multi-bit data. Note that the memory controller 110MC can function as a receiving device, and the semiconductor device 100 can function as a transmitting device.

[0120] The logic controller 103 controls the input / output circuit 102 and the sequencer 105 based on the control signal received from the memory controller 110.

[0121] Register circuit 104 holds status information, address information, commands, and the like. The status information is updated according to the state of semiconductor device 100. The upper status is output to memory controller 110 based on a command from memory controller 110. The address information may include a block address, a page address, a column address, and the like. The command includes a command related to various operations of semiconductor device 100.

[0122] The sequencer 105 controls the entire operation of the semiconductor device 100. For example, the sequencer 105 can perform a read operation, a write operation, an erase operation, and the like based on a command and address information stored in the register circuit 104.

[0123] The driver circuit 106 generates a voltage used in a read operation, a write operation, an erase operation, and the like. The driver circuit 106 then supplies the generated voltage to the memory cell array 101, the row decoder module 107, the sense amplifier module 108, and the like.

[0124] The row decoder module 107 is a circuit connected to the wiring (word lines WL and the like) in the row direction in the memory cell array 101. The row decoder module 107 includes a plurality of row decoders connected to the plurality of blocks BLK. Each row decoder includes a block decoder capable of decoding a block address. The row decoder module 107 selects the block BLK based on the decoding result of the block decoder of each row decoder. The row decoder module 107 transmits the voltage supplied by the driver circuit 106 to, for example, the word line WL in the selected block BLK via the associated row decoder RD.

[0125] The sense amplifier module 108 is a circuit coupled to the wiring (bit line BL) in the column direction provided in the memory cell array 101. The sense amplifier module 108 includes a plurality of sense amplifier units, each connected to the plurality of bit lines BL. Each sense amplifier unit has a function of applying a voltage to the associated bit line BL, a function of determining data based on the voltage of the bit line BL, and a function of temporarily storing data. In the read operation, the sense amplifier module 108 reads data from the memory cell array 101 and transmits the read data to the input / output circuit 102. In the write operation, the sense amplifier module 108 applies a desired voltage to the bit line BL based on the data received from the input / output circuit 102. (Configuration of input / output circuit 102)

[0126] Fig. 18 is a block diagram illustrating an example of a configuration of an input / output circuit 102 in a semiconductor device 100 (NAND flash memory) according to the first configuration example of the fifth embodiment. Fig. 18 illustrates a case where the memory controller 110 operates as a transmitting device and the semiconductor device 100 operates as a receiving device. As in Fig. 18, the semiconductor device 100 includes, for example, an input receiver (IREC) 111, a driver circuit 112, a write duty cycle adjuster (WDCA) 113, a plurality of data input circuits 114-0 to 114-7, and a processing circuit 115.

[0127] The IREC 111 is a circuit that transmits a signal within a chip. The IREC 111 is connected to a pad PD, to which the DQS signal is input, and a pad PD, to which the BDQS signal is input. The output signal of the IREC 111 is input to the driver circuit 112. Since the IREC 111 directly receives external signals (DQS and BDQS) with small signals, a large circuit area is required.

[0128] The driver circuit 112 is a circuit that transmits a signal in the input / output circuit 102 to the IREC 111. The driver circuit 112 amplifies the signal input from the IREC 111 and transmits the amplified signal to the WDCA 113. The circuit area of the driver circuit 112 is smaller than that of the IREC 111 and the WDCA, for example.

[0129] For example, the WDCA 113 is a circuit that adjusts the duty cycles of the DQS and BDQS signals received from the memory controller 110 at the time of the write operation. That is, the WDCA 113 compensates for the duty cycle deviation of the DQS and BDQS signals. The WDCA 113 then distributes the DQS and BDQS signals, with the duty cycle deviation compensated, to each data input circuit 114 as a clock signal CLK. Note that the WDCA 113 transmits a signal over a long-distance line in the input / output circuit 102 and therefore requires a large circuit area. The length of the wiring connecting the WDCA 113 and the data input circuit 114 varies depending on the location of the data input circuit 114.

[0130] The plurality of data input circuits 114-0 to 114-7 are respectively connected to the plurality of pads PD. Each data input circuit 114 is a circuit that converts an electrical signal input via the pad PD into a digital signal. Specifically, each data input circuit 114 samples data and the like included in the signal DQ input to the pad PD based on the clock signal CLK input from the WDCA 113 and the inverted signal / CLK of the clock signal CLK (not shown). Then, each data input circuit 114 supplies the sampled data to the processing circuit 115. The data input circuits 114-0 to 114-7 are respectively connected to the signals DQ <0> to DQ <7> tied together.

[0131] Processing circuit 115 is a circuit that processes data and the like input from data input circuits 114-0 to 114-7. Processing circuit 115 is, for example, a register circuit 104, a sense amplifier module 108, or the like.

[0132] In a case where the semiconductor device 100 exchanges the DQ signal, a transmitting-side device (e.g., the memory controller 110) transmits the DQS and / or DQS signals to a receiving-side device. Then, the receiving-side device samples the DQ signal at a timing based on the clock signal generated from the received DQS and / or DQS signals. In a case where the receiving-side device is the semiconductor device 100, for example, the data sampled by the data input circuit 114 is stored in the memory cell array 101.

[0133] Note that each of the IREC 111, the driver circuit 112, and the WDCA 113 includes, for example, a differential amplifier circuit. In other words, at least one of the semiconductor circuits 2, 2A to 2C can be connected to each of the IREC 111, the driver circuit 112, and the WDCA 113. (Configuration of data input circuit 113)

[0134] Fig. 19 is a block diagram illustrating an example of a configuration of the data input circuit 114 in the semiconductor device 100 (NAND flash memory) according to the first configuration example of the fifth embodiment. The data input circuit 114 includes, for example, a C2C circuit 120, a full-range amplifier (FS) 121, a CTLE 122, and a sampler 123.

[0135] The C2C circuit 120 amplifies the clock signal CLK input from the WDCA 113 and an inverted signal / CLK of the clock signal CLK (not illustrated). The C2C circuit 120 corresponds to one of the semiconductor circuits 1 and 1A described in the first embodiment. The C2C circuit 120 is typically small in area because it is a circuit after long-distance wiring from the WDCA 113.

[0136] The FS 121 is a circuit that converts a signal amplified by the C2C circuit 120 into a CMOS level. The FS 121 then supplies the clock signal CLK converted to the CMOS level to the sampler 123. In this specification, the CMOS level is a logic level corresponding to "0" data or "1" data. Hereinafter, the logic level voltage corresponding to "0" data is also referred to as the "L" level, and the logic level voltage corresponding to "1" data is also referred to as the "H" level.

[0137] The CTLE 122 is an equalization circuit that receives the electrical signal input to the data input circuit 114. The CTLE 122 compensates the input signal DQ and passes the signal DQ to the sampler 123. Multiple CTLEs 122 can be connected in series between the pad PD, which receives the signal DQ, and the sampler 123. At this time, the wiring length connecting the multiple CTLEs 122 can be long. Semiconductor circuit 3, 3A, 3B, or 3C can be used as the CTLE 122.

[0138] Sampler 123 samples the data of signal DQ based on the timing specified by clock signal CLK. Sampler 123 then transmits a sampling result (data DAT or the like) of signal DQ to processing circuit 115. (Configuration of the C2C circuit 120)

[0139] Fig. 20 is a circuit diagram illustrating an example of a configuration of the C2C circuit 120 included in the data input circuit 114 in the semiconductor device (NAND flash memory) 100 according to the first configuration example of the fifth embodiment. As shown in Fig. As illustrated in Figure 20, the C2C circuit 120 includes, for example, semiconductor circuits 1H and 1L. Each of the semiconductor circuits 1H and 1L has a similar circuit configuration to the semiconductor circuit 1 described in the first embodiment, except for the connection relationship between the input nodes IN and / IN. For example, the clock signal CLK is input to the input node IN, and the inverted signal / CLK of the clock signal is input to the input node / IN.

[0140] Specifically, the gate end of the N-type transistor NM10 of the semiconductor circuit 1H is coupled to the input node IN. A gate end of the N-type transistor NM11 of the semiconductor circuit 1H is coupled to the input node / IN. A gate end of the N-type transistor NM10 of the semiconductor circuit 1L is coupled to the input node / IN. A gate end of the N-type transistor NM11 of the semiconductor circuit 1L is coupled to the input node IN. In other words, the N-type transistor NM10 of the semiconductor circuit 1H and the N-type transistor NM11 of the semiconductor circuit 1H are coupled to the input node IN. The N-type transistor NM11 of the semiconductor circuit 1H and the N-type transistor NM10 of the semiconductor circuit 1L are coupled to the input node / IN.

[0141] As a result, semiconductor circuits 1H and 1L output complementary signals. For example, in a case where a HIGH-level signal is output from node ND11 of semiconductor circuit 1H, a LOW-level signal is output from node ND11 of semiconductor circuit 1L. Other configurations of semiconductor circuits 1H and 1L are similar to those of semiconductor circuit 1. When semiconductor circuits 1H and 1L are used in combination, a constant current source CS can be added to suppress the influence of process fluctuations.

[0142] Fig. 21 is a circuit diagram illustrating an example of a configuration of a C2C circuit 120A included in the data input circuit 114 in the semiconductor device 100 according to the first configuration example of the fifth embodiment. As shown in Fig. 21, the C2C circuit 120A includes the semiconductor circuits 1H and 1L and a constant current source CS12.

[0143] The constant current source CS12 is coupled between the power supply node VDD and the P-type transistor PM12 of the semiconductor circuit 1H, and between the power supply node VDD and the P-type transistor PM12 of the semiconductor circuit 1L. In other words, the input end of the constant current source CS12 is connected to the power supply node VDD. The output end of the constant current source CS12 is coupled to both the source of the P-type transistor PM12 of the semiconductor circuit 1H and the source of the P-type transistor PM12 of the semiconductor circuit 1L. With this configuration, the C2C circuit 120A can reduce sensitivity to process variations and realize a high-precision compensation circuit. <Zweites Konfigurationsbeispiel: NOR-Typ Flash-Speicher>

[0144] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can be used for a non-volatile random access semiconductor memory device (e.g., a NOR flash memory). As an example of such a NOR flash memory, a semiconductor device 200 according to a second configuration example of the fifth embodiment will be described below.

[0145] Fig. 22 is a block diagram illustrating an example of a configuration of the semiconductor device 200 (NOR flash memory) according to the second configuration example of the fifth embodiment. As shown in Fig. 22, the semiconductor device 200 includes, for example, a memory cell array 201, a row controller 202, a column controller 203, an address register 204, a data buffer 205, an input / output shift register 206, a voltage generator 207, and a sequencer 208.

[0146] The memory cell array 201 includes a plurality of memory cells (memory cell transistors) MTx. In the semiconductor device 200, a gate end of each memory cell MTx is connected to a corresponding one of the plurality of word lines WL. One end of the current path of each memory cell MTx is connected to a corresponding one of the plurality of bit lines BL. The other end of the current path of each memory cell MTx is coupled to the source line and, for example, grounded. The plurality of memory cells MTx are arranged in a two-dimensional array or a three-dimensional array. The memory cell MTx is a field-effect transistor with a stacked-gate structure having a charge storage layer. The charge storage layer may be a floating gate electrode or a charge trap film.

[0147] The row controller 202 selects a word line corresponding to the address information from the plurality of word lines WL. The row controller 202 applies a predetermined voltage to the selected word line (and the unselected word line) according to the write operation, the read operation, the erase operation, and the like.

[0148] The column controller 203 selects a bit line corresponding to the address information from the plurality of bit lines BL. The column controller 203 applies a predetermined voltage to the selected bit line (and the unselected bit line) according to the write operation, the read operation, the erase operation, and the like.

[0149] The address register 204 temporarily stores the address information sent by the input / output shift register 206. The address register 204 sends the address information to the row controller 202 and the column controller 203.

[0150] The data buffer 205 temporarily stores read data from the memory cell array 201 and write data from the input / output shift register 206.

[0151] The input / output shift register 206 temporarily stores a signal DQ transmitted between the memory cell array 201 and the outside of the semiconductor device 200. The input / output shift register 206 sends the address information to the address register 204. The input / output shift register 206 sends the write data to the data buffer 205. The input / output shift register 206 sends the read data supplied from the memory cell array 201 to the outside of the semiconductor device 200. The input / output shift register 206 can perform parallel-to-serial conversion of the data DQ.

[0152] The voltage generator 207 generates a variety of voltage types, each used for the write operation, the read operation, and the erase operation. The voltage generator 207 supplies the generated voltage to the row controller 202, the column controller 203, and the like.

[0153] The sequencer 208 controls the entire operation of the semiconductor device 200 based on various control signals such as a reset signal RESETn, a hold signal HOLDn and a write protect signal Wn.

[0154] Note that the configuration of semiconductor device 200 (NOR flash memory) is not limited to this. Semiconductor device 200 may also include other components, such as a status register. The status register temporarily stores a status signal indicating an operating status within semiconductor device 200 and an execution result of the operating sequence.

[0155] In the semiconductor device 200 according to the second configuration example of the fifth embodiment, for example, the C2C circuit (semiconductor circuit 1, 1A, 1B, 1C) described in the above embodiment can be applied to the sequencer 208 and the input / output shift register 206. <Drittes Konfigurationsbeispiel: Dynamischer Direktzugriffsspeicher (DRAM)>

[0156] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can be used for a volatile semiconductor memory device (e.g., a DRAM). A semiconductor device 300 according to a third configuration example of the fifth embodiment will be described below as an example of such a DRAM.

[0157] Fig. 23 is a block diagram illustrating an example of a configuration of the semiconductor device 300 (DRAM) according to the third configuration example of the fifth embodiment. As shown in Fig. 23, the semiconductor device 300 includes, for example, a memory cell array 301, a row decoder 302, a column decoder 303, a command decoder 304, an address decoder 305, a command / address input circuit 306, a sense amplifier circuit 307, a transfer gate 308, a read / write amplifier (RWAMP) circuit 309, an input / output circuit 310, a clock input circuit 311, an internal clock generator 312, and a voltage generator 313.

[0158] The memory cell array 301 includes a plurality of memory cells MC. Each of the memory cells MC of the semiconductor device 300 includes a cell capacitor CC and a cell transistor CT. A gate of the cell transistor CT is connected to a corresponding one of the plurality of word lines WL. One end of a current path of the cell transistor CT is coupled to the bit line BL. The other end of the current path of the cell transistor CT is connected to one end of the cell capacitor CC. The other end of the cell capacitor CC is connected to the ground node. The cell capacitor CC can store an amount of charge corresponding to the data to be stored. The cell transistor CT switches conduction / non-conduction (selection / non-selection of the memory cell) between the memory cell MC and the bit line BL. The plurality of memory cells MC are arranged in a two-dimensional array or a three-dimensional array in the memory cell array 301.For example, the memory cell array 201 includes a plurality of banks. Each bank is a control unit with a plurality of memory cells MC. The multiple banks can operate independently of each other.

[0159] The row decoder 302 controls the selection / de-selection of the wiring (e.g., the word line WL) in the row direction of the memory cell array 301 based on the decoding result of the address information and the decoding result of the instruction.

[0160] The column decoder 303 controls the selection / de-selection of the wiring (e.g., the bit line BL) in the column direction of the memory cell array 301 based on the decoding result of the address information and the decoding result of the command.

[0161] The instruction decoder 304 decodes the instruction received from the instruction / address input circuit 306. The instruction decoder 304 then sends the decoding result of the instruction to each of the row decoders 302 and the column decoder 303.

[0162] The address decoder 305 decodes the address information received from the command / address input circuit 306. The address decoder 305 then sends the decoding result of the address information to each of the row decoders 302 and the column decoder 303.

[0163] The command / address input circuit 306 receives an externally supplied command / address signal CA. The command / address signal CA contains a command and address information. The command / address input circuit 306 transmits the command and address information to the command decoder 304 and the address decoder 305, respectively.

[0164] The sense amplifier circuit 307 detects and amplifies the signal from the memory cell MC during the read operation. The sense amplifier circuit 307 transmits a signal from the memory cell MC as read data to the input / output circuit 310 via the transfer gate 308 and the RWAMP 309. The sense amplifier circuit 307 receives the write data from the input / output circuit 310 via the transfer gate 308 and the RWAMP 309. The sense amplifier circuit 307 outputs a signal corresponding to the write data to the bit line BL.

[0165] The transfer gate 308 controls the data transfer between the sense amplifier circuit 307 and the RWAMP 309.

[0166] The RWAMP 309 amplifies the level (signal value) of the signal corresponding to the read data and the level of the signal corresponding to the write data.

[0167] The input / output circuit 310 functions as an interface circuit for a signal DQ transmitted between the memory cell array 301 and the outside of the semiconductor device 300. The input / output circuit 310 sends write data to the memory cell array 301 at a timing synchronized with an internal clock CLK2. The input / output circuit 310 sends the read data to a device outside the semiconductor device 300 at a timing synchronized with the internal clock CLK2. For example, the input / output circuit 310 receives a data mask signal DM. The input / output circuit 310 performs mask processing on the signal DQ (data) based on the data mask signal DM.

[0168] The clock input circuit 311 receives a clock CLK1 from the outside (hereinafter referred to as the external clock). The clock input circuit 311 sends the external clock CLK1 to the internal clock generator 312.

[0169] The internal clock generator 312 generates an internal clock CLK2 based on the external clock CLK1. The internal clock generator 312 sends the generated internal clock CLK2 to the input / output circuit 310 and the like.

[0170] The voltage generator 313 generates a plurality of voltages to be used for each of the different operating sequences of the semiconductor device 300 using an external supply voltage (a voltage applied to the power supply node VDD and a voltage applied to the ground node VSS). The voltage generator 313 sends the generated voltage to another circuit (e.g., the RWAMP 309).

[0171] According to the third configuration example of the fifth embodiment, a case where the semiconductor device 300 is a DRAM is exemplified, but the present invention is not limited to this. The semiconductor device 300 may also be a random access memory other than DRAM. For example, the semiconductor device 300 may be a static RAM (SRAM).

[0172] In the semiconductor device 300 according to the third configuration example of the fifth embodiment, for example, the CTLE (semiconductor circuits 3, 3A, 3B, and 3C) described in the above embodiment can be applied to the input / output circuit 310, the clock input circuit 311, and the internal clock generator 312. <Viertes Konfigurationsbeispiel: Cross-Point-Speicher >

[0173] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can be used for a cross-point memory. A semiconductor device 400 according to a fourth configuration example of the fifth embodiment will be described below as an example of such a cross-point memory.

[0174] Fig. 24 is a block diagram illustrating an example of a configuration of the semiconductor device 400 (a cross-point memory) according to the fourth configuration example of the fifth embodiment. As shown in Fig. As illustrated in Figure 24, the semiconductor device 400 operates under the control of a memory controller 410. The memory controller 410 can instruct the semiconductor device 400 to perform a read operation, a write operation, and the like in response to a command from an external host device. The semiconductor device 400 is a memory device that uses a magnetic tunnel junction (MTJ) element for a memory cell and is a type of resistive random access memory. The MTJ element utilizes a magnetoresistance effect due to a magnetic tunnel junction. The MTJ element is also referred to as a magnetoresistance effect element. The semiconductor device 400 includes, for example, a memory cell array 401, an input / output circuit 402, a control circuit 403, a row selection circuit 404, a column selection circuit 405, a write circuit 406, and a read circuit 407.

[0175] The memory cell array 401 includes a plurality of memory cells MC, a plurality of word lines WL and a plurality of bit lines BL. Fig. Figure 24 illustrates a set of memory cells MC, word lines WL, and bit lines BL. The memory cell MC can store data in a non-volatile manner. The memory cell MC is connected between a word line WL and a bit line BL and is associated with a set of one row and one column. A row address is assigned to the word line WL. A column address is assigned to the bit line BL. One or more memory cells MC can be identified by selecting a row and one or more columns.

[0176] The input / output circuit 402 is coupled to the memory controller 410 and controls the communication between the semiconductor device 400 and the memory controller 410. The input / output circuit 402 transmits a control signal CNT and a command CMD received from the memory controller 410 to the control circuit 403. The input / output circuit 402 transmits the row address and the column address contained in the address signal ADD received from the memory controller 410 to the row selection circuit 404 and the column selection circuit 405, respectively. The input / output circuit 402 transmits the data DAT received from the memory controller 410 to the write circuit 406. The input / output circuit 402 sends the data DAT received from the read circuit 407 to the memory controller 2.

[0177] The control circuit 403 controls the entire operation of the semiconductor device 400. For example, the control circuit 403 performs a read operation, a write operation, and the like based on the control instructed by the control signal CNT and the command CMD. For example, the control circuit 403 generates a voltage used for writing data in the write operation and supplies the voltage to the write circuit 406. Furthermore, the control circuit 403 generates a voltage used for reading data in the read operation and supplies the voltage to the read circuit 407.

[0178] Row selection circuit 404 is connected to the plurality of word lines WL. Then, row selection circuit 404 selects a word line WL specified by the row address. The selected word line WL is electrically connected to a driver circuit (not shown).

[0179] Column selection circuit 405 is coupled to the plurality of bit lines BL. Column selection circuit 405 then selects one or more bit lines BL specified by the column address. The selected bit line BL is electrically coupled to a driver circuit (not shown).

[0180] The write circuit 406 provides a voltage used to write data to the column selection circuit 405 based on the control of the control circuit 403 and the data DAT (data to be written) received from the input / output circuit 402. When a current based on the data DAT flows through the memory cell MC, the desired data is written to the memory cell MC.

[0181] Sense circuit 407 includes a sense amplifier. Sense circuit 407 supplies a voltage used for reading data to column selection circuit 405 under the control of control circuit 403. The sense amplifier then determines the data stored in memory cell MC based on the voltage or current of the selected bit line BL. Sense circuit 407 then sends data DAT (data read from memory cell array 401) according to the determination result to input / output circuit 402.

[0182] In the fourth configuration example of the fifth embodiment, the case where the semiconductor device 400 is an MRAM was described, but the present invention is not limited to this. The semiconductor device 400 may be another resistive random access memory. For example, the semiconductor device 400 may be a memory device (e.g., a resistance change memory such as a resistive random access memory (ReRAM)) that uses a transition metal oxide element with a variable resistance characteristic as a memory element, a memory device (e.g., a phase change memory such as a phase change random access memory (PCRAM)) that uses a phase change element as a memory element, or a memory device (e.g., a ferroelectric memory such as a ferroelectric random access memory (FeRAM)) that uses a ferroelectric element as a memory element.

[0183] In the semiconductor device 400 according to the fourth configuration example of the fifth embodiment, for example, the CTLE (semiconductor circuits 3, 3A, 3B, and 3C) described in the above embodiment can be applied to the input / output circuit 402 and the control circuit 403. <Fünftes Konfigurationsbeispiel: Bildsensor>

[0184] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can be used for an image sensor. A semiconductor device 500 according to a fifth configuration example of the fifth embodiment will be described below as an example of such an image sensor.

[0185] Fig. 25 is a block diagram illustrating an example of a configuration of the semiconductor device 500 (image sensor) according to the fifth configuration example of the fifth embodiment. As shown in Fig. 25, the semiconductor device 500 includes, for example, a pixel array 501, a row scanning circuit 502, a column processing circuit 503, a column scanning circuit 504, a system controller 505, and a signal processing circuit 506.

[0186] The pixel array 501 includes a plurality of pixels PX. The plurality of pixels PX are arranged in a two-dimensional raster shape along the row and column directions. Each pixel PX includes a photoelectric conversion element. The photoelectric conversion element generates a charge corresponding to the amount of received light and accumulates the generated charge. In the pixel array 501, a filter may be provided for a light incident surface of each pixel PX. The arrangement pattern of the plurality of filters is, for example, a Bayer pattern. In the pixel array 501, the plurality of pixels PX arranged in the row direction are typically coupled to a pixel drive line PDL. In the pixel array 501, the plurality of pixels PX arranged in the column direction are typically coupled to the corresponding one of a plurality of vertical signal lines VSL.

[0187] The line scanning circuit 502 is connected to one end of the plurality of pixel drive lines PDL. The line scanning circuit 502 generates a drive signal for performing signal read drive from the pixels PX. The line scanning circuit 502 drives all the pixels PX of the pixel array 501 simultaneously or row by row via the plurality of pixel drive lines PDL. Signals output from the plurality of pixels PX driven by the line scanning circuit 502 are supplied to the column processing circuit 903 via the corresponding vertical signal line VSL for each pixel PX arranged in the row direction.

[0188] Column processing circuit 503 performs predetermined signal processing on the signal supplied via vertical signal line VSL. With its configuration, column processing circuit 503 can generate a pixel signal. Furthermore, column processing circuit 503 can temporarily store the generated pixel signal. Column processing circuit 503 can perform, for example, noise removal processing, analog-to-digital conversion (AD conversion) processing, and the like. The digital signal obtained by the AD conversion is output to signal processing circuit 506.

[0189] The column scanning circuit 504 sequentially selects read circuits corresponding to the arrangement of the pixel signals of the column processing circuit 503. Through the selective scanning by the column scanning circuit 504, pixel signals subjected to signal processing for each pixel in the column processing circuit 503 are output in a predetermined order.

[0190] The system controller 505 receives a system clock signal and the like via a controller (not shown) external to the semiconductor device 500. The system controller 505 includes a timing generator and the like. The timing generator generates various timing signals based on the system clock signal. In this configuration, the system controller 505 controls the row scanning circuit 502, the column processing circuit 503, the column scanning circuit 504, and the like based on the generated various timing signals.

[0191] The signal processing circuit 506 has at least one arithmetic processing function. The signal processing circuit 506 performs various types of signal processing, such as arithmetic processing, on the pixel signal output from the column processing circuit 503.

[0192] Note that the digital signal output from the signal processing circuit 506 is output to an image processing circuit 507 external to the semiconductor device 500. The image processing circuit 507 performs predetermined processing on the digital signal. Then, the image processing circuit 507 generates an image signal for displaying an image on a predetermined display device.

[0193] In the semiconductor device 500 according to the fifth configuration example of the fifth embodiment, for example, the CTLE (semiconductor circuits 3, 3A, 3B, and 3C) described in the above embodiment can be applied to the system controller 505 that receives a system clock signal. <Sechstes Konfigurationsbeispiel: Kommunikationsschnittstelle>

[0194] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can be used for a communication interface. Hereinafter, a semiconductor device 600 according to a sixth configuration example of the fifth embodiment will be described as an example of such a communication interface. Note that the communication interface may be a circuit compatible with wired communication such as light or Ethernet (registered trademark), or a circuit compatible with wireless communication such as RF.

[0195] Fig. 26 is a block diagram illustrating an example of a configuration of the semiconductor device 600 (a communication interface) according to the sixth configuration example of the fifth embodiment. As shown in Fig. 26, the semiconductor device 600 is a differential transmission input / output interface circuit (e.g., a transceiver). Specifically, the semiconductor device 600 includes input / output terminals 601A and 601B, resistor-capacitor (RC) circuits 602A and 602B, an analog-to-digital (AD) converter circuit 603, capacitor circuits 604A and 604B, a digital-to-analog (DA) converter circuit 605, a current sink circuit 606, a clock phase adjustment circuit 607, a control clock generator 608, an input monitor 609, an input / output monitor 610, a PVT monitor 611, a global bias generator 612, bias generators 613 and 614, and an input / output controller 615.

[0196] Input / output terminals 601A and 601B are a pair of differential input / output terminals. Semiconductor device 600 can transmit and receive differential signals IO+ and IO- via input / output terminals 601A and 601B, respectively. The two differential signals IO+ and IO are in a complementary relationship to each other. Note that the two input / output terminals 601A and 601B, which form a pair to perform differential transmission, may be referred to as a differential input / output terminal pair. A pair of signal lines for differential transmission in semiconductor device 600 may be referred to as a differential transmission path.

[0197] RC circuits 602A and 602B are provided corresponding to input / output terminals 601A and 601B, respectively. RC circuit 602A is connected to a signal path of input / output terminal 601A. RC circuit 602B is coupled to a signal path of input / output terminal 601B. RC elements 602A and 602B control a time constant with respect to the input signal. RC circuits 602A and 602B include a resistor and a capacitor and can be designed (programmed) after assembly. The RC circuit can be referred to as an RC network.

[0198] The AD converter circuit 603 receives the differential signals IO+ and IO- supplied to the semiconductor device 600 via the RC circuits 602A and 602B. The AD converter circuit 603 receives the reference signals IOMVR+ and IOMVR- from the bias generator 613. The AD converter circuit 603 converts the signals IO+ and IO- from analog signals to digital signals based on the reference signals IOMVR+ and IOMVR-.

[0199] Capacitor circuit 604A is provided between RC circuit 602A and DA converter circuit 605. Capacitor circuit 604B is arranged between RC circuit 602B and DA converter circuit 605. Capacitor circuit 604A is coupled to RC circuit 602A. Capacitor circuit 604B is coupled to RC circuit 602B. Capacitor circuits 604A and 604B include a plurality of capacitors. Capacitor circuits 604A and 604B perform signal smoothing.

[0200] The DA converter circuit 605 receives digital signals. The DA converter circuit 605 receives the reference signals IOMVR+ and IOMVR- from the bias generator 613. The DA converter circuit 605 generates analog signals DACOUT+ and DACOUT- based on the received digital signals and the reference signals IOMVR+ and IOMVR-. The analog signals DACOUT+ and DACOUT- are signals that are in a complementary relationship to each other. The DA converter circuit 605 sends the generated analog signal DACOUT+ to the input / output terminal 601A via the capacitor circuit 604A and the RC circuit 602A. The DA converter circuit 605 sends the generated analog signal DACOUT- to the input / output terminal 601B via the capacitor circuit 604B and the RC circuit 602B. In this configuration, the signals DACOUT+ and DACOUT are output as differential signals IO+ and IO-, respectively, to the outside of the semiconductor device 600.In addition, the DA converter circuit 605 sends the analog signals DACOUT+ and DACOUT- to the current sink circuit 606.

[0201] The current sink circuit 606 controls the magnitude of the current flowing through the input / output terminals 601 and the signal lines within an allowable range based on the specification of the communication interface.

[0202] The clock phase adjustment circuit 607 adjusts the phase of the reference clock signal and generates various clock signals used in the semiconductor device 600.

[0203] The control clock generator 608 adjusts the phase of the reference clock signal and generates various clock signals used in the semiconductor device 600.

[0204] The input monitor 609 monitors both the IO+ signal at the input / output terminal 601A and the IO- signal at the input / output terminal 601B.

[0205] The input / output monitor 610 monitors a plurality of clock signals received from the control clock generator 608.

[0206] The PVT monitor 611 monitors various bandgap voltages and bias voltages in the semiconductor device 600. The bandgap voltage is a voltage that serves as a reference (reference voltage) for the signal voltage amplitude. The bias voltage is a voltage for operating the individual circuit blocks in the semiconductor device 600.

[0207] The global bias generator 612 generates a main bias voltage used for each circuit block in the semiconductor device 600.

[0208] The bias generator 613 generates a voltage that serves as a reference for a bias voltage (bias signal) of the AD converter circuit 603 and the DA converter circuit 605.

[0209] The bias voltage generator 614 generates a bias voltage for the AD converter circuit 603 and the input / output controller 615.

[0210] The input / output controller 615 generates a control signal for each circuit block in the semiconductor device 600. The input / output controller 615 supplies the generated control signal to each circuit block.

[0211] For example, in the semiconductor device 600 according to the sixth configuration example of the fifth embodiment, the CTLE (semiconductor circuits 3, 3A, 3B, and 3C) described in the above embodiment can be applied to the control clock generator 608. Furthermore, in the semiconductor device 600 according to the sixth configuration example of the fifth embodiment, the differential amplifier circuit (semiconductor circuits 2, 2A, 2B, and 2C) described in the above embodiment can be applied to a circuit that processes differential signals (e.g., the AD converter circuit 603, the DA converter circuit 605, the current sink circuit 606, the input monitor 609, and the bias generator 613). <Siebtes Konfigurationsbeispiel: Drahtlosvorrichtung>

[0212] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can be used for a wireless device. As an example of such a wireless device, a semiconductor device 700 according to a seventh configuration example of the fifth embodiment will be described below.

[0213] Fig. 27 is a block diagram illustrating an example of a configuration of the semiconductor device 700 (a wireless device) according to the seventh configuration example of the fifth embodiment. As shown in Fig. 27, the semiconductor device 700 includes, for example, an upper layer 710, a transmitting unit 720, a switching unit 730, a receiving unit 740, a reference clock generator 750, and a clock generator 760.

[0214] The upper layer 710 is a functional block that processes frames transmitted and received by the semiconductor device 700. The upper layer 710 may perform, for example, MAC layer processing. For example, the upper layer 710 generates a frame using data traffic generated by an application of the wireless device and inputs the generated frame to the transmitting unit 720. Furthermore, the upper layer 710 extracts data from the frame received by the receiving unit 740 and inputs the extracted data to the application.

[0215] The transmitting unit 720 converts the frame input from the upper layer 710 into a radio signal and transmits the radio signal via an antenna. The transmitting unit 720 includes, for example, a modulator 721, a frequency converter 722, and an amplifier 723. The modulator 721 passes a signal obtained by modulating the input frame to the frequency converter 722. The frequency converter 722 converts the frequency of the input signal to a desired frequency and passes the frequency to the amplifier 723. The amplifier 723 is a solid-state power amplifier (SSPA) that amplifies an input signal. The amplifier 723 includes, for example, an amplifier circuit, an isolator, and a low-pass filter. The output signal of the amplifier 723 is radiated from the antenna via the switching unit 730.

[0216] The switching unit 730 is a circuit that can switch the connection to the antenna between the transmitting unit 720 and the receiving unit 740.

[0217] The receiving unit 740 extracts a frame from a radio signal received via the antenna and forwards the frame to the upper layer 710. The receiving unit 740 includes, for example, an amplifier 741, a frequency converter 742, and a demodulator 743. The amplifier 741 amplifies the signal received via the antenna and forwards the amplified signal to the frequency converter 742. The amplifier 741 includes, for example, a bandpass filter and an amplifier circuit. The frequency converter 742 converts the frequency of the input signal to a desired frequency and forwards the frequency to the demodulator 743. The demodulator 743 demodulates the input signal and extracts a frame contained in the radio signal. The demodulator 743 then forwards the extracted frame to the upper layer 710.

[0218] The reference clock generator 750 generates a reference clock signal used in the semiconductor device 700.

[0219] The clock generator 760 generates a plurality of clock signals based on the reference clock signal, which are used in the semiconductor device 700. Then, the clock generator 760 inputs the generated clock signal to, for example, the modulator 721, the frequency converters 722 and 742, and the demodulator 743.

[0220] In the semiconductor device 700 according to the seventh configuration example of the fifth embodiment, for example, the C2C circuit (semiconductor circuits 1, 1A, 1B, and 1C) described in the above embodiment can be applied to the demodulator 743. <Achtes Konfigurationsbeispiel: Mikrocontroller>

[0221] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can be used for a microcontroller. As an example of such a microcontroller, a semiconductor device 800 according to an eighth configuration example of the fifth embodiment will be described below.

[0222] Fig. 28 is a block diagram illustrating an example of a configuration of the semiconductor device 800 (a microcontroller) according to the eighth configuration example of the fifth embodiment. As shown in Fig. 28, for example, the semiconductor device 800 includes a processor 801, a bus controller 802, a flash memory 803, a RAM 804, a DA converter circuit 805, an AD converter circuit 806, a timer 807, an input / output terminal 808, an oscillator 809, and an interrupt controller 810. The bus of the semiconductor device 800 is connected to the processor 801, the bus controller 802, the flash memory 803, the RAM 804, the DA converter circuit 805, the AD converter circuit 806, the timer 807, and the input / output terminal 808. The bus of the semiconductor device 800 is a signal and data transmission path in the semiconductor device 800.

[0223] Processor 801 performs various processes in semiconductor device 800. Processor 801 performs various processes with the supplied data. Processor 801 is, for example, a CPU.

[0224] The bus controller 802 controls the bus of the semiconductor device 800. The bus controller 802 may be provided in the processor 801.

[0225] Flash memory 803 is a storage device that can store data in a non-volatile manner. Flash memory 803 is, for example, a NOR flash memory. Flash memory 803 may be a NAND flash memory.

[0226] RAM 804 is a memory device that temporarily stores data. RAM 804 is, for example, a random access memory such as SRAM or DRAM.

[0227] The DA converter circuit 805 converts a digital signal (digital value) into an analog signal (analog value).

[0228] The AD converter circuit 806 converts an analog signal into a digital signal.

[0229] The timer 807 manages the time (operation time) in the semiconductor device 800.

[0230] The input / output terminal 808 functions as an interface circuit in the semiconductor device 800. The input / output terminal 808 includes, for example, four terminals P1, P2, P3, and P4. The number of terminals of the input / output terminal 808 may be three or fewer, but may also be five or more. The input / output terminal 808 receives a signal containing data, an address, or the like from the outside of the semiconductor device 800 through each of the terminals P1, P2, P3, and P4. The input / output terminal 808 transmits a signal such as data to the outside of the semiconductor device 800 through each of the terminals P1, P2, P3, and P4. The input / output terminal 808 conforms to, for example, the GPIO (General Purpose Input / Output) standard, the USART (Universal Synchronous / Asynchronous Receiver Transmitter) standard, the I2C (Inter-Integrated Circuit) standard, or similar standards.

[0231] Oscillator 809 outputs a clock signal as a synchronization signal to processor 801. The clock signal has a specific period (number of clocks). In this configuration, processor 801 performs various types of processing at a rate synchronized with the clock signal. The clock signal's frequency is, for example, 4 MHz, 8 MHz, 12 MHz, 24 MHz, or the like.

[0232] The interrupt controller 810 receives an external interrupt command. The interrupt controller 810 has, for example, a register for managing the status of interrupt requests. The interrupt controller 810 sends various interrupt requests to the processor 801 based on the received external interrupt command. In response to the interrupt request, the processor 801 temporarily interrupts the ongoing processing and executes the processing of the interrupt request. After completing the processing of the interrupt request, the processor 801 resumes the interrupted processing.

[0233] In the semiconductor device 800 according to the eighth configuration example of the fifth embodiment, the microcontroller 1C of the present embodiment may be a system on a chip (SoC), a system in package (SIP), or a system on package (SoP). The semiconductor device 800 is used, for example, in an embedded system. The semiconductor device 800 can be used, for example, for an in-vehicle device, a home electrical appliance, a computer, an industrial machine, a railway vehicle, an aircraft, a ship, and the like.

[0234] Furthermore, the semiconductor device 800 can be classified based on a bus width, a memory structure, an instruction set, etc. The bus width indicates a size of the data bus. For example, the semiconductor device 800 is classified into an 8-bit microcontroller, a 16-bit microcontroller, or a 32-bit microcontroller based on the bus width. The semiconductor device 800 can achieve better performance with a large bus width.

[0235] In the semiconductor device 800 according to the eighth configuration example of the fifth embodiment, for example, the CTLE circuit (semiconductor circuits 3, 3A, 3B, and 3C) described in the above embodiment can be applied to the input / output terminal 808. Further, in the semiconductor device 800 according to the eighth configuration example of the fifth embodiment, for example, the C2C circuit (semiconductor circuits 1, 1A, 1B, and 1C) described in the above embodiment can be applied to the processor 801. <5-2> Effects of the fifth embodiment

[0236] As the storage capacity of the NAND flash memory increases, the frequency of a signal transmitted and received between the semiconductor memory device and the memory controller increases, and data transmission of the signal transmission circuit in the input / output circuit 102 becomes difficult. For example, since the wiring length from the WDCA 113 to each data input circuit 114 is different, skew deviation may occur in each of the plurality of data input circuits 114 that receive the various DQ signals.

[0237] Therefore, in the first configuration example of the fifth embodiment, the input / output circuit 102 of the semiconductor device 100 (NAND flash memory) includes the C2C circuit described in the above embodiment. With this configuration, the input / output circuit 102 can reduce the gain near the DC current and suppress skew fluctuations for each data input circuit 114. As a result, the semiconductor device 100 according to the first configuration example of the fifth embodiment can use a high-frequency signal and realize high-speed transmission of data and the like with the memory controller 110.

[0238] Similar to the first configuration example of the fifth embodiment, the second to eighth configuration examples of the fifth embodiment can realize high-speed signal transmission by using at least one of the C2C circuit, differential amplifier circuit, and CTLE described in the first to fourth embodiments, that is, at least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C. <6> Miscellaneous

[0239] In this specification, the voltage at the "H" level corresponds to a voltage equal to or higher than a threshold when the data is determined in binary. The voltage at the "L" level corresponds to a voltage lower than a threshold when the data is determined in binary. In this specification, the "logic level" corresponds to either the "H" level or the "L" level. In this specification, "connection" means an electrical connection and does not exclude the possibility of, for example, another element being interposed. "Electrically coupled" can be via an insulator as long as it can function in the same way as the electrically coupled one.

[0240] In this specification, one end and the other end of the transistor correspond to a source or drain end of the transistor, respectively. In this specification, the "conductivity type" corresponds to "N-type" or "P-type." For example, the transistor of the first conductivity type corresponds to either the N-type transistor or the P-type transistor, and the transistor of the second conductivity type corresponds to the other of the N-type transistor or the P-type transistor. One end and the other end may be referred to as the "first end" and the "second end." The ground node VSS may be referred to as a power supply node. The input end and the output end of the constant current source CS correspond to one end and the other end of the current path of the constant current source CS, respectively.One end of the constant current source CS corresponds to one of the two ends, namely the input end and the output end, and the other end of the constant current source CS corresponds to the other end, namely the input end and the output end.

[0241] In the above embodiment, each of the constant current sources CS 10, CS 20, CS 30, and CS 31 includes, for example, an N-type MOS transistor. Each of the constant current sources CS 11, CS 12, CS 21, CS 32, and CS 33 includes, for example, a P-type MOS transistor. Note that the constant current source CS may include a plurality of transistors. For example, the constant current source CS may include a current mirror circuit including two transistors. In this case, each of the constant current sources CS 10, CS 20, CS 30, and CS 31 includes a current mirror circuit including an N-type MOS transistor, and each of the constant current sources CS 11, CS 12, CS 21, CS 32, and CS 33 includes a current mirror circuit including a P-type MOS transistor.

[0242] Fig. Figure 29 is a circuit diagram illustrating an example of a circuit configuration of a constant current source CS having an N-type transistor (hereinafter referred to as constant current source CSN). As shown in Fig. 29, the constant current source CSN includes, for example, the N-type transistors NM90 and NM91 and the nodes ND90 to ND92. A drain end and a gate end of the N-type transistor NM90 are connected to the node ND90. A drain end of the N-type transistor NM91 is coupled to the node ND91. A gate end of the N-type transistor NM91 is coupled to the node ND90. The source ends of the N-type transistors NM90 and NM91 are coupled to the node ND92. The node ND92 is connected, for example, to a ground node VSS. In the constant current source CSN, the voltage of the node ND90 is controlled so that the current flowing through the N-type transistor NM91 becomes constant. In other words, the input end of the constant current source CSN corresponds to node ND91. The output end of the constant current source CSN corresponds to node ND92.

[0243] Fig. 30 is a circuit diagram illustrating an example of a circuit configuration of a constant current source CS having a P-type transistor (hereinafter referred to as constant current source CSP). As shown in Fig.30, the constant current source CSP includes, for example, the P-type transistors PM90 and PM91 and the nodes ND93 to ND95. The node ND93 is connected to a power supply node VDD. The source ends of the P-type transistors PM90 and PM91 are coupled to the node ND93. A gate end and a drain end of the P-type transistor PM90 are coupled to the node ND94. A gate end of the P-type transistor PM91 is coupled to the node ND94. A drain end of the P-type transistor PM91 is connected to the node ND95. In the constant current source CSP, the voltage of the node ND94 is controlled so that the current flowing through the P-type transistor PM91 becomes constant. In other words, the input end of the constant current source CSP corresponds to the node ND93. An output end of the constant current source CSP corresponds to the node ND95.

[0244] In this specification, transistor sizes are compared based on gate width, e.g., in the case of planar MOSFETs. In this specification, transistor sizes are compared based on the number of laminations, e.g., in the case of a FinFET. In this specification, transistor sizes are compared based on the number of stacked layers of the nanosheet, which is a semiconductor layer, e.g., in the case of a nanosheet transistor.

[0245] In a FinFET, the gate electrode faces two or more surfaces of the channel region. The channel region has a convex shape formed on the surface of the semiconductor substrate, and the convex semiconductor region is called a fin. A transistor can have a plurality of fins. If the number of fins in one transistor is smaller than the number of fins in the other transistors, one transistor is smaller than the other transistors. For example, in a case where the ratio between the size of one transistor (e.g., the P-type transistor PM12) and the size of the other transistor (e.g., the P-type transistor PM10) is 1:1, 2:7, or 3:1. If the number of fins in one transistor is one, the number of fins in the other transistor is two:7. If the number of fins in one transistor is two, the number of fins in the other transistor is three:14.

[0246] In the nanosheet, the gate electrodes face each other so that they enclose the channel region. The channel region is formed in a flat, plate-shaped semiconductor layer (nanosheet). Multiple flat, plate-shaped semiconductor layers can be stacked separately. If the number of semiconductor layers in a transistor is smaller than the number of semiconductor layers in the other transistors, one transistor will be smaller than the other transistors. In a case where the ratio of the size of one transistor (e.g., the P-type transistor PM12) to the size of the other transistor (e.g., the P-type transistor PM10) is 1:1, 2:7, for example,, when the semiconductor layer of one transistor is one layer, the semiconductor layer of the other transistor is two to seven layers, and when the semiconductor layer of one transistor is two layers, the number of stacked semiconductor layers of the other transistor is three to fourteen layers.

[0247] In this specification, "NMOS base" means that a transistor that receives an input signal is an N-type transistor. "PMOS base" means that the transistor that receives the input signal is a P-type transistor. Current Mode Logic (CML) is a circuit that transmits a small analog signal. CMOS stands for CMOS inverter and is a circuit that transmits a large digital signal. The C2C circuit corresponds to a circuit that converts a small analog signal into a large digital signal. A fixed pattern in which the signal is continuously at the "L" level or a pattern in which the signal is continuously at the "H" level can be regarded as a DC signal.

[0248] Although some embodiments of the present invention have been described, these embodiments have been presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included within the spirit and scope of the invention and are included within the invention described in the claims and the corresponding scope thereof. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 2021 / 0343328 A

[0003]

Claims

[1] Semiconductor circuit comprising: first to third transistors of a first conduction type; first and second transistors of a second conductivity type; and a constant current source, where one end and another end of the first transistor of the first conductivity type are coupled to a first power supply node and a first node, respectively, and a gate end of the first transistor of the first conductivity type is coupled to the first node via a resistor, one end and another end of the second transistor of the first conductivity type are coupled to the first power supply node and a second node, respectively, the second node is coupled to an output node, and a gate end of the second transistor of the first conductivity type is coupled to the first node, one end and another end of the first transistor of the second conductivity type are coupled to the first node and a third node, respectively, and a gate end of the first transistor of the second conductivity type is coupled to a first input node, one end and another end of the second transistor of the second conductivity type are coupled to the second node and the third node, respectively, and a gate end of the second transistor of the second conductivity type is coupled to a second input node, one end and another end of the constant current source are coupled to the third node and a second power supply node, respectively, and one end and another end of the third transistor of the first conductivity type are coupled to the first power supply node and the second input node, respectively, and a gate end of the third transistor of the first conductivity type is coupled to a gate end of the first transistor of the first conductivity type. [2] A semiconductor circuit according to claim 1, wherein the first line type is a P-type, the second line type is an N-type, and a voltage higher than a voltage of the second power supply node is applied to the first power supply node. [3] Semiconductor circuit according to claim 1, wherein the first line type is an N-type, the second conduction type is a P-type, and a voltage lower than a voltage of the second power supply node is applied to the first power supply node. [4] Semiconductor circuit according to claim 1, further comprising fourth to sixth transistors of the first conduction type, where one end and another end of the fourth transistor of the first conductivity type are coupled to the first power supply node and the second input node, respectively, and a gate end of the fourth transistor of the first conductivity type is coupled to the gate end of the first transistor of the first conductivity type, the fifth transistor of the first conduction type is coupled between the first power supply node and the third transistor of the first conduction type, the sixth transistor of the first conduction type is coupled between the first power supply node and the fourth transistor of the first conduction type, and different control signals are input to a gate end of the fifth transistor of the first conductivity type and to a gate end of the sixth transistor of the first conductivity type. [5] A semiconductor circuit according to claim 1, wherein the third transistor of the first conductivity type is smaller than the first transistor of the first conductivity type. [6] Semiconductor circuit according to claim 1, wherein a first clock signal is input to the first input node, and a second clock signal, which is an inverted signal of the first clock signal, is input to the second input node. [7] A semiconductor device comprising: a data input circuit including the semiconductor circuit according to claim 6; a first pad connected to the data input circuit and receiving a first signal from the outside; a second pad that receives a second signal from outside; a third pad that receives a third signal from outside; an amplifier circuit that generates the first clock signal based on the second signal and the third signal; and a processing circuit that processes the data output by the data input circuit, wherein the data input circuit samples the first signal based on the first clock signal and outputs sampled data to the processing circuit. [8] A semiconductor device according to claim 7, wherein the data input circuit includes a converter circuit which converts the first clock signal amplified by the semiconductor circuit into a CMOS level, a continuous-time linear equalizer that compensates and outputs the first signal, and a sampler that samples an output signal of the continuous-time linear equalizer based on the first clock signal converted into the CMOS level by the conversion circuit and outputs sampled data to the processing circuit. [9] Semiconductor circuit comprising: first to fourth transistors of a first conductivity type; first and second transistors of a second conductivity type; and a constant current source, where one end and another end of the first transistor of the first conductivity type are coupled to a first power supply node and a first node, respectively, a gate end of the first transistor of the first conductivity type is coupled to the first node via a first resistor, and the first node is coupled to a first output node, one end and another end of the second transistor of the first conductivity type are coupled to the first power supply node and a second node, respectively, a gate end of the second transistor of the first conductivity type is coupled to the second node via a second resistor different from the first resistor, and the second node is coupled to a second output node, one end and another end of the first transistor of the second conductivity type are coupled to the first node and a third node, respectively, and a gate end of the first transistor of the second conductivity type is coupled to a first input node, one end and another end of the second transistor of the second conductivity type are coupled to the second node and the third node, respectively, and a gate end of the second transistor of the second conductivity type is coupled to a second input node, one end and another end of the constant current source are coupled to the third node and a second power supply node, respectively, one end and another end of the third transistor of the first conductivity type are coupled to the first power supply node and the second input node, respectively, and a gate end of the third transistor of the first conductivity type is coupled to the gate end of the first transistor of the first conductivity type, and one end and another end of the fourth transistor of the first conductivity type are coupled to the first power supply node and the first input node, respectively, and a gate end of the fourth transistor of the first conductivity type is coupled to the gate end of the second transistor of the first conductivity type. [10] Semiconductor circuit according to claim 9, wherein the first line type is a P-type, the second line type is an N-type, and a voltage higher than a voltage of the second power supply node is applied to the first power supply node. [11] Semiconductor circuit according to claim 9, wherein the first line type is an N-type, the second conduction type is a P-type, and a voltage lower than a voltage of the second power supply node is applied to the first power supply node. [12] Semiconductor circuit according to claim 9, further comprising fifth to seventh transistors of the first conduction type, where one end and another end of the fifth transistor of the first conductivity type are coupled to the first power supply node and the second input node, respectively, and a gate end of the fifth transistor of the first conductivity type is coupled to the gate end of the first transistor of the first conductivity type, the sixth transistor of the first conduction type is coupled between the first power supply node and the third transistor of the first conduction type, the seventh transistor of the first conduction type is coupled between the first power supply node and the fifth transistor of the first conduction type, and different control signals are input to a gate end of the sixth transistor of the first conductivity type and to a gate end of the seventh transistor of the first conductivity type. [13] Semiconductor circuit according to claim 12, further comprising eighth to tenth transistors of the first conduction type, where one end and another end of the eighth transistor of the first conductivity type are coupled to the first power supply node and the first input node, respectively, and a gate end of the eighth transistor of the first conductivity type is coupled to the gate end of the second transistor of the first conductivity type, the ninth transistor of the first conduction type is coupled between the first power supply node and the fourth transistor of the first conduction type, the tenth transistor of the first conduction type is coupled between the first power supply node and the eighth transistor of the first conduction type, and different control signals are input to a gate end of the ninth transistor of the first conductivity type and to a gate end of the tenth transistor of the first conductivity type. [14] Semiconductor circuit comprising: first and second transistors of a first conductivity type; first and second transistors of a second conductivity type; first to third resistances; a capacitor; and a first and a second constant current source, wherein the first resistor is coupled between a first power supply node and a first node, and the first node is coupled to a first output node, the second resistor is coupled between the first power supply node and a second node, and the second node is coupled to a second output node, one end and another end of the first transistor of the second conductivity type are coupled to the first node and a third node, respectively, and a gate end of the first transistor of the second conductivity type is coupled to a first input node, one end and another end of the second transistor of the second conductivity type are coupled to the second node and a fourth node, respectively, and a gate end of the second transistor of the second conductivity type is coupled to a second input node, one end and another end of the first constant current source are respectively coupled to the third node and a second power supply node, one end and another end of the second constant current source are respectively coupled to the fourth node and the second power supply node, the third resistor and the capacitor are coupled in parallel between the third and fourth nodes, one end and another end of the first transistor of the first conductivity type are coupled to the first power supply node and the second input node, respectively, and a gate end of the first transistor of the first conductivity type is coupled to the first node, and one end and another end of the second transistor of the first conductivity type are coupled to the first power supply node and the first input node, respectively, and a gate end of the second transistor of the first conductivity type is coupled to the second node. [15] Semiconductor circuit according to claim 14, wherein the first line type is a P-type, the second line type is an N-type, and a voltage higher than a voltage of the second power supply node is applied to the first power supply node. [16] Semiconductor circuit according to claim 14, wherein the first line type is an N-type, the second conduction type is a P-type, and a voltage lower than a voltage of the second power supply node is applied to the first power supply node. [17] Semiconductor circuit according to claim 14, further comprising third to fifth transistors of the first conduction type, where one end and another end of the third transistor of the first conductivity type are coupled to the first power supply node and the second input node, respectively, and a gate end of the third transistor of the first conductivity type is coupled to the gate end of the first transistor of the first conductivity type, the fourth transistor of the first conduction type is coupled between the first power supply node and the first transistor of the first conduction type, the fifth transistor of the first conduction type is coupled between the first power supply node and the third transistor of the first conduction type, and different control signals are input to a gate end of the fourth transistor of the first conductivity type and to a gate end of the fifth transistor of the first conductivity type. [18] Semiconductor circuit according to claim 17, further comprising sixth to eighth transistors of the first conduction type, where one end and another end of the sixth transistor of the first conductivity type are coupled to the first power supply node and the first input node, respectively, and a gate end of the sixth transistor of the first conductivity type is coupled to the gate end of the second transistor of the first conductivity type, the seventh transistor of the first conduction type is coupled between the first power supply node and the second transistor of the first conduction type, the eighth transistor of the first conduction type is coupled between the first power supply node and the sixth transistor of the first conduction type, and different control signals are input to a gate end of the seventh transistor of the first conductivity type and to a gate end of the eighth transistor of the first conductivity type. [19] A semiconductor device comprising: a data input circuit including the semiconductor circuit according to claim 14; a first pad connected to the first input node and receiving a first signal from the outside; a second pad that receives a second signal from outside; a third pad that receives a third signal from outside; an amplifier circuit that generates a clock signal based on the second signal and the third signal; and a processing circuit that processes the data output by the data input circuit, wherein the data input circuit includes a sampler that samples an output signal of the semiconductor circuit generated on the basis of the first signal based on the clock signal and outputs sampled data to the processing circuit. [20] A semiconductor device according to claim 19, wherein the data input circuit contains a plurality of semiconductor circuits, and the plurality of semiconductor circuits are coupled in series between the first pad and the scanner.

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