Hardmask structure for the production of integrated circuits and method for producing an integrated circuit

Abstract

The present disclosure provides a hard mask structure for integrated circuit fabrication and a method for fabricating an integrated circuit related to a field of pattern transfer technology in a chip manufacturing process.The hard mask structure includes a first hard mask layer and a second hard mask layer stacked from top to bottom, the first hard mask layer being used to form a noble metal on a surface thereof and being used as a pattern transfer sacrificial layer, and the second hard mask layer being used as a protective layer and being used to etch a pattern transfer target material; the first hard mask layer and the second hard mask layer being made of different materials and being resistant to the etching of a highly oxidizing chemical liquid applied to remove the noble metal; the second hard mask layer being resistant to the etching of a chemical liquid applied to remove the first hard mask layer by wet corrosion, and the second hard mask layer having a predetermined corrosion rate selectivity ratio to the first hard mask layer.The present disclosure can prevent damage to the devices by noble metal ions, so that noble metal layers can be used in the manufacture of integrated circuits on a large scale.

Description

TECHNICAL FIELDThe present disclosure relates to a field of pattern transfer technology (pattern transfer technology) in a chip manufacturing process, and more particularly to a hard mask pattern for integrated circuit manufacturing and a method of manufacturing an integrated circuit.BACKGROUNDNoble metals have excellent chemical stability and do not warp in pattern transfer, especially in fine patterns. Therefore, a noble metal layer is an ideal hard mask material for pattern transfer.However, noble metal ions may degrade integrated circuit performance, and thus noble metals are not used in integrated circuit fabrication. At present, noble metals are used as hard masks only in a region of chip manufacture that is insensitive to noble metal ions, e.g., in the manufacture of non-volatile magnetic random access memories (MRAM).SUMMARYIn view of the above problems, the present disclosure provides a hard mask pattern for integrated circuit fabrication and a method of manufacturing an integrated circuit, so that noble metal layers can be used for large-scale integrated circuit fabrication.In one aspect, the present disclosure provides a hard mask pattern for integrated circuit manufacturing, including a first hard mask layer and a second hard mask layer stacked from top to bottom, wherein: the first hard mask layer is formed to form a noble metal on a surface thereof and formed as a pattern transfer sacrificial layer, and the second hard mask layer is formed as a protective layer and formed to etch a pattern transfer target material; the first hard mask layer and the second hard mask layer are made of different materials and are resistant to corrosion of a highly oxidizing chemical liquid applied to remove the noble metal; the second hard mask layer is resistant to corrosion by a chemical liquid deposited to remove the first hard mask layer by wet corrosion, and the second hard mask layer has a predetermined corrosion rate selectivity ratio to the first hard mask layer; and the noble metal includes a thin film or a combination of thin films selected from gold, silver, ruthenium, rhodium, palladium, osmium, iridium, or platinum.Optionally, the first hard mask layer and the second hard mask layer form a dual hard mask set, and the hard mask pattern includes a plurality of dual hard mask sets stacked in sequence.Optionally, the first hard mask layer is made of a non-metallic dielectric material selected from at least one of the following materials: silicon, silicon oxide, silicon nitride, polysilicon, amorphous silicon, silicon oxynitride, silicon oxide doped with boron or phosphorus, silicon carbide, gallium nitride, indium phosphide, aluminum oxide or titanium nitride; or the first hard mask layer is made of an organic material selected from a spin-on-carbon layer, an amorphous carbon layer, a silicon-rich antireflection layer or a carbon-rich antireflection layer.Optionally, the second hard mask layer is made of a non-metallic dielectric material selected from at least one of the following materials: silicon, silicon oxide, silicon nitride, polysilicon, amorphous silicon, silicon oxynitride, silicon oxide doped with boron or phosphorus, silicon carbide, gallium nitride, indium phosphide, aluminum oxide or titanium nitride; or the second hard mask layer is made of an organic material selected from a spin-on-carbon layer, an amorphous carbon layer, a silicon-rich antireflection layer or a carbon-rich antireflection layer.Optionally, the strong oxidizing chemical liquid contains aqua regia; or the strong oxidizing chemical liquid contains high purity HCl, high purity HNO 3 and H 2 O in a ratio of (0~1):(0~1):(0~1).Optionally, the first hard mask layer and the second hard mask layer are a combination of two thin films of different materials selected from: the first hard mask layer is made of Si 3 N 4 and the second hard mask layer is made of SiO 2; the first hard mask layer is a silicon-rich antireflection layer, and the second hard mask layer is a spin-on-carbon layer; or the first hard mask layer is made of polysilicon and the second hard mask layer is made of SiO 2.Another aspect of the present disclosure is a method of manufacturing an integrated circuit using the hard mask pattern for integrated circuit manufacturing as described above, including forming a second hard mask layer, a first hard mask layer, and a noble metal layer sequentially on a pattern transfer target material, coating a surface of the noble metal layer with a resist, and performing photolithography to form a mask pattern; performing ion etching on the noble metal layer and performing ion etching or reactive ion etching on the first hard mask layer to transfer the mask pattern to a surface of the second hard mask layer; removing the noble metal layer by corrosion and performing ion etching or reactive ion etching on the second hard mask layer to transfer the mask pattern to a surface of the pattern transfer target material; removing the first hard mask layer by corrosion and etching the pattern transfer target material according to the mask pattern; and removing the second hard mask layer by corrosion and cleaning an etched product to obtain a desired integrated circuit.Optionally, the method of manufacturing the integrated circuit further includes: after performing the reactive ion etching on the first hard mask layer, removing the photoresist.Optionally, the removing of the first hard mask layer by corrosion includes any selection of: removing the first hard mask layer by corrosion with H 3 PO 4 at 160° C. if the first hard mask layer is made of Si 3 N 4 and the second hard mask layer is made of SiO 2 ; removing the first hard mask layer by corrosion with dilute hydrofluoric acid at room temperature if the first hard mask layer is a silicon-rich antireflection layer and the second hard mask layer is a spin-on-carbon layer; or removing the first hard mask layer by corrosion with tetramethylammonium hydroxide at room temperature if the first hard mask layer is made of polysilicon and the second hard mask layer is made of SiO 2.Optionally, a corrosion rate of less than 1 nm / min is when removing the first hard mask layer by corrosion.Compared with the related art, the hard mask pattern for integrated circuit manufacturing and the method for manufacturing the integrated circuits provided by the present disclosure have at least the following advantageous effects.(1) Damage to devices by noble metal ions can be avoided, so that noble metal films can be used in large-scale integrated circuit fabrication.(2) The dual hard mask pattern is resistant to corrosion with a highly oxidizing chemical liquid applied to remove the noble metal, i.e., the material of the dual hard mask remains intact during wet corrosion with a strong acid without morphological deformation, while accurate pattern transfer is guaranteed. The dual hard mask pattern, which is made of at least two layers of different materials, can protect the pattern transfer target material from contamination by noble metal ions.BRIEF DESCRIPTION OF THE DRAWINGSThe above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which: FIG. 1 schematically illustrates a process flow diagram of a hard mask pattern for integrated circuit fabrication according to embodiments of the present disclosure; and FIG. 2 schematically illustrates a flow diagram of a method of manufacturing an integrated circuit according to embodiments of the present disclosure.[Description of Reference Numerals]1-pattern transfer target material; 2-second hard mask layer; 3-first hard mask layer; 4-noble metal layer; 5-resist; 6-mask pattern.DETAILED DESCRIPTION OF THE EMBODIMENTSIn order to better understand the objects, technical solutions, and advantages of the present disclosure, the present disclosure will be described below in combination with specific embodiments and with reference to the accompanying drawings. It should be understood that the described embodiments are only some embodiments and not all embodiments of the present disclosure. Starting from the embodiments of the present disclosure, all additional embodiments obtained by a person of ordinary skill in the art without inventive effort fall within the scope of protection of the present disclosure.The terms used herein are used to describe certain embodiments only and are not intended to limit the present disclosure. As used herein, the terms "including", "including", etc. indicate the presence of the feature, step, operation, and / or component, but do not preclude the presence or addition of one or more other features, steps, operations, or components.All terms (including technical and scientific terms) used herein have the meaning commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted as having a meaning that is consistent with the context of this specification and are not to be interpreted in an idealized or overly rigid manner.FIG. 1 schematically illustrates a process flow diagram of a hard mask pattern for integrated circuit fabrication according to embodiments of the present disclosure.Referring to FIG. 1, embodiments of the present disclosure provide a hard mask pattern for integrated circuit fabrication, including a first hard mask layer 3 and a second hard mask layer 2 stacked from top to bottom.The first hard mask layer 3 serves to form a noble metal 4 on one surface thereof and is used as a pattern transfer sacrificial layer. The noble metal comprises a thin film or a combination of thin films selected from gold, silver, ruthenium, rhodium, palladium, osmium, iridium or platinum. The second hard mask layer 2 serves as a protection layer and is used for etching a pattern transfer target material 1.The first hard mask layer 3 and the second hard mask layer 2 are made of different materials and are both resistant to corrosion by a strongly oxidizing chemical liquid applied to remove the noble metal.The second hard mask layer 2 is resistant to corrosion by a chemical liquid applied by wet corrosion to remove the first hard mask layer 3, and the second hard mask layer 2 has a predetermined corrosion rate selectivity ratio to the first hard mask layer 3.With the above-mentioned structure, the hard mask pattern can prevent damage of devices by noble metal ions, so that noble metal layers can be used in large-scale integrated circuit manufacturing. Moreover, the hard mask pattern is resistant to corrosion of a highly oxidizing chemical liquid used to remove the noble metal, i.e., a dual hard mask material remains intact without morphological deformation during wet corrosion with a strong acid, while ensuring accurate pattern transfer. The dual hard mask pattern, which is made of at least two layers of different materials, may protect the pattern transfer target material from contamination by noble metal ions.Note that the corrosion rate selectivity ratio may be set according to actual needs as long as the second hard mask layer 2 has a high corrosion rate selectivity ratio to the first hard mask layer 3.In embodiments of the present disclosure, the first hard mask layer 3 and the second hard mask layer 2 form a dual hard mask set, and the hard mask pattern includes a plurality of dual hard mask sets stacked in sequence. Therefore, the hard mask pattern is made of at least two layers of different materials, both of which are resistant to corrosion of the highly oxidizing chemical liquid. Depending on the requirements of pattern transfer, film layers of various materials may be added based on the principles mentioned above to form a three or four layer dual hard mask structure.In embodiments of the present disclosure, the first hard mask layer 3 may be made of a non-metallic dielectric material including, but not limited to, at least one of silicon, silicon oxide, silicon nitride, polysilicon, amorphous silicon, silicon oxynitride, silicon oxide doped with boron (B) or phosphorus (P), silicon carbide, gallium nitride, indium phosphide, aluminum oxide, or titanium nitride. Alternatively, the first hard mask layer 3 may also be made of an organic material including, but not limited to, a spin-on-carbon (SOC) layer, an amorphous carbon layer, a silicon-rich antireflection layer (SiBAC), or a carbon-rich antireflection layer (BARC).The first hard mask layer 3 and the second hard mask layer 2 are made of different materials. Based thereon, the second hard mask layer 2 may be made of a non-metallic dielectric material including, but not limited to, at least one of silicon, silicon oxide, silicon nitride, polysilicon, amorphous silicon, silicon oxynitride, silicon oxide doped with boron (B) or phosphorus (P), silicon carbide, gallium nitride, indium phosphide, aluminum oxide, or titanium nitride. Alternatively, the second hard mask layer 2 may also be made of an organic material including, but not limited to, a spin-on-carbon (SOC) layer, an amorphous carbon layer, a silicon-rich antireflection layer (SiBAC), or a carbon-rich antireflection layer (BARC).In embodiments of the present disclosure, the strong oxidizing chemical liquid contains aqua regia; or the strong oxidizing chemical liquid contains high purity hydrochloric acid (HCl), high purity nitric acid (HNO 3) and water (H 2 O) in a ratio of (0~1):(0~1):(0~1).Accordingly, the strongly oxidizing chemical liquid used for removing the noble metal is primarily an aqua regia-like liquid in which the ratio of high purity HCl, high purity HNO 3 and H 2 O (0~1):(0~1):(0~1) is. In addition, both the first hard mask layer 3 and the second hard mask layer 2 are resistant to the aqua regia-like strong oxidizing chemical liquid, and the corrosion rate is less than 1 nm / min.In embodiments of the present disclosure, the first hard mask layer 3 and the second hard mask layer 2 are a combination of two thin films made of different materials selected from wherein the first hard mask layer 3 is made of Si 3 N 4 and the second hard mask layer 2 is made of SiO 2 ; wherein the first hard mask layer 3 is a silicon-rich antireflection layer (SiBAC), and the second hard mask layer 2 is a spin-on-carbon (SOC) layer; or wherein the first hard mask layer 3 is made of poly-Si (polysilicon) and the second hard mask layer 2 is made of SiO 2.The first hard mask layer 3 is used as a pattern transfer sacrificial layer. After the mask pattern is formed with the noble metal, the layer of noble metal is removed. Subsequently, the first hard mask layer 3 is used to transfer the mask pattern to the second hard mask layer 2, and then the first hard mask layer 3 is removed, thereby avoiding residual noble metal ions in the first hard mask layer 3 and reducing a trace amount of noble metal ions on the wafer surface to an applicable level. In this method, the second hard mask layer 2 functions as a protection layer for protecting the pattern transfer target material from corrosion by the highly oxidizing chemical liquid applied to remove the noble metal and protecting a surface of the pattern transfer target material from contamination by noble metal ions.After completion of the above-mentioned process, the pattern transfer target material is etched with the second hard mask layer 2. Thereafter, the second hard mask layer 2 is removed to obtain the desired fine final pattern.FIG. 2 schematically illustrates a flow diagram of a method of manufacturing an integrated circuit according to embodiments of the present disclosure.Referring to FIGS. 1 and 2, the method of manufacturing the integrated circuit according to the embodiments may include operations S 210 to S 250.In operation S 210, a second hard mask layer 2, a first hard mask layer 3, and a noble metal layer 4 are sequentially formed on a pattern transfer target material, a resist 5 is applied to a surface of the noble metal layer 4, and photolithography for forming a mask pattern is performed.In operation S220, ion etching (IBE) is performed on the noble metal layer 4 and ion etching or reactive ion etching is performed on the first hard mask layer 3 to transfer the mask pattern to a surface of the second hard mask layer 2.Optionally, the method may also include removing the photoresist 5 after the reactive ion etching of the first hard mask layer 3.In operation S 230, the noble metal layer 4 is removed by corrosion, and the second hard mask layer 2 is processed by ion milling or reactive ion milling so that the mask pattern is transferred to a surface of the pattern transfer target material.In operation S 240, the first hard mask layer 3 is removed by corrosion, and the pattern transfer target material is etched according to the mask pattern.In operation S 250, the second hard mask layer 2 is removed by corrosion, and an etched product is cleaned to obtain a desired integrated circuit.For example, when the first hard mask layer 3 is made of Si 3 N 4 and the second hard mask layer 2 is made of SiO 2 both resist a highly corrosive chemical liquid similar to aqua regia. In this case, the first hard mask layer 3, i.e., Si 3 N 4, may be removed by corrosion with H 3 PO 4 at 160° C., while SiO 2 has a very slow corrosion rate in this environment and may not be damaged.If the first hard mask layer 3 is, for example, a silicon-rich antireflection layer (SiBAC) and the second hard mask layer 2 is a spin-on-carbon (SOC) layer, both resist a highly corrosive chemical liquid similar to aqua regia. In this case, the first hard mask layer 3 may be removed by corrosion with dilute hydrofluoric acid (HF) at room temperature, while SOC in this environment has a very slow corrosion rate and cannot be damaged.For example, when the first hard mask layer 3 is made of poly Si (polysilicon) and the second hard mask layer 2 is made of SiO 2 both resist a highly corrosive chemical liquid similar to aqua regia. In this case, poly Si can be removed by corrosion with TMAH (tetramethylammonium hydroxide) at room temperature, while SiO 2 is not substantially corroded in this environment.In embodiments of the present disclosure, the corrosion rate in a method of removing the first hard mask layer 3 by corrosion is less than 1 nm / min.Embodiments of the present disclosure may achieve a precise pattern transfer structure and avoid damage to noble metal ions on devices, so that noble metal layers may be used for large-scale integrated circuit fabrication.Moreover, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative meaning or implicitly the set of technical features stated. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more such features. In the description of the present disclosure, "multiple" means at least two, e.g., two, three, etc., unless clearly and specifically defined otherwise. Moreover, the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.The specific embodiments described above illustrate the objects, technical solutions, and advantageous effects of the present disclosure. It should be understood that the above embodiments are only specific embodiments of the present disclosure and are not intended to limit the present disclosure. All changes, equivalents, improvements, etc., made within the spirit and principles of the present disclosure should be included within the scope of the present disclosure.

Claims

A hard mask pattern for integrated circuit manufacturing, comprising a first hard mask layer and a second hard mask layer stacked from top to bottom, wherein the first hard mask layer is formed so that a noble metal can be formed on its surface and is formed as a pattern transfer sacrificial layer, and the second hard mask layer is formed as a protective layer and is formed to etch a pattern transfer target material; wherein the first hard mask layer and the second hard mask layer are made of different materials and are resistant to corrosion by a highly oxidizing chemical liquid applied to remove the noble metal; wherein the second hard mask layer is resistant to corrosion by a chemical liquid applied to remove the first hard mask layer by wet corrosion, and the second hard mask layer has a predetermined corrosion rate selectivity ratio to the first hard mask layer; and wherein the noble metal comprises a thin film or a combination of thin films selected from gold, silver, ruthenium, rhodium, palladium, osmium, iridium or platinum.The hard mask pattern for integrated circuit fabrication of claim 1, wherein the first hard mask layer and the second hard mask layer form a dual hard mask set, and the hard mask pattern includes a plurality of dual hard mask sets stacked in sequence.The hard mask structure for integrated circuit fabrication of claim 1, wherein the first hard mask layer is made of a non-metallic dielectric material selected from at least one of silicon, silicon oxide, silicon nitride, polysilicon, amorphous silicon, silicon oxynitride, silicon oxide doped with boron or phosphorous, silicon carbide, gallium nitride, indium phosphide, aluminum oxide, or titanium nitride; or wherein the first hard mask layer is made of an organic material selected from a spin-on-carbon layer, an amorphous carbon layer, a silicon-rich anti-reflection layer, or a carbon-rich anti-reflection layer.The hard mask structure for integrated circuit fabrication of claim 1, wherein the second hard mask layer is made of a non-metallic dielectric material selected from at least one of silicon, silicon oxide, silicon nitride, polysilicon, amorphous silicon, silicon oxynitride, silicon oxide doped with boron or phosphorous, silicon carbide, gallium nitride, indium phosphide, aluminum oxide, or titanium nitride; or wherein the second hard mask layer is made of an organic material selected from a spin-on-carbon layer, an amorphous carbon layer, a silicon-rich anti-reflection layer, or a carbon-rich anti-reflection layer.The hard mask structure for integrated circuit fabrication according to claim 1, wherein the strong oxidizing chemical liquid comprises aqua regia; or wherein the strong oxidizing chemical liquid contains high purity HCl, high purity HNO 3 and H 2 O in a ratio of (0~1):(0~1):(0~1).The hard mask structure for integrated circuit fabrication of claim 1, wherein the first hard mask layer and the second hard mask layer are a combination of two thin films of different materials selected from: wherein the first hard mask layer is made of Si 3 N 4 and the second hard mask layer is made of SiO 2 ; the first hard mask layer is a silicon-rich anti-reflection layer and the second hard mask layer is a spin-on-carbon layer; or wherein the first hard mask layer is made of polysilicon and the second hard mask layer is made of SiO 2.A method of manufacturing an integrated circuit device using the hard mask pattern for integrated circuit manufacturing according to claim 1, comprising: forming a second hard mask layer, a first hard mask layer, and a noble metal layer sequentially on a pattern transfer target material, coating a surface of the noble metal layer with a resist, and performing photolithography to form a mask pattern; performing ion etching on the noble metal layer and performing ion etching or reactive ion etching on the first hard mask layer to transfer the mask pattern to a surface of the second hard mask layer; removing the noble metal layer by corrosion and performing ion etching or reactive ion etching on the second hard mask layer to transfer the mask pattern to a surface of the pattern transfer target material; removing the first hard mask layer by corrosion and etching the pattern transfer target material corresponding to the mask pattern; and removing the second hard mask layer by corrosion and cleaning an etched product to obtain a desired integrated circuit.The method of manufacturing the integrated circuit of claim 7, further comprising: after performing the reactive ion etching on the first hard mask layer, removing the photoresist.The method of manufacturing the integrated circuit device of claim 7, wherein the removing the first hard mask layer by corrosion comprises any one of: removing the first hard mask layer by corrosion with H 3 PO 4 at 160°C if the first hard mask layer is made of Si 3 N 4 and the second hard mask layer is made of SiO 2 ; removing the first hard mask layer by corrosion with dilute hydrofluoric acid at room temperature if the first hard mask layer is a silicon-rich anti-reflection layer and the second hard mask layer is a spin-on carbon layer; or removing the first hard mask layer by corrosion with tetramethylammonium hydroxide at room temperature if the first hard mask layer is made of polysilicon and the second hard mask layer is made of SiO 2.The method for manufacturing the integrated circuit according to claim 7, wherein the corrosion rate is less than 1 nm / min when the first hard mask layer is removed by corrosion.

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