Semiconductor device and method for manufacturing a semiconductor device

Abstract

A semiconductor device according to the present disclosure comprises a semiconductor chip, a metal block having a first surface and a second surface opposite the first surface, wherein the first surface is bonded to the semiconductor chip with a bonding material, and a conduction electrode bonded to the second surface of the metal block, wherein a plurality of irregularities are formed on a surface of the conduction electrode opposite a surface of the same that is bonded to the metal block.

Description

Area

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. background

[0002] Patent document 1 discloses a structure in which a contact point sub-area and a conductive spacer are bonded in a semiconductor device. The bonding of the contact point sub-area and the spacer is carried out, for example, by ultrasonic bonding. List of literature on patent literature

[0003] [PTL1] WO 2020 / 105476 Summary Technical Problem

[0004] In a semiconductor device, such as a power semiconductor device, a semiconductor chip and a wiring component, such as a conduction electrode, can be bonded. One method of bonding the conduction electrode and the semiconductor chip involves, for example, discharging molten metal onto a major surface of the semiconductor chip. Another method involves placing a bonding material and conduction electrodes onto a semiconductor chip that has been pre-bonded to a circuit structure on an insulating substrate and then remelting them. In such a bonding method, the bonding area is larger than in a method of forming a circuit by bonding a metal wire and a semiconductor chip. Therefore, a high current and a long lifetime can be expected.

[0005] However, in the aforementioned method, it is necessary to heat the entire semiconductor device during the bonding step between the conduction electrode and the top surface of the semiconductor chip. Therefore, the bonding material of the bonding area between the semiconductor chip and the insulating substrate, which was previously bonded, may be remelted. At this time, it may be necessary to re-examine the bonding area on the back surface of the semiconductor chip. Furthermore, if a solder is used as a bonding material between the back surface of the semiconductor chip and the insulating substrate, a problem arises: the back surface electrode of the semiconductor chip can diffuse into the solder, reducing the bond strength.

[0006] On the other hand, to avoid the problem described above, it is considered that the semiconductor chip and the conduction electrode are bonded by applying an ultrasonic vibration; that is, ultrasonic bonding is performed. However, if the top surface of the semiconductor chip is used as a target area for the ultrasonic bonding, the semiconductor chip can be damaged, and thus a problem arose in that ultrasonic bonding could not be applied.

[0007] One objective of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device which can prevent damage to a semiconductor chip during ultrasonic bonding. Solution to the problem

[0008] A semiconductor device according to the present disclosure comprises a semiconductor chip; a metal block having a first surface and a second surface opposite the first surface, wherein the first surface is bonded to the semiconductor chip with a bonding material; and a conduction electrode bonded to the second surface of the metal block; wherein a plurality of irregularities are formed on a surface of the conduction electrode opposite a surface thereof that is bonded to the metal block.

[0009] A method for manufacturing a semiconductor device according to the present disclosure comprises, after bonding a semiconductor chip to a first surface of a metal block having the first surface and a second surface opposite the first surface, with a bonding material, applying an ultrasonic vibration from a surface of a conduction electrode opposite the metal block to bond the second surface of the metal block to the conduction electrode with ultrasound. Advantageous effects of the invention

[0010] In the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure, the metal block and the conduction electrode are bonded together using ultrasound, thus making it possible to prevent damage to the semiconductor chip during the ultrasonic bonding. Brief description of the drawings Fig. Figure 1 is a cross-sectional view of a semiconductor device according to a first embodiment. Fig. Figure 2 is a top view of the semiconductor device according to the first embodiment. Fig. Figure 3 is a view to explain another example of ultrasound bonding markers. Fig. Figure 4 is a cross-sectional view of a semiconductor device according to a second embodiment. Fig. Figure 5 is a cross-sectional view of a semiconductor device according to a third embodiment. Fig. Figure 6 is a cross-sectional view of a semiconductor device according to a fourth embodiment. Fig. Figure 7 is a cross-sectional view of a semiconductor device according to a fifth embodiment. Description of the embodiments

[0011] A semiconductor device and a method for manufacturing a semiconductor device according to each embodiment are described with reference to the drawings. Identical or corresponding components are assigned the same reference numerals, and the repeated description of such components may be omitted. First embodiment

[0012] Fig. Figure 1 is a cross-sectional view of a semiconductor device 100 according to the first embodiment. Fig. Figure 2 is a top view of the semiconductor device 100 according to the first embodiment. Fig. Figure 1 shows a configuration of a typical bonding sub-area of ​​the semiconductor chip 20, the metal block 24, and the conduction electrode in the semiconductor device 100. Fig. Figure 1 shows the semiconductor device 100 in a simplified manner, and, for example, lines, signal connections and the like, which are signal lines electrically connected to the semiconductor chip 20, have been omitted.

[0013] The semiconductor device 100 is, for example, a power semiconductor device. In the semiconductor device 100, a housing 10 is provided on a base plate 12. The base plate 12 is made of a material exhibiting excellent thermal conductivity, such as an aluminum alloy or copper. An insulating substrate 14 is bonded to a region of the upper surface of the base plate 12, which is surrounded by the housing 10, by means of a bonding material, such as a solder or a soft solder. The insulating substrate 14 has an insulating layer made of a ceramic material exhibiting excellent thermal conductivity, such as aluminum nitride or silicon nitride, or resin, and circuit structures 16 provided on both surfaces of the insulating layer. The circuit structure 16 is made of an aluminum alloy, copper, or the like. Fig. Figure 1 shows the circuit structure 16, which is provided on the upper surface of the insulating layer of the insulating substrate 14.

[0014] The semiconductor chip 20 comprises a substrate, an electrode 20a located on the upper surface of the substrate, and an electrode 20b located on the rear surface of the substrate. The electrode 20b of the semiconductor chip 20 is bonded to the circuit structure 16 using a bonding material 18. The bonding material 18 is, for example, a solder, a soft solder, or the like. The semiconductor chip 20 is, for example, an IGBT, a diode, a reverse-conducting IGBT, or the like, made of a silicon (Si) material. The semiconductor chip 20 can be a MOSFET, a Schottky diode, or the like, made of a material with a band gap larger than Si, such as silicon carbide (SiC) or gallium nitride (GaN). The number of semiconductor chips 20 on the insulating substrate 14 is not limited.A required number or type of semiconductor chips 20 can be attached according to the use of the semiconductor device 100.

[0015] The metal block 24 has a first surface and a second surface opposite the first surface. The first surface is bonded to the electrode 20a of the semiconductor chip 20 with a bonding material 22. The bonding material 22 is a solder, a soft solder, or the like. The metal block 24 is made of a metal that has excellent thermal conductivity and low electrical resistance, such as copper or aluminum. The metal block 24 is not limited to this and can be any metal that has the desired properties.

[0016] The lower surface of the metal conduction electrode 26 is bonded to the second surface of the metal block 24. The bond between the conduction electrode 26 and the metal block 24 is an ultrasonic bond. The metal block 24 and the conduction electrode 26 are bonded together without a bonding material. A plurality of irregularities 50 are formed on one surface of the conduction electrode 26 opposite the surface bonded to the metal block 24. The majority of irregularities 50 are ultrasonic bonding marks. The majority of irregularities 50 are formed at a position on the conduction electrode 26 that overlaps with the metal block 24 in a top view.

[0017] The ultrasonic bonding mark is also called an ultrasonic vibration application mark. The shape of the majority of irregularities 50, which are ultrasonic bonding marks, varies depending on the tip shape and the direction of vibration of the ultrasonic vibration tool 60. For example, when applying a unidirectional reciprocating vibration to the upper surface of the conduction electrode 26, as in Fig. Figure 2 shows an application marking in which parallel irregularities are continuous, forming the plurality of irregularities 50. Furthermore, depending on the shape of the tip of the ultrasonic vibration tool 60, a plurality of square pyramids can be continuously formed as the plurality of irregularities 50. Fig. Figure 3 is a view to explain another example of ultrasonic bonding markers. In the example of Fig. Figure 3 shows the plurality of irregularities 50a arranged in two directions. The plurality of irregularities 50a is, for example, formed within an area of ​​4 mm × 8 mm. The width of each protrusion contained within the plurality of irregularities 50a is, for example, approximately 0.1 mm to 10 mm.

[0018] A plurality of metal blocks 24 can be bonded to a semiconductor chip 20. The ultrasonic bonding marks are formed in a number corresponding to the number of metal blocks 24. In the example of Fig. 2 are two metal blocks 24 bonded to a semiconductor chip 20.

[0019] The conduction electrode 26 can be formed onto the semiconductor chip 20 by extending an external electrode 28, which is pre-inserted into the housing 10. The conduction electrode 26 can be attached to an external electrode 28, which is pre-inserted into the housing 10, by solder bonding, laser welding, ultrasonic bonding, or the like. Furthermore, a portion of the conduction electrode 26 can be connected to the circuit structure 16 by ultrasonic bonding, solder bonding, laser welding, or the like to form a circuit. Additionally, a conduction electrode 26 can be bonded to a plurality of semiconductor chips 20 via a plurality of metal blocks 24.

[0020] The following describes the procedure for assembling the semiconductor device 100 according to the present embodiment. First, the circuit structure 16 of the insulating substrate 14 and the semiconductor chip 20, and the semiconductor chip 20 and the first surface of the metal block 24, are bonded using bonding materials 18 and 22, such as a plate solder, a solder paste, and a soft solder. In the bonding step, the bonding materials 18 and 22 are first applied to the circuit structure 16 and the semiconductor chip 20. A solder is generally used for the bonding materials 18 and 22. The solder paste or the like, as well as the bonding materials 18 and 22, can be applied by screen printing or by using a dispensing device or the like.Next, the semiconductor device 100 is heated to a temperature that exceeds the melting point of the bonding materials 18 and 22, thereby performing the bonding.

[0021] The metal block 24 and the semiconductor chip 20 can be bonded simultaneously in the process of bonding the semiconductor chip 20 to the circuit structure 16. Alternatively, the semiconductor chip 20 can be bonded to the circuit structure 16, and then the semiconductor chip 20 can be bonded to the metal block 24. In this case, the bonding material 22 can be applied to the semiconductor chip 20 by screen printing, dispensing, or the like, the metal block 24 can be placed on the bonding material 22, and then the bonding material 22 can be locally heated by laser heating, hot air heating, or the like to bond it. This can prevent the bonding material 18 from being remelted.

[0022] Next, the housing 10 is bonded to the base plate 12. In this step, a silicon-based or epoxy-based adhesive is first applied to the bonding surface of the housing 10, which is to be bonded to the base plate 12. Then, the base plate 12, to which the semiconductor chip 20 and the insulating substrate 14 are bonded, is fitted to the housing 10, and a load is applied to the housing 10 to bring the housing 10 and the base plate 12 into close contact. The housing 10 and the base plate 12 can be fastened together by a sheet metal screw or the like. The adhesive can be heated and cured while the housing 10 and the base plate 12 are fixed with a clamping device or the like.

[0023] Next, the conduction electrode 26 is positioned on the second surface of the metal block 24. Next, as shown in Fig. As shown in Figure 1, an ultrasonic vibration is applied from the surface of the conducting electrode 26 on the opposite side to the metal block 24, and the second surface of the metal block 24 and the conducting electrode 26 are bonded by ultrasound. The conducting electrode 26 is pressed against the surface opposite the surface in contact with the metal block 24 by an ultrasonic tool 60. The conducting electrode 26 and the metal block 24 are bonded by applying the ultrasonic vibration while pressure with a constant load is applied.

[0024] Next, to form a signal circuit for controlling the semiconductor chip 20, the control electrode on the semiconductor chip 20 and the external signal connections are connected by a wire using ultrasonic bonding. Generally, aluminum or a similar material with high thermal and electrical conductivity is used for the wire.

[0025] Next, the interior of the housing 10 is sealed with a sealing resin. A silicone gel or an epoxy resin is often used as the sealing resin. The sealing resin is not limited to these, and any resin can be used as long as it possesses the desired physical properties, such as an elastic modulus, heat resistance, adhesion, and a coefficient of linear expansion. The semiconductor device 100 is then placed in a curing oven or similar appliance to cure the sealing resin, and the necessary curing is performed to complete the shape of the semiconductor device 100. Afterward, the semiconductor device 100 is completed by performing a check of its electrical properties and the like.

[0026] In the present embodiment, the metal block 24 is positioned between the semiconductor chip 20 and the conduction electrode 26. Ultrasonic bonding of the metal block 24 and the conduction electrode 26 prevents damage to the semiconductor chip 20 during the ultrasonic bonding process. This means that, since the upper surface of the semiconductor chip 20 does not become part of the bonding area during the ultrasonic bonding process, even when the ultrasonic vibration is applied while the conduction electrode 26 is pressed against it, damage to the semiconductor chip 20 is prevented. Consequently, in the present embodiment, ultrasonic bonding can be applied when a circuit is formed between the conduction electrode 26 and the semiconductor chip 20, and it is not necessary to heat the entire semiconductor device 100.Therefore, the bonding area between the semiconductor chip 20 and the insulating substrate 14, which are pre-bonded, can be prevented from being remelted. This eliminates the need for re-inspection of the bonding area on the back surface of the semiconductor chip 20, and allows the semiconductor device 100 to be manufactured at a lower cost. Furthermore, the bond strength of the back surface of the semiconductor chip 20 cannot be reduced.

[0027] As described above, the semiconductor chip 20 can be made from a wide-bandgap semiconductor. The wide-bandgap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. According to the present embodiment, even if the semiconductor chip 20 is made from a wide-bandgap semiconductor and a high current flows, a decrease in bond strength and a decrease in the reliability of the semiconductor device 100 can be prevented.

[0028] The modifications mentioned above can be suitably applied to semiconductor devices and methods for manufacturing semiconductor devices according to the following embodiments. It should be noted that the semiconductor devices and methods for manufacturing semiconductor devices according to the following embodiments have many similarities with the first embodiment, and therefore the description focuses mainly on the differences from the first embodiment. Second embodiment

[0029] Fig. Figure 4 is a cross-sectional view of a semiconductor device 200 according to the second embodiment. The semiconductor device 200 differs from the semiconductor device 100 of the first embodiment in the structures of the metal block 224 and the conduction electrode 226. The further configuration is the same as that of the first embodiment. A matching section, which is to be adapted to the conduction electrode 226, is formed on the second surface of the metal block 224. In particular, a convex section 224a is formed on the second surface of the metal block 224, and a concave section 226a is formed on the lower surface of the conduction electrode 226. The metal block 224 and the conduction electrode 226 are bonded by ultrasound in a state in which the convex section 224a of the metal block 224 enters the concave section 226a of the conduction electrode 226.Thus, the flat part of the upper surface of the convex part 224a of the metal block and the flat lower part of the concave part 226a of the conduction electrode 226 are bonded using ultrasound.

[0030] In the present embodiment, the metal block 224 and the conduction electrode 226 are adapted to one another, and thus, even if the conduction electrode 226 is not fixed before bonding, it can be easily positioned in the horizontal direction. Furthermore, the positioning accuracy of the conduction electrode 226 in the horizontal direction can be improved, and the semiconductor device 200 can be manufactured stably.

[0031] The shapes of the convex sub-region 224a and the concave sub-region 226a are not restricted as long as the metal block 224 and the conduction electrode 226 can be adapted to each other. Alternatively, a concave sub-region can be formed in the metal block 224 and a convex sub-region can be formed in the conduction electrode 226. Third embodiment

[0032] Fig. Figure 5 is a cross-sectional view of a semiconductor device 300 according to the third embodiment. The semiconductor device 300 differs from the semiconductor device 100 of the first embodiment in the structure of the conduction electrode 326. The further configuration is the same as that of the first embodiment. A recess 327 is formed on a surface of the conduction electrode 326 opposite the surface that is bonded to the metal block 24. The majority of irregularities 50, which are ultrasonic bonding marks, are formed on the underside surface of the recess 327.

[0033] In the present embodiment, the recess 327 is formed on the upper surface of the conduction electrode 326, thus preventing the scattering of metal fragments generated when the conduction electrode 26 and the metal block 24 are ultrasonically bonded. Therefore, the semiconductor device 300 can be manufactured stably. The depth of the recess 327 is preferably greater than the maximum depth of the plurality of irregularities 50. This can improve the effect of preventing the scattering of metal fragments. The maximum depth of the plurality of irregularities 50 is, for example, 0.5 mm to 0.8 mm.

[0034] The width of the recess 327 can be larger than the width of the area of ​​the conducting electrode 326 in contact with the metal block 24. The area of ​​the recess 327 can be larger than the area of ​​the area of ​​the conducting electrode 326 in contact with the metal block 24. Thus, even if the recess 327 is formed, the area of ​​the ultrasonic bonding sub-area can be sufficiently ensured. Fourth embodiment

[0035] Fig. Figure 6 is a cross-sectional view of a semiconductor device 400 according to the fourth embodiment. The semiconductor device 400 differs from the semiconductor device 100 of the first embodiment in the structure of the metal block 424. The further configuration is the same as that of the first embodiment. The metal block 424 has a copper layer 424a, which is bonded to the semiconductor chip 20 by the bonding material 22, and an aluminum layer 424b, which is bonded to the conduction electrode 26 by ultrasonic bonding. The metal block 424 is a coated material, which is formed, for example, by rolling and joining a copper material and an aluminum material by applying pressure to their surfaces.

[0036] In the present embodiment, the soft aluminum layer 424b is provided in a portion of the metal block 424. This reduces damage to the semiconductor chip 20 caused by ultrasonic vibration when the conduction electrode 26 and the metal block 424 are bonded together by ultrasound. Furthermore, it is unlikely that the aluminum material will form an intermetallic compound with the bonding material 22, such as a solder. The presence of the copper layer 424a on the surface, which is bonded to the semiconductor chip 20 by the bonding material 22, enables the semiconductor chip 20 to be bonded to the block 424. Therefore, the semiconductor device 400 can be manufactured stably. The metal block 424 can have the copper layer 424a and the aluminum layer 424b. Another metal layer can, for example, be provided between the copper layer 424a and the aluminum layer 424b. Fifth embodiment

[0037] Fig.Figure 7 is a cross-sectional view of a semiconductor device 500 according to the fourth embodiment. The thickness b of the metal block 524 of the semiconductor device 500 is equal to or greater than the thickness of the portion of the conduction electrode 26 that is bonded to the metal block 524. The further configuration is the same as that of the first embodiment. For example, if the conduction electrode 26 is 0.6 mm thick, the metal block 524 is 0.6 mm thick or thicker. In the present embodiment, during the ultrasonic bonding step of the conduction electrode 26 and the metal block 524, the metal block 524, which is thicker than the conduction electrode 26, is positioned between the semiconductor chip 20 and the conduction electrode 26. This further prevents damage to the semiconductor chip 20 when the ultrasonic vibration is applied to the conduction electrode 26 while pressure is being applied to the conduction electrode 26.Therefore, the semiconductor device 500 can be manufactured stably.

[0038] The technical features described in the embodiments can be used in a suitable combination. Reference symbol list

[0039] 10 Housing, 12 Base plate, 14 Insulating substrate, 16 Circuit structure, 18 Bonding material, 20 Semiconductor chip, 20a, 20b Electrode, 22 Bonding material, 24 Metal block, 26 Conducting electrode, 28 External electrode, 50, 50a Irregularities, 60 Ultrasonic vibration tool, 100, 200 Semiconductor device, 224 Metal block, 224a Convex sub-area, 226 Conducting electrode, 226a Concave sub-area, 300 Semiconductor device, 326 Conducting electrode, 327 Depression, 400 Semiconductor device, 424 Metal block, 424a Copper layer, 424b Aluminum layer, 500 Semiconductor device, 524 Metal block. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] WO 2020 / 105476

[0003]

Claims

[1] Semiconductor device comprising: a semiconductor chip; a metal block having a first surface and a second surface opposite the first surface, wherein the first surface is bonded to the semiconductor chip with a bonding material; and a conduction electrode that is bonded to the second surface of the metal block; wherein a plurality of irregularities are formed on a surface of the conducting electrode compared to a surface of the same that is bonded to the metal block. [2] Semiconductor device according to claim 1, wherein the majority of irregularities are ultrasonic bonding marks. [3] Semiconductor device according to claim 1 or 2, wherein the metal block and the conduction electrode are bonded together without a bonding material. [4] Semiconductor device according to one of claims 1 to 3, wherein an adaptation area to be adapted to the conduction electrode is formed on the second surface of the metal block. [5] Semiconductor device according to any one of claims 1 to 4, wherein a depression is formed in the surface of the conducting electrode opposite the surface of the electrode that is bonded to the metal block, and the plurality of irregularities are formed in a lower surface of the depression. [6] Semiconductor device according to claim 5, wherein a width of the recess is greater than a width of a region of the conduction electrode which is in contact with the metal block. [7] Semiconductor device according to claim 5 or 6, wherein a depth of the depression is greater than a maximum depth of the plurality of irregularities. [8] Semiconductor device according to any one of claims 1 to 7, wherein the metal block comprises an aluminium layer bonded to the conduction electrode and a copper layer bonded to the semiconductor chip. [9] Semiconductor device according to any one of claims 1 to 8, wherein the thickness of the metal block is equal to or greater than the thickness of a portion of the conduction electrode that is bonded to the metal block. [10] Semiconductor device according to any one of claims 1 to 9, wherein the semiconductor chip is made with a wide bandgap semiconductor. [11] Semiconductor device according to claim 10, wherein the wide bandgap semiconductor is silicon carbide, a gallium nitride-based material or diamond. [12] Method for manufacturing a semiconductor device, the method comprising: Following the bonding of a semiconductor chip to a first surface of a metal block, which has the first surface and a second surface opposite the first surface, with a bonding material, an ultrasonic vibration is applied from a surface of a conduction electrode opposite the metal block to bond the second surface of the metal block to the conduction electrode with ultrasound.

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