SEMICONDUCTOR STORAGE DEVICE

Abstract

A semiconductor memory device according to an embodiment of the present disclosure includes a first sub-wordline driver and a second sub-wordline driver. The first sub-wordline driver includes a first pull-down transistor and a first hold transistor. The second sub-wordline driver includes a second pull-down transistor and a second hold transistor. A source region of the first pull-down transistor and a source region of the second hold transistor are arranged to share a first doping region on a semiconductor substrate, and a source region of the second pull-down transistor and a source region of the first hold transistor are arranged to share a second doping region on the semiconductor substrate.

Description

[TECHNICAL FIELD]

[0001] The present disclosure relates to a semiconductor device and, more particularly, to a semiconductor memory device. [TECHNICAL BACKGROUND]

[0002] A semiconductor memory device can be classified as a volatile semiconductor memory device or a non-volatile semiconductor memory device. In a volatile memory device such as a dynamic random access memory (DRAM), in which data is stored by charging / discharging a cell capacitor, the stored data is retained as long as a power supply is applied, but the stored data is lost when power is not applied.

[0003] As the capacity of DRAM increases, the number of memory cells connected to a word line increases, and the spacing between word lines decreases. A method is used to control the word lines by dividing the word lines into a plurality of subword lines, each of which is controlled by a subword line driver. To improve the integration level of DRAM, a method for reducing the area occupied by the subword line driver is required. [DETAILED DESCRIPTION OF THE INVENTION][TECHNICAL PROBLEM]

[0004] An object of the present disclosure is to provide a semiconductor memory device that reduces the chip size by reducing the area on a semiconductor substrate occupied by a partial word line driver.

[0005] An object of the present disclosure is to provide a semiconductor memory device that enables various patterns included in a partial word line driver to be advantageously designed by adjusting the arrangement of transistors included in the partial word line driver. [TECHNICAL SOLUTION]

[0006] A semiconductor memory device according to an embodiment of the present disclosure for achieving the object includes a first sub-wordline driver and a second sub-wordline driver. The first sub-wordline driver includes a first pull-down transistor and a first hold transistor. The first pull-down transistor pulls down a first wordline in a deactivation interval of the first wordline. The first hold transistor maintains a voltage level of the pulled-down first wordline in the deactivation interval of the first wordline. The second sub-wordline driver includes a second pull-down transistor and a second hold transistor. The second pull-down transistor pulls down a second wordline in a deactivation interval of the second wordline. The second hold transistor maintains a voltage level of the pulled-down second wordline in the deactivation interval of the second wordline.A source region of the first pull-down transistor and a source region of the second hold transistor are arranged to share a first doping region on a semiconductor substrate, and a source region of the second pull-down transistor and a source region of the first hold transistor are arranged to share a second doping region on the semiconductor substrate.

[0007] A semiconductor memory device according to an embodiment of the present disclosure for achieving the above object includes a memory cell array and first to fourth sub-wordline drivers. The memory cell array includes a plurality of memory cells connected to a plurality of wordlines. The first to fourth sub-wordline drivers respectively activate a first wordline to a fourth wordline, which extend to one side of the memory cell array and are adjacent to each other, among the plurality of wordlines. The first sub-wordline driver includes a first pull-down transistor and a first hold transistor. The first pull-down transistor pulls down the first wordline in a deactivation interval of the first wordline. The first hold transistor maintains a voltage level of the pulled-down first wordline in the deactivation interval of the first wordline.The second partial wordline driver includes a second pull-down transistor and a second hold transistor. The second pull-down transistor pulls down the second wordline during a deactivation interval of the second wordline. The second hold transistor maintains a voltage level of the pulled-down second wordline during the deactivation interval of the second wordline. A source region of the first pull-down transistor and a source region of the second hold transistor are arranged to share a first doping region on a semiconductor substrate, and a source region of the second pull-down transistor and a source region of the first hold transistor are arranged to share a second doping region on the semiconductor substrate.

[0008] A semiconductor memory device according to an embodiment of the present disclosure for achieving the above object includes a first sub-wordline driver, a second sub-wordline driver, a first metal line, a second metal line, and a third metal line. The first sub-wordline driver includes a first pull-down transistor and a first hold transistor. The first pull-down transistor pulls down a first wordline in a deactivation interval of the first wordline. The first hold transistor maintains a voltage level of the pulled-down first wordline in the deactivation interval of the first wordline. The second sub-wordline driver includes a second pull-down transistor and a second hold transistor. The second pull-down transistor pulls down a second wordline in a deactivation interval of the second wordline.The second holding transistor maintains a voltage level of the pulled-down second word line in the deactivation interval of the second word line. The first metal line is electrically connected to the gates of the first and second pull-down transistors. The second metal line is electrically connected to a gate of the first holding transistor. The third metal line is electrically connected to a gate of the second holding transistor. A source region of the first pull-down transistor and a source region of the second holding transistor are arranged to share a first doping region on a semiconductor substrate, and a source region of the second pull-down transistor and a source region of the first holding transistor are arranged to share a second doping region on the semiconductor substrate.A drain region of the first holding transistor and a drain region of the first pull-down transistor are arranged to share a third doping region on the semiconductor substrate, and a drain region of the second holding transistor and a drain region of the second pull-down transistor are arranged to share a fourth doping region on the semiconductor substrate. [ADVANTAGEOUS EFFECTS OF THE INVENTION]

[0009] A semiconductor memory device according to an embodiment of the present disclosure can reduce the chip size by reducing the area occupied by a partial wordline driver on a semiconductor substrate.

[0010] The semiconductor memory device according to an embodiment of the present disclosure may enable various patterns included in the partial word line driver to be advantageously formed by adjusting the arrangement of transistors included in the partial word line driver. [DESCRIPTION OF THE DRAWINGS] Fig. 1 and Fig. 2 are block diagrams illustrating a semiconductor memory device with partial wordline drivers according to an embodiment of the present disclosure. Fig. 3 is a circuit diagram showing some of the Fig. 1 and Fig. 2 shows the partial wordline driver. Fig. 4 is a timing diagram describing the operation of the partial wordline drivers of Fig. 1. Fig. 5 and Fig. 6 are diagrams for describing embodiments of the arrangement of transistors used in partial word line drivers of Fig. 3 are included. Fig. 7 and Fig. 8 are diagrams for describing an embodiment of the arrangement of doping regions or metal lines used in the partial word line drivers of Fig. 1 are included. Fig. 9 and Fig. 10 are diagrams for describing an embodiment of the arrangement of transistors, doping regions or metal lines used in the partial word line drivers of Fig. 1 are included. Fig. 11 is a diagram for describing the arrangement of the partial word line drivers of Fig. 1. Fig. 12 is a diagram for describing one embodiment of the arrangement of transistors, doping regions, or metal lines included in partial wordline drivers according to one embodiment of the present disclosure. Fig. 13 is a diagram for describing the arrangement of partial word line drivers of Fig. 12. Fig. 14 is a diagram illustrating an embodiment of the arrangement of partial wordline drivers according to an embodiment of the present disclosure. Fig. 15 is a block diagram illustrating a semiconductor memory device with partial wordline drivers according to an embodiment of the present disclosure. Fig. 16 is a flowchart illustrating a method for designing and manufacturing a semiconductor memory device according to an embodiment of the present disclosure. Fig. 17A, Fig. 17B and Fig. 17C are diagrams describing photomasks for forming patterns used in the partial word line drivers of Fig. 12 are included. Fig. 18 is a block diagram illustrating a computer system with partial wordline drivers according to an embodiment of the present disclosure. Fig. 19 is a diagram illustrating a data center in which a semiconductor memory device with partial wordline drivers according to an embodiment of the present disclosure is deployed. [PREFERRED EMBODIMENT]

[0011] A drawing showing the best mode for carrying out the present disclosure is Fig. 1.

[0012] Hereinafter, embodiments of the present disclosure are described in sufficient detail and clarity to enable a person skilled in the art to readily implement the present disclosure.

[0013] Fig. 1 and Fig. 2 are block diagrams illustrating a semiconductor memory device with partial wordline drivers according to an embodiment of the present disclosure.

[0014] At the Fig. The semiconductor memory device 100 illustrated in Figure 1 may be a volatile memory device. In the following, the volatile memory device is assumed to be a dynamic random access memory (DRAM), but this is only an example. In one embodiment, the semiconductor memory device 100 may be any semiconductor memory device identical or similar in structure to the DRAM.

[0015] Semiconductor memory device 100 may include a memory cell array 101 and a plurality of sub-wordline drivers. Memory cell array 101 may include a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines and arranged in rows and columns. The plurality of sub-wordline drivers may respectively activate the plurality of wordlines.

[0016] In one embodiment, an activation interval and a deactivation interval may be defined for each of the plurality of wordlines. The activation interval may be an interval in which each of the plurality of wordlines maintains a first voltage level to drive selected memory cells in operating modes (e.g., a write operating mode, a read operating mode, and a self-refresh operating mode) of the semiconductor memory device 100. The deactivation interval may be an interval in which each of the plurality of wordlines maintains a second voltage level lower than the first voltage level to not drive unselected memory cells in each of the operating modes of the semiconductor memory device 100. The activation interval and the deactivation interval may be a specific time interval and may be referred to as a "drive time interval" and a "non-drive time interval," respectively.The activation interval and the deactivation interval are defined with reference to . Fig. 4 described.

[0017] The plurality of sub-wordline drivers may include a first sub-wordline driver 105 and a second sub-wordline driver 109. The first and second sub-wordline drivers 105 and 109 may respectively activate first and second wordlines WL1 and WL2 among the plurality of wordlines and drive corresponding memory cells (or memory cell rows) among the plurality of memory cells.

[0018] The first partial wordline driver 105 may include a first pull-down transistor PDTR1 and a first hold transistor KPTR1, and the second partial wordline driver 109 may include a second pull-down transistor PDTR2 and a second hold transistor KPTR2. Although in Fig. 1, each of the first sub-wordline driver 105 and the second sub-wordline driver 109 may further include a pull-up transistor for pulling up the corresponding wordline and one or more other transistors.

[0019] The first pull-down transistor PDTR1 can pull down the first word line WL1 during the deactivation interval of the first word line WL1, and the first hold transistor KPTR1 can maintain the voltage level of the thus-pulled-down first word line WL1. For example, during the deactivation interval of the first word line WL1, the first pull-down transistor PDTR1 can be turned on, so that the first word line WL1 is pulled down to a negative voltage VBB2 corresponding to the second voltage level, and the first hold transistor KPTR1 can be turned on, so that the voltage level of the thus-pulled-down first word line WL1 is maintained at the negative voltage VBB2.

[0020] The second pull-down transistor PDTR2 can pull down the second word line WL2 during the deactivation interval of the second word line WL2, and the second hold transistor KPTR2 can maintain the voltage level of the thus-pulled-down second word line WL2. For example, during the deactivation interval of the second word line WL2, the second pull-down transistor PDTR2 can be turned on, so that the second word line WL2 is pulled down to the negative voltage VBB2 corresponding to the second voltage level, and the second hold transistor KPTR2 can be turned on, so that the voltage level of the thus-pulled-down second word line WL2 is maintained at the negative voltage VBB2.

[0021] Each of the first pull-down transistor PDTR1, the first hold transistor KPTR1, the second pull-down transistor PDTR2, and the second hold transistor KPTR2 may include a drain region and a source region, as well as a channel region formed between the drain region and the source region when each transistor is turned on. The drain region may be referred to as an "active drain region" and the source region as an "active source region." Direct contacts for electrical connection to external circuits may be arranged on the drain region and the source region.

[0022] In one embodiment, the first pull-down transistor PDTR1, the first hold transistor KPTR1, the second pull-down transistor PDTR2 and the second hold transistor KPTR2 may be formed on a semiconductor substrate.

[0023] The source regions of the first pull-down transistor PDTR1 and the second hold transistor KPTR2 can be arranged on the semiconductor substrate such that they share a doping region SHRD_DPR1 on the semiconductor substrate. For example, the source regions of the first pull-down transistor PDTR1 and the second hold transistor KPTR2 can be formed on the doping region SHRD_DPR1 on the semiconductor substrate. For example, the doping region SHRD_DPR1 on the semiconductor substrate can include the source regions of the first pull-down transistor PDTR1 and the second hold transistor KPTR2.

[0024] The source regions of the second pull-down transistor PDTR2 and the first holding transistor KPTR1 can be arranged on the semiconductor substrate such that they share a doping region SHRD_DPR2 on the semiconductor substrate. For example, the source regions of the second pull-down transistor PDTR2 and the first holding transistor KPTR1 can be formed on the doping region SHRD_DPR2 on the semiconductor substrate. For example, the doping region SHRD_DPR2 on the semiconductor substrate can include the source regions of the second pull-down transistor PDTR2 and the first holding transistor KPTR1.

[0025] Although in Fig. 1, the drain regions of the first pull-down transistor PDTR1 and the first holding transistor KPTR1 may be arranged on the semiconductor substrate to share a different doping region than the doping regions SHRD_DPR1 and SHRD_DPR2. The drain regions of the second pull-down transistor PDTR2 and the second holding transistor KPTR2 may be arranged on the semiconductor substrate to share a different doping region than the doping regions SHRD_DPR1 and SHRD_DPR2.

[0026] Referring to Fig. 2, a semiconductor memory device 100a may include memory cells (or a "memory cell array") 111, 113, and 115, partial wordline drivers 131 and 133, sense amplifier blocks 151, 152, 153, 154, 155, and 156, conjunction circuits 171, 172, 173, and 174, and a row decoder 190. Row decoder 190 may include a control signal generator 191.

[0027] The row decoder 190 may receive a row address RADO and generate signals for controlling selected memory cells from the memory cells 111, 113, and 115. For example, based on the row address RADO, the row decoder 190 may generate one or more word line enable signals NWEIB <0> , NWEIB <1> etc. and one or more partial wordline driver control signals PXID <0> , ..., PXID <7> ..., PXIB <0> , ..., PXIB <7> etc. and control the selected memory cells.

[0028] In one embodiment, row decoder 190 may include one or more of the word line enable signals NWEIB <0> , NWEIB <1> etc. based on first bits of the row address RADO, and the control signal generator 191 included in the row decoder 190 can generate one or more of the partial word line driver control signals PXID <0> , ..., PXID <7> ..., PXIB <0> , ..., PXIB <7> etc. based on second bits of the row address RADO. For example, if a result of decoding the first bits and the second bits of the row address RADO indicates that one or more of the memory cells MC0, MC1, MC2, MC3, MC4, MC5, MC6, and MC7 are being addressed, the row decoder 190 may output the word line enable signal NWEIB <0> In the case of controlling one or more (e.g. MC0, MC2, MC4 and MC6) of the memory cells, the control signal generator 191 can generate one or more (e.g., PXID <0> , PXIB <0> , PXID <2> , PXIB <2> , PXID <4> , PXIB <4> , PXID <6> and PXIB <6> ) of the partial word line driver control signals PXID <0> , ..., PXID <7> ..., PXIB <0> , ..., PXIB <7> , etc., generate In this case, the partial word line drivers SWDO, SWD2, SWD4 and SWD6 can generate the word lines WL <0> , WL <2> , WL <4> and WL <6> based on the word line enable signal NWEIB <0> and the partial wordline driver control signals PXID <0> , PXIB <0> , PXID <2> , PXIB <2> , PXID <4> , PXIB <4> , PXID <6> and PXIB <6> activate.

[0029] The conjunction circuits 171 to 174 may include metal lines for supplying power to the sense amplifier blocks 151 to 156, the partial word line drivers 131 and 133, and the memory cells 111, 113, and 115, or for providing electrical signals generated therefrom, as well as various circuits for any other operations of the memory device 100a.

[0030] Each of the partial wordline drivers SWD0, SWD1, SWD2, SWD3, SWD4, SWD5, SWD6, and SWD7 may include a pull-down transistor and a holding transistor. A source region of a pull-down transistor included in one partial wordline driver and a source region of a holding transistor included in another partial wordline driver may share a doping region on a semiconductor substrate. The drain regions of a pull-down transistor and a holding transistor included in a partial wordline driver may share a different doping region on the semiconductor substrate. The shared doping regions may be arranged on the semiconductor substrate to be spaced apart from each other, and some of the shared doping regions may be arranged to be symmetrical. The shared doping regions are described with reference to the Fig. 7 and Fig. 9 described.

[0031] According to the above configuration, a semiconductor memory device according to an embodiment of the present disclosure can reduce the area occupied by the partial wordline driver on the semiconductor substrate, and thus reduce the chip size. Furthermore, various patterns included in the partial wordline driver can be advantageously formed by adjusting the arrangement of transistors included in the partial wordline driver.

[0032] Fig. 3 is a circuit diagram showing some of the Fig. 1 and Fig. 2 shows the partial wordline driver.

[0033] In the Fig. 1 to 3, components with the same reference numbers / symbols can perform essentially the same functions. Fig. 3, some 133a of subwordline drivers may include subwordline drivers SWDO, SWD2, SWD4, and SWD6, and each of subwordline drivers SWDO, SWD2, SWD4, and SWD6 may include a pull-up transistor, a pull-down transistor, and a holding transistor. The pull-up transistor may be formed from a MOS transistor of a first conductivity type, and the pull-down transistor and the holding transistor may each be formed from a MOS transistor of a second conductivity type.

[0034] For example, the partial wordline driver SWDO may include a pull-up transistor PM0 consisting of a PMOS transistor SWD0-P, as well as a pull-down transistor NM0 and a hold transistor KP0, each consisting of an NMOS transistor SWDO-N. Accordingly, the PMOS transistor SWD0-P of the partial wordline driver SWD0 may refer to the pull-up transistor PM0, and the NMOS transistor SWDO-N of the partial wordline driver SWDO may refer to the pull-down transistor NM0 and the hold transistor KP0.

[0035] The pull-up transistor PM0 included in the partial word line driver SWDO can be connected between a terminal to which the partial word line driver control signal PXID <0> is applied, and the corresponding word line (e.g. WL <0> ), and the pull-down transistor NM0 and the hold transistor KP0 included in the partial word line driver SWDO may be connected in parallel between the corresponding word line and terminals to which the negative voltage VBB2 is applied. For example, the partial word line driver control signal PXID <0> to the source region of pull-up transistor PM0, and negative voltage VBB2 can be applied to the source region of each pull-down transistor NM0 and the holding transistor KP0. The drain region of pull-up transistor PM0, pull-down transistor NM0, and holding transistor KP0 can be connected to the corresponding word line.

[0036] The remaining subwordline drivers SWD2, SWD4 and SWD6 can also be implemented to be identical or similar to the subwordline driver SWDO.

[0037] In one embodiment, the partial wordline driver SWD2 may include a pull-up transistor PM2 formed from a PMOS transistor SWD2-P, as well as a pull-down transistor NM2 and a hold transistor KP2 each formed from an NMOS transistor SWD2-N, and the partial wordline driver control signal PXID <2> and the negative voltage VBB2 may be applied to the partial wordline driver SWD2. The partial wordline driver SWD4 may include a pull-up transistor PM4 formed from a PMOS transistor SWD4-P, and a pull-down transistor NM4 and a hold transistor KP4, each formed from an NMOS transistor SWD4-N, and the partial wordline driver control signal PXID. <4> and the negative voltage VBB2 can be applied to the partial word line driver SWD4.The partial word line driver SWD6 may include a pull-up transistor PM6 formed of a PMOS transistor SWD6-P, and a pull-down transistor NM6 and a hold transistor KP6 each formed of an NMOS transistor SWD6-N, and the partial word line driver control signal PXID <6> and the negative voltage VBB2 can be applied to the partial word line driver SWD6.

[0038] In this case, each of the pull-up transistors PM0, PM2, PM4 and PM6 and the pull-down transistors NM0, NM2, NM4 and NM6 included in the partial wordline drivers SW0, SWD2, SWD4 and SWD6 may have a gate terminal configured to provide the wordline enable signal NWEIB <0> receives. Each of the holding transistors KP0, KP2, KP4 and KP6 included in the partial wordline drivers SW0, SWD2, SWD4 and SWD6 may include a gate terminal configured to receive a corresponding control signal from among the partial wordline driver control signals PXIB <0> , PXIB <2> , PXIB <4> and PXIB <6> receives. Partial wordline driver control signals applied to the hold transistors KP0, KP2, KP4, and KP6, respectively, may be referred to as a "hold control signal."

[0039] The partial word line drivers SWDO, SWD2, SWD4 and SWD6 can each control the word lines WL <0> , WL <2> , WL <4> and WL <6> activate.

[0040] In one embodiment, the word lines WL <0> , WL <2> , WL <4> and WL <6> correspond to the partial wordline drivers SWDO, SWD2, SWD4 and SWD6, respectively. In one embodiment, the wordlines WL <0> , WL <2> , WL <4> and WL <6> Word lines that extend to one side of the memory cell array and are adjacent to each other.

[0041] Fig. 4 is a timing diagram describing the operation of the partial wordline drivers of Fig. 1. Of the Fig. 2 and Fig. 3, only the components associated with the partial wordline driver SWDO are described; however, this is only an example. The remaining partial wordline drivers can also operate essentially like the partial wordline driver SWDO. Fig. 4 are the signal levels of the word line enable signal NWEIB <0> and the partial wordline driver control signals PXID <0> and PXIB <0> , which are applied to the partial word line driver SWDO while the times t1, t2 and t3 pass, and a voltage level of the word line WL <0> , which the partial word line driver SWD0 activates.

[0042] With reference to Fig. 3 and Fig. 4, the word line enable signal NWEIB <0> have a high level (H) or a low level (L), and the partial word line driver control signals PXID <0> and PXIB <0> can have a voltage level VSS or a voltage level VPP. The high level can be a signal level sufficient to turn off the pull-up transistor PM0 and turn on the pull-down transistor NM0, and the low level can be a signal level sufficient to turn on the pull-up transistor PM0 and turn off the pull-down transistor NM0. The voltage level VPP can be a high voltage level sufficient to activate the word line WL <0> sufficient, and the voltage level VSS can be a low voltage level used to deactivate the word line WL <0> is sufficient.

[0043] The word line enable signal NWEIB <0> may be high before t1, transition to low at t1, and maintain this level until t2. In addition, the word line enable signal NWEIB <0> go to the high level at t2 and maintain it until t3.

[0044] The partial wordline driver control signal PXID <0> may have the voltage level VSS before t1, transition to the voltage level VPP at t1, and maintain the voltage level VPP until t2. In addition, the partial wordline driver control signal PXID <0> transition to the voltage level VSS at t2 and maintain the voltage level VSS at t3. When the partial wordline driver control signal PXID <0> the voltage level VSS, the partial word line driver control signal PXIB <0> have the voltage level VPP; when the partial word line driver control signal PXID <0> the voltage level VPP, the partial word line driver control signal PXIB <0> have the voltage level VSS.

[0045] Before t1 or between t2 and t3, because the word line enable signal NWEIB <0> has the high level and the partial word line driver control signal PXIB <0> has the voltage level VPP, the pull-down transistor NM0 and the hold transistor KP0 can be turned on, and the voltage level of the word line WL <0> can display the negative voltage VBB2.

[0046] Between t1 and t2 or after t3, because the word line enable signal NWEIB <0> has the low level and the partial word line driver control signal PXIB <0> the voltage level VSS, the pull-up transistor PM0 can be turned on, and the voltage level of the word line WL <0> can display the voltage level VPP, which is the voltage level of the partial word line driver control signal PXID <0> is.

[0047] Between t1 and t2, the word line WL <0> be activated. Before t1 or between t2 and t3, the word line WL <0> be deactivated.

[0048] As in Fig. 1, the activation interval and the deactivation interval of the word line WL <0> The time interval from t1 to t2 can be defined as the activation interval of the word line WL <0> and the time interval from t2 to t3 may correspond to the deactivation interval of the word line WL <0> are equivalent to.

[0049] Fig. 5 and Fig. 6 are diagrams for describing embodiments of the arrangement of transistors used in partial word line drivers of Fig. 3 are included.

[0050] With reference to Fig. 3 and Fig. 5, some 133b of sub-wordline drivers may include the sub-wordline drivers SWDO, SWD2, SWD4, and SWD6, and each of the sub-wordline drivers SWDO, SWD2, SWD4, and SWD6 may include a pull-up transistor, a pull-down transistor, and a hold transistor.

[0051] In one embodiment, the sub-wordline drivers SWDO, SWD2, SWD4 and SWD6 may be formed on the semiconductor substrate.

[0052] A source region of a pull-down transistor included in one partial wordline driver and a source region of a hold transistor included in another partial wordline driver may be arranged on the semiconductor substrate to share a doping region on the semiconductor substrate.

[0053] In one embodiment, the subwordline driver SWDO may include the pull-down transistor NM0 and the holding transistor KP0, and the subwordline driver SWD2 may include the pull-down transistor NM2 and the holding transistor KP2. For example, the source regions of the pull-down transistor NM2 and the holding transistor KP0 may be arranged to share a doping region SHRD_DPR1-1, and the source regions of the pull-down transistor NM0 and the holding transistor KP2 may be arranged to share a doping region SHRD_DPR2-1.

[0054] In one embodiment, the subwordline driver SWD4 may include the pull-down transistor NM4 and the holding transistor KP4, and the subwordline driver SWD6 may include the pull-down transistor NM6 and the holding transistor KP6. For example, the source regions of the pull-down transistor NM6 and the holding transistor KP4 may be arranged to share a doping region SHRD_DPR1-2, and the source regions of the pull-down transistor NM4 and the holding transistor KP6 may be arranged to share a doping region SHRD_DPR2-2.

[0055] As in the Fig. 5 and Fig. As shown in Figure 6, an active region ACT located between the insulation layers ST1 and ST2 may be defined on a semiconductor substrate SUB.

[0056] The doping regions DPR1, DPR2 and DPR3 may be formed in the active region ACT, and the pull-down transistor NM0 included in the partial word line driver SWDO and the hold transistor KP2 included in the partial word line driver SWD2 may be formed.

[0057] The pull-down transistor NM0 can provide the word line enable signal NWEIB <0> via the gate terminal and can have a drain region NM0_DR, which is connected to the word line WL via a direct contact DC1 <0> and a source region NM0_SR connected via a direct contact DC2 to the terminal supplying the negative voltage VBB2. The holding transistor KP2 can supply the partial wordline driver control signal PXIB <2> via the gate terminal and can have a drain region KP2_DR, which is connected to the word line WL <2> connected via a direct contact DC3, and a source region KP2_SR connected to the terminal providing the negative voltage VBB2 via the direct contact DC2.

[0058] As in Fig. 6, the source regions of the pull-down transistor NM0 and the holding transistor KP2 can be arranged to share a doping region (e.g., DPR2). Although in Fig. 6, the source regions of the pull-down transistor NM2 and the holding transistor KP0, the source regions of the pull-down transistor NM6 and the holding transistor KP4, and the source regions of the pull-down transistor NM4 and the holding transistor KP6 may be arranged to share a doping region.

[0059] Fig. 7 and Fig. 8 are diagrams for describing an embodiment of the arrangement of doping regions or metal lines used in the partial word line drivers of Fig. 1 are included.

[0060] A plan view of the semiconductor substrate shown in FIG. Fig. 1, Fig. 2, Fig. 5 and Fig. 6 is seen in the vertical direction in Fig. 7, and only areas corresponding to the pull-down transistors NM0 and NM2 and the holding transistors KP0 and KP2 of some (e.g. SWDO and SWD2) of the partial word line drivers SWDO, SWD2, SWD4 and SWD6 of Fig. 5 can be formed in a semiconductor substrate made of Fig. 7. The directions D1, D2, and D3 may be orthogonal, and a direction D4 may indicate a direction between D1 and D2. The directions D1, D2, D3, and D4 may be used together to describe a semiconductor memory device according to an embodiment of the present disclosure.

[0061] With reference to Fig. 7, doping regions DPR11, DPR13, DPR15 and DPR17 and metal lines ML1, ML2 and ML3 may be formed in the semiconductor substrate, and direct contacts DC11, DC13, DC15 and DC17 for applying specific signals or voltages may be formed in the doping regions DPR11, DPR13, DPR15 and DPR17.

[0062] In one embodiment, the doping regions DPR11, DPR13, DPR15 and DPR17 may be arranged on the semiconductor substrate such that they are spaced apart from each other.

[0063] In one embodiment, the drain regions may be formed in the doping regions DPR11 and DPR15, and the source regions may be formed in the doping regions DPR13 and DPR17. For example, the drain regions of the pull-down transistor NM0 and the holding transistor KP0 may be formed in the doping region DPR11, and the source regions of the pull-down transistor NM0 and the holding transistor KP2 may be formed in the doping region DPR13. The drain regions of the holding transistor KP2 and the pull-down transistor NM2 may be formed in the doping region DPR15, and the source regions of the pull-down transistor NM2 and the holding transistor KP0 may be formed in the doping region DPR17.

[0064] Metal lines ML1, ML2, and ML3 may be electrically connected to the gates of pull-down transistors NM0 and NM2 and holding transistors KP0 and KP2. For example, metal line ML1 may be electrically connected to the gates of pull-down transistors NM0 and NM2, metal line ML2 may be electrically connected to the gate of holding transistor KP2, and metal line ML3 may be electrically connected to the gate of holding transistor KP0.

[0065] In one embodiment, gate signals (e.g., NWEIB <0> , PXIB <0> and PXIB <2> ) to the pull-down transistors NM0 and NM2 and the keeping transistors KP0 and KP2 via the metal lines ML1, ML2, and ML3. For example, a word line enable signal (e.g., NWEIB <0> ) are applied to the pull-down transistors NM0 and NM2 via the metal line ML1, a partial word line driver control signal (e.g., PXIB <2> ) can be applied to the holding transistor KP2 via the metal line ML2, and a partial word line driver control signal (or a holding control signal) (e.g. PXIB <0> ) can be applied to the holding transistor KP0 via the metal line ML3.

[0066] The direct contacts DC11, DC13, DC15, and DC17 can be arranged on the doping regions DPR11, DPR13, DPR15, and DPR17. For example, the direct contact DC11 can be arranged on the doping region DPR11, the direct contact DC13 on the doping region DPR13, the direct contact DC15 on the doping region DPR15, and the direct contact DC17 on the doping region DPR17.

[0067] In one embodiment, a negative voltage (e.g. VBB2 from Fig. 1). For example, the pull-down transistor NM0 and the holding transistor KP2 can receive the negative voltage via the direct contact DC13, and the pull-down transistor NM2 and the holding transistor KP0 can receive the negative voltage via the direct contact DC17.

[0068] In Fig. 8 only the metal lines ML1, ML2 and ML3 are shown. According to Fig. 8, the metal line ML1 may extend in the first direction D1 by a first length L1 (e.g., from point P1 to point P2), may then extend in the second direction D4 deviating from the first direction D1 by a second length L2 (e.g., from point P2 to point P3), and may then extend in the first direction D1 by a third length L3 (e.g., from point P3 to point P4).

[0069] In one embodiment, the first direction D1 may be a direction in which the word lines WL <0> and WL <2> which are controlled by the partial wordline drivers SWDO and SWD2, and the second direction D4 can form a specific angle θ1 with the first direction D1. For example, the angle θ1 can be 45 degrees or have a value close to 45 degrees.

[0070] The metal line ML2 and the metal line ML3 may be arranged so as to be symmetrical to the metal line ML1 extending in the second direction D4.

[0071] In one embodiment, the metal line ML2 and the metal line ML3 may be arranged on a virtual line VL1 that is perpendicular to the second direction D4.

[0072] In one embodiment, the metal line ML2 and the metal line ML3 may be arranged on another virtual line that forms a certain angle θ2 with the line VL1. For example, the angle θ2 may be 0 degrees or have a value close to 0 degrees. A point P23 at which the metal line ML1 extending in the second direction D4 and the line VL1 intersect is determined with reference to Fig. 10. Point P23 can be used as a guide for the formation of metal lines or gate regions of certain holding transistors.

[0073] Fig. 9 and Fig. 10 are diagrams for describing an embodiment of the arrangement of transistors, doping regions or metal lines used in partial wordline drivers of Fig. 1 are included.

[0074] A plan view of a semiconductor substrate substantially identical to the semiconductor substrate of Fig. 7 is identical, is in Fig. 9, and only areas corresponding to the pull-down transistors NM0 and NM2 and the holding transistors KP0 and KP2 of some (e.g. SWDO and SWD2) of the partial word line drivers SWDO, SWD2, SWD4 and SWD6 of Fig. 5 can be formed in a semiconductor substrate made of Fig. 9. In Fig. 7 and Fig. 9, components with the same reference numbers / symbols can perform essentially the same functions.

[0075] Referring to Fig. 9, the doping regions DPR11, DPR13, DPR15 and DPR17 and the metal lines ML1, ML2 and ML3 may be formed on the semiconductor substrate, and transistor regions NM0R and NM2R in which the pull-down transistors NM0 and NM2 are formed, respectively, and transistor regions KP0R and KP2R in which the holding transistors KP0 and KP2 are formed, respectively, may be further formed on the semiconductor substrate.

[0076] In one embodiment, the source region NM0_SR of the pull-down transistor NM0 and the source region KP2_SR of the holding transistor KP2 may be formed in the doping region DPR13. For example, the source regions NM0_SR and KP2_SR of the pull-down transistor NM0 and the holding transistor KP2 may be arranged to share the doping region DPR13.

[0077] In one embodiment, a source region NM2_SR of the pull-down transistor NM2 and a source region KP0_SR of the holding transistor KP0 may be formed in the doping region DPR17. For example, the source regions NM2_SR and KP0_SR of the pull-down transistor NM2 and the holding transistor KP0 may be arranged to share the doping region DPR17.

[0078] In one embodiment, the drain region NM0_DR of the pull-down transistor NM0 and a drain region KP0_DR of the holding transistor KP0 may be formed in the doping region DPR11. For example, the drain regions NM0_DR and KP0_DR of the pull-down transistor NM0 and the holding transistor KP0 may be arranged to share the doping region DPR11.

[0079] In one embodiment, a drain region NM2_DR of the pull-down transistor NM2 and the drain region KP2_DR of the holding transistor KP2 may be formed in the doping region DPR15. For example, the drain regions NM2_DR and KP2_DR of the pull-down transistor NM2 and the holding transistor KP2 may be arranged to share the doping region DPR15.

[0080] In one embodiment, the doping region DPR13 may be referred to as the "first doping region," the doping region DPR17 as the "second doping region," the doping region DPR11 as the "third doping region," and the doping region DPR15 as the "fourth doping region." In this case, the first to fourth doping regions may be arranged clockwise in the order of the first doping region, the fourth doping region, the second doping region, and the third doping region with respect to a virtual central axis perpendicular to the semiconductor substrate. In this case, the first doping region and the third doping region may be arranged to form point symmetry with the second doping region and the fourth doping region.

[0081] In one embodiment, the pull-down transistor NM0 and the holding transistor KP0 may be arranged on the semiconductor substrate to form a point symmetry with the pull-down transistor NM2 and the holding transistor KP2.

[0082] A gate region NM0_GR in which the gate of the pull-down transistor NM0 is formed may be arranged in a region where the metal line ML1 and the transistor region NM0R overlap, and a gate region NM2_GR in which the gate of the pull-down transistor NM2 is formed may be arranged in a region where the metal line ML1 and the transistor region NM2R overlap. A gate region KP2_GR in which the gate of the hold transistor KP2 is formed may be arranged in a region where the metal line ML2 and the transistor region KP2R overlap, and a gate region KP0_GR in which the gate of the hold transistor KP0 is formed may be arranged in a region where the metal line ML3 and the transistor region KP0R overlap.

[0083] With reference to the Fig. 9 and Fig. 10, virtual lines VL2-1 and VL2-2 can be defined on the semiconductor substrate, passing through point P23 and crossing each other so that they are perpendicular to each other. As shown in Fig. 8, the point P23 may, for example, be a point where the metal line ML1 extending in the second direction DR and the line VL1 intersect.

[0084] The semiconductor substrate may be divided into four regions based on the lines VL2-1 and VL2-2, and the gate regions NM0_GR, NM2_GR, KP0_GR, and KP2_GR of the pull-down transistor NM0, the pull-down transistor NM2, the hold transistor KP0, and the hold transistor KP2, respectively, may be arranged in the four regions.

[0085] In one embodiment, the gate region NM0_GR and the gate region NM2_GR may be arranged such that they are spaced apart from each other and arranged point-symmetrically with respect to point P23. The gate region KP0_GR and the gate region KP2_GR may be arranged such that they are spaced apart from each other and arranged point-symmetrically with respect to point P23.

[0086] In one embodiment, the gate regions NM0_GR and KP0_GR and the gate regions KP2_GR and NM2_GR may be arranged to be spaced apart from each other and arranged point-symmetrically with respect to point P23. The gate regions NM0_GR and KP2_GR and the gate regions KP0_GR and NM2_GR may be arranged to be spaced apart from each other and arranged point-symmetrically with respect to point P23.

[0087] Fig. 11 is a diagram for describing the arrangement of the partial word line drivers of Fig. 1.

[0088] The transistor areas NM0R, KP0R, NM2R and KP2R are in Fig. 11. The transistor regions NM0R, KP0R, NM2R and KP2R are essentially the same as those shown in Fig. 9 described transistor areas NM0R, KP0R, NM2R and KP2R.

[0089] With reference to the Fig. 9 and Fig. 11, transistor regions included in a partial wordline driver according to embodiments of the present disclosure may be implemented by changing the arrangement of transistor regions according to the prior art. For example, the arrangement of transistor regions NM2R and KP2R among transistor regions NM0R, KP0R, NM2R, and KP2R may be implemented into any other arrangement (e.g., 305) by changing the arrangement (e.g., 301) according to the prior art.

[0090] In one embodiment, each of the arrangements 301 and 305 may include the transistor region NM2R in which the pull-down transistor NM2 is formed, and the transistor region KR2R in which the holding transistor KP2 is formed. As in Fig. As shown in Figure 11, the arrangement 305 can be realized by rotating the arrangement 301 by up to 180 degrees around a virtual line passing through the drain region of the pull-down transistor NM2.

[0091] When the arrangement 301 is changed to the arrangement 305, the axial symmetry formed by the transistor regions NM0R and KP0R with the transistor regions NM2R and KP2R can be changed to the point symmetry formed by the transistor regions NM0R and KP0R with the transistor regions NM2R and KP2R. In this case, the shortest distance between the transistor region NM2R and the transistor region KR0R can be reduced, and the shortest distance between the transistor region KP2R and the transistor region NM0R can be reduced.

[0092] When the arrangement 301 is changed to the arrangement 305, the source region NM0_SR of the pull-down transistor NM0 and the source region KP2_SR of the holding transistor KP2 may be arranged to share a doping region, and the source region NM2_SR of the pull-down transistor NM2 and the source region KP0_SR of the holding transistor KP0 may be arranged to share a doping region. In this case, the area on the semiconductor substrate occupied by a portion of a partial wordline driver may be reduced by the size (e.g., w1 × h1) of a region 309.

[0093] When the arrangement 301 is changed to the arrangement 305, the metal lines can be arranged as in Fig. 8 described.

[0094] Fig. 12 is a diagram for describing one embodiment of the arrangement of transistors, doping regions, or metal lines included in partial wordline drivers according to one embodiment of the present disclosure.

[0095] A plan view of a semiconductor substrate substantially identical to the semiconductor substrate of Fig. 7 is identical, is in Fig. 12. The semiconductor substrate made of Fig. 12 may contain the areas corresponding to the pull-down transistors NM0, NM2, NM4 and NM6 and the holding transistors KP0, KP2, KP4 and KP6 of the partial word line drivers SW00, SWD2, SWD4 and SWD6 of Fig. 5, and may further comprise regions corresponding to the pull-down transistors NM8, NM10, NM12 and NM14 and the holding transistors KP8, KP10, KP12 and KP14 of the partial wordline drivers SWD8, SWD10, SWD12 and SWD14 shown in Fig. 5 are not shown. Although in Fig. 12 are not shown, are processed in the same or similar manner as in the Fig. 5, Fig. 6 and Fig. In the manner described in Figure 9, doping regions can be shared between the pull-down transistors NM0, NM2, NM4, NM6, NM8, NM10, NM12 and NM14 and the holding transistors KP0, KP2, KP4, KP6, KP8, KP10, KP12 and KP14 of the partial wordline drivers SW00, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12 and SWD14.

[0096] With reference to Fig. 2, Fig. 3 and Fig. 12, the partial word line drivers SWD8, SWD10, SWD12 and SWD14 can each control the word lines WL <8> , WL <10> , WL <12> and WL <14> activate, and the word lines WL <8> , WL <10> , WL <12> and WL <14> can be word lines that extend in the same direction on one side of the memory cell array.12> and WL <14> can be word lines extending to one side of the memory cell array in the same direction as the word lines WL <0> , WL <2> , WL <4> and WL <6> extend and are adjacent to each other.

[0097] In one embodiment, a partial word line driver region SWDO-NR may be defined in the semiconductor substrate, which includes the transistor regions NM0R and KP0R in which the pull-down transistor NM0 and the holding transistor KP0 are formed, and a partial word line driver region SWD2-NR may be defined, which includes the transistor regions NM2 and KP2R in which the pull-down transistor NM2 and the holding transistor KP2 are formed. The partial word line driver regions SWD4-NR, SWD6-NR, SWD8-NR, SWD10-NR, SWD12-NR, and SWD14-NR may be defined as described above. The partial wordline driver regions SWDO-NR, SWD2-NR, SWD4-NR, SWD6-NR, SWD8-NR, SWD10-NR, SWD12-NR, and SWD14-NR may each include NMOS transistors SWDO-N, SWD2-N, SWD4-N, SWD6-N, SWD8-N, SWD10-N, SWD12-N, and SWD14-N of the partial wordline drivers SWDO, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12, and SWD14.In this case, all subword line driver areas SW0-NR and SWD2-NR can be arranged to form axial symmetry with all subword line driver areas SWD4-NR and SWD6-NR. All subword line driver areas SWD8-NR and SWD10-NR can be arranged to form axial symmetry with all subword line driver areas SWD12-NR and SWD14-NR. All subword line driver areas SWD0-NR, SWD2-NR, SWD4-NR, and SWD6-NR can be arranged to form axial symmetry with all subword line driver areas SWD8-NR, SWD10-NR, SWD12-NR, and SWD14-NR.

[0098] Furthermore, since the subwordline driver regions SWD0-NR and SWD2-NR and the subwordline driver regions SWD8-NR and SWD10-NR are adjacent to each other, sharing of impurity regions may occur. For example, the source region of the pull-down transistor NM0 included in the subwordline driver region SWD0NR and the source region of the holding transistor KP2 included in the subwordline driver region SWD2-NR may share a doping region. The source region of the pull-down transistor NM8 included in the subwordline driver region SWD8-NR and the source region of the holding transistor KP10 included in the subwordline driver region SWD10-NR may share a doping region. All source regions of the pull-down transistors NM0 and NM8 and the hold transistors KP2 and KP10 can also share a doping region.For example, the source region of pull-down transistor KP4, which is included in the partial wordline driver region SWD4-NR, and the source region of pull-down transistor NM6, which is included in the partial wordline driver region SWD6-NR, may share a common doping region. The source region of pull-down transistor KP12, which is included in the partial wordline driver region SWD12-NR, and the source region of pull-down transistor NM14, which is included in the partial wordline driver region SWD14-NR, may share a doping region. All source regions of pull-down transistors NM6 and NM14, and of the holding transistors KP4 and KP12, may also share a doping region.

[0099] In one embodiment, the NMOS transistors of the first to fourth subwordline drivers may be arranged in the subwordline driver regions SWD0NR, SWD2-NR, SWD4-NR, and SWD6-NR, respectively. The first subwordline driver may include a first pull-down transistor and a first hold transistor, and the second subwordline driver may include a second pull-down transistor and a second hold transistor. The third subwordline driver may include a third pull-down transistor and a third hold transistor, and the fourth subwordline driver may include a fourth pull-down transistor and a fourth hold transistor.

[0100] In one embodiment, a first metal line may be electrically connected to the gates of the first to fourth pull-down transistors, and a second metal line may be electrically connected to a gate of the first holding transistor. A third metal line may be electrically connected to a gate of the second holding transistor, a fourth metal line may be electrically connected to a gate of the third holding transistor, and a fifth metal line may be electrically connected to a gate of the fourth holding transistor.

[0101] In one embodiment, the third metal line and the fourth metal line may consist of one metal line and may provide the same partial wordline driver control signal to the gates of the second holding transistor and the third holding transistor. For example, the same partial wordline driver control signal (e.g., PXIB <2> out of Fig. 5) to the gates of the holding transistors in the transistor areas KP2R and KP10R. For example, the same partial word line driver control signal (e.g., PXIB <4> out of Fig. 5) to gates of holding transistors in the transistor regions KP4R and KP12R.

[0102] In one embodiment, the first metal line may extend in a first direction by a first length, then extend in a second direction different from the first direction by a second length, and then extend in the first direction by a third length. After the first metal line extends in the first direction by the third length, the first metal line may extend in a third direction different from the first direction by the second length, and then extend in the first direction by a fifth length. In this case, the first direction may be a direction in which word lines of the memory cell array extend toward one side. The second direction may form a 45-degree angle with the first direction, and the third direction may form a 45-degree angle with the first direction and a 90-degree angle with the second direction.

[0103] Fig. 13 is a diagram for describing the arrangement of the partial word line drivers of Fig. 12.

[0104] With reference to the Fig. 11, Fig. 12 and Fig. 13, transistor regions included in a partial wordline driver according to embodiments of the present disclosure may be implemented by partially changing the arrangement of transistor regions according to the prior art. For example, the arrangement of the partial wordline driver region may be implemented by changing the arrangement (e.g., 311) according to the prior art to any other arrangement (e.g., 315). In this case, the area on the semiconductor substrate occupied by a part of a partial wordline driver may be reduced by the size (e.g., w2 × h2) of a region 319.

[0105] When the arrangement 311 is changed to the arrangement 315, the metal lines can be arranged as in Fig. 8 described.

[0106] Fig. 14 is a diagram illustrating an embodiment of the arrangement of partial wordline drivers according to an embodiment of the present disclosure.

[0107] A plan view of a semiconductor substrate substantially identical to the semiconductor substrate of Fig. 7 is identical, is in Fig. 14. The semiconductor substrate made of Fig. 14 may include the regions corresponding to the NMOS transistors SWD0N, SWD2-N, SWD4-N, SWD6-N, SWD8-N, SWD10-N, SWD12-N and SWD14-N of the sub-wordline drivers SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12 and SWD14, and may further include regions corresponding to the PMOS transistors SWD0-P, SWD2-P, SWD4-P, SWD6-P, SWD8-P, SWD10-P, SWD12-P and SWD14-P of the sub-wordline drivers SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12 and SWD14.

[0108] Referring to Fig. 2, Fig. 3, Fig. 12 and Fig. 14, the partial word line drivers SWD8, SWD10, SWD12 and SWD14 can each control the word lines WL <8> , WL <10> , WL <12> and WL <14> activate, and the word lines WL <8> , WL <10> WL <8> , WL <10> , WL <12> and WL <14> can be word lines extending to one side of the memory cell array in the same direction as the word lines WL <0> , WL <2> , WL <4> and WL <6> and are adjacent to each other. Although in Fig. 14 is not shown, the method is identical or similar to that shown in the Fig. 5, Fig. 6, Fig. 9 and Fig. In the manner described in Figure 12, doping regions can be shared or jointly used between the pull-down transistors NM0, NM2, NM4, NM6, NM8, NM10, NM12 and NM14 and the holding transistors KP0, KP2, KP4, KP6, KP8, KP10, KP12 and KP14 of the partial wordline drivers SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12 and SWD14.

[0109] In one embodiment, a partial word line driver region SWD0-PR may be defined in the semiconductor substrate, which includes a transistor region in which the pull-up transistor PM0 is formed, and a partial word line driver region SWD2-PR may be defined, which includes a transistor region in which the pull-up transistor PM2 is formed. The partial word line driver regions SWD4-PR, SWD6-PR, SWD8-PR, SWD10-PR, SWD12-PR, and SWD14-PR may be defined as described above. The partial wordline driver regions SWD0PR, SWD2-PR, SWD4-PR, SWD6-PR, SWD8-PR, SWD10-PR, SWD12-PR, and SWD14-PR may each include the PMOS transistors SWD0-P, SWD2-P, SWD4-P, SWD6-P, SWD8-P, SWD10-P, SWD12-P, and SWD14-P of the partial wordline drivers SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12, and SWD14.In this case, all subwordline driver regions SWD4-PR, SWD6-PR, SWD8-PR, SWD10-PR, SWD12-PR, and SWD14-PR may be arranged on the first pages of all subwordline driver regions SWD0-NR, SWD2-NR, SWD4-NR, SWD6-NR, SWD8-NR, SWD10-NR, and SWD12-NR. All subwordline driver regions SWD0-PR, SWD2-PR, SWD4-PR, and SWD6-PR may be arranged to form axial symmetry with all subwordline driver regions SWD8-PR, SWD10-PR, SWD12-PR, and SWD14-PR.

[0110] In Fig. 14, the order in which the respective partial word line driver regions SWD0-PR, SWD2-PR, SWD4-PR, SWD6-PR, SWD8-PR, SWD10-PR, SWD12-PR, SWD14-PR, SWD0-NR, SWD2-NR, SWD4-NR, SWD6-NR, SWD8-NR, SWD10-NR, SWD12-NR and SWD14-NR are arranged is shown only as an example.

[0111] In one embodiment, when the order of the partial wordline driver regions SWD0-NR, SWD2-NR, SWD4-NR, SWD6-NR, SWD8-NR, SWD10-NR, SWD12-NR, and SWD14-NR is changed, the order of the partial wordline driver regions SWD0-PR, SWD2-PR, SWD4-PR, SWD6-PR, SWD8-PR, SWD10-PR, SWD12-PR, and SWD14-PR, respectively corresponding thereto, may also be changed together.

[0112] Fig. 15 is a block diagram illustrating a semiconductor memory device with partial wordline drivers according to an embodiment of the present disclosure.

[0113] Referring to Fig. 15, a semiconductor memory device 500 may include a control logic circuit 510, a row decoder 520, a bank array 530, sense amplifiers 531, an input / output gating circuit 540, a column decoder 550, an ECC engine 560, a data input / output buffer 570, and an on-die termination (ODT) circuit 580. The control logic circuit 510 may include a command decoder 511, sense amplifier control logic 512, a mode register 513, a refresh counter 515, an address register 517, and bank control logic 519. The semiconductor memory device 500 may be, for example, a volatile memory device, and in particular, may be a DRAM.

[0114] The bank array 530 may include a plurality of bank arrays. The row decoder 520 may include a plurality of bank row decoders, each connected to the plurality of bank arrays, the column decoder 550 may include a plurality of bank column decoders, each connected to the plurality of bank arrays, and the sense amplifiers 531 may include a plurality of bank sense amplifiers, each connected to the plurality of bank arrays. The plurality of bank arrays, the plurality of bank row decoders, the plurality of bank column decoders, and the plurality of bank sense amplifiers may form a plurality of banks. Each of the plurality of bank arrays may include a plurality of memory cells MCs formed at the intersection points of a plurality of word lines WLs and a plurality of bit lines BLs. The row decoder 520 may be provided to the row decoder 190. Fig. 2, and the partial word line drivers SWD1, SWD2, SWD3, SWD4, SWD5, SWD6, SWD7 etc. Fig. 2 may be included in the bank array 530 and activate corresponding word lines from the plurality of word lines WLs.

[0115] Address register 517 may receive an address ADDR including a bank address, a row address, and a column address from a memory controller. Address register 517 may forward the bank address to bank control logic 519, the row address to row decoder 520, and the column address to column decoder 550.

[0116] Bank control logic 519 may generate a bank control signal in response to the bank address. A bank row decoder and a bank column decoder corresponding to the bank address may be activated based on the bank control signal.

[0117] Refresh counter 515 can generate a refresh row address that is sequentially incremented or decremented under the control of control logic circuit 510. Activated bank-column decoders among the plurality of bank-column decoders can activate sense amplifiers 531 corresponding to the bank address, row address, and column address using input / output gating circuit 540.

[0118] A codeword CW read from one of the plurality of bank arrays may be detected by sense amplifiers corresponding to the one bank array. The ECC engine 560 may perform ECC decoding on the detected codeword CW, and a DQ signal may be output to the memory controller via the data input / output buffer 295 as the ECC decoding result. The data DAT transferred from an input / output pad 590 to the data input / output buffer 295 may be multi-level data. The data input / output buffer 295 may include receive drivers for encoding the multi-level data and receive reference voltages for encoding.

[0119] The data DAT to be written to one of the plurality of bank arrays may be provided to the ECC engine 560, the ECC engine 560 may generate parity bits based on the data DAT and may provide a codeword including the data DAT and the parity bits to the input / output gate circuit 540, and the input / output gate circuit 540 may write the codeword to the one bank array.

[0120] The ODT circuit 580 may be connected to the data input / output pad 590 and the data input / output buffer 570 and perform impedance matching.

[0121] The control logic circuit 510 can control the operation of the memory device 500. For example, the control logic circuit 510 can generate control signals so that the memory device 500 performs the write operation or the read operation. The control logic circuit 510 can include the command decoder 511, which decodes a CMD command received from the memory controller, and the mode register 513 for setting an operating mode of the memory device 500. For example, the command decoder 511 can decode a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc., and generate the control signals corresponding to the CMD command.

[0122] Fig. 16 is a flowchart illustrating a method for designing and manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0123] As in Fig. As shown in Figure 16, a high-level design of a semiconductor integrated circuit can be performed using a computer system (S110). High-level design may mean that an integrated circuit to be designed is described in a high-level computer language. For example, a high-level language such as C may be used. The circuits designed using the high-level design can be described in more detail through register transfer level (RTL) coding or simulation. Furthermore, the code generated by the register transfer level coding can be converted into a netlist and synthesized into a complete semiconductor device. The synthesized schematic circuit can be verified by a simulation tool, and depending on the verification result, an adaptation process can be accompanied.

[0124] A layout design for implementing a logically complete semiconductor integrated circuit on a silicon substrate may be performed (S120). The layout design may be performed, for example, with reference to the schematic circuit synthesized in the high-level design or the corresponding netlist. The layout design may include a routing method for placing and connecting various cells provided in a cell library depending on a prescribed design rule. When designing a layout associated with embodiments of the present disclosure, the design of a plurality of metal lines may be included. The plurality of metal lines may correspond to a plurality of metal layers stacked sequentially on the silicon substrate. Routing, by which data paths are connected, may be performed while each metal line is being arranged.

[0125] The cell library for layout design may also contain information about a cell's operation, speed, and power consumption. The cell library for representing a circuit with a specific gate level as a layout is defined in most layout design tools. Layout may be a method for defining the shape or size of a pattern containing transistors, doping regions, and metal lines to be formed on the silicon substrate. For example, layout patterns such as PMOS, NMOS, N-WELL, gate lines, and metal lines to be arranged thereon may be arranged in a suitable manner to actually form an inverter circuit on the silicon substrate. For this purpose, it may be possible to search for and select suitable inverters from among those predefined in the cell library. Furthermore, routing may be performed for the selected and arranged cells.Most of these processes can be performed automatically or passively by the layout design tool.

[0126] After routing, the layout can be reviewed to determine if there is any part that violates the design rule. Elements to be reviewed include a design rule check (DRC), which verifies that the layout complies with the design rule; an electronic rule check (ERC), which verifies that the internal electrical connection was correctly established without any interrupted connection; and a layout vs. schematic (LVS), which verifies that the layout complies with the gate-level netlist.

[0127] Optical proximity correction (OPC) can be performed (S130). The layout patterns obtained through the layout design can be implemented on the silicon substrate using a photolithography process. In this case, optical proximity correction can be a technique for correcting a distortion phenomenon that may occur during the photolithography process. That is, optical proximity correction can correct the distortion phenomenon, such as refraction or a process effect caused by a light property during exposure to the thus-created pattern. The shapes and positions of the designed layout patterns can be slightly changed during the optical proximity correction.

[0128] A photomask can be fabricated based on the layout modified by optical proximity correction (S140). Generally, the photomask can be fabricated by imaging the layout patterns with a thin chromium layer on a glass substrate.

[0129] A semiconductor device can be manufactured using the generated photomask (S150). Various types of exposure and etching processes can be repeated during the manufacture of the semiconductor device using the photomask. Through these processes, patterns used in the design of a layout on the silicon substrate can be formed sequentially.

[0130] Fig. 17A, Fig. 17B and Fig. 17C are diagrams describing photomasks for forming patterns used in the partial word line drivers of Fig. 12 are included.

[0131] In Fig. 17A, Fig. 17B and Fig. 17C shows positions 711 and 715 respectively, which correspond to positions 311 and 315 in Fig. 13 correspond.

[0132] The photomasks MSKP11-1, MSKP11-2 and MSKP11-3 for producing the arrangement 711 and the photomasks MSKP15-1, MSKP15-2, MSKP15-3 and MSKP15-4 for producing the arrangement 715 are together in Fig. 17A. The photomasks MSKP21-1, MSKP21-2, MSKP21-3, MSKP21-4 and MSKP21-5 for producing the arrangement 711 and the photomasks MSKP25-1, MSKP25-2, MSKP25-3, MSKP25-4 and MSKP25-5 for producing the arrangement 715 are shown in Fig. 17B. The photomasks MSKP31-1 and MSKP31-2 for the production of the arrangement 711 and the photomask MSKP35-1 for the production of the arrangement 715 are shown together in Fig. 17C.

[0133] In one embodiment, the photomasks MSKP11-1, MSKP11-2, MSKP11-3, MSKP15-1, MSKP15-2, MSKP15-3 and MSKP15-4 may be Fig. 17A are used to identify source regions of pull-down transistors of partial word line drivers (e.g. SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12 and SWD14 from Fig. 12).

[0134] In one embodiment, the photomasks MSKP21-1, MSKP21-2, MSKP21-3, MSKP21-4, MSKP21-5, MSKP25-1, MSKP25-2, MSKP25-3, MSKP25-4 and MSKP25-5 may be Fig. 17B for forming drain regions of pull-down transistors and holding transistors of the partial word line drivers (e.g., SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12 and SWD14 of Fig. 12).

[0135] In one embodiment, the photomasks MSKP31-1, MSKP31-2 and MSKP35-1 may be Fig. 17C serve to identify the source regions of the pull-down transistors of the partial word line drivers (e.g. SWD0, SWD2, SWD4, SWD6, SWD8, SWD10, SWD12 and SWD14 from Fig. 12).

[0136] With reference to Fig. 17A, Fig. 17B and Fig. 17C, the photomasks for forming the device 715 may be more powerful than the photomasks for forming the device 711. For example, various patterns included in a partial wordline driver may be shaped to resemble the ideal patterns according to the Fig. 16 described design rule or layout.

[0137] In one embodiment, the performance of the photomasks may be evaluated based on photomask intervals including an average interval, a maximum interval, and a minimum interval between photomasks, a dispersion value and a standard deviation of the photomask intervals, and a height and a width of each of the photomasks.

[0138] In one embodiment, when the performance of the photomask is improved, different patterns can be elaborately formed in the partial wordline driver. For example, different patterns in the partial wordline driver can include the transistors, the doping regions, and the metal lines described with reference to the Fig. 7 to 12 are described.

[0139] Fig. 18 is a block diagram illustrating a computer system with partial wordline drivers according to an embodiment of the present disclosure.

[0140] Fig. 18 is a block diagram showing a computer system including a semiconductor memory device according to embodiments of the present disclosure. Referring to Fig. 18, a computer system 1000 includes a processor 1100, an input / output hub 1200, an input / output controller hub 1300, at least one DRAM module 1400, and a graphics card 1500. The computer system 1000 may be a PC (personal computer), a server computer, a workstation, a laptop, a mobile phone, a smartphone, a PDA (personal digital assistant), a PMP (portable multimedia player), a digital camera, a digital television, a set-top box, a music player, a portable game console, or a navigation system.

[0141] The processor 1100 can perform various computing functions, such as specific calculations or tasks. The processor 1100 can be, for example, a microprocessor or a central processing unit (CPU). The processor 1100 can include one processor core (i.e., a single core) or a plurality of processor cores (i.e., a multi-core). For example, the processor 1100 can include a multi-core such as a dual-core, a quad-core, or a hexa-core. Furthermore, the computer system 1000 with a processor 1100 in Fig. 18, but computer system 1000 may include a plurality of processors. Processor 1100 may also include a cache memory located within the processor or externally.

[0142] The processor 1100 may include a memory controller 1150 that controls the operation of the DRAM module 1400. The memory controller 1150 included in the processor 1100 may be referred to as an integrated memory controller (IMC). A memory interface between the memory controller 1150 and the DRAM module 1400 may be implemented with a channel having a plurality of signal lines or with a plurality of channels. Furthermore, one or more DRAM modules 1400 may be connected to each channel. The memory controller 1150 may be housed in the input / output hub 1200. The input / output hub 1520, which includes the memory controller 1150, may be referred to as a memory controller hub (MCH).

[0143] The DRAM module 1400 may include a plurality of DRAM devices that store data provided by the memory controller 1150. Each of the DRAM devices may be connected to the semiconductor memory device 500 of Fig. 15. That is, each of the DRAM devices may include a semiconductor memory device that reduces the chip size according to the embodiments of the present disclosure and enables patterns included in a partial word row driver to be formed intricately.

[0144] The input / output hub 1200 can manage data transfer between the processor 1100 and devices such as the graphics card 1500. The input / output hub 1200 can be connected to the processor 1510 via various types of interfaces. For example, the input / output hub 1200 and the processor 1100 can be connected via various interface standards such as FSB (Front Side Bus), System Bus, HyperTransport, LDT (Lightning Data Transport), QPI (QuickPath Interconnect), and CSI (Common System Interface). The computing system 1000 with an input / output hub 1200 is Fig. 10, however, the computing system 1000 may include a plurality of input / output hubs.

[0145] The input / output hub 1200 can provide various interfaces to devices. For example, the input / output hub 1200 can provide an AGP (Accelerated Graphics Port) interface, a PCIe (Peripheral Component Interface-Express) interface, a CSA (Communications Streaming Architecture) interface, and so on.

[0146] The graphics card 1500 can be connected to the input / output hub 1200 via APG or PCIe. The graphics card 1500 can control a display device (not shown) to display an image. The graphics card 1500 can include an internal semiconductor memory device and an internal processor for image data processing. According to one embodiment, the input / output hub 1200 can include a graphics device in the input / output hub 1200 along with the graphics card 1500, which is located outside the input / output hub 1200 or in place of the graphics card 1500. The graphics unit included in the input / output center 1520 can be referred to as integrated graphics. The input / output hub 1200, which includes the memory controller and the memory device, can also be referred to as a graphics memory controller hub (GMCH).

[0147] The input / output controller hub 1300 can perform data buffering and interface arbitration, allowing various system interfaces to operate efficiently. The input / output controller hub 1300 can be connected to the input / output hub 1200 via an internal bus. For example, the input / output hub 1200 and the input / output controller hub 1300 can be connected via a DMI (Direct Media Interface), a hub interface, an ESI (Enterprise Southbridge Interface), PCIe, etc.

[0148] The 1300 input / output controller hub can provide various interfaces with peripheral devices. For example, the 1300 input / output controller hub can provide a USB (Universal Serial Bus) port, a SATA (Serial Advanced Technology Attachment) port, a GPIO (General Purpose Input / Output) port, a LPC (Low Pin Count) bus, an SPI (Serial Peripheral Interface), PCI, PCIe, etc.

[0149] In one embodiment, the processor 1100, the input / output hub 1200, and the input / output controller hub 1300 may be implemented with separate chipsets or integrated circuits, or two or more components of the processor 1100, the input / output hub 1200, or the input / output controller hub 1300 may be implemented with one chipset.

[0150] Fig. 19 is a diagram illustrating a data center in which a semiconductor memory device with partial wordline drivers according to an embodiment of the present disclosure is deployed.

[0151] With reference to Fig.19, a data center 3000, which is a facility that collects various types of data and provides services, may be referred to as a "data storage facility." The data center 3000 may be a system for operating a search engine and a database, and may be a computer system used by enterprises such as banks or government agencies. The data center 3000 may include application servers 3100 to 3100n and storage devices 3200 to 3200m. The number of application servers 3100 to 3100n and the number of storage devices 3200 to 3200m may vary depending on the embodiment, and the number of application servers 3100 to 3100n may be different from the number of storage devices 3200 to 3200m.

[0152] The application server 3100 or the storage server 3200 may include at least one of the processors 3110 and 3210 and the memories 3120 and 3220. The memory device 3200 is described here as an example. The processor 3210 may control all operations of the memory device 3200, access the memory 3220, and execute instructions and / or data loaded into the memory 3220. The memory 3220 may be implemented with a DDR SDRAM (Double Data Rate Synchronous DRAM), an HBM (High Bandwidth Memory), an HMC (Hybrid Memory Cube), a DIMM (Dual In-line Memory Module), an Optane DIMM, and / or an NVMDIMM (Non-Volatile DIMM). In some embodiments, the number of processors 3210 included in storage device 3200 and the number of memories 3220 included in storage device 3200 may be selected differently. In one embodiment, processor 3210 and memory 3220 may form a processor-memory pair.In one embodiment, the number of processors 3210 may differ from the number of memories 3220. Processor 3210 may be a single-core processor or a multi-core processor. The above description of storage device 3200 may similarly apply to application server 3100. According to one embodiment, application server 3100 may not include a storage device 3150. Storage server 3200 may include at least one storage device 3250. The number of storage devices 3250 included in storage server 3200 may vary depending on the embodiment.

[0153] Application servers 3100 to 3100n can communicate with storage devices 3200 to 3200m via a network 3300. Network 3300 can be implemented via Fiber Channel (FC) or Ethernet. In this case, the FC can be a medium for relatively fast data transmission and use a high-performance, high-availability optical switch. Storage devices 3200 to 3200m can be deployed as file storage, block storage, or object storage, depending on the access method of network 3300.

[0154] In one embodiment, network 3300 may be a storage-related network such as a storage area network (SAN). For example, the SAN may be an FC-SAN that uses an FC network and is implemented according to an FC protocol (FCP). As another example, the SAN may be an IP-SAN that uses a TCP / IP network and is implemented according to iSCSI (SCSI over TCP / IP or Internet SCSI). In another embodiment, network 3300 may be a general-purpose network such as a TCP / IP network. For example, network 3300 may be implemented according to a protocol such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabrics (NVMe-oF).

[0155] The following mainly describes the application server 3100 and the storage device 3200. A description of the application server 3100 can be applied to another application server 3100n, and a description of the storage server 3200 can be applied to another storage device 3200m.

[0156] The application server 3100 can store data requested by a user or client in one of the storage devices 3200 to 3200m via the network 3300. The application server 3100 can also retrieve data requested by the user or client from one of the storage devices 3200 to 3200m via the network 3300. The application server 3100 can be implemented, for example, as a web server or as a database management system (DBMS).

[0157] The application server 3100 may access a memory 3120n or a storage device 3150n included in another application server 3100n via the network 3300; alternatively, the application server 3100 may access memories 3220 to 3220m or storage devices 3250 to 3250m included in the memory servers 3200 to 3200m via the network 3300. As described above, the application server 3100 may perform various operations on data stored in the application servers 3100 to 3100n and / or the storage devices 3200 to 3200m. For example, the application server 3100 may execute a command to move or copy data between the application servers 3100 to 3100n and / or the storage devices 3200 to 3200m.In this case, the data can be moved from the storage devices 3250 to 3250m of the storage servers 3200 to 3200m to the memories 3120 to 3120n of the application servers 3100 to 3100n directly or via the memories 3220 to 3220m of the storage servers 3200 to 3200m. The data transmitted over the network 3300 can be encrypted for security or privacy purposes.

[0158] Storage server 3200 is described as an example. An interface 3254 may establish a physical connection between processor 3210 and a controller 3251, as well as a physical connection between a NIC 3240 and the controller 3251. Interface 3254 may be implemented, for example, using a Direct Attached Storage (DAS) scheme in which storage device 3250 is directly connected with a dedicated cable. In addition, the 3254 interface can be implemented in various interface types such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (Universal Serial Bus), an SD (Secure Digital) card, MMC (Multi-Media Card), eMMC (embedded Multi-Media Card), UFS (Universal Flash Storage), eUFS (embedded Universal Flash Storage) and / or CF (Compact Flash) card.

[0159] The storage server 3200 may also include a switch 3230 and the NIC 3240. Under the control of the processor 3210, the switch 3230 may selectively connect the processor 3210 to the storage device 3250 or selectively connect the NIC 3240 of the storage device 3250.

[0160] In one embodiment, NIC 3240 may include a network interface card, a network adapter, etc. NIC 3240 may be connected to network 3300 via a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. NIC 3240 may include internal memory, a digital signal processor (DSP), a host bus interface, etc., and may be connected to processor 3210 and / or switch 3230 via the host bus interface. The host bus interface may be implemented using one of the above examples of interface 3254. In one embodiment, NIC 3240 may be integrated with at least one of the following: processor 3210, switch 3230, and storage device 3250.

[0161] In the memory devices 3200 to 3200m or the application servers 3100 to 3100n, a processor can send a command to the memory devices 3150 to 3150n and 3250 to 3250m or the memories 3120 to 3120n and 3220 to 3220m and program or read data. In this case, the data may be data whose errors are corrected by an ECC engine. The data may be data for which data bus inversion (DBI) or data masking (DM) is performed, and it may include cyclic redundancy code (CRC) information. The data may be data that is encrypted for security or privacy reasons.

[0162] Memory devices 3150 to 3150n and 3250 to 3250m may transmit a control signal and a command / address signal to NAND flash memory devices 3252 to 3252m in response to a read command received from the processor. In this case, when reading data from NAND flash memory devices 3252 to 3252m, a read enable signal (RE) may be input as a data output control signal, allowing the data to be output to a DQ bus. A data strobe DQS may be generated using the RE signal. The command and address signals may be latched in a page buffer in response to a rising or falling edge of a write enable signal (WE).

[0163] The controller 3251 can control all operations of the storage device 3250. In one embodiment, the controller 3251 can include an SRAM. The controller 3251 can write data to the NAND flash 3252 in response to a write command or read data from the NAND flash 3252 in response to a read command. The write command and / or the read command can be provided, for example, by the processor 3210 of the storage server 3200, the processor 3210m of another storage server 3200m, or the processors 3110 and 3110n of the application servers 3100 and 3100n. A DRAM 3253 can temporarily store (or buffer) data to be written to or read from the NAND flash 3252. In addition, the DRAM 3253 can store metadata. The metadata is user data or data generated by the control unit 3251 to manage the NAND flash 3252.The storage device 3250 may include a SE (Secure Element) for security or data protection.

[0164] All or part of DRAM 3253 may include a semiconductor memory device according to embodiments of the present disclosure. Accordingly, each DRAM 3253 may include a semiconductor memory device that reduces chip size according to embodiments of the present disclosure and allows patterns included in a partial wordline driver to be formed with complexity.

[0165] As described above, the semiconductor memory device according to embodiments of the present disclosure can reduce the chip size by reducing the area occupied by the partial word line driver on a semiconductor substrate, and can enable patterns included in partial word line drivers to be elaborately formed by adjusting the arrangement of transistors included in a partial word line driver.

[0166] The above description refers to embodiments for implementing the present disclosure. In addition to the embodiments described above, the present disclosure may also include embodiments in which the design is easily changed or can be easily changed. Technologies that can be easily changed and implemented by using the above-mentioned embodiments may also be included in the present disclosure. Accordingly, the scope of the present disclosure should not be limited to the above-mentioned embodiments and should be determined by those that correspond to the claims of the invention and the claims described below. [INDUSTRIAL APPLICABILITY]

[0167] Embodiments of the present disclosure may be usefully used in any electronic device and system including a semiconductor memory device. For example, embodiments of the present disclosure may be usefully used in electronic systems such as a personal computer (PC), a server computer, a data center, a workstation, a laptop, a mobile phone, a smartphone, an MP3 player, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital television, a digital camera, a portable game console, a navigation system, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an e-book, a virtual reality (VR) device, an augmented reality (AR) device, and a drone.

Claims

[1] A semiconductor memory device comprising: a first partial wordline driver having a first pull-down transistor that pulls down a first wordline and a first hold transistor that maintains a voltage level of the pulled-down first wordline in a deactivation interval of the first wordline; and a second partial word line driver having a second pull-down transistor that pulls down a second word line and a second hold transistor that maintains a voltage level of the pulled-down second word line in a deactivation interval of the second word line, wherein a source region of the first pull-down transistor and a source region of the second holding transistor are arranged to share a first doping region on a semiconductor substrate, and wherein a source region of the second pull-down transistor and a source region of the first holding transistor are arranged to share a second doping region on the semiconductor substrate. [2] The semiconductor memory device according to claim 1, wherein a drain region of the first holding transistor and a drain region of the first pull-down transistor are arranged to share a third impurity region on the semiconductor substrate, and wherein a drain region of the second holding transistor and a drain region of the second pull-down transistor are arranged to share a fourth impurity region on the semiconductor substrate. [3] The semiconductor memory device according to claim 2, wherein the first to fourth impurity regions are arranged on the semiconductor substrate so as to be spaced apart from each other and are arranged clockwise in the order of the first impurity region, the fourth impurity region, the second impurity region and the third impurity region with respect to a virtual central axis perpendicular to the semiconductor substrate. [4] A semiconductor memory device according to claim 2, wherein the first doping region and the third doping region are arranged to form point symmetry with the second doping region and the fourth doping region. [5] The semiconductor memory device according to claim 1, wherein the first pull-down transistor and the first hold transistor are arranged on the semiconductor substrate so as to form a point symmetry with the second pull-down transistor and the second hold transistor. [6] The semiconductor memory device according to claim 1 further comprises: a first metal line electrically connected to the gates of the first and second pull-down transistors; a second metal line electrically connected to a gate of the first holding transistor; and a third metal line electrically connected to a gate of the second holding transistor. [7] The semiconductor memory device according to claim 6, wherein the first metal line extends in a first direction by a first length, then extends in a second direction different from the first direction by a second length, and again extends in the first direction by a third length. [8] The semiconductor memory device according to claim 7, wherein the first direction is a direction in which the first word line extends, and wherein the second direction forms an angle of 45 degrees with the first direction. [9] The semiconductor memory device according to claim 7, wherein the second metal line and the third metal line are arranged to be symmetrical with respect to the first metal line extending in the second direction. [10] The semiconductor memory device according to claim 9, wherein the second metal line and the third metal line are arranged on a virtual line perpendicular to the second direction. [11] A semiconductor memory device according to claim 7, wherein the first metal line provides a first word line enable signal to the first and second pull-down transistors, and wherein the second metal line and the third metal line provide first and second hold control signals to the first and second hold transistors, respectively. [12] A semiconductor memory device according to claim 1 further comprising: a first direct contact arranged on the first doping region; and a second direct contact arranged on the second doping region, wherein the first pull-down transistor and the second holding transistor receive a negative voltage via the first direct contact, and wherein the second pull-down transistor and the first holding transistor receive the negative voltage via the second direct contact. [13] The semiconductor memory device according to claim 1, wherein the first and second pull-down transistors and the first and second holding transistors are a metal oxide semiconductor (MOS) transistor having a first conductivity. [14] The semiconductor memory device according to claim 1, wherein the first word line and the second word line extend to one side of a memory cell array and are adjacent to each other. [15] A semiconductor memory device comprising: a memory cell array having a plurality of memory cells connected to a plurality of word lines; and a first sub-word line driver to a fourth sub-word line driver, wherein the first to fourth partial word line drivers each activate a first word line to a fourth word line extending to one side of the memory cell array and adjacent to each other from the plurality of word lines, where the first sub-wordline driver contains: a first pull-down transistor that pulls the first word line down in a deactivation interval of the first word line; and a first holding transistor that maintains a voltage level of the pulled-down first word line in the deactivation interval of the first word line, where the second sub-wordline driver contains: a second pull-down transistor that pulls the second word line down in a deactivation interval of the second word line; and a second holding transistor that maintains a voltage level of the pulled-down second word line in the deactivation interval of the second word line, wherein a source region of the first pull-down transistor and a source region of the second holding transistor are arranged to share a first doping region on a semiconductor substrate, and wherein a source region of the second pull-down transistor and a source region of the first holding transistor are arranged to share a second doping region on the semiconductor substrate. [16] The semiconductor memory device according to claim 15, wherein the third sub-word line driver comprises: a third pull-down transistor that pulls the third word line down in a deactivation interval of the third word line; and a third holding transistor that maintains a voltage level of the pulled-down third word line in the deactivation interval of the third word line, and where the fourth sub-wordline driver contains: a fourth pull-down transistor that pulls the fourth word line down in a deactivation interval of the fourth word line; and a fourth holding transistor that maintains a voltage level of the pulled-down fourth word line in the deactivation interval of the fourth word line. [17] A semiconductor memory device according to claim 16, further comprising: a first metal line electrically connected to the gates of the first to fourth pull-down transistors; a second metal line electrically connected to a gate of the first holding transistor; a third metal line electrically connected to a gate of the second holding transistor; a fourth metal line electrically connected to a gate of the fourth holding transistor; and a fifth metal line electrically connected to a gate of the fourth holding transistor. [18] The semiconductor memory device according to claim 17, wherein the first metal line extends in a first direction by a first length, then extends in a second direction different from the first direction by a second length, and again extends in the first direction by a third length, wherein after the first metal line extends in the first direction by the third length, the first metal line extends in a third direction different from the first direction by a second length and again extends in the first direction by a fifth length. [19] A semiconductor memory device according to claim 18, wherein the first direction is a direction in which the first word line extends, wherein the second direction forms an angle of 45 degrees with the first direction, and wherein the third direction forms an angle of 45 degrees with the first direction and forms an angle of 90 degrees with the second direction. [20] A semiconductor memory device comprising: a first partial wordline driver including a first pull-down transistor that pulls down a first wordline and a first hold transistor that maintains a voltage level of the pulled-down first wordline in a deactivation interval of the first wordline; a second partial wordline driver having a second pull-down transistor that pulls down a second wordline and a second hold transistor that maintains a voltage level of the pulled-down second wordline in a deactivation interval of the second wordline; a first metal line electrically connected to the gates of the first and second pull-down transistors; a second metal line electrically connected to a gate of the first holding transistor; and a third metal line electrically connected to a gate of the second holding transistor, wherein a source region of the first pull-down transistor and a source region of the second keeping transistor are arranged to share a first doping region on a semiconductor substrate, wherein a source region of the second pull-down transistor and a source region of the first holding transistor are arranged to share a second doping region on the semiconductor substrate, wherein a drain region of the first holding transistor and a drain region of the first pull-down transistor are arranged to share a third doping region on the semiconductor substrate, and wherein a drain region of the second holding transistor and a drain region of the second pull-down transistor are arranged to share a fourth doping region on the semiconductor substrate.

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