SEMICONDUCTOR COMPONENT, ENGINE SYSTEM AND VEHICLE

Abstract

A semiconductor device (1) comprises: an upper control input terminal (T1p, T2p, T3p); a lower control input terminal (T1n, T2n, T3n); a power supply terminal (Tvb); a control logic unit (16); a reference power supply circuit (2) configured to receive the power supply voltage input and to generate a reference power supply voltage (VDD) which is supplied to the control logic unit; and a switching circuit (3) with switches (SW1p, SW2p, SW3p, SW1n, SW2n, SW3n) which are each provided for the upper control input signal and the lower control input signal and are switched between on and off in response to the logic level of the upper control input signal and the lower control input signal, respectively.The reference power supply circuit is designed to be activated based on a combination of the logic levels of the upper input control signal and the lower control input signal.

Description

STATE OF THE ART

[0001] The present disclosure relates to a semiconductor device. BACKGROUND

[0002] A semiconductor device is conventionally known in which a half-bridge configured to connect an upper transistor (high-side transistor) and a lower transistor (low-side transistor) is controllable. Such a semiconductor device includes, for example, a motor control device that drives a three-phase brushless DC motor using half-bridges of three phases (U-phase, V-phase, W-phase) (Patent Document 1, for example). PRIOR ART DOCUMENT PATENT DOCUMENT

[0003] Patent Document 1: Japanese Patent Application Publication No. 2014-40404 SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0004] The semiconductor component described above is to be made smaller by reducing the number of external connections (number of pins) while maintaining a comparable function.

[0005] In a configuration that makes a half-bridge drivable, the present disclosure is intended to provide a semiconductor device that can be downsized by reducing the number of external terminals. MEANS TO SOLVE THE PROBLEM

[0006] For example, a semiconductor device according to the present disclosure is a semiconductor device that enables at least one half-bridge to be controlled and includes an upper transistor and a lower transistor. The semiconductor device includes: an upper control input terminal configured to cause an upper control input signal to be input to control the driving of the upper transistor; a lower control input terminal configured to cause a lower input control signal to be input to control the driving of the lower transistor; a power supply terminal configured to allow input of a power supply voltage; a control logic unit; a reference power supply circuit configured to receive the supply of the reference power supply voltage and to cause a reference power supply voltage to be generated to be supplied to the control logic unit; and a switching circuit having switches each provided for the upper control input signal and the lower control input signal and each switched between on and off in response to the logic level of the upper control input signal and the lower control input signal, wherein the reference power supply circuit is configured to be activated based on a combination of the logic levels of the upper input control signal and the lower control input signal. EFFECT OF THE INVENTION

[0007] In a configuration that enables a half-bridge to be driven, the semiconductor device according to the present disclosure is capable of being downsized by reducing the number of external terminals. SHORT DESCRIPTION OF THE CHARACTERS Fig. 1 illustrates the configuration of a motor system using a comparative example; Fig. 2 is a timing chart relating to the activation of the semiconductor device according to the comparative example; Fig. 3 illustrates the configuration of an engine system according to an embodiment of the present disclosure; Fig. 4 shows exemplary specific configurations of a reference power supply circuit and a switching circuit; Fig. 5 is a timing diagram relating to the activation of a semiconductor device according to the embodiment of the present disclosure; Fig. 6 shows the configuration of a switching circuit according to a modified example; and Fig. 7 is an external view illustrating an exemplary configuration of a vehicle mounted with the engine system. DETAILED DESCRIPTION

[0008] An illustrative embodiment of the present disclosure will be described below with reference to the drawings. <1. Comparison example>

[0009] Before describing the embodiment of the present disclosure, a comparative example will be described for comparison. This will clarify a problem addressed in the present disclosure. <1.1 Overall configuration>

[0010] Fig. 1 illustrates the configuration of a motor system 50 according to the comparative example. The motor system 50 according to the Fig. The comparative example illustrated in Figure 1 includes a semiconductor device 10, a brushless DC motor (hereinafter referred to simply as a motor) 35, and a microcontroller 30. The semiconductor device 10 is configured as a gate driver that drives transistors in the three-phase half-bridges UH, VH, and WH provided for driving the three-phase (U-phase, V-phase, W-phase) motor 35. The motor 35 is to be mounted on a vehicle.

[0011] The semiconductor device 10 includes a regulator 11, a reference power supply circuit 12, a Schmitt buffer 13, Schmitt buffers 14A to 14F, a charge pump 15, a control logic unit 16, pre-drivers 17H and 17L, pre-drivers 18H and 18L, and pre-drivers 19H and 19L integrated into a chip, and is packaged by sealing the chip with a sealing member (e.g., resin).

[0012] The semiconductor device 10 includes external terminals (pins) for establishing an electrical connection to the outside, and these terminals include a power supply terminal Tvb, a regulator output terminal Tvcc, an enable terminal Teb, an upper U-phase control input terminal T1p, a lower U-phase control input terminal T1n, an upper V-phase control input terminal T2p, a lower V-phase control input terminal T2n, an upper W-phase control input terminal T3p, a lower W-phase control input terminal T3n, an upper U-phase drive power terminal DUH, an upper U-phase source terminal VSUH, a lower U-phase drive power terminal DUL, a lower U-phase source terminal VSUL, an upper V-phase drive power terminal DVH, an upper V-phase source terminal VSVH, a lower V-phase drive power terminal DVL, a lower V-phase source terminal VSVL,an upper W-phase drive power terminal DWH, an upper W-phase source terminal VSWH, a lower W-phase drive power terminal DWL, a lower W-phase source terminal VSWL.,

[0013] In addition, the semiconductor component 10 comprises Fig. 1, a terminal for connection to a capacitor for the charge pump, a terminal that functions both for the output of the charge pump and for controlling a power supply relay (not shown in the drawings) and is provided between an application terminal for the charging voltage VB and the half-bridges UH, VH, WH, a terminal for controlling a transistor of the motor relay (not shown in the drawings), which is provided between the half-bridges UH, VH, WH and the motor 35, a terminal for connection to a shunt resistor of each phase (a shunt resistor is provided in Fig. 1 not illustrated), a terminal for outputting a voltage generated by amplifying a voltage across the shunt resistor of each phase using an amplifier to the microcontroller 30, a terminal for SPI (serial peripheral interface) communication with the microcontroller 30, and others. <1.2 Motor drive configuration>

[0014] The motor system 50 includes the U-phase half-bridge UH, the V-phase half-bridge VH, the W-phase half-bridge WH, the capacitors C1H, C1L, C2H, C2L, C3H, C3L and R1H, R1L, R2H, R2L, R3H, R3L.

[0015] The U-phase half-bridge UH comprises an upper U-phase transistor Q1H and a lower U-phase transistor Q1L. The upper U-phase transistor Q1H and the lower U-phase transistor Q1L each consist of an n-channel MOSFET (metal oxide semiconductor field-effect transistor). A drain of the upper U-phase transistor Q1H is connected to the application terminal of the power supply voltage VB. The power supply voltage VB is a battery voltage.

[0016] A source of the upper U-phase transistor Q1H is connected to a drain of the lower U-phase transistor Q1L. A source of the lower U-phase transistor Q1L is connected to an application terminal of a ground potential via a shunt resistor not shown in the drawings.

[0017] The pull-down resistor R1H is connected to a gate of the upper U-phase transistor Q1H. The capacitor C1H is connected between the gate and source of the upper U-phase transistor Q1H. The pull-down resistor R1L is connected to a gate of the lower U-phase transistor Q1L. The capacitor C1L is connected between the gate and source of the lower U-phase transistor Q1L.

[0018] Here, in semiconductor device 10, the power supply terminal Tvb is connected to the power supply voltage application terminal VB. The charge pump 15 boosts the power supply voltage VB input to the supply terminal Tvb and outputs a lower boost voltage VCPL and a higher boost voltage VCPH. The lower boost voltage VCPL is an output of the first stage of the charge pump 15. The higher boost voltage VCPH is an output of the second stage of the charge pump 15. VCPH is greater than VCPL.

[0019] The gate of the upper U-phase transistor Q1H is connected to the upper U-phase drive output terminal DUH. An output end of the pre-driver 17H is connected to the upper U-phase driver output terminal DUH. The source of the upper U-phase transistor Q1H is connected to the upper U-phase source terminal VSUH. The pre-driver 17H is connected to an application terminal of the upper boost voltage VCPH and the upper U-phase source terminal VSUH.

[0020] The gate of the lower U-phase transistor Q1L is connected to the lower output terminal DUL of the U-phase drive power supply. The output end of the pre-driver 17L is connected to the lower U-phase driver output terminal DUL. The source of the lower U-phase transistor Q1L is connected to the lower U-phase source terminal VSUL. The pre-driver 17L is connected to an application terminal of the lower boost voltage VCPL and to the lower U-phase source terminal VSUL.

[0021] The V-phase half-bridge VH comprises an upper V-phase transistor Q2H and a lower V-phase transistor Q2L. The upper V-phase transistor Q2H and the lower V-phase transistor Q2L each consist of an N-channel MOSFET. A drain of the upper V-phase transistor Q2H is connected to the application terminal of the power supply voltage VB.

[0022] A source of the upper V-phase transistor Q2H is connected to a drain of the lower V-phase transistor Q2L. A source of the lower V-phase transistor Q2L is connected to an application terminal of a ground potential via a shunt resistor not shown in the drawings.

[0023] The pull-down resistor R2H is connected to the gate of the upper V-phase transistor Q2H. The capacitor C2H is connected between the gate and source of the upper V-phase transistor Q2H. The pull-down resistor R2L is connected to the gate of the lower V-phase transistor Q2L. The capacitor C2L is connected between the gate and source of the lower V-phase transistor Q2L.

[0024] The gate of the upper V-phase transistor Q2H is connected to the upper V-phase drive power output terminal DVH. The output end of the pre-driver 18H is connected to the upper V-phase driver output terminal DVH. The source of the upper V-phase transistor Q2H is connected to the upper V-phase source terminal VSVH. The pre-driver 18H is connected to the upper boost voltage application terminal VCPH and to the upper V-phase source terminal VSVH.

[0025] The gate of the lower V-phase transistor Q2L is connected to the lower V-phase drive power output terminal DVL. The output end of the pre-driver 18L is connected to the lower V-phase drive terminal DVL. The source of the lower V-phase transistor Q2L is connected to the lower V-phase source terminal VSVL. The pre-driver 18L is connected to the lower boost voltage application terminal VCPL and to the lower V-phase source terminal VSVL.

[0026] The W-phase half-bridge WH comprises an upper W-phase transistor Q3H and a lower W-phase transistor Q3L. The upper W-phase transistor Q3H and the lower W-phase transistor Q3L each consist of an N-channel MOSFET. A drain of the upper W-phase transistor Q3H is connected to the application terminal of the power supply voltage VB.

[0027] A source of the upper W-phase transistor Q3H is connected to a drain of the lower W-phase transistor Q3L. A source of the lower W-phase transistor Q3L is connected to an application terminal of a ground potential via a shunt resistor not shown in the drawings.

[0028] The pull-down resistor R3H is connected to the gate of the upper W-phase transistor Q3H. The capacitor C3H is connected between the gate and source of the upper W-phase transistor Q3H. The pull-down resistor R3L is connected to the gate of the lower W-phase transistor Q3L. The capacitor C3L is connected between the gate and source of the lower W-phase transistor Q3L.

[0029] The gate of the upper W-phase transistor Q3H is connected to the upper W-phase output terminal DWH. The output end of the pre-driver 19H is connected to the upper W-phase driver output terminal DWH. The source of the upper W-phase transistor Q3H is connected to the upper W-phase source terminal VSWH. The pre-driver 19H is connected to the upper boost voltage application terminal VCPH and to the upper W-phase source terminal VSWH.

[0030] The gate of the lower W-phase transistor Q3L is connected to the lower W-phase drive output terminal DWL. The output end of the pre-driver 19L is connected to the lower output terminal DWL of the W-phase driver. The source of the lower W-phase transistor Q3L is connected to the lower W-phase source terminal VSWL. The pre-driver 19L is connected to the lower boost voltage application terminal VCPL and the lower W-phase source terminal VSWL.

[0031] The upper U-phase transistor Q1H and the lower U-phase transistor Q1L are connected to a node NU, and the node NU is connected to a U-phase coil (not shown in the drawings) that includes the motor 35. The upper V-phase transistor Q2H and the lower V-phase transistor Q2L are connected to a node NV, and the node NV is connected to a V-phase coil (not shown in the drawings) that includes the motor 35. The upper W-phase transistor Q3H and the lower W-phase transistor Q3L are connected to a node NW, and the node NW is connected to a W-phase coil (not shown in the drawings) that includes the motor 35. The coil of each phase is connected in a so-called star connection. The coil of each phase can be connected in a delta connection.

[0032] In the semiconductor device 10, the regulator 11 regulates down the power supply voltage VB supplied to the power supply terminal Tvb to generate a power supply voltage VCC, and outputs the generated power supply voltage VCC to the microcontroller 30 from the regulator output terminal Tvcc.

[0033] An upper U-phase control input signal IN1P is input from the microcontroller 30 to the upper U-phase control input terminal T1p. The upper U-phase control input signal IN1P is input to the control logic unit 16 via the Schmitt buffer 14A. A lower U-phase control input signal IN1N is input from the microcontroller 30 to the lower control input terminal T1n. The lower U-phase control input signal IN1N is input to the control logic unit 16 via the Schmitt buffer 14B.

[0034] An upper V-phase control input signal IN2P is input from the microcontroller 30 to the upper V-phase control input terminal T2p. The upper V-phase control input signal IN2P is input to the control logic unit 16 via the Schmitt buffer 14C. A lower V-phase control input signal IN2N is input from the microcontroller 30 to the lower control input terminal T2n. The lower V-phase control input signal IN2N is input to the control logic unit 16 via the Schmitt buffer 14D.

[0035] An upper W-phase control input signal IN3P is input from the microcontroller 30 to the upper W-phase control input terminal T3p. The upper W-phase control input signal IN3P is input to the control logic unit 16 via the Schmitt buffer 14E. A lower W-phase control input signal IN3N is input from the microcontroller 30 to the lower W-phase control input terminal T3n. The lower W-phase control input signal IN3N is input to the control logic unit 16 via the Schmitt buffer 14F.

[0036] Each of the control input signals IN1P to IN3N is a pulse signal with a high level and a low level. Each of the Schmitt buffers 14A to 14F binarizes a corresponding one of the control input signals IN1P to IN3N input to it into a high level and a low level and outputs a resulting signal.

[0037] The control logic unit 16 controls the pre-driver 17H based on the output of the Schmitt buffer 14A. This causes the pre-driver 17H to output the upper boost voltage VCPH or a potential at the upper source terminal VSUH of the upper U-phase transistor Q1H to the gate. The upper U-phase transistor Q1H is then driven to switch.

[0038] The control logic unit 16 controls the pre-driver 17L based on the output of the Schmitt buffer 14B. This causes the pre-driver 17L to output the lower boost voltage VCPL or a potential at the lower U-phase source terminal VSUL to the gate of the lower U-phase transistor Q1L. The lower U-phase transistor Q1L is then driven to switch.

[0039] The control logic unit 16 controls the pre-driver 18H based on the output of the Schmitt buffer 14C. This causes the pre-driver 18H to output the upper boost voltage VCPH or a potential at the upper V-phase transistor VSVH to the gate of the upper V-phase transistor Q2H. The upper V-phase transistor Q2H is then driven to switch.

[0040] The control logic unit 16 controls the pre-driver 18L based on the output of the Schmitt buffer 14D. This causes the pre-driver 18L to output the lower boost voltage VCPL or a potential at the lower V-phase source terminal VSVL to the gate of the lower V-phase transistor Q2L. The lower V-phase transistor Q2L is then driven to switch.

[0041] The control logic unit 16 controls the pre-driver 19H based on the output of the Schmitt buffer 14E. This causes the pre-driver 19H to output the upper boost voltage VCPH or a potential at the upper W-phase source terminal VSWH to the gate of the upper W-phase transistor Q3H. The upper W-phase transistor Q3H is then driven to switch.

[0042] The control logic unit 16 controls the pre-driver 19L based on the output of the Schmitt buffer 14F. This causes the pre-driver 19L to output the lower boost voltage VCPL or a potential at the lower W-phase source terminal VSWL to the gate of the lower W-phase transistor Q3L. The lower W-phase transistor Q3L is then driven to switch.

[0043] As described above, the control of each transistor in each of the half-bridges UH, VH, and WH of the respective phases is controlled based on a corresponding one of the control input signals IN1P to IN3N. This makes it possible to control the drive of the motor 35.

[0044] In each of the set signals of the U-phase control input signals IN1P and IN1N, the V-phase control input signals IN2P and IN2N, and the W-phase control input signals IN3P and IN3N, the upper control input signal and the lower control input signal are at mutually complementary levels. Specifically, when one of these signals is at a high level, the other is at a low level. When one of these signals is at a low level, the other is at a high level. In this way, in each of the half-bridges UH, VH, and WH of the respective phases, the upper transistor and the lower transistor are controlled complementarily. Specifically, when one of these transistors is in the on state, the other is off. When one of these transistors is in the off state, the other is in the on state.A dead time (a period of simultaneous turn-off) can be provided when both the upper and lower transistors are turned off simultaneously. In this case, the upper control input signal and the lower control input signal are simultaneously at low levels.

[0045] The transistors in the half-bridges UH, VH, and WH of the respective phases are controlled depending on the tasks of the control input signals, thereby exerting PWM (pulse width modulation) control. This generates drive voltages with phase-shifted AC waveforms at the nodes NU, NV, and NW, which drive motor 35. <1.3 Reference power supply circuit>

[0046] In the semiconductor device 10, an enable signal EB is applied externally to the enable terminal Teb. The enable signal EB is generated from the power supply voltage VB. The enable signal EB input to the enable terminal Teb is converted by the Schmitt buffer 13 into a binarized high-level and low-level enable signal ENA. The enable signal ENA is input to the reference power supply circuit 12.

[0047] The reference power supply circuit 12 includes a low dropout (LDO) (not shown) as a series switching regulator. The power supply voltage VB is converted into a reference power supply voltage VDD by being down-converted by the LDO. The reference power supply voltage VDD is supplied to the control logic unit 16 as a power supply.

[0048] The activation of the semiconductor device 10 is described here with reference to the timing diagram in Fig. 2. In Fig. 2, the power supply voltages VB and VCC, the enable signal EB and the state of the semiconductor device 10 are illustrated in this order from the top.

[0049] When the ignition of a vehicle mounted with the engine system 50 is turned on, the power supply voltage (battery voltage) VB turns on. This causes the power supply voltage VB to start rising from 0 V, as shown in Fig. 2. This also increases the power supply voltage VCC, which is used to supply the microcontroller 30.

[0050] At this time, the enable signal EB also rises. When the enable signal EB exceeds a threshold voltage for the Schmitt buffer 13, the enable signal ENA to be output by the Schmitt buffer 13 switches from a low level to a high level. This activates the reference power supply circuit 12 (LDO) and turns on the reference power supply voltage VDD. Thus, the semiconductor device 10 transitions from a sleep state to a standby state in which the control logic unit 16 is ready to operate in response to the supply of the reference power supply voltage VDD.

[0051] As described above, according to the comparative example, it is possible to activate the semiconductor device 10 using the enable signal EB. Meanwhile, the need for the enable terminal Teb causes the problem of an increased number of external connections (an increased number of pins) of the semiconductor device 10. More specifically, assuming that, for example, a 48-pin package and a 64-pin package are prepared for a semiconductor device, the need for the enable terminal Teb makes it impossible to control the pins to a number equal to or less than 48, resulting in a number of pins such as 49. In some cases, this inevitably requires the use of a 64-pin package for the semiconductor device 10. An increased number of pins leads to an increase in the size of the semiconductor device 10. <2. Embodiment of the present disclosure>

[0052] To solve the above-described problem, the embodiment of the present disclosure described below is implemented. Specifically, the present disclosure aims to reduce the number of pins while maintaining the function of activating a semiconductor device. <2. 1. Configuration of the semiconductor device>

[0053] Fig. 3 illustrates the configuration of an engine system 5 according to the embodiment of the present disclosure. Fig. The engine system 5 illustrated in Figure 3 differs from that of the comparative example described above ( Fig. 1) in that it comprises a semiconductor component 1. Since in the motor system 5, the structures outside the semiconductor component 1 (motor 35, microcontroller 30, half-bridges of the respective phases, etc.) correspond to those of the comparative example, the description of these structures is omitted here.

[0054] As in Fig. 3, the semiconductor component 1 differs from the semiconductor component 10 ( Fig. 1) according to the comparative example in that it includes a reference power supply circuit 2 and a switching circuit 3. Since structures other than the reference power supply circuit 2 and the switching circuit 3 in the semiconductor device 1 are the same as those of the semiconductor device 10 according to the comparative example, the description of these structures is omitted here.

[0055] Unlike the semiconductor device 10 according to the comparative example, the semiconductor device 1 according to the present disclosure does not include the enable terminal EB as an external terminal. The reason why the enable terminal EB becomes unnecessary is explained below. Since the other external terminals of the semiconductor device 1 are identical to those of the semiconductor device 10 according to the comparative example, the description of these external terminals is omitted here. <2. 2. Reference power supply circuit configuration>

[0056] Fig. 4 exemplifies specific configurations of the reference power supply circuit 2 and the switching circuit 3. The reference power supply circuit 2 includes a Zener diode 21, a resistor 22, a PDMOS transistor (P-channel double diffusion MOSFET) 23, a resistor 24, a Zener diode 25, an NDMOS transistor (N-channel double diffusion MOSFET) 26, a resistor 27, a bandgap reference 28, and an LDO 29.

[0057] A cathode of the Zener diode 21 is connected to the application terminal of the power supply voltage VB. An anode of the Zener diode 21 is connected to one end of the resistor 22. The other end of the resistor 22 is connected to the switching circuit 3. The Zener diode 21 and the resistor 22 are connected to a node N1, and the node N1 is connected to a gate of the PDMOS transistor 23. A source of the PDMOS transistor 23 is connected to the application terminal of the power supply voltage VB. A drain of the PDMOS transistor 23 is connected to one end of the resistor 24. The other end of the resistor 24 is connected to a cathode of the Zener diode 25. An anode of the Zener diode 25 is connected to an application terminal of a ground potential. The resistor 24 and the Zener diode 25 are connected to a node N2, and the node N2 is connected to a gate of the NDMOS transistor 26.A drain of the NDMOS transistor 26 is connected to one end of the resistor 27. The other end of the resistor 27 is connected to the application terminal of the power supply voltage VB.

[0058] Switching circuit 3 includes an upper U-phase switch SW1p, a lower U-phase switch SW1n, an upper V-phase switch SW2p, a lower V-phase switch SW2n, an upper W-phase switch SW3p, and a lower W-phase switch SW3n. Each of these switches consists of an n-channel MOSFET.

[0059] A drain of the upper U-phase transistor SW1p is connected to the other end of the resistor 22. A source of the upper U-phase transistor SW1p is connected to a drain of the lower U-phase switch SW1n. A source of the lower U-phase switch SW1n is connected to a drain of the upper V-phase switch SW2p. A source of the upper V-phase switch SW2p is connected to a drain of the lower V-phase switch SW2n. A source of the lower V-phase switch SW2n is connected to a drain of the upper W-phase switch SW3p. A source of the upper W-phase switch SW3p is connected to a drain of the lower W-phase switch SW3n. A source of the lower W-phase switch SW3n is connected to an application terminal of a ground potential. Specifically, all switches SW1p to SW3n are connected in series. The order in which the switches are connected is not limited to the Fig. 4 illustrated configuration, but can be determined arbitrarily.

[0060] The upper U-phase control input signal IN1P is input to a gate of the upper U-phase switch SW1p. The lower U-phase control input signal IN1N is input to a gate of the lower U-phase switch SW1n. The upper V-phase control input signal IN2P is input to a gate of the upper V-phase switch SW2p. The lower V-phase control input signal IN2N is input to a gate of the lower V-phase switch SW2n. The upper W-phase control input signal IN3P is input to a gate of the upper W-phase switch SW3p. The lower W-phase control input signal IN3N is input to a gate of the lower W-phase switch SW3n.

[0061] The activation of the semiconductor device 1 using the Fig. The configuration illustrated in Figure 4 is shown in the timing diagram in Fig. 5 described. Fig. 5 illustrates the power supply voltages VB and VCC, the control input signals IN1P, IN1N, IN2P, IN2N, IN3P, IN3N, and the state of the semiconductor device 1 in this order from the top.

[0062] When the ignition of a vehicle fitted with the engine system 5 is turned on, the power supply voltage (battery voltage) VB turns on. As a result, the power supply voltage VB starts to rise from 0 V (time t1), as shown in Fig. 5. This also increases the power supply voltage VCC, which is used to supply the microcontroller 30.

[0063] After time t2, when the control supply voltages VB and VCC rise to a steady state (high level), the microcontroller 30 switches each of the control input signals IN1P, IN1N, IN2P, IN2N, IN3P, and IN3N from a low level to a high level (time t3). This places each of the switches SW1p through SW3n in an on state, causing a current to flow in the Zener diode 21.

[0064] A voltage V1 generated at node N1 is clamped to a lower voltage than the power supply voltage VB by a breakdown voltage of the Zener diode 21. This causes the PDMOS transistor 23 to be turned on, causing a current to flow in the Zener diode 25. In this way, a voltage V2 to be applied to the gate of the NDMOS transistor 26 (a voltage at node N2) is clamped to a breakdown voltage of the Zener diode 25. Thus, a source voltage at the NDMOS transistor 26, which is substantially equal to the voltage V2, is applied to the bandgap reference 28. The bandgap reference 28 generates a reference voltage Vref based on the source voltage at the NDMOS transistor 26.

[0065] When the reference voltage Vref is turned on, the LDO 29 is activated. The LDO 29 switches the power supply voltage VB down to generate the reference power supply voltage VDD. The generated reference power supply voltage VDD is supplied to the control logic unit 16. In this way, the semiconductor device 1 transitions from a sleep state to a standby state in which the control logic unit 16 is ready for operation in response to the supply of the reference power supply voltage VDD.

[0066] Here, the control logic unit 16 comprises, as in Fig. 4 illustrates a flip-flop 16A. The semiconductor device 1 includes a power-on reset unit 4. The flip-flop 16A has a terminal D to which a reset enable signal RST output from the power-on reset unit 4 is input. The flip-flop 16A has a clock terminal to which a clock signal CLK is input.

[0067] The switching circuit 3 includes a blocking switch 3A. The blocking switch 3A consists of an n-channel MOSFET. A drain of the blocking switch 3A is connected to the drain of the upper U-phase transistor SW1p. A source of the blocking switch 3A is connected to a ground potential via an application terminal. Specifically, the blocking switch 3A is connected in parallel to a configuration in which the switches SW1p to SW3n are connected in series. An output terminal Q of the flip-flop 16A is connected to a gate of the blocking switch 3A.

[0068] A pull-down resistor Rp is connected to the gate of the blocking switch 3A. This allows the gate of the blocking switch 3A to be fixed at a low level using the pull-down resistor Rp, even when the output terminal Q is open while the flip-flop 16A is not activated. At this time, the blocking switch 3A is in an off state.

[0069] When the power-on reset unit 4 determines that the reference power supply voltage VDD is turned on as described above, the power-on reset unit 4 outputs the reset enable signal RST, which represents the reset enable. At this time, the reset enable signal RST is at a high level, so a high-level signal is output from the output terminal Q of the flip-flop 16A. This sets the non-latching switch 3A to an on state. Then, regardless of the logic level of each of the control input signals IN1P to IN3N, a state in which a current flows in the Zener diode 21 and the reference power supply voltage VDD is turned on is maintained.

[0070] As described above, according to the present embodiment, the reference power supply circuit 2 is activated by using the control signals IN1P to IN3N together to drive the corresponding transistors in the half-bridges UH, VH, and WH of the respective phases, thereby enabling the semiconductor device 1 to be activated. After activating the semiconductor device 1, it is possible to maintain the activated state regardless of the logic level of each of the control input signals IN1P to IN3N (for example, during the driving of the motor 35).

[0071] Specifically, the switching circuit 3 according to the present embodiment is provided with switches SW1p to SW3n, each corresponding to all the input control signals IN1P to IN3N for driving the three-phase motor 35. Thus, even if one of the control input signals IN1P to IN3N output from the microcontroller 30 becomes unstable during the rise of the control supply voltage VCC to be supplied to the microcontroller 30, the reference power supply circuit 2 will not be activated unless all the control input signals IN1P to IN3N are brought to high levels. Thus, it is possible to reduce the probability that the reference power supply circuit 2 will be activated at an inadvertent time.In particular, it is possible to activate the reference power supply circuit 2 in a time-controlled manner when the control input signals IN1P to IN3N are brought to high levels according to a control sequence implemented by the microcontroller 30 (with deliberate timing). <2.3 modified examples>

[0072] Fig. Fig. 6 illustrates the configuration of a switching circuit 3 according to a modified example. Unlike the previously illustrated switching circuit ( Fig. 4) are in the Fig. In the switching circuit 3 illustrated in Figure 6, the switches SW1p, Sw2n, and Sw3p are constructed from P-channel MOSFETs instead of N-channel MOSFETs. Thus, after the control supply voltages VB and VCC rise, all switches SW1p through SW3n are turned on to activate the reference power supply circuit 2 when the input control signals are set by the microcontroller 30 to the following values: IN1P = low level, IN1N = high level, IN2P = high level, IN2N = low level, IN3P = low level, and IN3N = high level.

[0073] The switching circuit 3 can be configured to activate the reference power supply circuit 2 when a combination of the logic levels of the control input signals is different from that described above. <2.3 Vehicle registration>

[0074] Fig. 7 is an external view illustrating an exemplary configuration of a vehicle mounted with the previously described engine system 5. In Fig. 7, various types of motors X11 to X17 mounted on a vehicle X are illustrated as exemplary applications of the motor 35.

[0075] X11 is a motor for an electric power steering system. X12 is a motor for an electric oil pump. X13 is a motor for driving headlights. X14 is a motor for an electric parking brake. X15 is a motor for a blade cooling fan in a car. X16 is a motor for opening and closing doors. X17 is a motor for the door lock. <3. Miscellaneous>

[0076] The various technical features disclosed in the present specification can be embodied in any manner other than the above-described embodiments, and allow for many modifications within a scope that does not deviate from the spirit of the technical creations. The above embodiments should be understood to be illustrative and not restrictive in all respects. The technical scope of the present invention is not limited to the above embodiment, but should be understood to include any modified example having a spirit and scope consistent with those of the claims.

[0077] The semiconductor component is not limited to a configuration as a gate driver for controlling motors, but can also be configured, for example, as a gate driver for a DC / DC converter with a half-bridge. <4. Notes>

[0078] As described above, a semiconductor device (1) according to one aspect of the present disclosure has, for example, a configuration (first configuration) in which the semiconductor device makes at least one half-bridge (UH, VH, WH) including an upper transistor (Q1H, Q2H, Q3H) and a lower transistor (Q1L, Q2L, Q3L) drivable, and comprises: an upper control input terminal (T1p, T2p, T3p) configured to allow the input of an upper control input signal (IN1P, IN2P, IN3P) for controlling the driving of the upper transistor; a lower control input terminal (T1n, T2n, T3n) configured to allow the input of a lower control input signal (IN1N, IN2N, IN3N) for controlling the driving of the lower transistor; a power supply terminal (Tvb) configured to allow the input of a power supply voltage (VB); a control logic unit (16); a reference power supply circuit (2) configured to receive the supply of the reference power supply voltage and to cause a reference power supply voltage (VDD) to be generated to be supplied to the control logic unit; and a switching circuit (3) with switches (SW1p, SW2p, SW3p, SW1n, SW2n, SW3n), each provided for the upper control input signal and the lower control input signal, which are switched between on and off in response to the logic level of the upper control input signal and the lower control input signal, wherein the reference power supply circuit is configured to be activated based on a combination of the logic levels of the upper input control signal and the lower control input signal.

[0079] The first configuration may comprise a configuration (a second configuration), wherein the reference power supply circuit (2) is configured to be activated when both the upper input control signal (IN1P, IN2P, IN3P) and the lower control input signal (IN1N, IN2N, IN3N) are at a high level.

[0080] The second circuit may have a configuration (a third circuit) wherein all switches (SW1p, SW2p, SW3p, SW1n, SW2n, SW3n) consist of n-channel MOSFETs and are connected in series between the reference power supply circuit (2) and a ground potential.

[0081] Each of the first to third configurations may have a configuration (a fourth configuration) in which the reference power supply circuit (2) comprises: a first diode (21) whose cathode is connected to an application terminal of the power supply voltage (VB); a first resistor (22) having a first end connected to an anode of the first diode and a second end connected to the switching circuit (3); a PMOS transistor (23) whose gate is connected to a first node (N1) to which the first diode and the first resistor are connected, and whose source is connected to the application terminal of the power supply voltage; a second resistor (24) having a first end connected to a drain of the PMOS transistor; a second diode (25) having its cathode connected to a second end of the second resistor and its anode connected to an application terminal of a ground potential; an NMOS transistor (26) whose gate is connected to a second node (N2) to which the second resistor and the second diode are connected; a third resistor (27) connected between the application terminal of the power supply voltage and a drain of the NMOS transistor; a bandgap reference (28) connected to a source of the NMOS transistor; and an LDO (29) configured to be activated based on a reference voltage output from the bandgap reference and to generate the reference power supply voltage from the power supply voltage.

[0082] Each of the first to fourth configurations may have a configuration (a fifth configuration), wherein the semiconductor device further comprises a detection unit (4) configured to detect the activation of the reference power supply voltage (VDD), wherein the switching circuit (3) comprises a blocking switch (3A) connected in parallel to a configuration in which the switches (SW1p, SW2p, SW3p, SW1n, SW2n, SW3n) are connected in series, and the control logic unit (16) is configured to maintain the blocking switch in an on state based on the detection by the detection unit.

[0083] Each of the first to fifth configurations may have a configuration (a sixth configuration) wherein the at least one half-bridge comprises half-bridges (UH, VH, WH) of a U-phase, a V-phase and a W-phase connected to a three-phase brushless DC motor (35), the upper control input signal comprises an upper U-phase control input signal (IN1P), an upper V-phase control input signal (IN2P) and an upper W-phase control input signal (IN3P), the lower control input signal comprises a U-phase control input signal (IN1N), a V-phase control input signal (IN2N) and a W-phase control input signal (IN3N), and the switches include: an upper U-phase switch (SW1p) that allows the input of the upper U-phase control input signal, an upper V-phase switch (SW2p) that allows the input of the upper V-phase control input signal, an upper W-phase switch (SW3p) that allows the input of the upper W-phase control input signal, a lower U-phase switch (SW1n) that allows the input of the lower U-phase control input signal, a lower V-phase switch (SW2n) that allows the input of the lower V-phase control input signal, and a lower W-phase switch (SW3n) that allows the input of the lower W-phase control input signal.

[0084] The sixth configuration may include a configuration (a seventh configuration) wherein the upper U-phase switch (SW1p), the upper V-phase switch (SW2p), the upper W-phase switch (SW3p), the lower U-phase switch (SW1n), the lower V-phase switch (SW2n), and the lower W-phase switch (SW3n) are all composed of n-channel MOSFETs and are connected in series between the reference power supply circuit (2) and a ground potential.

[0085] A motor system (5) according to one aspect of the present disclosure has a configuration (an eighth configuration), the motor system comprising: the semiconductor device (1) according to the sixth or seventh configuration; the U-phase, V-phase, and W-phase half-bridges (UH, VH, WH) controllable by the semiconductor device; and the three-phase brushless DC motor (35) connected to the U-phase, V-phase, and W-phase half-bridges.

[0086] A vehicle (X) according to an aspect of the present disclosure includes the engine system according to the eighth configuration. INDUSTRIAL APPLICABILITY

[0087] The present disclosure relates to an engine system to be mounted, for example, on a vehicle. LIST OF REFERENCE SYMBOLS 1 semiconductor component 2 Reference power supply circuit 3 Switch circuit 3A blocking switch 4 Power-on reset unit 5 Engine system 10 semiconductor component 11 controllers 12 Reference power supply circuit 13 Schmitt buffers 14A to 14E Schmitt buffer 15 Charge pump 16 Control logic unit 16A flip-flop 17H, 17L pre-driver 18H, 18L pre-driver 19H, 19L pre-driver 21 Zener diode 22 Resistance 23 PDMOS transistor 24 Resistance 25 Zener diode 26 NDMOS transistor 27 Resistance 28 Band gap reference 30 microcontrollers 35 engine 50 engine system C1H, C1L, C2H, C2L, C3H, C3L capacitor Q1H upper U-phase transistor Q1L lower U-phase transistor Q2H upper V-phase transistor Q2L lower V-phase transistor Q3H upper W-phase transistor Q3L lower W-phase transistor R1H pull-down resistor R1L pull-down resistor R2H pull-down resistor R2L pull-down resistor R3H pull-down resistor R3L pull-down resistor Rp pull-down resistor SWln lower U-phase switch SW1p upper U-phase transistor SW2n lower V-phase switch SW2p upper V-phase switch SW3n lower W-phase switch SW3p upper W-phase switch UH U-phase half bridge VH V-phase half bridge WH W-phase half bridge X vehicle QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2014-40404

[0003]

Claims

[1] Semiconductor component which causes at least one half-bridge to be controllable, which comprises an upper transistor and a lower transistor, the semiconductor component comprising: an upper control input terminal configured to cause an upper control input signal to be input to control the driving of the upper transistor; a lower control input terminal configured to cause a lower input control signal to be input to control the driving of the lower transistor; a power supply terminal configured to allow input of a power supply voltage; a control logic unit; a reference power supply circuit configured to receive the supply of the reference power supply voltage and to cause a reference power supply voltage to be generated to be supplied to the control logic unit; and a switching circuit having switches each provided for the upper control input signal and the lower control input signal and each switched between on and off in response to the logic level of the upper control input signal and the lower control input signal, wherein the reference power supply circuit is configured to be activated based on a combination of the logic levels of the upper input control signal and the lower control input signal. [2] The semiconductor device according to claim 1, wherein the reference power supply circuit is configured to be activated when both the upper input control signal and the lower control input signal are at a high level. [3] A semiconductor device according to claim 2, wherein all switches comprise n-channel MOSFETs and are connected in series between the reference power supply circuit and a ground potential. [4] Semiconductor device according to one of claims 1 to 3, wherein the reference power supply circuit (2) comprises: a first diode whose cathode is connected to an application terminal of the power supply voltage; a first resistor having a first end connected to an anode of the first diode and a second end connected to the switching circuit; a PMOS transistor having a gate connected to a first node to which the first diode and the first resistor are connected, and a source connected to the application terminal of the power supply voltage; a second resistor having a first end connected to a drain of the PMOS transistor; a second diode having its cathode connected to a second end of the second resistor and its anode connected to an application terminal of a ground potential; an NMOS transistor whose gate is connected to a second node to which the second resistor and the second diode are connected; a third resistor connected between the application terminal of the power supply voltage and a drain of the NMOS transistor; a bandgap reference connected to a source of the NMOS transistor; and an LDO configured to be activated based on a reference voltage output from the bandgap reference and to generate the reference power supply voltage from the power supply voltage. [5] Semiconductor device according to one of claims 1 to 4, further comprising: a detection unit configured to detect the activation of the reference power supply voltage, wherein the switching circuit comprises a blocking switch connected in parallel in a configuration in which the switches are connected in series, and the control logic unit is configured to maintain the blocking switch in an on state based on the detection by the detection unit. [6] Semiconductor device according to one of claims 1 to 5, wherein which comprises at least one half-bridge of a U-phase, a V-phase and a W-phase connected to a three-phase brushless DC motor, the upper control input signal comprises an upper U-phase control input signal, an upper V-phase control input signal and an upper W-phase control input signal, the lower control input signal comprises a U-phase control input signal, a V-phase control input signal and a W-phase control input signal, and the switches include: an upper U-phase switch that allows the input of the upper U-phase control input signal, an upper V-phase switch that allows the input of the upper V-phase control input signal, an upper W-phase switch that allows the input of the upper W-phase control input signal, a lower U-phase switch that allows the input of the lower U-phase control input signal, a lower V-phase switch that allows the input of the lower V-phase control input signal, and a lower W-phase switch that allows the input of the lower W-phase control input signal. [7] The semiconductor device according to claim 6, wherein the upper U-phase switch, the upper V-phase switch, the upper W-phase switch, the lower U-phase switch, the lower V-phase switch, and the lower W-phase switch all comprise N-channel MOSFETs and are connected in series between the reference power supply circuit and a ground potential. [8] Engine system comprising: the semiconductor device according to claim 6 or 7; the half-bridges of the U-phase, the V-phase and the W-phase can be controlled by the semiconductor component; and the three-phase brushless DC motor connected to the U-phase, V-phase and W-phase half-bridges. [9] A vehicle having the engine system according to claim 8.

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