Semiconductor Device and Semiconductor Module

Abstract

A semiconductor device is provided comprising: a semiconductor substrate with an active section having a transistor section; an emitter electrode arranged over a front face of the semiconductor substrate; and a protective film arranged over the emitter electrode, wherein the active section comprises: an emitter region of a first conductivity type arranged on the front face of the semiconductor substrate; a contact region of a second conductivity type; and a plurality of trench sections, wherein the emitter electrode includes an exposed section not covered by the protective film, and wherein the active section comprises: in a region where the exposed section is arranged, a first region; and a second region arranged on an outer circumference of the first region and having a lower channel density than the first region.

Description

BACKGROUND 1. TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device and a semiconductor module. 2. STATE OF THE ART

[0002] Patent Document 1 discloses that solder bonding is used to electrically connect a device electrode and a terminal with a coupling conductor. Prior art documentsPatent document

[0003] Patent Document 1: Japanese Patent Application Publication No. 2009-38140

[0004] When operating the transistor section, it is necessary to suppress local concentration of current. GENERAL REVELATION

[0005] A first aspect of the present invention relates to a semiconductor device.A semiconductor device comprising: a semiconductor substrate having an active section including a transistor section; an emitter electrode disposed over a front surface of the semiconductor substrate; and a protective film disposed over the emitter electrode, the active section comprising: an emitter region of a first conductivity type disposed on the front surface of the semiconductor substrate; a contact region of a second conductivity type; and a plurality of trench sections, the emitter electrode including an exposed section not covered by the protective film, and the active section comprising: a first section in a section where the exposed section is disposed; and a second section disposed at an outer periphery of the first section and having a lower channel density than the first section.

[0006] In a plan view of the semiconductor substrate, the second region may be arranged to surround the entire outer periphery of the first region.

[0007] In a plan view of the semiconductor substrate, an area of ​​the first region may be equal to or greater than 0.5 times and equal to or less than ten times an area of ​​the second region.

[0008] In a plan view of the semiconductor substrate, the first region may be spaced from an end portion of the exposed portion by at least 0 µm and at most 1500 µm.

[0009] A channel density of a mesa portion of the transistor portion in the second region may be smaller than a channel density of a mesa portion of the transistor portion in the first region.

[0010] The emitter region and the contact region may be arranged alternately in a trench extension direction in a mesa portion of the transistor portion, and in a plan view of the semiconductor substrate, a ratio of the emitter region to the contact region in a mesa portion of the transistor portion in the first region may be greater than a ratio of the emitter region to the contact region in a mesa portion of the transistor portion in the second region.

[0011] In a plan view of the semiconductor substrate, a length of the contact region arranged in a mesa portion of the transistor portion in the second region in a trench extension direction may be greater than a length of the contact region arranged in a mesa portion of the transistor portion in the first region in the trench extension direction.

[0012] In a plan view of the semiconductor substrate, the emitter region of the transistor section in the second region may be arranged to correspond to the emitter region of the transistor section in the first region in a trench arrangement direction, and in a plan view of the semiconductor substrate, the emitter region of the transistor section in the first region may be arranged to correspond to either the emitter region or the contact region of the transistor section in the second region in the trench arrangement direction.

[0013] A channel density of a mesa portion of the transistor portion in the second region may be equal to or less than 50% of a channel density of a mesa portion of the transistor portion in the first region.

[0014] The active portion may include a diode portion arranged alternately with the transistor portion in a trench arrangement direction, and in a plan view of the semiconductor substrate, a ratio of the diode portion to the transistor portion in the second region may be larger than a ratio of the diode portion to the transistor portion in the first region.

[0015] In a plan view of the semiconductor substrate in the second region, an area of ​​the transistor section may be larger than an area of ​​the diode section.

[0016] A second aspect of the present invention relates to a semiconductor module comprising the semiconductor device according to any one of the first aspects.

[0017] The semiconductor module may include: a soldering portion disposed above the emitter electrode; and a lead frame disposed on the soldering portion and electrically connected to the emitter electrode.

[0018] In a plan view of the semiconductor substrate, a boundary between the first region and the second region may be arranged within an end portion of the lead frame.

[0019] A distance between a boundary between the first region and the second region and the end portion of the lead frame may be equal to or greater than 400 µm and equal to or less than 800 µm.

[0020] An outer circumferential end of the second region may be located outside an end portion of the soldering portion.

[0021] A distance between the outer circumferential end of the second region and the end portion of the soldering portion may be equal to or greater than 0 µm and equal to or less than 1500 µm.

[0022] The summary section does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a subcombination of the features described above. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing an example of a semiconductor device 100 according to an embodiment. Fig. 2 is an example of an enlarged view of the active section 120. Fig. 3 is a diagram showing an example of a cross section aa in Fig. 2 shows. Fig. 4 is a diagram showing an example of the configurations of a first region 121 and a second region 122. Fig. 5 is a plan view showing an example of the mesa section 60. Fig. Figure 6 is another example of an enlarged view of the active portion 120. Fig. 7 is a diagram showing an example of a cross section bb in Fig. 6 shows. Fig. 8 is a diagram showing an exemplary arrangement of the transistor section 70 and the diode section 80. Fig. 9 is a plan view showing an example of a semiconductor module 300 according to an embodiment. Fig. 10 is a side view of the semiconductor substrate 10 mounted on a packaging substrate 200. DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0023] The present invention will be described below using embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all combinations of features described in the embodiments are essential to the solution of the invention.

[0024] As used herein, one side in a direction parallel to a depth direction of a semiconductor substrate is referred to as the "upper" side, and the other side is referred to as the "lower" side. One of two main surfaces of a substrate, layer, or other element is referred to as the upper surface, and another surface is referred to as the lower surface. "Upper" and "lower" directions are not limited to a direction of gravity or a direction in which a semiconductor device is mounted.

[0025] In this specification, technical matters may be described using the orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely specify the relative positions of components and do not restrict a specific direction. For example, the Z-axis is not limited to indicating the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without describing the symbols, it means that the direction is parallel to the +Z-axis and -Z-axis. As used herein, it may also be referred to as "viewed from above" when viewed from the +Z-axis direction.

[0026] In this specification, a case where a term such as "same" or "equal" is mentioned may include a case where an error is present due to manufacturing variation or the like. The error is, for example, within 10%.

[0027] In this specification, a conductivity type of a doping region in which an impurity has been doped is described as P-type or N-type. It should be noted that conductivity types of respective doping regions may each have opposite polarities. Furthermore, in this specification, a description as P + -like or N + -type a higher doping concentration than P-type or N-type, and a description as P - -like or N - -type means a lower doping concentration than P-type or N-type.

[0028] In the present specification, the doping concentration refers to a concentration of an impurity activated as a donor or an acceptor. Herein, in some cases, a concentration difference between a donor and an acceptor may be a higher concentration of the majority of the donor or acceptor. The concentration difference may be measured by the capacitance-voltage profiling (CV) method. In addition, a carrier concentration measured by the scattering resistance (SR) measurement method may be a concentration of a donor or an acceptor. Furthermore, in a case where a concentration distribution of a donor or an acceptor has a peak, the peak value may be a concentration of a donor or an acceptor in the region.For example, if a concentration of a donor or an acceptor is approximately uniform in a region where the donor or the acceptor is present, the average value of a concentration of a donor or an acceptor in the region may be a donor or acceptor concentration.

[0029] Fig. 1 is a plan view showing an example of a semiconductor device 100 according to an embodiment. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed from a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate 10 has one end face 102 in plan view. The semiconductor substrate 10 of the present example has two sets of end faces 102 that face each other in plan view. Fig. 1 shows a pair of a first end face 102-1 and a second end face 102-2 facing each other. In Fig. 1, a direction parallel to the first end side 102-1 and the second end side 102-2 is referred to as a Y-axis direction, and a direction perpendicular to the first end side 102-1 and the second end side 102-2 is referred to as an X-axis direction.

[0030] The semiconductor substrate 10 includes an active portion 120. The active portion 120 is a region where a main current flows in the depth direction between the front surface and a back surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in an on state. In the present example, a region corresponding to an emitter electrode 52 is defined as the active portion 120. The active portion 120 may include a transistor portion including a transistor device such as an IGBT (Insulated Gate Bipolar Transistor).

[0031] The active section 120 may also include a diode section comprising a diode device such as a FWD (freewheeling diode).

[0032] The semiconductor device 100 includes the emitter electrode 52 and a pad 50 disposed over a front surface of the semiconductor substrate 10. The emitter electrode 52 and the pad 50 are electrodes containing a metal such as aluminum. A dielectric film is disposed between the emitter electrode 52 and the pad 50 and the semiconductor substrate 10. The emitter electrode 52 and the pad 50 are connected to the semiconductor substrate 10 via a contact hole formed in the dielectric film. Fig. 1, the dielectric film and the contact hole were omitted.

[0033] The emitter electrode 52 is arranged above the active section 120. The emitter electrode 52 is connected to the active section 120 via the contact hole described above. The emitter electrode 52 includes an exposed section 53 that is not covered by a protective film, which will be described below. The exposed section 53 is an area including a center Ac of the active section 120. The center Ac of the active section 120 is the geometric center of gravity of the active section 120 in a plan view. A lead frame, which will be described below, is arranged on a top surface of the exposed section 53. The emitter electrode 52 is electrically connected to the lead frame, and a predetermined emitter voltage is applied thereto.

[0034] The emitter electrode 52 is formed of a material containing a metal. For example, at least a portion of the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy. The emitter electrode 52 may have a barrier metal formed of titanium, a titanium compound, or the like under a portion formed of aluminum or the like. The emitter electrode 52 may further include a plug formed of tungsten or the like filled in the contact hole to be in contact with the barrier metal and aluminum or the like. A plating layer may also be disposed on an upper surface of the emitter electrode 52. The plating layer may be a metal material different from the emitter electrode 52, such as nickel and gold.

[0035] The pad 50 is, for example, a gate pad. The emitter electrode 52 and the pad 50 are arranged so that they are separated from each other in plan view. A wire or the like is connected to an upper surface of the pad 50, through which a predetermined gate voltage is applied. The gate voltage applied to the pad 50 is supplied to the transistor section of the active section 120 via a gate mover or the like, which will be described below. The pad 50 of the present example is arranged in the vicinity of the end face 102-1.

[0036] In addition to the configuration of semiconductor device 100, an anode pad 174, a cathode pad 176, and a current sensing pad 172 are provided. Semiconductor device 100 may further include a current sensor with a structure similar to the transistor portion of the semiconductor substrate to simulate the operation of the transistor portion and detect a current flowing between the front surface and the back surface of the semiconductor substrate. The anode pad 174, the cathode pad 176, and the current sensing pad 172 of the present example are arranged in the vicinity of the end face 102-2, and a region where these pads are arranged may be referred to as a pad region.

[0037] The semiconductor device 100 includes a protective film 150 disposed over the front surface of the semiconductor substrate 10. The protective film 150 is formed of polyimide or the like and covers the front surface side of the semiconductor substrate 10 to protect the front surface device structure. Fig. 1 shows a region where the protective film 150 is shown hatched with diagonal lines. The protective film 150 includes an opening portion corresponding to the exposed portion 53 on the emitter electrode 52. The protective film 150 may also include opening portions at positions corresponding to the pad 50, the anode pad 174, the cathode pad 176, the current sensing pad 172, and the pad area.

[0038] In Fig. 1, additional active sections may also be provided above and below the pad 50 and the pad area (in the +Y-axis direction and the -Y-axis direction).

[0039] In this case, the emitter electrode 52 may be provided to extend over the additional active portion.

[0040] Fig. 2 is an example of an enlarged view of the active section 120. The active section 120 of the present example includes the transistor section 70. Fig. 2 shows a region of the active portion 120 around an end portion on the side in the -Y-axis direction.

[0041] The semiconductor device 100 may include a gate runner 48 arranged to surround the active portion 120 in plan view. The gate runner 48 is a wiring formed from a conductive material such as polysilicon with an impurity added thereto or metal. The gate runner 48 supplies a gate voltage to the transistor portion 70, which is applied to the gate pad 50. The gate runner 48 may be arranged over a well region 11, which will be described below.

[0042] The semiconductor device 100 of the present example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15, which are arranged inside the front surface side of the semiconductor substrate 10.

[0043] Fig. Figure 2 shows a region where the emitter electrode 52 is arranged. The emitter electrode 52 of the present example is arranged in a region that does not overlap with the gate slider 48, but can overlap with the gate slider 48. In this case, a dielectric film is arranged between the emitter electrode 52 and the gate slider 48. An interlayer dielectric film is arranged between the emitter electrode 52 and the front surface of the semiconductor substrate 10, although in Fig. 2 is omitted. The interlayer dielectric film of the present example is provided with contact holes 56 and a contact hole 54 penetrating the interlayer dielectric film.

[0044] The emitter electrode 52 is in contact with the emitter region 12, the contact region 15 and the base region 14 on the front surface of the semiconductor substrate 10 through the contact hole 54.

[0045] Furthermore, the emitter electrode 52 is connected to a conductive dummy portion in the dummy trench portion 30 via the contact hole 56. A connecting portion 25 formed from a conductive material such as polysilicon doped with the impurities may be disposed between the emitter electrode 52 and the conductive dummy portion. The connecting portion 25 is disposed above the front surface of the semiconductor substrate 10. A dielectric film is disposed between the connecting portion 25 and the front surface of the semiconductor substrate 10.

[0046] A dielectric film is disposed between the gate slider 48 and the front surface of the semiconductor substrate 10. The gate slider 48 is connected to a gate conductive portion in the gate trench portion 40 on the front surface of the semiconductor substrate 10. The gate slider 48 is not connected to the conductive dummy portion in the dummy trench portion 30. The gate slider 48 of the present example is arranged to overlap with an edge portion 41 of the gate trench portion 40. The edge portion 41 is an end portion closest to the gate slider 48 in the gate trench portion 40. At the edge portion 41 of the gate trench portion 40, the gate line portion is exposed to the front surface of the semiconductor substrate 10 to be in contact with the gate slider 48.

[0047] One or more gate trench sections 40 and one or more dummy trench sections 30 are arranged at a predetermined interval along a predetermined arrangement direction in a region of the transistor section 70. In the present example, the arrangement direction (also referred to as a trench arrangement direction) is the X-axis direction. In the present example, one or more gate trench sections 40 and one or more dummy trench sections 30 may be arranged alternately along the arrangement direction.

[0048] The gate trench portion 40 of the present example may include two extension portions 39 (a straight portion of a trench along an extension direction) extending along an extension direction (also referred to as a trench extension direction) perpendicular to the arrangement direction, and the edge portion 41 connecting the two extension portions 39. The extension direction of the present example is the Y-axis direction. At least a part of the edge portion 41 is preferably provided in a curved shape. The end portions, which are the ends of the straight shape along the extension direction, of the two extension portions 39 of the gate trench portion 40 are connected by the edge portion 41, so that the electric field strength at the end portions of the extension portions 39 can be reduced.

[0049] The dummy trench portion 30 of the present example is provided between the respective extending portions 39 of the gate trench portion 40. These dummy trench portions 30 may have a straight shape to extend in the extending direction.

[0050] The emitter electrode 52 is provided over the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The well region 11 is provided at a predetermined distance from the contact hole 54. A diffusion depth of the well region 11 may be greater than a depth of the gate trench portion 40 and the dummy trench portion 30. The end portions of the gate trench portion 40 and the dummy trench portion 30 in the extension direction are provided in the well region 11.

[0051] The mesa portion 60, which is arranged between the adjacent trench portions, is provided with the base region 14. A mesa portion refers to a portion of the semiconductor substrate 10 arranged between the trench portions and a region on the front surface side with respect to the deepest bottom portion of the trench portion. The base region 14 is of the second conductivity type and has a doping concentration lower than that of the well region 11. The base region 14 of this example is P-type, and the well region 11 is P + -like.

[0052] The contact region 15 of the second conductivity type, which has a doping concentration higher than that of the base region 14, is provided on the upper surface of the base region 14 of the mesa section 60. The contact region 15 of the present example is P +-like. The well region 11 may be provided so as to be separated from the contact region 15 which is the outermost in the trench extension direction (the -Y-axis direction in Fig. 2) is arranged below the contact regions 15 in the direction of the gate rotor 48. In addition, in the transistor section 70, the emitter regions 12 of the first conductivity type, which have a doping concentration higher than that of a drift region 18, which will be described below, are selectively arranged on the upper surface of the base region 14. The emitter region 12 of the present example N + -like.

[0053] The contact region 15 and the emitter region 12 are each formed from one of the adjacent trench sections to the other. One or more contact regions 15 and one or more emitter regions 12 of the transistor section 70 are arranged such that they are alternately exposed to the upper surface of the mesa section 60 along the extension direction of the trench section.

[0054] In another example, in the mesa section 60 of the transistor section 70, the contact regions 15 and the emitter regions 12 may also be arranged in a stripe pattern along the extension direction. For example, the emitter region 12 is arranged in a region in direct contact with the trench section, and the contact region 15 is arranged in a region enclosed between the emitter regions 12.

[0055] In transistor section 70, contact hole 54 is arranged above contact region 15 and emitter region 12. Contact hole 54 is not arranged in a region corresponding to base region 14 or well region 11.

[0056] Fig. 3 is a diagram showing an example of a cross section aa in Fig. 2. Cross section aa lies on an XZ plane passing through the emitter region 12. A semiconductor device 100 in this example includes a semiconductor substrate 10, an interlayer dielectric film 38, an emitter electrode 52, and a collector electrode 24 in cross section. The emitter electrode 52 is arranged on the upper surfaces of the interlayer dielectric film 38 and the semiconductor substrate 10.

[0057] The collector electrode 24 is arranged on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as metal. As used herein, a direction in which the emitter electrode 52 and the collector electrode 24 are connected to each other is referred to as the depth direction. The depth direction of the present example refers to the Z-axis direction.

[0058] The semiconductor substrate 10 can be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride or the like. In the present example, the semiconductor substrate 10 is a silicon substrate. The P-type base region 14 is arranged on the cross-sectional side of the front surface 21 of the semiconductor substrate 10.

[0059] On the cross section, in the side of the front surface 21 of the semiconductor substrate 10 in the transistor section 70 of the N +-type emitter region 12, the P-type base region 14 and the N + -like collecting area 16 are arranged in this order from the side of the front surface 21 of the semiconductor substrate 10.

[0060] In the transistor section 70, an N-type drift region 18 is disposed below the accumulation region 16. The accumulation region 16, which has a higher concentration than the drift region 18, is disposed between the drift region 18 and the base region 14, so that it is possible to increase a charge injection enhancement effect (IE effect), thereby reducing the on-state voltage.

[0061] The collection region 16 of the present example is arranged in each mesa section 60 of the transistor section 70. The collection region 16 may be arranged to cover the entire lower surface of the base region 14 in each mesa section 60. The N +-like buffer region 20 is arranged below the drift region 18. In addition, a plurality of collection regions 16 may be arranged in the depth direction.

[0062] The buffer region 20 is provided at the bottom of the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 can function as a field stop layer to prevent a depletion layer extending from the bottom surface of the base region 14 from affecting the P + -like collector area 22 and the N + -like cathode region 82. The P + -like collector area 22 is arranged below the buffer area 20.

[0063] The one or more gate trench portions 40 and the one or more dummy trench portions 30 are provided in the front surface 21 side of the semiconductor substrate 10. Each trench portion is provided to extend from the front surface 21 of the semiconductor substrate 10 and penetrate the base region 14 to reach the drift region 18. In a region where at least one of the emitter region 12, the contact region 15, and the collection region 16 is provided, each trench portion penetrates these regions to reach the drift region 18.

[0064] The trench portion penetrating the impurity region is not limited to those formed in the order of forming the impurity region and then forming the trench portion. The configuration of the trench portions penetrating the impurity region also includes a configuration of forming the trench portions and then forming the impurity region between the trench portions.

[0065] The gate trench portion 40 includes a gate dielectric film 42 and a gate line portion 44 disposed on the front surface 21 side of the semiconductor substrate 10. The gate dielectric film 42 is disposed to cover the inner wall of the gate trench portion 40. The gate dielectric film 42 can be formed by oxidizing or nitriding semiconductors on the inner wall of the gate trench portion 40. The gate line portion 44 is disposed within the gate dielectric film 42 in the gate trench portion 40. That is, the gate dielectric film 42 insulates the gate line portion 44 from the semiconductor substrate 10. The gate line portion 44 is formed of a conductive material such as polysilicon.

[0066] The gate line portion 44 includes a region opposite the base region 14, which is sandwiched between the gate dielectric film 42. The gate trench portion 40 in cross section is covered by the interlayer dielectric film 38 on the front surface 21 of the semiconductor substrate 10. When a predetermined voltage is applied to the gate line portion 44, an inversion layer of electrons serving as a channel is formed on a surface layer in contact with the base region 14 and the gate trench.

[0067] The dummy trench sections 30 may have the same structure as the gate trench sections 40 in cross section. The dummy trench section 30 includes a dummy trench, a dummy dielectric film 32, and a dummy conductive section 34 arranged on the front surface 21 side of the semiconductor substrate 10. The dummy dielectric film 32 is arranged to cover an inner wall of the dummy trench. The dummy conductive section 34 is arranged in the dummy trench and is located within the dummy dielectric film 32. The dummy dielectric film 32 insulates the dummy conductive section 34 from the semiconductor substrate 10. The dummy conductive section 34 may be formed of the same material as the gate conductive section 44.

[0068] Fig. 4 is a diagram showing an example of the configurations of a first region 121 and a second region 122. The protective film 150 includes an opening portion corresponding to the exposed portion 53 on the emitter electrode 52. Fig. 4 shows a region where the protective film 150 is shown hatched with diagonal lines. A lead frame is disposed on top of the exposed portion 53, and the emitter electrode 52 is electrically connected to the lead frame. A dimension of the exposed portion 53 is determined according to a dimension of the disposed lead frame.

[0069] The first region 121 of the present example is a region including the center Ac of the active portion 120 in a region of the exposed portion 53 corresponding to the exposed portion 53. The center Ac of the active portion 120 is the geometric center of gravity of the active portion 120 in a plan view. The lead frame is arranged to cover the first region 121. In a plan view, a distance W between the first region 121 and an end portion of the exposed portion 53 is at least equal to or greater than 0 µm and equal to or less than 1500 µm.

[0070] The second region 122 is a region located on an outer periphery of the first region 121 in a region of the active portion 120 corresponding to the exposed portion 53 and having a lower channel density than the first region 121. The second region 122 of the present example is arranged to surround the entire outer periphery of the first region 121 in plan view, and an outer circumferential end of the second region 122 is aligned with the end portion of the exposed portion 53. Note that in another example, the second region 122 may be arranged only in a part of a region of the outer periphery of the first region 121. An end portion of the lead frame is arranged in the second region 122.

[0071] When operating the transistor section 70, a current generated in the vicinity of a region where the lead frame is disposed flows toward the lead frame in the semiconductor substrate 10. Therefore, current accumulation occurs particularly in a region from the vicinity of an end portion of the lead frame to an end portion of a solder portion connecting the lead frame to the upper surface of the emitter electrode 52. In this region, an increase in current density may cause a decrease in turn-off resistance and a decrease in reliability due to heat generation.

[0072] According to the semiconductor device 100 of the present example, the channel density of the second region 122, in which the end portion of the lead frame is disposed, is lower than the channel density of the first region 121 directly below the lead frame to suppress current generation in the second region 122. This reduces current accumulation in the second region 122 when driving the transistor portion 70, so that a reduction in turn-off resistance and a reduction in reliability due to heat generation can be suppressed.

[0073] In plan view, an area of ​​the first region 121 is equal to or larger than 0.5 times and equal to or smaller than ten times an area of ​​the second region 122. The area ratio is within this range, so that a sufficient amount of currents can be secured throughout the entire semiconductor device 100 while reducing the current accumulation in the second region 122.

[0074] The outer peripheral end of the second region 122 of the present example is aligned with the end portion of the exposed portion 53. However, in another example, it may be located within the end portion of the exposed portion 53. In this case, the outer side of the second region 122 may have the front surface device structure similar to that of the first region 121. This may reduce current accumulation in the second region 122 while facilitating current generation across the entire active portion 120.

[0075] Fig. 5 is a plan view showing an example of the mesa section 60. The active section 120 of the present example includes the transistor section 70 as shown in Fig. 2 and Fig. 3. The emitter regions 12 and the contact regions 15 are arranged alternately in the mesa section 60 of the transistor section 70 in the trench extension direction.

[0076] In the present example, the channel density of the mesa section 60 of the transistor section 70 in the second region 122 is smaller than that of the mesa section 60 of the transistor section 70 in the first region 121. The channel density in the transistor section 70 is determined depending on a ratio of the contact regions 15 and the emitter regions 12 in the trench extension direction. In plan view, a ratio of the emitter regions 12 to the contact regions 15 in the mesa section 60 of the transistor section 70 in the first region 121 is greater than a ratio of the emitter regions 12 to the contact regions 15 in the mesa section 60 of the transistor section 70 in the second region 122.

[0077] In plan view, a length L2 of the contact region 15 arranged in the mesa section 60 of the transistor section 70 in the second region 122 in the trench extension direction is greater than a length L1 of the contact region 15 arranged in the mesa section 60 of the transistor section 70 in the first region 121 in the trench extension direction.

[0078] In plan view, the emitter regions 12 of the transistor section 70 in the second region 122 may be arranged to correspond to the emitter regions 12 of the transistor section 70 in the first region 121 in the trench arrangement direction, and the emitter regions 12 of the transistor section 70 in the first region 121 may be arranged to correspond to the emitter regions 12 or the contact regions 15 of the transistor section 70 in the second region 122 in the trench arrangement direction.

[0079] While the emitter regions 12 of the present example are arranged to extend over a plurality of mesa portions 60 of the first region 121 in the trench arrangement direction, some emitter regions 12 also extend over a plurality of mesa portions 60 in the second region 122, and other emitter regions 12 do not extend to the second region 122 and end in the first region 121.

[0080] That is, some emitter regions 12 are thinned in the second region 122 compared to the first region 121, thereby reducing the channel density. For example, the channel density of the mesa section 60 of the transistor section 70 in the second region is equal to or less than 50% of the channel density of the mesa section 60 of the transistor section 70 in the first region 121. This suppresses current generation in the second region 122.

[0081] Fig. 6 is another example of an enlarged view of the active portion 120. The active portion 120 of the present example includes the transistor portions 70 and the diode portions 80 arranged alternately in the trench arrangement direction. Here, a difference from the example of Fig. 2, which includes only the transistor section 70, and the same elements are not described.

[0082] In the diode section 80, the N + -like cathode region 82 is provided in a region in direct contact with the back surface of the semiconductor substrate 10. In Fig. 6, the area provided with the cathode region 82 is shown with a dotted line. In the active section 120, an area that does not have the cathode region 82 on the rear surface side of the semiconductor substrate 10 can be provided with the P + -like collector area.

[0083] In the active portion 120, a projection area overlapping with the cathode region 82 in the Z-axis direction is defined as the diode portion 80. That is, a projection area in which the cathode region 82 is projected onto the front surface of the semiconductor substrate 10 in a direction perpendicular to the back surface of the semiconductor substrate 10 is defined as the diode portion 80. Furthermore, an extension area of ​​the projection area to the well region in the Y-axis direction may also be defined as the diode portion 80. Furthermore, in the active portion 120, a projection region in which the collector region 22 is projected onto the front surface of the semiconductor substrate 10 in a direction perpendicular to the rear surface of the semiconductor substrate 10 and in which predetermined unit configurations including the emitter regions 12 and the contact regions 15 are regularly arranged is defined as the transistor portion 70.

[0084] Although Fig. 6 shows a mesa portion 60 of the diode portion 80. The diode portion 80 may include a plurality of mesa portions 60 in the X-axis direction. The mesa portion 60 of the diode portion 80 is provided with the contact region 15 and the base region 14 exposed to the front surface of the semiconductor substrate 10 in a region not provided with the contact region 15. The emitter region 12 may not be provided in the mesa portion 60 of the diode portion 80. In the mesa portion 60 adjacent to the transistor portion 70, the contact region 15 is provided on the front surface of the semiconductor substrate 10. The contact hole 54 is provided above the contact region 15 and the base region 14.

[0085] In the diode section 80, one or more dummy trench sections 30 are arranged at a predetermined interval along the X-axis direction. The dummy trench section 30 of the diode section 80 may include an extension section 29 and an edge section 31. The edge section 31 and the extension section 29 have shapes similar to the edge section 41 and the extension section 39, respectively. The dummy trench section 30, which has the edge section 31 and the dummy trench section 30 in a straight shape, may have the same length in the extension direction.

[0086] In the transistor section 70, an intermediate region, which is not provided with the emitter region on one surface, may be provided at a boundary adjacent to the diode section 80. The mesa section 60 of the intermediate region may be provided with the contact region 15 over a larger area than in the mesa section 60 of the transistor section 70. Furthermore, in the transistor section 70, a plurality of dummy trench sections 30 may be continuously arranged at a portion adjacent to the intermediate region. The dummy trench section 30 provided at the portion adjacent to the intermediate region may also include the extension sections 29 and the edge section 31.

[0087] Fig. 7 is a diagram showing an example of a cross section bb in Fig. 6 shows. In the cross section, the base region 14 is provided on the front surface 21 side of the semiconductor substrate 10 in the diode section 80. The diode section 80 of the present example is not provided with the collection region 16. Alternatively, in another example, the diode section 80 may be provided with one collection region 16. Moreover, a plurality of collection regions 16 may be provided in the depth direction.

[0088] In the diode section 80, the drift region 18 is provided below the base region 14. In the diode section 80, the N + -like cathode region 82 is provided below the buffer region 20.

[0089] Fig. 8 is a diagram showing an exemplary arrangement of the transistor section 70 and the diode section 80. Fig. Figure 8 shows the transistor section 70 with a symbol of I and the diode section 80 with a symbol of F. In the active section 120 of the present example, the transistor sections 70 and the diode sections 80, which are shown in Fig. 6 and Fig. 7 are arranged alternately in the X-axis direction. In plan view, an area of ​​each transistor section 70 is larger than an area of ​​each diode section 80.

[0090] In plan view, a ratio of the diode sections 80 to the transistor sections 70 in the second region 122 is greater than a ratio of the diode sections 80 to the transistor sections 70 in the first region 121. In the first region 121 of the present example, a width I1 of the transistor section 70 is greater than a width of the diode section 80 in the X-axis direction. In the second region 122 of the present example, some diode sections 80 have the same width as that of the diode section 80 in the first region 121, and a width of other diode sections 80 is greater than a width of the diode section 80 in the first region 121.

[0091] In this way, in the second region 122, the area ratio of the diode sections 80 to the transistor sections 70 is higher than that of the first region 121, so that the channel density is lower than that of the first region 121. This suppresses current generation in the second region 122.

[0092] It should be noted that, in plan view, even in the second region 122 having a higher area ratio of the diode sections 80, an area of ​​the transistor sections 70 is larger than an area of ​​the diode sections 80. This can ensure a sufficient amount of currents throughout the entire semiconductor device 100 while reducing current accumulation in the second region 122.

[0093] Fig. 9 is a plan view showing an example of a semiconductor module 300 according to an embodiment. The semiconductor module 300 includes a first semiconductor device 100-1 and a second semiconductor device 100-2. Each of the first semiconductor device 100-1 and the second semiconductor device 100-2 is one of the Fig. 1 to Fig. 8. The semiconductor module 300 may include a plurality of pairs of the first semiconductor device 100-1 and the second semiconductor device 100-2.

[0094] The semiconductor module 300 of the present example includes a housing 88. The housing 88 accommodates each semiconductor device 100. A coolant flows within the housing 88 to cool the semiconductor device 100. The semiconductor module 300 further includes a temperature sensor and / or a current sensor.

[0095] The housing 88 includes main terminals 86 and control terminals 99. At least some of the main terminals 86 are electrically connected to the emitter electrode 52 of the semiconductor device 100. At least some of the control terminals 99 are electrically connected to the pad 50 of the semiconductor device 100. Furthermore, at least some of the control terminals 99 are electrically connected to sensors of the semiconductor device 100.

[0096] Fig. 10 is a side view of the semiconductor substrate 10 mounted on a packaging substrate 200. In Fig. 10, the collector electrode 24, the interlayer dielectric film 38, and the like have been omitted. The semiconductor substrate 10 is fixed to the packaging substrate 200 by a bonding portion 160 such as solder. A soldering portion 162 and a lead frame 163 disposed on the soldering portion 162 and electrically connected to the emitter electrode 52 are disposed over the exposed portion 53 of the emitter electrode 52. Furthermore, a protective film 150 including an opening portion corresponding to the exposed portion 53 is disposed over the front surface 21 of the semiconductor substrate 10 and the emitter electrode 52.

[0097] As in Fig. As shown in Figure 10, the soldering portion 162 has a cross-section with a flared shape to increase the connection strength with the emitter electrode 52. The protective film 150 is provided to prevent the soldering portion 162 from extending to the pad 50, the pad region, or the like located around the emitter electrode 52.

[0098] Furthermore, the protective film 150 restricts the extension range of the soldering portion 162 to suppress the positional deviation of the soldering portion 162. The positional deviation of the soldering portion 162 causes the center of gravity of the semiconductor device 100 to shift, so that the semiconductor substrate 10 is mounted in an inclined state during the process of mounting the semiconductor substrate 10 on the packaging substrate 200 and the connecting portion 160. The protective film 150 is provided to suppress the positional deviation of the soldering portion 162, so that the inclination of the semiconductor substrate 10 during mounting can be suppressed.

[0099] As described above, when the transistor section 70 in the semiconductor substrate 10 is driven, a current generated in the vicinity of a region where the lead frame 163 is disposed flows toward the lead frame 163. Therefore, current accumulation particularly occurs in a region from the vicinity of the end portion of the lead frame 163 to the end portion of the soldering portion 162. In this region, an increase in current density may cause a decrease in turn-off resistance and a decrease in reliability due to heat generation.

[0100] Therefore, in the present example, the region from the vicinity of the end portion of the lead frame 163 to the end portion of the solder portion 162, in which current accumulation occurs when the transistor portion 70 is driven, is located in the second region 122, which has a lower channel density. A boundary between the first region 121 and the second region 122 of the present example is provided within the end portion of the lead frame 163. A distance D1 between the boundary between the first region 121 and the second region 122 and the end portion of the lead frame 163 is equal to or greater than 400 µm and equal to or less than 800 µm.

[0101] Furthermore, the outer peripheral end of the second region 122 of the present example is provided outside the end portion of the soldering portion 162. A distance D2 between the outer peripheral end of the second region 122 and the end portion of the soldering portion 162 is equal to or greater than 0 μm and equal to or less than 1500 μm. In this way, in the present example, current generation in the second region 122 is suppressed, so that current accumulation in the second region 122 when driving the transistor portion 70 is reduced to suppress a decrease in turn-off resistance and a decrease in reliability due to heat generation.

[0102] It should be noted that in Fig. 1 to Fig.10, the examples were described in which the first region 121 and the second region 122 are provided to correspond to the lead frame in the exposed portion 53, which is a region including the center Ac of the active portion. However, when the additional active portions are provided above and below the land 50 and the land portion (in the +Y-axis direction and the -Y-axis direction), the exposed portions 53 in which the lead frames are to be arranged may also be provided in the extended emitter electrodes 52 provided above the additional active portions, and each of the exposed portions 53 may be provided with the first region 121 and the second region 122.

[0103] Although the present invention has been described with the embodiments, the technical scope of the present invention is not limited to the above-described embodiments. It is obvious to those skilled in the art that various modifications or improvements can be made to the above-described embodiments. It is also obvious from the description of the claims that embodiments added with such modifications or improvements can be included within the technical scope of the present invention.

[0104] It should be noted that the operations, procedures, steps, and stages of each process performed by an apparatus, system, program, and method shown in the claims, embodiments, or diagrams may be performed in any order, as long as the order is not indicated by "previous," "before," or the like, and as long as the output from a previous process is not used in a subsequent process. Even if the flow of operations is described using terms such as "first" or "next" within the scope of the claims, specification, or drawings, this does not necessarily mean that the process must be performed in that order. LIST OF REFERENCE SYMBOLS 10 Semiconductor substrate 11 Bath area 12 Emitter area 14 Basic area 15 Contact area 16 Collection area 18 Drift area 20 Buffer area 21 Front surface 22 Collector area 23 Back surface 24 Collector electrode 25 connecting section 29 Extension section 30 Dummy trench section 31 marginal section 32 dielectric dummy film 34 Dummy line section 38 dielectric interlayer film 39 Extension section 40 gate ditch section 41 marginal section 42 dielectric gate film 44 gate line section 48 gate runners 50 connection area 52 Emitter electrode 53 exposed section 54 contact hole 56 contact holes 60 Mesa section 70 transistor section 80 diode section 82 Cathode area 86 Main connection terminal 88 housings 99 Control terminal 100 semiconductor devices 102 End page 120 active section 121 first area 122 second area 150 protective film 160 connecting section 162 soldering section 163 ladder frames 172 Current measuring field 174 Anode field 176 Cathode field 200 packaging substrate 300 semiconductor modules

Claims

[1] A semiconductor device comprising: a semiconductor substrate having an active portion including a transistor portion; an emitter electrode disposed over a front surface of the semiconductor substrate; and a protective film arranged over the emitter electrode, wherein the active section comprises: an emitter region of a first conductivity type arranged on the front surface of the semiconductor substrate; a contact region of a second conductivity type; and a plurality of trench sections, wherein the emitter electrode includes an exposed portion not covered by the protective film, and wherein the active portion comprises: a first region in a region in which the exposed portion is disposed; and a second region disposed at an outer periphery of the first region and having a lower channel density than the first region. [2] A semiconductor device according to claim 1, wherein in a plan view of the semiconductor substrate, the second region is arranged so that it surrounds the entire outer circumference of the first region. [3] A semiconductor device according to claim 1, wherein in a plan view of the semiconductor substrate, an area of ​​the first region is equal to or greater than 0.5 times and equal to or less than ten times an area of ​​the second region. [4] A semiconductor device according to claim 1, wherein in a plan view of the semiconductor substrate, the first region is spaced from an end portion of the exposed portion by at least 0 µm and at most 1500 µm. [5] A semiconductor device according to claim 1, wherein a channel density of a mesa section of the transistor section in the second region is smaller than a channel density of a mesa section of the transistor section in the first region. [6] A semiconductor device according to claim 1, wherein the emitter region and the contact region are arranged alternately in a trench extension direction in a mesa section of the transistor section, and in a plan view of the semiconductor substrate, a ratio of the emitter region to the contact region in a mesa section of the transistor section in the first region is greater than a ratio of the emitter region to the contact region in a mesa section of the transistor section in a second region. [7] A semiconductor device according to claim 6, wherein in a plan view of the semiconductor substrate, a length of the contact region arranged in a mesa section of the transistor section in the second region in a trench extension direction is greater than a length of the contact region arranged in a mesa section of the transistor section in the first region in the trench extension direction. [8] A semiconductor device according to claim 7, wherein in a plan view of the semiconductor substrate, the emitter region of the transistor section in the second region is arranged so that it corresponds to the emitter region of the transistor section in the first region in a trench arrangement direction, and in a plan view of the semiconductor substrate, the emitter region of the transistor section in the first region is arranged to correspond to either the emitter region or the contact region of the transistor section in the second region in the trench arrangement direction. [9] A semiconductor device according to claim 5, wherein a channel density of a mesa section of the transistor section in the second region is equal to or less than 50% of a channel density of a mesa section of the transistor section in the first region. [10] A semiconductor device according to claim 1, wherein the active section has a diode section arranged alternately with the transistor section in a trench arrangement direction, and in a plan view of the semiconductor substrate, a ratio of the diode section to the transistor section in the second region is greater than a ratio of the diode section to the transistor section in the first region. [11] A semiconductor device according to claim 10, wherein in a plan view of the semiconductor substrate in the second region, an area of ​​the transistor section is larger than an area of ​​the diode section. [12] A semiconductor module comprising the semiconductor device according to any one of claims 1 to 11. [13] A semiconductor module according to claim 12, comprising: a soldering portion disposed above the emitter electrode; and a lead frame disposed on the soldering portion and electrically connected to the emitter electrode. [14] Semiconductor module according to claim 13, wherein in a plan view of the semiconductor substrate, a boundary between the first region and the second region is arranged within an end portion of the lead frame. [15] Semiconductor module according to claim 14, wherein a distance between a boundary between the first region and the second region and the end portion of the lead frame is equal to or greater than 400 µm and equal to or less than 800 µm. [16] Semiconductor module according to claim 14, wherein an outer peripheral end of the second region is arranged outside an end portion of the soldering portion. [17] Semiconductor module according to claim 16, wherein a distance between the outer circumferential end of the second region and the end portion of the soldering portion is equal to or greater than 0 µm and equal to or less than 1500 µm.

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