Embedded ReRAM with rear contact

Abstract

Provided is a semiconductor structure including a one-transistor-one-capacitor (1T1R) device having an embedded resistive random access memory (ReRAM) with a width greater than 1 gate pitch present at the front or back of the structure, wherein a front-side contact structure is electrically connected to a source region of the transistor of the 1T1R device and a back-side contact structure is electrically connected to a drain region of the transistor of the 1T1R device.

Description

BACKGROUND

[0001] The present application relates to semiconductor technology and, more particularly, to a semiconductor structure including an embedded resistive random access memory (ReRAM) having a backside contact for lowering the forming voltage of the ReRAM.

[0002] Non-volatile memory (NVM) or non-volatile storage is a type of computer memory that can retain stored data even after the power supply is removed. In contrast, volatile memory requires a constant power supply to retain data. NVMs such as ReRAM (or sometimes just RRAM), phase-change random access memory (PCRAM), and conductive bridge random access memory (CBRAM) are receiving renewed attention due to potential applications to neuromorphic computing with in-memory processing capability, significantly reducing power consumption and eliminating data bus time between the memory and the central processing unit (CPU) of conventional complementary metal oxide semiconductor (CMOS)-based neuromorphic computing.ReRAM is considered a promising technology for devices with electronic synapses or memristors for neuromorphic computing, as well as for high-density, high-speed NVM applications. In neuromorphic computing applications, a resistive memory device such as ReRAM can be used as a connection (i.e., synapse) between a preneuron and a postneuron, with the connection weight represented by the device's resistance. SUMMARY

[0003] Provided is a semiconductor structure including a one-transistor-one-capacitor (1T1R) device having an embedded ReRAM present on the front or back of the structure, wherein a front-side contact structure is electrically connected to a source region of the transistor of the 1T1R device and a back-side contact structure is electrically connected to a drain region of the transistor of the 1T1R device. By arranging these two contact structures on opposite sides of the structure, a low-voltage switching ReRAM can be achieved without increasing the size of the ReRAM or the forming voltage itself. The ReRAM can have a width greater than 1 gate pitch. Throughout this application, the term "gate pitch" refers to a distance from a point on one gate structure to the exact point on a next adjacent gate structure.

[0004] In one embodiment (i.e., a front-side ReRAM embodiment) of the present application, a semiconductor structure comprises a transistor disposed in a memory device region and including, among other things, a gate structure, a source region disposed on a first side of the gate structure, and a drain region disposed on a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The structure further comprises a ReRAM disposed in the memory device region and positioned over the transistor, a front-side contact structure electrically connecting the ReRAM to the source region of the transistor, and a back-side contact structure electrically connecting the drain region of the transistor to a back-side back-end-of-the-line (BEOL) structure.In this front-side ReRAM embodiment, the switching range of the ReRAM is effectively increased without increasing the gate pitch.

[0005] In this front-side ReRAM embodiment, the transistor may be a nanosheet transistor including a plurality of vertically stacked and spaced-apart semiconductor channel material nanosheets, wherein the gate structure of the transistor encloses a central portion of each semiconductor channel material nanosheet of the plurality of vertically stacked and spaced-apart semiconductor channel material nanosheets. In such an embodiment, the structure may further include a bottom dielectric isolation layer and a backside interlayer dielectric layer disposed beneath the nanosheet transistor, wherein the backside contact structure extends through both the backside interlayer dielectric layer and the bottom dielectric isolation layer and is in direct physical contact with the drain region of the transistor.

[0006] In this front-side ReRAM embodiment, the structure may further comprise a source / drain contact structure disposed between the front-side contact structure and the source region of the transistor, wherein the front-side contact structure is in direct physical contact with a first surface of the source / drain contact structure and a second surface of the source / drain contact structure, opposite the first surface, is in direct physical contact with the source region of the transistor.

[0007] In this front-side ReRAM embodiment, the structure may further include a front-side BEOL structure disposed over the ReRAM, wherein the front-side BEOL structure is electrically connected to a top electrode of the ReRAM through a front-side BEOL-to-ReRAM metal via. In such an embodiment, the front-side BEOL-to-ReRAM metal via extends through a dielectric layer present on the ReRAM.

[0008] In this front-side ReRAM embodiment, the structure may further include a carrier wafer disposed on a surface of the front-side BEOL structure.

[0009] In this front-side ReRAM embodiment, the ReRAM is embedded in a front-side interlayer dielectric layer.

[0010] In this front-side ReRAM embodiment, the structure may further comprise a logic unit region disposed adjacent to the memory unit region, the logic unit region comprising a further transistor, the further transistor comprising: a further gate structure, a further source region disposed on the first side of the further gate structure, and a further drain region disposed on the second side of the further gate structure, the second side of the further gate structure being opposite the first side of the further gate structure. In such an embodiment, the structure may further comprise a further front-side contact structure electrically connecting the further source region of the further transistor to a front-side BEOL structure, and a further back-side contact structure electrically connecting the further drain region of the further transistor to a back-side BEOL structure.

[0011] In another embodiment (i.e., a back-side ReRAM embodiment) of the present application, a semiconductor structure comprises a transistor arranged in a memory device region and including, among other things, a gate structure, a source region arranged on a first side of the gate structure, and a drain region arranged on a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The structure of this back-side ReRAM embodiment further comprises a ReRAM arranged in the memory device region and positioned below the transistor, a front-side contact structure electrically connecting the source region of the transistor to a front-side BEOL structure, and a back-side contact structure electrically connecting the drain region of the transistor to the ReRAM.In this rear-side ReRAM embodiment, the switching range of the ReRAM is effectively increased without increasing the gate pitch.

[0012] In this backside ReRAM embodiment, the transistor is a nanosheet transistor including a plurality of vertically stacked and spaced-apart semiconductor channel material nanosheets, wherein the gate structure of the transistor encloses a central portion of each semiconductor channel material nanosheet of the plurality of vertically stacked and spaced-apart semiconductor channel material nanosheets. In such an embodiment, the structure may further include a bottom dielectric isolation layer and a backside interlayer dielectric layer disposed beneath the nanosheet transistor, wherein the backside contact structure extends through both the backside interlayer dielectric layer and the bottom dielectric isolation layer and is in direct physical contact with the drain region of the transistor.

[0013] In this rear-side ReRAM embodiment, the structure may further comprise a source / drain contact structure disposed between the front-side contact structure and the source region of the transistor, wherein the front-side contact structure is in direct physical contact with a first surface of the source / drain contact structure and a second surface of the source / drain contact structure, opposite the first surface, is in direct physical contact with the source region of the transistor.

[0014] In this rear ReRAM embodiment, the structure may further include a front-side metal via disposed between the front-side contact structure and the front-side BEOL structure, the front-side metal via having a first surface directly contacting the front-side BEOL structure and a second surface opposite the first surface directly contacting the front-side contact structure.

[0015] In this backside ReRAM embodiment, the structure may further include a backside BEOL structure disposed beneath the ReRAM, wherein the backside BEOL structure is electrically connected to a bottom electrode of the ReRAM through a backside BEOL-to-ReRAM metal via.

[0016] In this rear-side ReRAM embodiment, the structure may further comprise a carrier wafer disposed on a surface of the front-side BEOL structure.

[0017] In this rear ReRAM embodiment, the ReRAM is embedded in a rear interlayer dielectric layer.

[0018] In this rear-side ReRAM embodiment, the structure may further comprise a logic unit region disposed adjacent to the memory unit region, the logic unit region comprising a further transistor, the further transistor comprising a further gate structure, a further source region disposed on the first side of the further gate structure, and a further drain region disposed on the second side of the further gate structure, the second side of the further gate structure being opposite the first side of the further gate structure. In such an embodiment, the structure may further comprise a further front-side contact structure electrically connecting the further source region of the further transistor to a front-side BEOL structure, and a further back-side contact structure electrically connecting the further drain region of the further transistor to a back-side BEOL structure. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a cross-sectional view of an exemplary structure present in a memory device region of a semiconductor substrate, the exemplary structure including a transistor, a ReRAM, a front-side contact structure, a front-side BEOL structure, and a carrier wafer, all present at the front side of the semiconductor substrate. Fig. 1B is a cross-sectional view of an exemplary structure present in a logic unit region of the semiconductor substrate, wherein the logic unit region is adjacent to the Fig. 1A, wherein the exemplary structure in the logic unit region includes a transistor, a front-side contact structure, a front-side BEOL structure, and a carrier wafer, all present on the front side of the semiconductor substrate. Fig. 2A and Fig. 2B are cross-sectional views of the Fig. 1A and 1B, respectively, after removal of the semiconductor substrate to enable backside processing in both the memory device region and the logic device region. Fig. 3A and Fig. 3B are cross-sectional views of the Fig. 2A and 2B, respectively, after forming a backside interlayer dielectric layer in both the memory device region and the logic device region. Fig. 4A and Fig. 4B are cross-sectional views of the Fig. 3A and 3B, respectively, after forming a backside contact structure in both the memory device region and the logic device region. Fig. 5A and Fig. 5B are cross-sectional views of the Fig. 4A and 4B respectively, after forming a backside BEOL structure. Fig. 6A is a cross-sectional view of another exemplary structure present in a memory device region of a semiconductor substrate, the exemplary structure including a transistor, a front-side contact structure, a front-side BEOL structure, and a carrier wafer, all present at the front side of the semiconductor substrate. Fig. 6B is a cross-sectional view of another exemplary structure present in a logic unit region of the semiconductor substrate, wherein the logic unit region is adjacent to the Fig. 6A, wherein the exemplary structure in the logic unit region includes a transistor, a front-side contact structure, a front-side BEOL structure, and a carrier wafer, all present on the front side of the semiconductor substrate. Fig. 7A and Fig. 7B are cross-sectional views of the Fig. 6A and 6B, respectively, after removal of the semiconductor substrate to enable backside processing in both the memory device region and the logic device region. Fig. 8A and Fig. 8B are cross-sectional views of the Fig. 7A and 7B, respectively, after forming a first backside interlayer dielectric layer in both the memory device region and the logic device region. Fig. 9A and Fig. 9B are cross-sectional views of the Fig. 8A and 8B, respectively, after forming a backside contact structure in both the memory device region and the logic device region. Fig. 10A and Fig. 10B are cross-sectional views of the Fig. 9A and 9B, respectively, after further backside processing, including forming a ReRAM in the memory device region and forming a backside BEOL structure. DETAILED DESCRIPTION

[0019] The present application will now be described in more detail with reference to the following discussion and the drawings accompanying this application. It should be noted that the drawings of this application are for illustrative purposes only and are therefore not drawn to scale. It should also be noted that like and corresponding elements are designated by like reference numerals.

[0020] In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of various embodiments of the present application. However, it will be apparent to one skilled in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0021] When an element such as a layer, region, or substrate is described as being "on" or "over" another element, it is understood that it may be directly on top of the other element or that intervening elements may be present. On the other hand, when an element is described as being "directly on" or "directly above" another element, no intervening elements are present. When an element is described as being "below" or "under" another element, it is also understood that it may be directly below or under the other element or that intervening elements may be present. On the other hand, when an element is described as being "directly below" or "directly beneath" another element, no intervening elements are present.

[0022] Conventional filament-switching ReRAM devices require a forming step to create a soft breakdown. On the one hand, reducing the switching area increases the forming voltage, requiring an additional external device and resulting in power consumption. On the other hand, increasing the switching area of ​​the ReRAM to reduce the forming voltage results in a loss of area. The present application solves the above problem by providing a 1T1R device in which the ReRAM (serving as a storage element in the 1T1R structure) is present on either the front or back side of the device, and the source and drain contacts are arranged on opposite sides of the device.In particular, and in the present application, a front contact is present on the front side of the device, which is electrically connected to the source region of the transistor, and a back contact structure is present on the back side of the device, which is electrically connected to the drain region of the transistor. Here, the front side of the device is a region that includes the transistor and is arranged above it, while the back side of the device is the region arranged below the transistor. The switching range of the ReRAM is therefore not limited by the drain contact (as is the case in a conventional 1T1R device). In the present application, the ReRAM size can be larger than 1 gate pitch. This aspect of the present application can reduce the forming voltage without increasing the size of the 1T1R device.

[0023] In the present application, and as in Fig. 1A to 10B, a memory unit region 100 and a logic unit region 102 are typically present. The logic unit region 102 is arranged adjacent to the memory unit region 100. In the present application, the transistors present in the memory unit region 100 and the logic unit region 102 are arranged on a same semiconductor substrate 10. The memory unit region 100 includes a 1T1R device comprising a ReRAM and a transistor T1. The ReRAM may be arranged on a front side or a back side of the semiconductor substrate 10. The logic unit region 102 also includes a transistor T2. In the memory unit region 100 and the logic unit region 102, a front-side contact is made to the source region of the transistor present in each respective unit region, and a back-side contact is made to the drain region of the transistor in each respective unit region.This provides a low voltage switching ReRAM in the memory device region 100 without having to increase the size of the ReRAM.

[0024] In the present application, the term "transistor" refers to a three-terminal device including a gate electrode, a source region, and a drain region; the gate electrode is a component of the gate structure. In the present application, the transistors in the memory device region 100 and the logic device region are both illustrated as nanosheet transistors. The term "nanosheet transistor" refers to a type of transistor in which the channel of the transistor is a plurality of vertically stacked and spaced-apart semiconductor channel material nanosheets. For nanosheet transistors, the gate structure wraps around each of the semiconductor channel material nanosheets of the plurality of vertically stacked and spaced-apart semiconductor channel material nanosheets.Nanosheet transistors are advantageous for the present application because such transistors typically have a lower dielectric isolation layer, allowing backside processing without adversely affecting the transistor channel. In some embodiments, a transistor formed on a semiconductor-on-insulator substrate may be used instead of nanosheet transistors because the semiconductor-on-insulator substrate has a buried isolation layer.

[0025] Now referring to Fig. 1A illustrates an exemplary structure present in a memory device region 100 of a semiconductor substrate 10, the exemplary structure including a transistor T1, a ReRAM 34 / 35 / 36, a front-side contact structure 32, a front-side BEOL structure 44, and a carrier wafer 46, all present on the front side of the semiconductor substrate 10. The transistor T1 present in the memory device region 100 includes a plurality of vertically stacked and spaced-apart semiconductor channel material nanosheets 16, a gate structure 22 enclosing a central portion of each semiconductor channel material nanosheet 16, a source region 26 disposed on one side of the gate structure 22, and a drain region 27 disposed on the opposite side of the gate structure 22. The example structure also shows dummy gate regions to the left and right of transistor T1.Each dummy gate region also includes at least one gate structure 22 enclosing an end portion of each of the semiconductor channel material nanosheets 16; the dummy transistors lack at least one of a source region or a drain region. Also present in the memory device region 100 are: a shallow trench isolation structure 12, internal spacers 18, gate spacers 20, a gate cap 24, front-side source / drain contact structures 28, a first front-side interlayer dielectric layer 30, a dielectric layer 38, a second front-side interlayer dielectric layer 40, and a front-side BEOL-to-ReRAM metal via 42. In the present application, the shallow trench isolation structure 12 is formed in the semiconductor substrate 10 and may surround an unetched portion of the semiconductor substrate 10.The structure further comprises a lower dielectric insulation layer 14 which is present between the transistor T1 and the semiconductor substrate 10.

[0026] As in Fig. 1A, the ReRAM 34 / 35 / 36 is a front-side ReRAM arranged above the transistor T1 present in the memory device region 100. As further illustrated in Fig. As illustrated in Figure 1A, the front-side contact structure 32 electrically connects the ReRAM 34 / 35 / 36 to the source region 26 of the transistor T1; one of the front-side source / drain contact structures 28 is disposed between the front-side contact structure 32 and the source region 26 of the transistor T1 in the memory device region 100. In the present application, the front-side contact structure 32 has a first surface physically contacting the front-side source / drain contact structure 28 and a second surface opposite the first surface physically contacting the first electrode 34 of the ReRAM 34 / 35 / 36. The front-side BEOL-to-ReRAM metal via 42 electrically connects a second electrode 36 of the ReRAM 34 / 35 / 36 to the front-side BEOL structure 44, and a carrier wafer 46 is disposed on the front-side BEOL structure 44.The dielectric layer 38 is present along a top surface and a sidewall surface of the ReRAM 34 / 35 / 36; this dielectric layer is also present between the first front-side interlayer dielectric layer 30 and the second front-side interlayer dielectric layer 40. In this embodiment of the present application, and as shown in FIG. Fig. 1A, the first front-side interlayer dielectric layer 30 embeds the transistors T1 and the dummy transistors, the front-side source / drain contact structures 28, the front-side contact structure 32, the bottom dielectric isolation layer 14, and the second front-side interlayer dielectric layer 40 embeds at least the ReRAM 34 / 35 / 36 and the front-side BEOL-to-ReRAM metal via 42.

[0027] Now referring to Fig. 1B, an exemplary structure is illustrated that is present in a logic unit region 102 of the semiconductor substrate 10. It is noted that the logic unit region 102 and the memory unit region 100 are present on the same substrate, ie, the semiconductor substrate 10. The logic unit region 102 is adjacent to the Fig. 1A, and the exemplary structure in the logic unit region 102 includes a transistor T2, a front-side contact structure 32, a front-side BEOL structure 44, and a carrier wafer 46, all present on the front side of the semiconductor substrate 10. The transistor T2 present in the logic unit region 102 includes a plurality of vertically stacked and spaced-apart semiconductor channel material nanosheets 16, a gate structure 22 enclosing a central portion of each semiconductor channel material nanosheet 16, a source region 26 disposed on one side of the gate structure 22, and a drain region 27 disposed on the opposite side of the gate structure 22. The exemplary structure also shows dummy gate regions to the left and right of the transistor T2.Each dummy gate region also includes at least one gate structure 22 enclosing an end portion of each of the semiconductor channel material nanosheets 16; the dummy transistors lack at least one of a source region and a drain region. Also present in the logic device region 102 are: the shallow trench isolation structure 12, internal spacers 18, gate spacers 20, the gate cap 24, front-side source / drain contact structures 28, the first front-side interlayer dielectric layer 30, the dielectric layer 38, the second front-side interlayer dielectric layer 40, and a front-side metal via 43. The front-side interlayer dielectric layer 30 shown in FIG. Fig. The structure shown in Figure 1B further comprises a lower dielectric insulation layer 14 which is present between the transistor T2 and the semiconductor substrate 10.

[0028] As in Fig. 1B, the front-side contact structure 32 electrically connects the front-side BEOL structure 44 to the source region 26 of the transistor T2; one of the front-side source / drain contact structures 28 is positioned between the front-side contact structure 32 and the source region 26 of the transistor T2 in the logic unit region 102. In the present application, the front-side contact structure 32 has a first surface physically contacting the front-side source / drain contact structure 28 and a second surface physically contacting the metal via 43 disposed between the front-side BEOL structure 44 and the front-side contact structure 32. In the logic unit region 102, the dielectric layer 38 is present between the first front-side interlayer dielectric layer 30 and the second front-side interlayer dielectric layer 40.In this embodiment of the present application, and as shown in . Fig. 1B, the first front-side interlayer dielectric layer 30 embeds the transistors T2 and the dummy transistors, the front-side source / drain contact structure 28, the front-side contact structure 32, the lower dielectric isolation layer 14, and the second front-side interlayer dielectric layer 40 embeds at least the metal via 43.

[0029] The semiconductor substrate 10, which is present in both the memory unit region 100 and the logic unit region 102, is composed of at least one semiconductor material having semiconducting properties. Examples of semiconductor materials that may be used to provide the semiconductor substrate 12 may include, but are not limited to, silicon (Si), a silicon-germanium alloy (SiGe alloy), a silicon-germanium carbide alloy (SiGeC alloy), germanium (Ge), III / V compound semiconductors, or II / VI compound semiconductors.

[0030] The shallow trench isolation structure 12, which is present in both the memory device region 100 and the logic device region 102, may include a trench dielectric and an optional trench liner. If present, the trench liner is formed along a sidewall and a bottom wall of the trench dielectric. The trench dielectric may be made of any trench dielectric, for example, silicon oxide, while the trench liner may be made of any trench liner material, such as silicon nitride.

[0031] The lower dielectric isolation layer 14, present in both the memory device region 100 and the logic device region 102, is composed of a spacer dielectric, including, but not limited to, SiN, SiBCN, SiOCN, SiON, or SiOC. Typically, but not necessarily, the spacer dielectric providing the lower dielectric isolation layer 14 is the same in composition as the spacer dielectric providing the gate spacer 20.

[0032] Each semiconductor channel material nanosheet 16 is made of one of the semiconductor materials mentioned above for the semiconductor substrate 10. In one example, each semiconductor channel material nanosheet 16 is made of Si or SiGe. In some embodiments, each semiconductor channel material nanosheet 16 may be made of a semiconductor material capable of providing high channel mobility for nFET devices. In other embodiments, each semiconductor channel material nanosheet 16 may be made of a semiconductor material capable of providing high channel mobility for pFET devices. Each semiconductor channel material nanosheet 16 typically has a width of 6 nm to 100 nm and a vertical height of 4 nm to 15 nm.

[0033] Each inner spacer 18 is disposed beneath each semiconductor channel material nanosheet 16. Each inner spacer 18 is comprised of a spacer dielectric, including, but not limited to, SiN, SiBCN, SiOCN, SiON, or SiOC.

[0034] Each gate spacer 20 provided along the sidewall of the gate structures 22 may also be comprised of a spacer dielectric. The spacer dielectric providing the gate spacer 20 may be the same in composition as, or different in composition from, the dielectric spacer material providing the inner spacer 18.

[0035] The gate structure 22 includes a gate dielectric and a gate electrode, both of which are not shown separately, but which are intended to be located within the region defined by the gate structure 22. As is known to those skilled in the art, the gate dielectric directly contacts one or more physically exposed surfaces of each semiconductor channel material structure, and the gate electrode is formed on the gate dielectric. The gate dielectric of the gate structure 22 has a dielectric constant of 4.0 or greater. All dielectric constants mentioned herein are measured in a vacuum unless otherwise stated. Illustrative examples of gate dielectrics may include silicon dioxide, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiO x N y), tantalum oxide (TaO x ), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3), and / or lead zinc niobite (Pb(Zn,Nb)O). The gate dielectric may further comprise dopants such as La, Al, and / or Mg.

[0036] The gate electrode of gate structure 22 may include a work function metal (WFM) and optionally a conductive metal. The WFM may be used to adjust the threshold voltage of the transistor to a desired value. In some embodiments, the WFM may be selected to cause a shift in the n-type threshold voltage. As used herein, "n-type threshold voltage shift" refers to a shift in the effective work function of the work function metal-containing material toward a conduction band of silicon in a silicon-containing material. In one embodiment, the work function of the n-type work function metal ranges from 4.1 eV to 4.3 eV.Examples of such materials that can cause a shift in the n-type threshold voltage include, but are not limited to, titanium-aluminum, titanium-aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium-silicon, or combinations thereof. In other embodiments, the WFM can be selected to cause a shift in the p-type threshold voltage. In one embodiment, the work function of the p-type work function metal ranges from 4.9 eV to 5.2 eV. As used herein, the "threshold voltage" is the lowest achievable gate voltage that turns on a semiconductor device, e.g., a transistor, by rendering the device's channel conductive. As used herein, the term “p-type threshold voltage shift” refers to a shift of the effective work function of the WFM-containing material toward a valence band of silicon in the silicon-containing material.Examples of such materials that can cause a shift in the p-type threshold voltage include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof. The optionally conductive metal may include, but is not limited to, Al, W, or Co.

[0037] Each gate cap 24 present in the memory device region 100 and the logic device region 102 may be made of a dielectric hard mask material such as silicon nitride and / or silicon oxynitride. The gate cap 24 is present on the top surface of the gate structure 22 and is laterally surrounded by an upper portion of the gate spacer 20; a lower portion of the gate spacer 20 laterally surrounds the gate structure 20. At this point in the present application, the top surface of the gate cap 24 is coplanar with the top surface of the gate spacer 20.

[0038] The source region 26 and the drain region 27 present in the memory device region 100 and the logic device region 102 comprise a semiconductor material and a dopant. The dopant may be either an n-type dopant or a p-type dopant, both as defined further herein. The semiconductor material providing the source region 26 and the drain region 27 comprises one of the semiconductor materials mentioned above in providing the semiconductor substrate 10. The semiconductor material providing the source region 26 and the drain region 27 may be compositionally the same as or different from the semiconductor material provided by each semiconductor channel material nanosheet 16. The term "n-type" refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor.In a silicon-containing semiconductor material, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus. The term "p-type" refers to the addition of impurities to an intrinsic semiconductor, which creates deficiencies in valence electrons. In a silicon-containing semiconductor material, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, and indium. The concentration of the n-type or p-type dopant in the source region 26 and the drain region 27 can range from 1×10 18 atoms / cm 3 up to 1×10 21 atoms / cm 3 sufficient, although dopant concentrations greater than 1×10 21 atoms / cm 3 or smaller than 1×10 18 atoms / cm 3 are also conceivable.

[0039] The first interlayer dielectric layer 30 present in the memory device region 100 and the logic device region 102 may be comprised of a dielectric, including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), boron phosphorus silicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. As used throughout this application, the term "low-k" refers to a dielectric having a dielectric constant of less than 4.0. The first interlayer dielectric layer 30 typically comprises a plurality of the aforementioned dielectrics.

[0040] Each front-side source / drain contact structure 28 present in the memory device region 100 and the logic device region 102 is arranged on a surface of the source region 26 and a surface of the drain region 27. Each front-side source / drain contact structure 28 is composed of at least one contact conductor material. The contact conductor material may, for example, include a silicide liner, such as Ni, Pt, NiPt, an adhesion metal liner, such as TiN, and conductive metals such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or an alloy thereof. Each front-side source / drain contact structure 28 may also include one or more contact liners (not shown). In one or more embodiments, the contact liner (not shown) may include a diffusion barrier material.Example diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, an alloy thereof, or a stack thereof, such as Ti / TiN and Ti / WC. In one or more embodiments where a contact liner is present, the contact liner (not shown) may include a silicide liner such as Ti, Ni, NiPt, etc., and a diffusion barrier material as defined above.

[0041] The front-side contact structure 32 present in the memory device region 100 and the logic device region 102 consists of at least one contact conductor material, as mentioned above for the front-side source / drain contact structures 28. The front-side contact structure 32 may also include a diffusion barrier material, as defined above, present along a sidewall and a bottom wall of the front-side contact structure 32. In the memory device region 100, the front-side contact structure 32 and the front-side source / drain contact structure 28 electrically connect the front-side ReRAM 34 / 35 / 36 to the source region 26 of the transistor T1.

[0042] The front-side ReRAM 34 / 35 / 36 includes a first electrode 34, a filament-forming layer 35 (also referred to herein as a dielectric switching layer), and a second electrode 36. The first electrode 34 may be made of an electrically conductive material such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Cu, Co, CoWP, CoN, W, WN, or any combination thereof. The first electrode 34 may have a thickness of 2 nm to 80 nm; other thicknesses are possible and may be used in the present application as the thickness of the first electrode 34. The filament-forming layer 35 is made of a dielectric, such as a metal oxide dielectric, having a dielectric constant of 4.0 or greater.The filament-forming layer 35 is electrically insulating at this point in the present application, and in functional use, a filament that is electrically conductive may be formed in the filament-forming layer 35. Examples of dielectric metal oxides that may be used as the filament-forming layer 35 include, but are not limited to, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, or combinations thereof. In some embodiments, hydrogen may be present in the dielectric providing the filament-forming layer 35. The filament-forming layer 35 may have a thickness of 1 nm to 50 nm, but other thicknesses are contemplated and may be used as the thickness of the filament-forming layer 35. The second electrode 36 may comprise one of the electrically conductive materials mentioned above for the first electrode 34.In some embodiments, the electrically conductive material providing the second electrode 36 is compositionally the same as the electrically conductive material providing the first electrode 34. In one example, the electrically conductive material providing both the first electrode 34 and the second electrode 36 is TiN. In other embodiments, the electrically conductive material providing the second electrode 36 is compositionally different from the electrically conductive material providing the first electrode 34. In one example, the electrically conductive material providing the first electrode 34 is TaN, and the electrically conductive material providing the second electrode 36 is TiN. The lateral width of the ReRAM may be greater than 1 gate pitch.

[0043] The dielectric layer 38, which is arranged on a top surface and on the sidewalls of the ReRAM 34 / 35 / 36 and on the first front-side interlayer dielectric layer 30, may be made of a dielectric hardmask material, for example, silicon nitride and / or silicon oxynitride. The dielectric layer 38 present in the memory device region may be referred to as a dielectric encapsulation material layer. The dielectric layer 38 may have a thickness of 5 nm to 50 nm; however, other thicknesses are possible and may be used in the present application as the thickness of the dielectric layer 38. The dielectric layer 38 may be a conformal dielectric layer. By “conformal” is meant that a material layer has a vertical thickness along horizontal surfaces that is substantially equal (i.e.within ± 10%) as the lateral thickness along vertical surfaces.

[0044] The second front-side interlayer dielectric layer 40 is composed of a dielectric as mentioned above for the first front-side interlayer dielectric layer 30. The dielectric providing the second front-side interlayer dielectric layer 40 may be the same in composition as or different in composition from the dielectric providing the first front-side interlayer dielectric layer 30.

[0045] The front-side BEOL-to-ReRAM metal via 42 present in the memory device region 100 and the logic device region 102 is made of at least one contact conductor material as mentioned above for the front-side source / drain contact structures 28. The front-side BEOL-to-ReRAM metal via 42 may also include a diffusion barrier material, as defined above, present along a sidewall and a bottom wall of the front-side BEOL-to-ReRAM metal via 42. In the memory device region 100, the front-side BEOL-to-ReRAM metal via 42 electrically connects the second (i.e., top) electrode 36 of the front-side ReRAM 34 / 35 / 36 to the front-side BEOL structure 44. As illustrated, the front-side BEOL-to-ReRAM metal via 42 extends through the dielectric layer 38 present on the topmost surface of the ReRAM 34 / 35 / 36.

[0046] A front-side metal via 43 is present in the logic device region 102, electrically connecting the front-side BEOL structure 44 to the front-side contact structure 32. The front-side metal via 43 is composed of at least one contact conductor material, as mentioned above for the front-side source / drain contact structures 28. The front-side metal via 43 may also include a diffusion barrier material, as defined above, present along a sidewall and a bottom wall of the front-side metal via 43.

[0047] The front-side BEOL structure 44 present in the memory device region 100 and the logic device region 102 may include one or more interconnecting dielectric layers (including one of the dielectrics mentioned above for the first front-side interlayer dielectric layer 30) containing one or more interconnection regions (wherein the interconnection regions may comprise any electrically conductive metal (e.g., Cu) or an electrically conductive metal alloy (e.g., Cu-Al)) embedded therein. The carrier wafer 46 may comprise one of the semiconductor materials mentioned above for the semiconductor substrate 10.

[0048] The Fig. 1A and Fig. The exemplary structures illustrated in Figure 1B may be formed using a combination of front-end-of-the-line (FEOL) processing, middle-of-the-line (MOL) processing, and front-side BEOL processing, each of which processing steps are known to those skilled in the art. FEOL processing may comprise a conventional process for forming a nanosheet device, which is also known to those skilled in the art. MOL processing and BEOL processing may comprise metallization processes, which are also known to those skilled in the art. Metallization may comprise forming an opening in at least one material layer and then filling that opening with at least one conductive material. Filling may comprise depositing the conductive material followed by a planarization process, such as chemical mechanical polishing (CMP).BEOL processing also includes a processing step of the ReRAM device, which is also known to those skilled in the art. To avoid obscuring the method of the present application, the details of FEOL processing, MOL processing, and BEOL processing are not provided here.

[0049] Now referring to Fig. 2A and Fig. 2B are the ones in Fig. 1A and 1B, respectively, after removal of the semiconductor substrate 10 to enable backside processing in both the memory device region 100 and the logic device region 102. Before removing the semiconductor substrate 10, the wafer is typically rotated 180° to expose a backside of the semiconductor substrate 10; for simplicity, the wafer flipping is not shown in the drawings. Backside processing occurs on a side of a wafer opposite the transistors. Flipping the structure may be performed manually or using a mechanical means, such as a robotic arm. Removal of the semiconductor substrate 10 may be performed using a material removal process (e.g., a wet chemical etch) that is selective in removing the semiconductor material that the semiconductor substrate 10 provides.This material removal process may comprise a single step, or multiple steps may be used depending on the compositional structure of the semiconductor substrate 10. Note that the material removal process that removes the semiconductor substrate 10 in both the memory device region 100 and the logic device region 102 forms a gap 48 between the shallow trench isolation structure 12, exposing the lower dielectric isolation layer 14.

[0050] Now referring to Fig. 3A and Fig. 3B are the ones in Fig. 2A and 2B, respectively, after a backside interlayer dielectric layer 50 has been formed in both the memory device region 100 and the logic device region 102. The backside interlayer dielectric layer 50 is formed in each gap 48 formed by removing the semiconductor substrate 10 from the structures. The backside interlayer dielectric layer 50 has a surface directly contacting the bottom dielectric isolation layer 14 and another surface opposite the surface contacting the bottom dielectric isolation layer 14 that is coplanar with a physically exposed horizontal surface of the shallow trench isolation structure 12.The backside interlayer dielectric layer 50 comprises a dielectric as mentioned above for the first frontside interlayer dielectric layer 30. The backside interlayer dielectric layer 50 may be formed by deposition followed by planarization. The deposition of the backside interlayer dielectric layer 50 may comprise chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or spin-on coating. The planarization may comprise CMP and / or grinding.

[0051] Now referring to Fig. 4A and Fig. 4B are the ones in Fig. 3A and 3B, respectively, after a back contact structure 52 has been formed in both the memory device region 100 and the logic device region 102. Each back contact structure 52 is in direct physical contact with the drain region 27 of the respective transistor, i.e., T1 or T2, present in the region of the specific device. Each back contact structure 52 extends through the back interlayer dielectric layer 50 and the bottom dielectric isolation layer 14. Each back contact structure 52 is comprised of at least one contact conductor material, as mentioned above for the front source / drain contact structures 28. Each back contact structure 52 may also include a diffusion barrier material, as defined above, present along a sidewall and a bottom wall of each back contact structure 52.Each back contact structure 52 may be formed by a metallization process as defined above.

[0052] Now referring to Fig. 5A and Fig. 5B are the ones in Fig. 4A and 4B, respectively, after a backside BEOL structure 54 has been formed in each of the memory device region 100 and the logic device region 102. The backside BEOL structure 54 comprises materials as mentioned above for the frontside BEOL structure 44. The backside BEOL structure 54 may be formed using any interconnect device process, including, for example, a damascene process. As illustrated, the backside contact structure 52 in the memory device region 100 electrically connects the drain region 27 of the transistor T1 to the backside BEOL structure 54, and the backside contact structure 52 in the logic device region 102 electrically connects the drain region 27 of the transistor T2 to the BEOL structure 54.

[0053] Fig. 5A particularly illustrates a semiconductor structure according to an embodiment of the present application, including transistor T1 arranged in memory device region 100. Transistor T1 includes gate structure 22, source region 26 arranged on a first side of gate structure 22, and drain region 27 arranged on a second side of gate structure 22, wherein the second side of gate structure 22 is opposite to the first side of gate structure 22. The structure further includes front-side ReRAM 34 / 35 / 36 arranged in memory device region 100 and positioned above transistor T1. Also present is front-side contact structure 32 electrically connecting front-side ReRAM 34 / 35 / 36 to source region 26 of transistor T1.Also present is the rear contact structure 52, which electrically connects the drain region 27 of the transistor T1 to the rear BEOL structure 54. In the embodiment shown in . Fig. 5A, the switching area of ​​the front-side ReRAM 34 / 35 / 36 is effectively increased without increasing the gate pitch. Since this is an application for an embedded memory, there is a wiring advantage for the structure (see Fig. 5B) present in the logic unit region 102.

[0054] Now referring to Fig. 6A, there is illustrated another exemplary structure present in the memory device region 100 of the semiconductor substrate 10, this exemplary structure comprising the transistor T1 as defined above, the front-side contact structure 32, the front-side BEOL structure 44 and the carrier wafer 46, all of which are present on the front side of the semiconductor substrate 10 and all of which are made of materials as described above for the Fig. 1A and Fig. 1B shown exemplary structures were mentioned. In the Fig. The transistor T1 shown in Figure 6A is a nanosheet transistor comprising the lower dielectric insulation layer 14, the semiconductor channel material nanosheets 16, the inner spacer 18, the gate spacer 20, the gate structure 22, the gate cap 24, the source region 26 and the drain region 27, all of which are described above in connection with the Fig. 1A and Fig. 1B shown exemplary structure. The Fig. 6A further comprises the source / drain contact structure 28, the first front-side interlayer dielectric layer 30 and the second front-side interlayer dielectric layer 40, each of which is described above with respect to the structure shown in Fig. 1A and Fig. 1B. In this embodiment and in the memory device region 100, the front-side metal via 43 is present in the second front-side interlayer dielectric layer, which electrically connects the front-side BEOL structure 44 to the front-side contact structure 32 present in the first front-side interlayer dielectric layer 30. It should be noted that at the front side of the Fig. 6A, no front-side ReRAM 34 / 35 / 36 or dielectric layer 38 is present. The front-side metal via 43 present in the memory device region 100 comprises materials as mentioned above for the front-side metal via 43 shown in Fig. 1B was present.

[0055] Now referring to Fig. 6B, there is illustrated another exemplary structure present in the logic unit region 102 of the semiconductor substrate 100, wherein the logic unit region 102 is adjacent to the Fig. 6A illustrated memory unit region 100. The Fig. 6B illustrates another exemplary structure has an element as described above in Fig. 1B. Note that at the front side of the logic device region 102, there is no dielectric layer 38 separating the first front side interlayer dielectric layer 30 from the second front side interlayer dielectric layer 40.

[0056] The Fig. 6A and Fig. The exemplary structures illustrated in Figure 6B may be formed using a combination of FEOL processing, MOL processing, and front-side BEOL processing, each of which processing steps is known to those skilled in the art. The FEOL processing may comprise a conventional process with respect to the nanosheet device, which is also known to those skilled in the art. The MOL processing and BEOL processing may comprise metallization processes (as defined above), which are also known to those skilled in the art. In order not to obscure the method of the present application, the details of the FEOL processing, MOL processing, and BEOL processing are not provided here.

[0057] Now referring to Fig. 7A and Fig. 7B are the Fig. 6A and 6B, respectively, after removal of the semiconductor substrate 10 to enable backside processing in both the memory device region 100 and the logic device region 102. Before removing the semiconductor substrate 10, the wafer is typically rotated 180° to expose a backside of the semiconductor substrate 10; for simplicity, the wafer flipping is not shown in the drawings. Backside processing occurs on a side of a wafer opposite the transistors. Flipping the structure may be performed manually or using a mechanical means, such as a robotic arm. Removal of the semiconductor substrate 10 may be performed using a material removal process (e.g., a wet chemical etch) that is selective in removing the semiconductor material that the semiconductor substrate 10 provides.This material removal process may comprise a single step, or multiple steps may be used depending on the compositional structure of the semiconductor substrate 10. Note that the material removal process that removes the semiconductor substrate 10 in both the memory device region 100 and the logic device region 102 forms a gap 48 between the shallow trench isolation structure 12, exposing the lower dielectric isolation layer 14.

[0058] Now referring to Fig. 8A and Fig. 8B are the ones in Fig. 7A and 7B, respectively, after a backside interlayer dielectric layer 50 has been formed in both the memory device region 100 and the logic device region 102. The backside interlayer dielectric layer 50 is formed in each gap 48 formed by removing the semiconductor substrate 10 from the structures. The backside interlayer dielectric layer 50 has a surface directly contacting the bottom dielectric isolation layer 14 and another surface opposite the surface contacting the bottom dielectric isolation layer 14 that is coplanar with a physically exposed horizontal surface of the shallow trench isolation structure 12.The backside interlayer dielectric layer 50 comprises a dielectric as mentioned above for the first frontside interlayer dielectric layer 30. The backside interlayer dielectric layer 50 may be formed by deposition followed by planarization as defined above to provide the backside interlayer dielectric layer 50 shown in FIG. Fig. 3A and Fig. 3B is illustrated.

[0059] Now referring to Fig. 9A and Fig. 9B are the ones in Fig. 8A and 8B, respectively, after a back contact structure 52 has been formed in both the memory device region 100 and the logic device region 102. Each back contact structure 52 is in direct physical contact with a drain region of the respective transistor, i.e., T1 or T2, present in the region of the specific device. Each back contact structure 52 extends through the back interlayer dielectric layer 50 and the bottom dielectric isolation layer 14. Each back contact structure 52 is comprised of at least one contact conductor material, as mentioned above for the front source / drain contact structures 28. Each back contact structure 52 may also include a diffusion barrier material, as defined above, present along a sidewall and a bottom wall of each back contact structure 52.Each back contact structure 52 may be formed by a metallization process as defined above.

[0060] Now referring to Fig. 10A and Fig. 10B are the ones in Fig. 9A and 9B, respectively, after further backside processing, including forming a ReRAM 56 / 57 / 58 in the memory device region 100 and forming a backside BEOL structure 54. The ReRAM 56 / 57 / 58 is a backside ReRAM and includes a first electrode 56, a filament-forming layer 57, and a second electrode 58. The first electrode 56 includes a conductive material as mentioned above for the first electrode 34 of the frontside ReRAM, the filament-forming layer 57 includes a dielectric as mentioned above for the filament-forming layer 35 of the frontside ReRAM, and the second electrode 58 includes a conductive material as mentioned above for the second electrode 36 of the frontside ReRAM.This backside ReRAM 56 / 57 / 58 can be formed by depositing the various material layers, followed by lithographically patterning these various deposited material layers; these processing steps can be used to form the in . Fig. 1A. As shown in Fig. 10A, the backside ReRAM 56 / 57 / 58 has a surface that is in direct physical contact with the backside contact structure 52 formed in contact with the drain region 27 of the transistor T1 present in the memory device region 100.

[0061] After forming the backside ReRAM 56 / 57 / 58, the dielectric layer 59 is formed. The dielectric layer 59 comprises a dielectric as mentioned above for the dielectric layer 38. The dielectric layer 59 encapsulates the backside ReRAM 56 / 57 / 58; ie, it is present on physically exposed surfaces of the backside ReRAM 56 / 57 / 58.

[0062] The second backside dielectric layer 60 is then formed on the dielectric layer 59. The second backside dielectric layer 60 embeds the backside ReRAM 56 / 57 / 58. The second backside dielectric layer 60 comprises a dielectric as mentioned above for the first frontside interlayer dielectric layer 30, and the second backside dielectric layer 60 can be formed by a deposition process, for example, CVD, PECVD, or spin-on plating.

[0063] The backside BEOL-to-ReRAM metal via 62 is then formed in the memory device region 100, and the backside metal via 63 is formed in the logic device region 102. The backside BEOL-to-ReRAM metal via 62 and the backside metal via 63 are composed of at least one contact conductor material, as mentioned above for the frontside source / drain contact structures 28. These via structures may also include a diffusion barrier material, as defined above, present along a sidewall and a bottom wall of each of the via structures. The backside BEOL-to-ReRAM metal via 62 and the backside metal via 63 may be formed by a metallization process, as defined above.As illustrated, the backside BEOL-to-ReRAM metal via 62 extends through the dielectric layer 59 and contacts the second electrode 58 of the backside ReRAM 56 / 57 / 58.

[0064] The backside BEOL structure 54 includes materials as mentioned above for the frontside BEOL structure 44. The backside BEOL structure 54 may be formed using any interconnect device process, including, for example, a damascene process. As illustrated, the backside contact structure 52 in the memory device region 100 electrically connects the drain region 27 of the transistor T1 to the backside ReRAM 56 / 57 / 58, and the backside BEOL-to-ReRAM metal via 62 electrically connects the backside ReRAM 56 / 57 / 58 to the backside BEOL structure 54. The backside contact structure 52 and the backside metal via 63 in the logic device region 102 electrically connect the drain region 27 of the transistor T2 to the backside BEOL structure 54.

[0065] Fig. In particular, Figure 10A illustrates a semiconductor structure according to another embodiment, including transistor T1 arranged in memory device region 100. Transistor T1 includes gate structure 22, source region 26 arranged on a first side of gate structure 22, and drain region 27 arranged on a second side of gate structure 22, wherein the second side of gate structure 22 is opposite to the first side of gate structure 22. The structure of this embodiment further includes a ReRAM 56 / 57 / 58 arranged in memory device region 100 and positioned above transistor T1. Even further, the structure comprises the front-side contact structure 32, which electrically connects the source region 26 of the transistor T1 to the front-side BEOL structure 44, and the back-side contact structure 52, which electrically connects the drain region 27 of the transistor T1 to the ReRAM 56 / 57 / 58.This rear ReRAM 56 / 57 / 58 is electrically connected to the rear BEOL structure 54 through the rear BEOL-to-ReRAM metal via 62. In the embodiment shown in . Fig. 10A, the switching area of ​​the rear ReRAM 56 / 57 / 58 is effectively increased without increasing the gate pitch. In other words, the lateral width of the ReRAM can be larger than 1 gate pitch. Since this is an application for an embedded memory, there is a wiring advantage for the structure (see Fig. 10B) present in the logic unit region 102. In this embodiment of the present application, there is no need to move the gate contact (not shown) as is required for the Fig. 5A illustrated embodiment would be the case.

[0066] While this application has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made without departing from the scope of this application. It is therefore intended that this application not be limited to the precise forms and details described and illustrated, but rather be within the scope of the appended claims.

Claims

[1] Semiconductor structure that has: a transistor arranged in a memory unit region and having a gate structure, a source region arranged on a first side of the gate structure, and a drain region arranged on a second side of the gate structure, the second side of the gate structure being opposite the first side of the gate structure. a resistive random access memory (ReRAM) disposed in the memory device region and positioned above the transistor; a front-side contact structure that electrically connects the ReRAM to the source region of the transistor; and a backside contact structure that electrically connects the drain region of the transistor to a backside back-end-of-the-line (BEOL) structure. [2] The semiconductor structure of claim 1, wherein the transistor is a nanosheet transistor comprising a plurality of vertically stacked and spaced-apart semiconductor channel material nanosheets, and wherein the gate structure of the transistor encloses a central portion of each semiconductor channel material nanosheet of the plurality of vertically stacked and spaced-apart semiconductor channel material nanosheets. [3] The semiconductor structure of claim 2, further comprising a bottom dielectric isolation layer and a back interlayer dielectric layer disposed beneath the nanosheet transistor, wherein the back contact structure extends through both the back interlayer dielectric layer and the bottom dielectric isolation layer and is in direct physical contact with the drain region of the transistor. [4] The semiconductor structure of claim 1, further comprising a source / drain contact structure disposed between the front-side contact structure and the source region of the transistor, wherein the front-side contact structure is in direct physical contact with a first surface of the source / drain contact structure and a second surface of the source / drain contact structure, opposite the first surface, is in direct physical contact with the source region of the transistor. [5] The semiconductor structure of claim 1, further comprising a front-side BEOL structure disposed over the ReRAM, the front-side BEOL structure being electrically connected to a top electrode of the ReRAM by a front-side BEOL-to-ReRAM metal via. [6] The semiconductor structure of claim 5, wherein the front-side BEOL-to-ReRAM metal via passes through a dielectric layer present on the ReRAM. [7] The semiconductor structure of claim 5, further comprising a carrier wafer disposed on a surface of the front-side BEOL structure. [8] The semiconductor structure of claim 1, wherein the ReRAM is embedded in a front-side interlayer dielectric layer. [9] The semiconductor structure of claim 1, further comprising a logic unit region disposed adjacent to the memory unit region, the logic unit region comprising a further transistor, the further transistor comprising a further gate structure, a further source region disposed on the first side of the further gate structure, and a further drain region disposed on the second side of the further gate structure, the second side of the further gate structure being opposite the first side of the further gate structure. [10] The semiconductor structure of claim 9, further comprising a further front-side contact structure electrically connecting the further source region of the further transistor to a front-side BEOL structure, and a further back-side contact structure electrically connecting the further drain region of the further transistor to a back-side BEOL structure. [11] Semiconductor structure having: a transistor arranged in a memory unit region and having a gate structure, a source region arranged on a first side of the gate structure, and a drain region arranged on a second side of the gate structure, the second side of the gate structure being opposite the first side of the gate structure; a resistive random access memory (ReRAM) disposed in the memory unit region and positioned below the transistor; a front-side contact structure electrically connecting the source region of the transistor to a front-side back-end-of-the-line (BEOL) structure; and a backside contact structure that electrically connects the drain region of the transistor to the ReRAM. [12] The semiconductor structure of claim 11, wherein the transistor is a nanosheet transistor comprising a plurality of vertically stacked and spaced-apart semiconductor channel material nanosheets, and wherein the gate structure of the transistor encloses a central portion of each semiconductor channel material nanosheet of the plurality of vertically stacked and spaced-apart semiconductor channel material nanosheets. [13] The semiconductor structure of claim 12, further comprising a bottom dielectric isolation layer and a back interlayer dielectric layer disposed beneath the nanosheet transistor, wherein the back contact structure extends through both the back interlayer dielectric layer and the bottom dielectric isolation layer and is in direct physical contact with the drain region of the transistor. [14] The semiconductor structure of claim 11, further comprising a source / drain contact structure disposed between the front-side contact structure and the source region of the transistor, wherein the front-side contact structure is in direct physical contact with a first surface of the source / drain contact structure and a second surface of the source / drain contact structure, opposite the first surface, is in direct physical contact with the source region of the transistor. [15] The semiconductor structure of claim 11, further comprising a front-side metal via disposed between the front-side contact structure and the front-side BEOL structure, the front-side metal via having a first surface directly contacting the front-side BEOL structure and a second surface opposite the first surface directly contacting the front-side contact structure. [16] The semiconductor structure of claim 11, further comprising a backside BEOL structure disposed beneath the ReRAM, the backside BEOL structure being electrically connected to a bottom electrode of the ReRAM by a backside BEOL-to-ReRAM metal via. [17] The semiconductor structure of claim 11, further comprising a carrier wafer disposed on a surface of the front-side BEOL structure. [18] The semiconductor structure of claim 11, wherein the ReRAM is embedded in a backside interlayer dielectric layer. [19] The semiconductor structure of claim 11, further comprising a logic unit region disposed adjacent to the memory unit region, the logic unit region comprising a further transistor, the further transistor comprising a further gate structure, a further source region disposed on the first side of the further gate structure, and a further drain region disposed on the second side of the further gate structure, the second side of the further gate structure being opposite the first side of the further gate structure. [20] The semiconductor structure of claim 19, further comprising a further front-side contact structure electrically connecting the further source region of the further transistor to a front-side BEOL structure, and a further back-side contact structure electrically connecting the further drain region of the further transistor to a back-side BEOL structure.

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