Semiconductor package assembly

Abstract

A semiconductor package assembly is provided, comprising a semiconductor structure (e.g., an integrated circuit chip) and a package substrate electrically connected to the semiconductor structure. The assembly also includes a ceramic capacitor including alternating dielectric layers and internal electrode layers, wherein the internal electrode layers include first internal electrode layers and second internal electrode layers. The capacitor further includes external terminals disposed on a first surface of the capacitor and electrically connected to the semiconductor structure, and external terminals disposed on the second surface of the capacitor and electrically connected to the package substrate.

Description

Related registration

[0001] This application is based upon and claims priority from U.S. Provisional Patent Application Serial No. 63 / 420,761, filed October 31, 2022, which is hereby incorporated by reference. Background of the invention

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a wide variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density is largely due to repeated reductions in the minimum feature size, allowing more components to be integrated into a given area. With the increasing demand for ever smaller electronic devices, a need has arisen for smaller and more creative packaging techniques for semiconductor chips. To enable high-density implementation of semiconductor chips, interposers made of organic, inorganic (e.g., glass), or silicon materials are often used. Such an assembly is often referred to as a chip-on-interposer or chip-on-wafer (CoW) structure when the interposer is made of a semiconductor material (e.g., silicon).The CoW structure can then be attached to a build-up packaging substrate to form the CoWoS structure, and the resulting package can finally be connected to a printed circuit board. One or more ceramic capacitors are typically also used as part of the chip's power supply system, so that in the event of a sudden power demand, the chip can be supplied with a constant or near-constant voltage. Unfortunately, however, increased switching speeds in chips have led to increased parasitic inductances. Therefore, there is currently a need for improved semiconductor packaging assemblies that utilize a ceramic capacitor. Brief description of the invention

[0003] According to one embodiment of the present invention, a semiconductor package assembly comprising a semiconductor structure and a package substrate electrically connected to the semiconductor structure is disclosed. The assembly further includes a ceramic capacitor having a first surface and an opposite second surface, the ceramic capacitor including alternating dielectric layers and internal electrode layers. The internal electrode layers include first internal electrode layers and second internal electrode layers.The capacitor further includes a first external terminal electrically connected to the first internal electrode layers and disposed on a first surface of the capacitor, a second external terminal electrically connected to the first internal electrode layers and disposed on the second surface of the capacitor, a third external terminal electrically connected to the second internal electrode layers and disposed on the first surface of the capacitor, and a fourth external terminal electrically connected to the second internal electrode layers and disposed on the second surface of the capacitor. The first external terminal and the third external terminal are electrically connected to the semiconductor structure (e.g., optionally via an interposer), and the second external terminal and the fourth external terminal of the ceramic capacitor are electrically connected to the package substrate.

[0004] Further features and aspects of the present invention are set forth in more detail below. Short description of the characters

[0005] In the remainder of the specification and with reference to the accompanying drawings, a full and reproducible disclosure of the present invention, including the best mode thereof, is particularly set forth for those skilled in the art, in which: Fig. 1 is a cross-sectional view of one embodiment of a semiconductor package assembly of the present invention attached to a circuit board; Fig. 2 is a cross-sectional view of another embodiment of a semiconductor package assembly of the present invention; Fig. 3A is a perspective view of one embodiment of a ceramic capacitor that can be used in the present invention; Fig. 3B is a side view of the internal electrode layers of the capacitor of Fig. 3A; Fig. 4A is a perspective view of another embodiment of a ceramic capacitor that can be used in the present invention; Fig. 4B is an end view of the capacitor of Fig. 4A; Fig. 4C a side view of the capacitor of Fig. 4A; Fig. 5A is a perspective view of another embodiment of a ceramic capacitor that can be used in the present invention; Fig. 5B is a side view of the internal electrode layers of the capacitor of Fig. 5A; Fig. 6A is a perspective view of another embodiment of a ceramic capacitor that can be used in the present invention; Fig. 6B is a side view of the internal electrode layers of the capacitor of Fig. 6A; Fig. 6C is a perspective view of the internal electrode layers of the capacitor of Fig. 6A; Fig. 6D is a perspective cross-sectional view of the capacitor of Fig. 6A; Fig. 7A is a perspective view of another embodiment of a ceramic capacitor that can be used in the present invention; Fig. 7B is a side view of the internal electrode layers of the capacitor of Fig. 7A; Fig. 7C is a perspective view of the internal electrode layers of the capacitor of Fig. 7A; Fig. 7D is a perspective cross-sectional view of the capacitor of Fig. 7A; Fig. 8A is a perspective view of another embodiment of a ceramic capacitor that can be used in the present invention; Fig. 8B is a perspective cross-sectional view of the capacitor of Fig. 8A; Fig. 9A is a perspective view of yet another embodiment of a ceramic capacitor that can be used in the present invention; Fig. 9B is a perspective side view of a configuration of the internal electrode layers of the capacitor of Fig. 9A; and Fig. 9C is a perspective side view of another configuration of the internal electrode layers of the capacitor of Fig. 9A.

[0006] Where reference numerals are used multiple times in the present description and the drawings, these are intended to represent the same or analogous features or elements of the invention. Detailed description of representative embodiments

[0007] Those skilled in the art should appreciate that the present discussion is only a description of exemplary embodiments and is not intended to limit the broader aspects of the present invention.

[0008] Generally speaking, the present invention relates to a semiconductor package assembly comprising a semiconductor structure, a package substrate electrically connected to the semiconductor structure, and optionally an interposer located between and electrically connected to the semiconductor structure and the package substrate. The assembly further comprises a ceramic capacitor having a first surface and an opposite second surface. The ceramic capacitor includes alternating dielectric layers and internal electrode layers, wherein the internal electrode layers comprise first internal electrode layers and second internal electrode layers.A first external terminal is electrically connected to the first internal electrode layers and disposed on the first surface of the capacitor, and a second external terminal is electrically connected to the first internal electrode layers and disposed on the second surface of the capacitor. Similarly, a third external terminal is electrically connected to the second internal electrode layers and disposed on the first surface of the capacitor, and a fourth external terminal is electrically connected to the second internal electrode layers and disposed on the second surface of the capacitor. Typically, the first and second external terminals have the same polarity (e.g., positive), and the third and fourth external terminals have the same polarity (e.g., negative).Independently, the first external terminal and the third external terminal of the ceramic capacitor are electrically connected to the semiconductor structure, and the second external terminal and the fourth external terminal of the ceramic capacitor are electrically connected to the package substrate.

[0009] Various embodiments of the present invention will now be described in more detail. I. Semiconductor structure

[0010] Within the semiconductor packaging assembly, one or more semiconductor structures (e.g., chips, wafers, integrated circuits, etc.) may generally be used. Generally speaking, a semiconductor structure may include an insulating material (e.g., a dielectric material formed from multiple layers known in the art) and a plurality of conductive traces extending through the insulating material. The insulating material may include a dielectric material such as silicon dioxide, silicon nitride, oxynitride, a polyimide material, a glass fiber reinforced epoxy matrix material, or a low-k or ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, a photoimageable dielectric, and / or a benzocyclobutene-based polymer). The insulating material may also include a semiconductor material such as silicon, germanium, or a III-V material (e.g.,Gallium nitride) and one or more additional materials. For example, an insulating material may comprise silicon oxide or silicon nitride. The conductive paths of a chip may comprise conductive traces and / or conductive vias and may connect any conductive contacts in the chip in any suitable manner. The semiconductor structure may comprise a mixed-pitch chip (in the sense that the chip has sets of conductive contacts with different pitches); for example, the chip may have "coarser" conductive contacts for coupling to the interposer of the semiconductor packaging assembly. The structure may also comprise a single-sided chip (has only conductive contacts on a single surface) and / or a double-sided chip (conductive contacts on a first surface and on an opposite second surface).The conduction paths in the chips can be defined by lining materials, such as adhesion liners and / or barrier liners, as needed. The semiconductor structure can also comprise a wafer. In some embodiments, the semiconductor structure comprises monolithic silicon, a fan-out or fan-in package die, or a die stack (e.g., wafer-stacked, die-stacked, or multilayer die-stacked).

[0011] The semiconductor structure may also comprise integrated circuit ("IC") structures, such that it takes the form of a discrete IC device or "chip." Such an IC device may include one or more device layers disposed on a chip substrate. The chip substrate may be a semiconductor substrate composed of semiconductor material systems, including, for example, n-type or p-type material systems (or a combination of both). The chip substrate may, for example, comprise a crystalline substrate formed using a bulk silicon or silicon-on-insulator (SOI) substructure. In some embodiments, the chip substrate may be formed using alternative materials that may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.Other materials classified as Group II-VI, III-V, or IV may also be used to fabricate the chip substrate. The device layers may include one or more transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)), supporting circuitry for passing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other IC components. The device layers may include, for example, one or more source and / or drain (S / D) regions, a gate for controlling current flow in the transistors between the S / D regions, and one or more S / D contacts for conducting electrical signals to / from the S / D regions. Each transistor may include a gate consisting of at least two layers: a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers.The one or more layers may comprise silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric. The high-k dielectric may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve its quality when using a high-k material.

[0012] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers may be included for other purposes, such as a barrier layer. Metals that may be used for the gate electrode of a PMOS transistor include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning).Metals that can be used for the gate electrode of an NMOS transistor include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with respect to a PMOS transistor (e.g., for work function tuning). Electrical signals, such as power and / or input / output (I / O) signals, can be routed to and / or from the devices (e.g., transistors) of the device layer through one or more interconnect layers disposed on the device layer. For example, electrically conductive features of the device layer (e.g., the gate and S / D contacts) can be electrically coupled to the interconnect structures, which can optionally form a metallization stack (also referred to as an "ILD stack") of the IC device.The interconnect structures may include lines and / or vias filled with an electrically conductive material, such as a metal. The lines may be arranged to conduct electrical signals in a direction of a plane that is substantially parallel to a surface of the chip substrate on which a device layer is formed. The vias may be arranged to conduct electrical signals in a direction of a plane that is substantially perpendicular to the surface of the chip substrate on which a device layer is formed.

[0013] The IC device may include, for example, a memory device (e.g., a random access memory (RAM) device such as a static RAM (SRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a conductive bridge RAM (CBRAM), an erasable programmable read-only memory (EPROM), a non-volatile memory (e.g., 3D XPoint), a volatile memory (e.g., high-bandwidth memory), a stacked memory, etc.); a logic device (e.g., an AND, OR, NAND, or NOR gate, a programmable logic device, etc.); a processor device (e.g., a central processing unit (CPU), a graphics processing unit (GPU), etc.); application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), platform controller hubs (PCHs), etc.), as well as any other suitable memory, logic, and / or processor device. Multiple components can be combined on a single structure.For example, a memory array consisting of multiple memory devices may be formed on the same chip as a processing device or other logic configured to store information in the memory devices or to execute instructions stored in the memory array.

[0014] The semiconductor structure may also be a "chiplet," a small integrated circuit (IC) that contains a well-defined subset of functions and is part of a processing module that, in turn, forms a larger integrated circuit, such as a computer processor. In some embodiments, one or more chiplets are coupled to the host chip in various ways, with each of the one or more chiplets containing a corresponding cache—for example, a last-level cache (LLC)—accessible by one or more cores of the host chip. The host chip may include one or more processor cores, each of which can act as a consumer of memory resources, and the chiplet may include one or more memory arrays coupled to be accessible by a corresponding processor core of the host chip.In this specific context, the terms "memory," "memory array," "memory resource," and related terms generally refer to either cache memory or non-cache memory (such as system memory). Likewise, the term "memory controller" generally refers to controller circuitry that provides access to cache memory or non-cache memory. The host chip may include a processor core that acts as a consumer of memory resources. For example, the host chip may execute an operating system, a binary input / output system (BIOS), and / or various other software processes. To facilitate the execution of such software, a chiplet may include one or more memory arrays coupled to be accessible to the processor core through a hardware interface.In one embodiment, the memory array comprises static random access memory (SRAM) or dynamic random access memory (DRAM) cells. Additionally or alternatively, the processor core may be coupled to cache data in the memory array—for example, when the processor core is coupled to access a last-level cache (LLC) of a memory array. In various other embodiments, the memory array may include non-volatile memory (NVM) cells. The chiplet may also include a memory controller coupled between the hardware interface and the memory array to control memory access on behalf of a process executing with the core. By providing the memory array in a chiplet disposed between the hardware interface and the host chip, data locality for use by one or more cores of the packaged device may be improved.This improved data locality enables access to storage resources that is more space-efficient, time-efficient, and / or energy-efficient.

[0015] The semiconductor structures may be arranged in a two-dimensional configuration or array, as known in the art (e.g., 2D, 2.1D, 2.3D, or 2.5D heterogeneous integration), or stacked in a 3D configuration. When using a stacked configuration, the semiconductor structure may include two or more semiconductor substrates (e.g., chips, interposers, etc.) mounted on a circuit board. When implemented as semiconductor chips, the substrates may consist of a variety of different types of circuit devices used in electronics, such as microprocessors, graphics processors, combined microprocessor / graphics processors, application-specific integrated circuits, memory devices, or the like, and may be single- or multi-core processors.The substrates can be made of bulk semiconductors, such as silicon or germanium, or of semiconductor-on-insulator materials, such as silicon-on-insulator materials. The circuit board can be a semiconductor chip packaging substrate, a printed circuit board, or virtually any other type of circuit board. A monolithic structure could be used for the circuit board, but a more typical configuration uses a build-up design. In this regard, the circuit board can consist of a central core on which one or more build-up layers are formed, and below which one or more further build-up layers are formed. The core itself can consist of a stack of one or more layers. Electrical paths between the substrates and the circuit board, as well as between the individual substrates, can be provided by interconnect structures. II. Housing substrate

[0016] In addition to the semiconductor structures, the semiconductor package assembly also includes a package substrate to support the bridging of high-density interconnects and functions. Generally speaking, the package substrate includes an insulating material and one or more conductive traces through the insulating material (e.g., including conductive traces and / or conductive vias, as shown). The insulating material may include, for example, organic materials such as bismaleimide triazine ("BT") resin materials (e.g., BT, BT epoxies, etc.), epoxy resin materials (e.g., glass fiber reinforced epoxy resin (e.g., FR4)), polyimide materials, low-k and ultra-low-k dielectrics (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, and an organic polymer dielectric). The insulating material may also be an inorganic material, such as ceramic materials (e.g.,glass) or semiconductor materials such as silicon, germanium and other materials of groups III-V (e.g. gallium nitride) and IV.

[0017] Depending on the particular configuration of the semiconductor package assembly, the conductive traces of the package substrate can serve a variety of different purposes. For example, in embodiments where the package substrate is directly connected to the semiconductor structure, the conductive traces can help connect the semiconductor structure to a printed circuit board. In embodiments where an interposer is employed, the conductive traces can help couple the interposer to the printed circuit board. In general, any suitable arrangement of conductive traces through any suitable number of insulating layers can be used. The conductive traces can be made of any suitable conductive material, such as copper. The conductive traces can be bounded by liner materials, such as adhesive liners and / or barrier liners, as needed.In certain embodiments, the packaging substrate may be a lower density medium, and the semiconductor structure and / or the optional interposer may be a higher density medium. The terms "lower density" and "higher density" are relative herein and indicate that the conductive traces (e.g., including conductive lines and conductive vias) in a lower density medium are larger and / or have a wider pitch than the conductive traces in a higher density medium. For example, a higher density medium may be manufactured using a modified semi-additive process or a semi-additive build process with advanced lithography (with small vertical interconnect features formed by advanced laser or lithography processes), while a lower density medium may be a PCB manufactured using a standard PCB process (e.g.,a standard subtractive process using chemical etchants to remove areas of unwanted copper and coarse vertical interconnect features formed by a standard laser process).

[0018] As noted above, the semiconductor structures may be electrically connected to one or more interposers, such that the resulting semiconductor package assembly is considered a "chip-on-interposer" structure. Among other things, the interposer may provide an intermediate substrate to help extend a connection to a greater distance or reroute a connection to another connection. In such embodiments, the semiconductor structure may be electrically connected to the interposer through one or more coupling components. The coupling components may electrically and mechanically couple the chip-on-interposer structure to the package substrate and may include, for example, solder bumps, solder balls, plug and socket portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.The underfill material may be an insulating material, such as a suitable epoxy material. When used, an underfill material may be a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material may include an epoxy flux that aids in soldering the semiconductor structure and then polymerizes and encapsulates the interconnects in the interposer. The interposer generally comprises an insulating material, as described above, and one or more conductive paths through the insulating material (e.g., including conductive traces and / or conductive vias, as shown). Such paths may include one or more metallic interconnects and vias, as is known in the art.For example, in one embodiment, the interposer may be made of silicon, and through-contacts called “through-silicon vias” (“TSVs”) may be formed therein.

[0019] Depending on the particular embodiment, the interposer, if employed, can be passive or active. By "passive" we generally mean that the interposer contains no embedded electronic components. An "active" interposer, on the other hand, generally contains one or more electronic components embedded in the insulating material. Examples of such electronic components include capacitors (e.g., the ceramic capacitors described here), resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, and microelectromechanical systems (MEMS) can also be formed in the interposer. For example, an active interposer may include an active layer and a bulk semiconductor layer.The front side of the active layer may be referred to herein as the "active side" and the opposite surface of the bulk semiconductor layer as the "back side." In one embodiment, the active layer may include one or more electronic components formed on the active side, such as level one (L1) memory elements used as memory caches for storing configuration bitstreams for configuring logic sectors in a coprocessor. The active layer may optionally include decryption / decompression circuitry for processing encrypted and / or decompressed configuration bitstreams. The semiconductor layer may include TSVs that connect electronic components (e.g., L1 memory elements) in the active layer to coupling elements (e.g., solder balls). For example, L1 caches may receive configuration bitstreams from a host processor via solder balls and TSVs.In this way, the energy efficiency of the signal and power transmission between the active layer of the interposer and the package substrate can be improved. III. Ceramic capacitor

[0020] As stated, at least one ceramic capacitor is electrically connected to the semiconductor structure and the package substrate so that the assembly can achieve "package-level decoupling." In one embodiment, for example, the ceramic capacitor may be directly connected to the semiconductor structure and the package substrate. However, in other embodiments, an interposer may be used between the semiconductor structure and the package substrate. In such embodiments, the ceramic capacitor may be located between the semiconductor structure and the interposer, such that the capacitor is electrically connected to the package substrate via the interposer. In another embodiment, the ceramic capacitor may be located between the interposer and the package substrate, such that the capacitor is electrically connected to the semiconductor structure via the interposer.

[0021] Regardless of the particular configuration of the assembly, the ceramic capacitor includes a main body comprising alternating dielectric layers and internal electrode layers. The internal electrode layers include at least first internal electrode layers and second internal electrode layers. The capacitor may, for example, include at least two, such as at least three, such as at least four, sets of internal electrode layers. It should be understood, of course, that the capacitor may include any number of sets of alternating dielectric layers and internal electrode layers and is not necessarily limited. Typically, the capacitor includes a top surface (e.g., first surface) and a bottom surface (e.g., second surface) opposite the top surface.The capacitor also comprises at least one side surface, in particular at least two side surfaces, extending between the upper surface and the lower surface. The capacitor may also comprise at least one end surface, in particular at least two end surfaces, extending between the upper surface and the lower surface. The side surfaces may extend in a length direction (L) and generally have a longer dimension than end surfaces extending in a width direction (W) and generally have a shorter dimension. In one embodiment, the capacitor may have the shape of a parallelepiped, such as a cuboid. The overall dimensions of the capacitor may depend on the particular application.Typically, however, the height or thickness of the capacitor is about 10 µm to about 5000 µm, in some embodiments about 20 µm to about 2500 µm, in some embodiments about 50 µm to about 1500 µm, and in some embodiments about 100 µm to about 1000 µm. When surrounded by a ball grid array, the height of the capacitor may be within 10%, such as within 7%, such as within 5%, such as within 3%, such as within 2%, such as within 1%, of the height (or diameter) of the balls of the ball grid array. For example, this height may correspond to the original height before reflow soldering.The length of the capacitor in the "L" direction may also be about 50 µm to about 10,000 µm, in some embodiments about 100 µm to about 7,500 µm, and in some embodiments about 1,000 µm to about 5,000 µm, and the width of the capacitor in the "W" direction may be about 25 µm to about 5,000 µm, in some embodiments about 50 µm to about 3,500 µm, and in some embodiments about 500 µm to about 2,500 µm.

[0022] The first internal electrode layers and the second internal electrode layers may be interleaved in an opposing and spaced-apart relationship with a dielectric layer located between each two internal electrode layers. The respective sets of alternating dielectric layers and internal electrode layers may be separated from an adjacent set by a certain distance. For example, this distance may be greater than the thickness of a single dielectric layer in the set, such as at least 2 times, in some embodiments at least 3 times, in some embodiments at least 5 times, and in some embodiments at least 10 times the thickness of a dielectric layer in the set.Each set of internal electrode layers and / or the entire capacitor may include from about 10 to about 4000, in some embodiments from about 50 to about 2000, and in some embodiments from about 100 to about 1000 internal electrode layers. The thickness of the dielectric layers and / or the internal electrode layers is not limited and may be any thickness depending on the performance characteristics. For example, the thickness of the internal electrode layers and / or the individual dielectric layers may range from about 100 nm to about 10 μm, in some embodiments from about 500 nm to about 8 μm, and in some embodiments from about 1 μm to about 5 μm.In certain embodiments, when the capacitor comprises a second set of alternating dielectric layers and internal electrode layers, the distance between the first internal electrode layer of one set and the last internal electrode layer of another set may be greater than the distance between adjacent internal electrode layers within a given set. For example, the distance between the first internal electrode layer of a first set and the last internal electrode layer of a second set may be greater than the distance between the first internal electrode layer and the second internal electrode layer of the first set.

[0023] Although by no means required, dielectric regions of the ceramic capacitor may also include one or more cavities. In this regard, the dielectric region may be a region that includes dielectric material but does not include the internal electrode material. Thus, the dielectric region may form a region that does not include alternating dielectric layers and internal electrode layers. Accordingly, the dielectric region may include the dielectric material between the respective sets of alternating dielectric layers and internal electrode layers in a "W" direction.Furthermore, the dielectric region may comprise the dielectric material between a side edge of the electrodes in a given set of alternating dielectric layers and internal electrode layers and an adjacent end face in the longitudinal direction, for example, to the extent that the internal electrode layers do not extend to the end face, so that they are offset from the end face. It should be understood that while such dielectric regions may be formed from ceramic green sheets of alternating dielectric layers and internal electrode layers, such regions do not comprise internal electrode material or corresponding layers. As a result, air voids may be provided within such regions.Furthermore, the dielectric regions may comprise the dielectric material present between the first internal electrode layer of the respective sets and an adjacent side surface of the capacitor. The dielectric regions may also comprise the dielectric material present between the last internal electrode layer of the respective sets and an adjacent side surface of the capacitor. The dielectric regions may also comprise the dielectric material between side edges of adjacent terminal tabs extending from the main body of the internal electrode layers. In a particular embodiment, the dielectric region may comprise the region within the capacitor located between two external terminals. Furthermore, it should be understood that the dielectric region may comprise a combination of any of the above-mentioned regions.

[0024] As stated, the dielectric regions include those that include dielectric material but do not include the internal electrode material. Accordingly, the dielectric regions may include 90 vol.% or more, such as 93 vol.% or more, such as 95 vol.% or more, such as 97 vol.% or more, such as 98 vol.% or more, such as 99 vol.% or more, such as 100 vol.%, of dielectric material, excluding the air voids. Such air voids may not include any material, in particular, dielectric material or internal electrode material. In one embodiment, the air voids may be enclosed, such as partially or completely, by a containment material. In one embodiment, the air voids may be partially enclosed by a containment material. "Partially enclosed" means that the containment material is only partially present around the interior of the air void, such that it is partially separated from the dielectric material.In this regard, at least a certain extent of the air pore may be in direct contact with the dielectric material of the dielectric region. In another embodiment, the air pores may be completely or entirely enclosed by a containment material. "Fully enclosed" means that the containment material is present around the interior of the air pore such that it is completely separated from the dielectric material. Regardless, the containment material may be used to serve as a barrier between the interior of the air pore and the dielectric material of the dielectric region. In one embodiment, the containment material may be a non-conductive material. However, it should be understood that in one embodiment, the air pores are not, even partially, enclosed by a containment material.

[0025] The air voids may be present without any barrier between the air void and the dielectric material of the dielectric region. The air void may have any shape and is not necessarily limited. For example, the shape may be a sphere, a cylinder, etc. In one embodiment, the shape may be a sphere. The air void may have a maximum dimension (e.g., length, width, diameter, etc.) of about 5 µm to about 5000 µm, in some embodiments from about 50 µm to about 2500 µm, and in some embodiments from about 100 µm to about 1000 µm. These voids may be formed by any known method, such as by printing specific patterns into the ceramic green sheets and then laminating and firing the stacked laminated sheets.Alternatively, the pores may also be formed using various drilling methods to provide any desired shape within the dielectric material or dielectric region. The pores may also be presented using one or more contact holes (e.g., vias). The vias may not be filled with material, such as any conductive or non-conductive material, so that air is present inside them. Furthermore, in one embodiment, the vias may be provided so that they are only present within the dielectric region. In this regard, the vias may be provided so that they do not contact any of the internal electrode layers. In one embodiment, the vias may extend from the top surface of the capacitor to the bottom surface of the capacitor.In this regard, the vias may extend columnarly through the thickness of the capacitor. Accordingly, the via may be a conductive via hole. In another embodiment, the vias may extend only partially through the thickness of the capacitor. For example, the vias may extend only partially through the capacitor thickness, for example, from about 10% to about 90%, and in some embodiments, from about 20% to about 80% of the capacitor thickness.

[0026] In addition to the alternating internal electrode layers and dielectric layers, the ceramic capacitor also includes a first external terminal electrically connected to the first internal electrode layers and disposed on a first surface of the capacitor (e.g., the top surface), and a second external terminal electrically connected to the first internal electrode layers and disposed on a second surface of the capacitor (e.g., the bottom surface). Likewise, a third external terminal is electrically connected to second internal electrode layers and disposed on the first surface of the capacitor, and a fourth external terminal is electrically connected to the second internal electrode layers and disposed on the second surface of the capacitor. Typically, the first and second external terminals have the same polarity (e.g.,positive), and the third and fourth external terminals have the same polarity (e.g., negative). Regardless, the first external terminal and the third external terminal of the ceramic capacitor may be electrically connected to the semiconductor structure, and the second external terminal and the fourth external terminal of the ceramic capacitor may be electrically connected to the package substrate.

[0027] The capacitor may also include external terminals on opposite end faces. For example, one or more of the external terminals may extend from the first face (e.g., top face) and / or the second face (e.g., bottom face) to an end face. If present on the end face, the external terminal may be only partially present on the end face, such that it does not cover the entire end face. In another embodiment, the capacitor may not include external terminals on opposite end faces. In a particular embodiment, the external terminals may not be present on a side face of the capacitor. Regardless, the external terminals generally include at least one terminal of a first polarity and at least one terminal of a second, opposite polarity.The capacitors may comprise at least one, such as at least two, such as at least four, such as at least six, such as at least eight, terminals of a first polarity and / or terminals of a second, opposite polarity on an upper surface of the capacitor. Furthermore, the capacitors may comprise the above-mentioned number of terminals on a lower surface of the capacitor.

[0028] The capacitors may include an equal number of terminals of a first polarity and / or terminals of a second polarity on the top and bottom surfaces of the capacitor. The number of terminals of the first polarity may be equal to the number of terminals of the second, opposite polarity on an top surface of a capacitor. The number of terminals of the first polarity may be equal to the number of terminals of the second, opposite polarity on a bottom surface of a capacitor. The total number of terminals present on an top surface of the capacitor may be equal to the total number of terminals present on a bottom surface of the capacitor.The total number of terminals of the first polarity present on an upper surface and a lower surface of the capacitor may be equal to the total number of terminals of the second, opposite polarity present on an upper surface and a lower surface of the capacitor. Typically, the like-polarity terminals on the lower surface of the capacitor, corresponding to a certain set of alternating dielectric layers and internal electrode layers, are electrically connected to the like-polarity terminals on the upper surface of the capacitor. The like-polarity terminals on an upper surface and a lower surface of a capacitor may not interdigitate.In this regard, corresponding terminals of the same polarity on a top and bottom surface may not be offset by one terminal position, but may instead be located directly above or below another terminal of the same polarity on the opposite top or bottom surface, respectively. In other words, corresponding terminals of the same polarity corresponding to a particular set of alternating dielectric layers and internal electrode layers, and in particular the corresponding terminal tabs of such a set, may be substantially aligned with each other. "Substantially aligned" means that the offset from a side edge of a side edge of a terminal of one polarity on a top surface is within + / -10%, such as within + / -5%, such as within + / -4%, such as within + / -3%, such as within + / -2%, such as within + / -1%, such as within + / -0.5% of the offset from a side edge of a terminal of the corresponding polarity is on a lower surface.

[0029] The pitch (i.e., the nominal center-to-center spacing, also referred to as center-to-center spacing) of the external terminals may be fixed by the particular package substrate configuration. The pitch between external terminals in one direction (i.e., x- or y-direction) may be the same as the pitch between adjacent external terminals in the other direction (i.e., y- or x-direction, respectively). That is, the pitch between any two adjacent external terminals may be substantially the same as the pitch between any two other adjacent external terminals. The pitch may, for example, range from about 0.1 to about 2 mm, in some embodiments, about 0.2 to about 1.5 mm, and in some embodiments, about 0.4 to about 1.4 mm.

[0030] If desired, the external terminals can be placed similarly to a ball grid array configuration. For example, the external terminals can be provided to make contacts as is typically employed in a ball grid array, particularly in a surrounding ball grid array. In this regard, the regular pitch of the external terminals can be the same as the regular pitch of a surrounding ball grid array. That is, the regular pitch can be within 10%, such as within 5%, such as within 2%, such as within 1%, such as within 0.5%, such as within 0.1% of the regular pitch of a surrounding ball grid array. Furthermore, the external terminals can be provided in rows and columns, as in a ball grid array. That is, the external terminals can be provided to be present in at least one row and at least two columns.For example, the external terminals may be present in at least two rows, such as at least three rows, such as at least four rows. The number of rows may be fixed by the number of different sets of alternating dielectric layers and internal electrode layers. Furthermore, the external terminals may be present in at least two columns, such as at least three columns, such as at least four columns. The number of columns may be fixed by the number of different column-like tabs of the internal electrodes.

[0031] The length (i.e., extending in the longitudinal direction from one end face to another end face) of an external terminal extending along the top surface may be the same as the length of a corresponding external terminal extending along the bottom surface. For example, the length of an external terminal may be about 0.3 to about 1.1 mm, in some embodiments about 0.4 to about 1 mm, and in some embodiments about 0.5 to about 0.9 mm. The length of an external terminal may also be less than the length of the capacitor, such as 50% or less, such as 40% or less, such as 30% or less, such as 25% or less, such as 20% or less, such as 15% or less, of the length of the capacitor. If desired, each external terminal may have a different length.For example, the external terminal adjacent to an end face may have a length that is greater than the offset of the external terminal from the end face. In this regard, the ratio of the length of the external terminal adjacent to an end face to the length of the external terminal offset from the end face may be about 0.3 to about 5, in some embodiments about 0.5 to about 4, and in some embodiments about 0.7 to about 3. The width of an external terminal extending from one side face to an opposite side face may be the same on the top face and the bottom face. For example, the width may range from about 0.3 to about 1.1 mm, in some embodiments about 0.4 to about 1 mm, and in some embodiments about 0.5 to about 0.9 mm.

[0032] If we focus on the Fig. 3A-3B, a particular embodiment of a ceramic capacitor 10 that can be used in the semiconductor package assembly of the present invention is shown in more detail. The capacitor 10 generally has a thickness "T," a width "W," and a length "L," as described above. Furthermore, the capacitor 10, as shown, has a 1-by-2 configuration, i.e., it includes two external terminals along a dimension of the top surface and the bottom surface. That is, the capacitor 10 includes a first external terminal 12 and a second external terminal 14 on an upper surface, and two corresponding third and fourth external terminals (not shown) on a lower surface. The first external terminal 12 and the third external terminal (not shown) may have the same polarity (i.e.,positive), and the second external terminal 14 and the fourth external terminal (not shown) may also have the same polarity (i.e., negative). The width "BW" and length "BL" of the external terminals 12 and / or 14 may be within the ranges discussed above. Although by no means required, a cavity 1350 may form in the capacitor 10 between the terminals 12 and 14, as described above.

[0033] The capacitor 10 also includes dielectric layers (not shown) and internal electrode layers 110, as shown in Fig. 3B. That is, the internal electrode layers 110 include first internal electrode layers 105 and a second set of internal electrode layers 115. In the particular embodiment shown, the internal electrode layers 105, 115 include at least one terminal tab 120, 130, 140, 150 extending from a top edge and a bottom edge of the main body of the internal electrode layers. The terminal tabs 120, 130, 140, 150 of the internal electrode layers 105, 115 may extend to the top surface and the bottom surface of the capacitor and assist in forming the external terminals. In this regard, the terminal tabs 120, 130, 140, 150 may be exposed on the top surface and the bottom surface of the capacitor and enable connection between the main body of the internal electrode layers and the external terminals.For example, the terminal tabs 120, 130, 140, 150 may include leading edges 123, 133, 143, 153 that extend to an edge of a dielectric layer and enable the formation of the external terminals. The length of the terminal tabs 120, 130, 140, 150 may vary as desired, but is typically about 0.3 to about 1.2 mm, in some embodiments about 0.4 to about 1.1 mm, and in some embodiments about 0.5 to about 1 mm. If more than one terminal tab is present along an edge, each terminal tab may have the same length. In another embodiment, each terminal tab may have a different length. For example, the terminal tab that is substantially aligned with the side edge of the internal electrode layer may have a length greater than the terminal tab that is offset from the side edges of the internal electrode layer.In this regard, the ratio of the length of the terminal tab aligned with the side edge of the inner electrode layer to the length of the terminal tab offset from the side edges of the inner electrode layer may be about 0.3 to about 5, in some embodiments about 0.5 to about 4, and in some embodiments about 0.7 to about 3. "Substantially aligned" generally means that the offset from a side edge of a lateral edge of a first terminal tab and / or second terminal tab at a top edge is within + / -10%, such as within + / -5%, such as within + / -4%, such as within + / -3%, such as within + / -2%, such as within + / -1%, such as within + / -0.5% of the offset from a side edge of a corresponding lateral edge of a first terminal tab and / or second terminal tab at a bottom edge.

[0034] As in Fig. 3B, a first internal electrode layer 105 comprises precisely one guide tab 120, 130 along an upper edge 105c and a lower edge 105d extending away from the main body 135. A second internal electrode layer 115 comprises precisely one guide tab 140, 150 along an upper edge and a lower edge extending away from the main body 145. The terminal tabs 120, 130 at the upper edge and at the lower edge of the first internal electrode layer 105 may be aligned in a perpendicular direction. That is, a lateral edge 121, 122 of a first terminal tab 120 along an upper edge 105c may be aligned with a lateral edge 131, 132 of a first terminal tab 130 along a lower edge 105d opposite the upper edge 105c. In addition, such lateral edges 121, 131 may also be aligned with the lateral edge 105a of the internal electrode layer 105.However, it should be understood that both lateral edges 121, 122 of the first terminal tab 120 may be aligned along an upper edge 105c with the lateral edges 131, 132 of a first terminal tab 130 along a lower edge 105d opposite the upper edge 105c. In other words, both lateral edges 122, 132 may be aligned and offset from the lateral edges 105a-b by the same distance along a lower edge 105d and the upper edge 105c. Likewise, the terminal tabs 140, 150 may be aligned in a perpendicular direction at the upper edge and the lower edge of the second internal electrode layer 115. That is, a lateral edge 141, 142 of a first terminal tab 140 along an upper edge may be aligned with a lateral edge 151, 152 of a first terminal tab 150 along a lower edge opposite the upper edge.In one embodiment, both lateral edges 141, 142 of the first terminal tab 140 along an upper edge may be aligned with the lateral edges 151, 152 of a first terminal tab 150 along a lower edge opposite the upper edge. The relationship between lateral edges of a first terminal tab at an upper edge and a first terminal tab at a lower edge, as mentioned with respect to the internal electrode layer 105, may also apply to the internal electrode layer 115. With such an arrangement, a gap may arise between terminal tab 120 of the first internal electrode layer 105 and terminal tab 140 of the second internal electrode layer 115. Likewise, a gap may arise between terminal tab 130 of the first internal electrode layer 105 and terminal tab 150 of the second internal electrode layer 115. The size of the respective gap may be substantially the same.

[0035] Terminal tabs 120 and 140 may be arranged parallel to terminal tabs 130 and 150, respectively, extending from internal electrode layers 105 and 115, such that terminal tabs extending from alternating electrode layers 105 and 115 may be aligned in a respective column. For example, terminal tabs 120 and 130 of internal electrode layer 105 may be arranged in a corresponding stacked configuration, while terminal tabs 140 and 150 of internal electrode layer 115 may be arranged in a corresponding stacked configuration.

[0036] It should be noted that terminal tabs 120 are connected to external terminal 12, while terminal tabs 140 are connected to external terminal 14. Accordingly, the respective terminal tabs 120 interlock with the respective terminal tabs 140 in a manner similar to the external terminals 12 and 14. The interlocking terminal tabs can provide multiple adjacent current injection points on the associated main electrode portions.

[0037] The spacing between adjacent exposed terminal tabs of the internal electrode layers in a given column may be specifically designed to ensure guided terminal formation. For example, the spacing between the exposed terminal tabs of the internal electrode layers in a given column may range from about 0.25 to about 10 µm, in some embodiments from about 0.5 to about 5 µm, and in some embodiments from about 1 to about 4 µm. In addition, the spacing between adjacent columnar stacks of electrode tabs may be, although not limited, at least a factor of two greater than the spacing between adjacent electrode tabs in a given column to ensure that different terminals do not run together.In some embodiments, the spacing between adjacent columnar stacks of exposed metallization is about 4x the spacing between adjacent exposed electrode tabs in a given stack. However, this spacing may vary depending on the desired capacitance performance and package substrate configuration. For example, the spacing may be about 0.1 to about 1.5 mm, in some embodiments about 0.2 to about 1.3 mm, and in some embodiments about 0.3 to about 1 mm, as determined from the center point of each terminal tab or from the distance between adjacent side edges of the terminal tabs. Additionally, this spacing may correspond to the ball separation distance on a ball grid array.

[0038] In the in the Fig. In the embodiments shown in Figures 3A-3B, the capacitor includes two external terminals extending to the ends of the capacitor. However, this is by no means required. For example, refer to Figures Fig. 4A-4C, an embodiment of a capacitor 10 is shown in which the first external terminal 12, the second external terminal 14, and the third and fourth external terminals (not shown) do not extend to one end of the capacitor. To help achieve such a configuration in this particular embodiment, the capacitor 10 includes the internal electrode layers 110, which include first internal electrode layers 105 and second internal electrode layers 115. The first internal electrode layers 105 may extend to a top surface of the capacitor 10, and the second internal electrode layers 115 may extend to a bottom surface of the capacitor. The extensions assist in forming the external terminals.In this regard, the internal electrode layers may be exposed on the top surface and the bottom surface of the capacitor and enable connection between the main body of the internal electrode layers and the external terminals. For example, the internal electrode layers 105, 115 may extend to an edge of a dielectric layer and enable the formation of the external terminals. The lateral or side edges of the internal electrode layers 105, 115 may be aligned with each other in a vertical direction. That is, a lateral edge of a first internal electrode layer 105 may be aligned with a lateral edge of a second internal electrode layer 115. In one embodiment, both lateral edges may be aligned.In another embodiment, the contact point of a first internal electrode layer 105 with an external terminal may be aligned with the contact point of a second internal electrode layer 115 with an external terminal. Furthermore, the capacitor 10 of FIG. Fig. 4A, at least one terminal of a first polarity and at least one terminal of a second, opposite polarity on a top surface. Although not shown, the bottom surface includes at least one terminal of a first polarity and one terminal of a second, opposite polarity.

[0039] In the in the Fig. 3A-3B and 4A-4C, the capacitor includes two external terminals on each face. However, as already stated, the present invention is not limited by the number of external terminals and / or the number of terminal tabs extending from a top edge and / or a bottom edge. When we refer to the Fig. 5A and Fig. 5B, for example, a capacitor 20 is shown having a 1-by-4 array configuration and thus including four external terminals on each face. That is, the capacitor includes four terminals along two dimensions of the top face and the bottom face. In this regard, the capacitor includes a total of four external terminals on an upper face—i.e., first external terminals 22a and 22b and second external terminals 24a and 24b—and corresponding sets of third and fourth external terminals (not shown) on a lower face. The first external terminals 22a, 22b and the third external terminals (not shown) generally have the same polarity (i.e., positive), and the second external terminals 24a, 24b and the fourth external terminals (not shown) also generally have the same polarity (i.e., negative).The capacitor 20 also generally has a thickness "T," width "W," and length "L" as described above, and the width "BW" and lengths "BLA" and "BLB" of the external terminals 22a, 22b, and / or 24a, 24b may be within the ranges discussed above. Although by no means required, cavities 1350 may also form in the capacitor 20 between the external terminals 22a, 24b, 22b, and / or 24a, as described above.

[0040] The capacitor 20 also includes internal electrode layers 210, which include first internal electrode layers 205 and second internal electrode layers 215 in an alternating arrangement. The internal electrode layers 205, 215 include at least one terminal tab 220a-b, 230a-b, 240a-b, 250a-b extending from a top edge and a bottom edge of the main body of the internal electrode layers. The terminal tabs 220a-b, 230a-b, 240a-b, 250a-b of the internal electrode layers 205, 215 extend to the top surface and bottom surface of the capacitor and assist in forming the external terminals. In this regard, the terminal tabs 220a-b, 230a-b, 240a-b, 250a-b may be exposed on the top surface and the bottom surface of the capacitor and enable connection between the main body of the internal electrode layers and the external terminals.For example, the terminal tabs 220a-b, 230a-b, 240a-b, 250a-b may include leading edges 223a-b, 233a-b, 243a-b, 253a-b that extend to an edge of a dielectric layer and enable the formation of the external terminals. The internal electrode layers 205, 215 include at least two terminal tabs 220a-b, 230a-b, 240a-b, 250a-b along an upper edge and a lower edge. A first internal electrode layer 205 includes two guide tabs 220a-b, 230a-b, each along an upper edge 205c and a lower edge 205d, extending away from the main body 235. A second internal electrode layer 215 includes two guide tabs 240a-b, 250a-b each along an upper edge and a lower edge extending away from the main body 245.

[0041] The terminal tabs 220a-b, 230a-b at the upper edge 205c and the lower edge 205d of the first internal electrode layer 205 may be aligned in a perpendicular direction. That is, a lateral edge 221a, 222a of a first terminal tab 220 along an upper edge 205c may be aligned with a lateral edge 231a, 232a of a first terminal tab 230 along a lower edge 205d opposite the upper edge 205c. Furthermore, such lateral edges 221a, 231a may also be aligned with the lateral edge 205a of the internal electrode layer 205. However, it should be understood that both lateral edges 221a, 222a of the first terminal tab 220a along an upper edge 205c may be aligned with the lateral edges 231a, 232a of a first terminal tab 230a along a lower edge 205d opposite the upper edge 205c.In other words, both lateral edges 222a, 232a may be offset from the lateral edges 205a-b by the same distance along a lower edge 205d and the upper edge 205c. If an upper edge 205c and a lower edge 205d include at least two terminal tabs 220a-b, 230a-b, at least one lateral edge of each terminal tab at an upper edge 205c may be aligned with a corresponding lateral edge of a terminal tab at the lower edge 205d. Furthermore, both lateral edges of each terminal tab at an upper edge 205c may be aligned with a corresponding lateral edge of the terminal tabs at the lower edge 205d. Likewise, the terminal tabs 240a-b, 250a-b at the upper edge and at the lower edge of the second internal electrode layer 215 may be aligned in a perpendicular direction.That is, a lateral edge 241a, 242a of a first terminal tab 240 along an upper edge may be aligned with a lateral edge 251a, 252a of a first terminal tab 250 along a lower edge opposite the upper edge.

[0042] Both lateral edges 241a, 242a of the first terminal tab 240 along an upper edge may be aligned with the lateral edges 251a, 252a of a first terminal tab 250 along a lower edge opposite the upper edge. The relationship between lateral edges of a first terminal tab at an upper edge and a first terminal tab at a lower edge, as mentioned with respect to the internal electrode layer 205, may also apply to the internal electrode layer 215. With such an arrangement, a gap may arise between any of the terminal tabs along an upper edge 205c of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, a gap may arise between any terminal tabs 220a-b, 240a-b extending from the upper edges of the respective internal electrode layers.Additionally, a gap may form between any of the terminal tabs along an upper edge 205d of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, a gap may form between any terminal tabs 230a-b, 250a-b extending from the upper edges of the respective internal electrode layers. Furthermore, the size of a gap between two respective tabs extending from an upper edge, whether from the same internal electrode layer or from adjacent internal electrode layers, may be substantially the same as the size of a gap between the corresponding two respective tabs extending from a lower edge. For example, the gap between terminal tabs 220a and 220b may be substantially the same as the gap between terminal tabs 230a and 230b.Likewise, the gap between terminal tabs 220a and 240a may be substantially the same as the gap between terminal tabs 230 and 250a.

[0043] Any or all of the terminal tabs 220a-b, 240a-b may be arranged parallel to the respective terminal tabs 230a-b, 250a-b extending from the layers 205 and 215, such that the terminal tabs extending from alternating electrode layers 205 and 215 may be aligned in a respective column. For example, the terminal tabs 220a-b and 230a-b of the internal electrode layer 205 may be arranged in a corresponding stacked configuration, while the terminal tabs 240a-b and 250a-b of the internal electrode layer 215 may be arranged in a corresponding stacked configuration. It should be noted that the terminal tabs 220a-b are connected to the respective external terminals 22a-b, while the terminal tabs 240a-b are connected to the respective external terminals 24a-b.Accordingly, the respective terminal tabs 220a-b interlock with the respective terminal tabs 240a-b in a manner similar to the external terminals 22a-b and 24a-b. The interlocking terminal tabs can provide multiple adjacent current injection points on the associated main electrode portions.

[0044] In the embodiments discussed above, the external connections are arranged linearly (e.g., 1 x 2 or 1 x 4 configuration) in a single dimension. It should, of course, be understood that multidimensional arrays of external connections can also be used. For example, if we look at the Fig. 6A-6D, a particular embodiment of a capacitor 10 is shown having a 2 x 2 array configuration. In such a configuration, the capacitor includes a total of four external terminals on the top side (first external terminal 12 and second external terminal 14) and a corresponding number of external terminals (third and fourth external terminals, not shown) on the bottom side. The first external terminals 12 and the third external terminals (not shown) generally have the same polarity (i.e., positive), and the second external terminals 14 and the fourth external terminals (not shown) also generally have the same polarity (i.e., negative). Although by no means required, a cavity 1350 may form in the capacitor 10 between the external terminals 12 and 14, as described above.

[0045] The capacitor 10 comprises alternating dielectric layers and internal electrode layers 110, which include first internal electrode layers 105 and second internal electrode layers 115, in an alternating arrangement. Similar to the arrangement shown above in the Fig. 3A-3B, the internal electrode layers 105, 115 also comprise at least one terminal tab 120, 130, 140, 150 extending from an upper edge and a lower edge of the main body of the internal electrode layers. In contrast to the internal electrodes of Fig. 3A-3B, however, a lateral edge 121, 122 of a first terminal tab 120 along an upper edge 105c may be aligned with a lateral edge 131, 132 of a first terminal tab 130 along a lower edge 105d opposite the upper edge 105c. In other words, a lateral edge 121, 122 of a first terminal tab 120 along an upper edge 105c may be offset from a lateral edge 105a-b by the same amount as a lateral edge 131, 132 of a first terminal tab 130 along a lower edge 105d opposite the upper edge 105c (indicated by "O"). However, it should be understood that both lateral edges 121, 122 of the first terminal tab 120 along an upper edge 105c may be aligned with the lateral edges 131, 132 of a first terminal tab 130 along a lower edge 105d opposite the upper edge 105c.In other words, both lateral edges 121, 122 of a first connecting tab 120 along an upper edge 105c can be offset from a lateral edge 105a-b by the same amount as the two lateral edges 131, 132 of a first connecting tab 130 along a lower edge 105d opposite the upper edge 105c.

[0046] Likewise, the terminal tabs 140, 150 at the top and bottom edges of the second internal electrode layer 115 may be aligned in a perpendicular direction. That is, a lateral edge 141, 142 of a first terminal tab 140 along an upper edge may be aligned with a lateral edge 151, 152 of a first terminal tab 150 along a lower edge opposite the top edge. In one embodiment, both lateral edges 141, 142 of the first terminal tab 140 along an upper edge may be aligned with the lateral edges 151, 152 of a first terminal tab 150 along a lower edge opposite the top edge. The relationship between lateral edges of a first terminal tab at an upper edge and a first terminal tab at a lower edge, as mentioned with respect to the internal electrode layer 105, may also apply to the internal electrode layer 115.With such an arrangement, a gap may be created between terminal tab 120 of the first internal electrode layer 105 and terminal tab 140 of the second internal electrode layer 115. A gap may be created between terminal tab 130 of the first internal electrode layer 105 and terminal tab 150 of the second internal electrode layer 115. The size of each gap may be substantially the same.

[0047] Terminal tabs 120 and 140 may be arranged parallel to terminal tabs 130 and 150, respectively, extending from internal electrode layers 105 and 115, such that terminal tabs extending from alternate electrode layers 105 and 115 may be aligned in a respective column. For example, terminal tabs 120 and 130 of internal electrode layer 105 may be arranged in a corresponding stacked configuration, while terminal tabs 140 and 150 of internal electrode layer 115 may be arranged in a corresponding stacked configuration. Note that terminal tabs 120 are connected to external terminal 12, while terminal tabs 140 are connected to external terminal 14.Accordingly, the respective terminal tabs 120 interlock with the respective terminal tabs 140 in a manner similar to the external terminals 12 and 14. The interlocking terminal tabs can provide multiple adjacent current injection points on the associated main electrode portions.

[0048] As in Fig. 6D, multiple sets 110a and 110b of internal electrode layers 110 may be used to form the Fig. 6A. Typically, the distance "t" between sets 110a and 110b is about 0.2 to about 10 µm, in some embodiments about 0.5 to about 8 µm, and in some embodiments about 1 to about 5 µm. Moreover, the distance "t" may be, but is not limited to, at least 2 times, in some embodiments at least about 3 times, and in some embodiments about 4 to about 8 times greater than the distance between adjacent terminal tabs in a given column to ensure that different terminals do not run together.

[0049] In the Fig. 7A-7D illustrate an embodiment of a capacitor 20 having a 2 x 4 array configuration. In such a configuration, the capacitor includes a total of eight external terminals on the top side (first external terminals 22a, 22b and second external terminals 24a, 24b) and a corresponding number of external terminals (third and fourth external terminals, not shown) on the bottom side. The first external terminals 22a, 22b and the third external terminals (not shown) generally have the same polarity (i.e., positive), and the second external terminals 24a, 24b and the fourth external terminals (not shown) also generally have the same polarity (i.e., negative). Although by no means required, cavities 1350 may also form in the capacitor 20 between the external terminals 22a, 22b, 24a, and / or 24b, as described above.

[0050] The capacitor 20 also includes two sets 210a and 210b of alternating internal electrode layers 210, as shown in Fig. 7D. As shown in the Fig. 7B and Fig. As shown in Figure 7C, each set of alternating dielectric layers and internal electrode layers 210 includes first internal electrode layers 205 and second internal electrode layers 215 in an alternating arrangement. The internal electrode layers 205, 215 include at least one terminal tab 220a-b, 230a-b, 240a-b, 250a-b extending from a top edge and a bottom edge of the main body of the internal electrode layers. The terminal tabs 220a-b, 230a-b, 240a-b, 250a-b of the internal electrode layers 205, 215 extend to the top surface and bottom surface of the capacitor and assist in forming the external terminals. In this regard, the terminal tabs 220a-b, 230a-b, 240a-b, 250a-b may be exposed on the top surface and the bottom surface of the capacitor and enable connection between the main body of the internal electrode layers and the external terminals.For example, the terminal tabs 220a-b, 230a-b, 240a-b, 250a-b may include leading edges 223a-b, 233a-b, 243a-b, 253a-b that extend to an edge of a dielectric layer and enable the formation of the external terminals. The internal electrode layers 205, 215 include at least two terminal tabs 220a-b, 230a-b, 240a-b, 250a-b along an upper edge and a lower edge. A first internal electrode layer 205 includes two guide tabs 220a-b, 230a-b, each along an upper edge 205c and a lower edge 205d, extending away from the main body 235. A second internal electrode layer 215 includes two guide tabs 240a-b, 250a-b each along an upper edge and a lower edge extending away from the main body 245.

[0051] The terminal tabs 220a-b, 230a-b at the upper edge 205c and the lower edge 205d of the first internal electrode layer 205 may be aligned in a perpendicular direction. That is, a lateral edge 221a, 222a of a first terminal tab 220 along an upper edge 205c may be aligned with a lateral edge 231a, 232a of a first terminal tab 230 along a lower edge 205d opposite the upper edge 205c. In other words, a lateral edge 121, 122 of a first terminal tab 220 along an upper edge 205c may be offset from a lateral edge 205a-b by the same amount as a lateral edge 231a, 232a of a first terminal tab 230 along a lower edge 205d opposite the upper edge 205c (indicated by "O").Furthermore, both lateral edges 221a, 222a of the first terminal tab 220 along an upper edge 205c can be aligned with the lateral edges 231a, 232a of a first terminal tab 230 along a lower edge 205d opposite the upper edge 205c. That is, both lateral edges can be offset the same distance from a lateral edge 205a-b. If an upper edge 205c and a lower edge 205d include at least two terminal tabs 220a-b, 230a-b, at least one lateral edge of each terminal tab at an upper edge 205c can be aligned with a corresponding lateral edge of a terminal tab at the lower edge 205d. Furthermore, both lateral edges of each terminal tab at an upper edge 205c can be aligned with a corresponding lateral edge of the terminal tabs at the lower edge 205d.

[0052] Likewise, the terminal tabs 240a-b, 250a-b can be aligned in a perpendicular direction at the top and bottom edges of the second internal electrode layer 215. That is, a lateral edge 241a, 242a of a first terminal tab 240 along an upper edge can be aligned with a lateral edge 251a, 252a of a first terminal tab 250 along a lower edge opposite the upper edge. Both lateral edges 241a, 242a of the first terminal tab 240 along an upper edge can be aligned with the lateral edges 251a, 252a of a first terminal tab 250 along a lower edge opposite the upper edge. The relationship between lateral edges of a first terminal tab at an upper edge and a first terminal tab at a lower edge, as mentioned with respect to the internal electrode layer 205, may also apply to the internal electrode layer 215.With such an arrangement, a gap may be formed between any of the terminal tabs along an upper edge 205c of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, a gap may be formed between any terminal tabs 220a-b, 240a-b extending from the upper edges of the respective internal electrode layers. Furthermore, a gap may be formed between any of the terminal tabs along an upper edge 205d of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, a gap may be formed between any terminal tabs 230a-b, 250a-b extending from the upper edges of the respective internal electrode layers.Furthermore, the size of a gap between two respective tabs extending from a top edge, whether from the same internal electrode layer or from adjacent internal electrode layers, may be substantially the same as the size of a gap between the corresponding two respective tabs extending from a bottom edge. For example, the gap between terminal tabs 220a and 220b may be substantially the same as the gap between terminal tabs 230a and 230b. Likewise, the gap between terminal tabs 220a and 240a may be substantially the same as the gap between terminal tabs 230a and 250a.

[0053] Any or all of the terminal tabs 220a-b, 240a-b may be arranged parallel to the respective terminal tabs 230a-b, 250a-b extending from the layers 205 and 215, such that the terminal tabs extending from alternating electrode layers 205 and 215 may be aligned in a respective column. For example, the terminal tabs 220a-b and 230a-b of the internal electrode layer 205 may be arranged in a corresponding stacked configuration, while the terminal tabs 240a-b and 250a-b of the internal electrode layer 215 may be arranged in a corresponding stacked configuration. It should be noted that the terminal tabs 220a-b are connected to the respective external terminals 22a-b, while the terminal tabs 240a-b are connected to the respective external terminals 24a-b.Accordingly, the respective terminal tabs 220a-b interlock with the respective terminal tabs 240a-b in a manner similar to the external terminals 22a-b and 24a-b. The interlocking terminal tabs can provide multiple adjacent current injection points on the associated main electrode portions.

[0054] As in Fig. 7D, multiple quantities 210a and 210b of internal electrode layers 110 may be used to form the Fig. 7A. Typically, the distance "t" between sets 110a and 110b is about 0.2 to about 10 µm, in some embodiments about 0.5 to about 8 µm, and in some embodiments about 1 to about 5 µm. Moreover, the distance "t" may be, but is not limited to, at least 2 times, in some embodiments at least about 3 times, and in some embodiments about 4 to about 8 times greater than the distance between adjacent terminal tabs in a given column to ensure that different terminals do not run together.

[0055] In the Fig. 8A-8B illustrates an embodiment of a capacitor 20 having a 4x4 array configuration. In such a configuration, the capacitor includes a total of sixteen external terminals on the top surface (first external terminals 32a, 32b and second external terminals 34a, 34b) and a corresponding number of external terminals (third and fourth external terminals, not shown) on the bottom surface. The first external terminals 32a, 32b and the third external terminals (not shown) generally have the same polarity (i.e., positive), and the second external terminals 34a, 34b and the fourth external terminals (not shown) also generally have the same polarity (i.e., negative). Although by no means required, cavities 1350 may also form within the capacitor 20 between the external terminals 32a, 32b, 34a, and / or 34b, as described above.The capacitor 30 also includes internal electrode layers 210 arranged in four sets 210a, 210b, 210c and 210d, as shown in . Fig. 8B. Similar to the embodiments discussed above, the distances "t1", "t2", and / or "t3" between the sets may be about 0.2 to about 10 μm, in some embodiments about 0.5 to about 8 μm, and in some embodiments about 1 to about 5 μm. Furthermore, the distances "t1", "t2", and / or "t3" may be, but are not limited to, at least 2 times, in some embodiments at least about 3 times, and in some embodiments about 4 to about 8 times the distance between adjacent terminal tabs in a given column to ensure that different terminals do not run together.

[0056] In the embodiments described above, the internal electrode layers are aligned in a substantially vertical configuration. This is, of course, by no means required, and other geometric configurations, such as a horizontal configuration, may also be used. For example, refer to the Fig. 9A-9C, a capacitor 20 is shown which is similar to that in the Fig. 8A-8B has a 4x4 configuration of external terminals 32 and 34, but employs a horizontal internal electrode configuration. That is, as shown in Fig. 9B-9C, the capacitor 20 includes a plurality of internal electrode layers 205 and 215 and a plurality of dielectric layers in an alternating arrangement, wherein the electrode layers are interleaved in an opposed and spaced-apart relationship with dielectric layers located between any two adjacent electrode layers. The internal electrode layers are electrically connected to an external terminal via conductive vias, such as a first conductive via 225 and a second conductive via 285. The conductive vias extend to a top surface 235 of the capacitor and a bottom surface 245 of the capacitor. In this regard, the conductive vias may be exposed on the top surface 235 of the capacitor and the bottom surface 245 of the capacitor.The exposure can assist in forming the external terminals on the top surface 235 and bottom surface 245 of the capacitor. Furthermore, the internal electrode layers 205 and 215 have a rectangular configuration and are designed so that they do not extend to a side surface of the capacitor.

[0057] If desired, the capacitor 20 may further include a first shield region 255 and a second shield region 265, and each of the shield regions may include one or more shield electrode layers 275. As shown, the shield regions are provided above and below the active electrode region and active electrode layers 205, 215. Fig. 9C also illustrates the use of a first armature electrode 305 and a second armature electrode 295. The first armature electrode 305 is provided in the first active electrode layer 205 with the first active electrode. In this regard, the first active electrode is electrically connected to the first conductive via 225, while the first armature electrode is connected to the second conductive via 285. Likewise, the first armature electrode 295 is provided in the first active electrode layer 215 with the first active electrode. In this regard, the second active electrode is electrically connected to the second conductive via 285, while the second armature electrode is connected to the first conductive via 225.

[0058] The first conductive via 225 extends through the first plurality of internal electrode layers 205 and establishes electrical contact. However, the first conductive via 225 extends through a contactless hole 105, forming a gap 105 between the first conductive via 225 and the electrodes of the second plurality of internal electrode layers 215. Such a gap 105 enables the second plurality of internal electrode layers 215 to be isolated from the first conductive via 225. Likewise, the second conductive via 285 extends through the second plurality of internal electrode layers 215 and establishes electrical contact.However, the second conductive via 285 extends through a contactless hole 115, forming a gap 115 between the second conductive via 285 and the electrodes of the first plurality of internal electrode layers 205. Such a gap 115 enables the first plurality of internal electrode layers 205 to be isolated from the second conductive via 285. When anchor (or dummy) electrodes are present, as shown in FIG. Fig. As shown, such layers also include gaps 125 and 135. The first conductive via 225 extends through the first plurality of internal electrode layers 205 and contacts second anchor tabs 295. However, the second anchor tab 295 is isolated from the active electrodes of the second plurality of internal electrode layers 215 by a gap 125 formed between the anchor tab 295 and the active electrode 215. Such a gap 125 enables the second plurality of internal electrode layers 215 to be isolated from the second anchor tab 295 and the first conductive via 225.

[0059] The dielectric layers of the ceramic capacitor described herein are typically made of a ceramic material. The ceramic material may have a relatively high dielectric constant. For example, the dielectric constant may be 3 or more, in some embodiments from about 10 to about 20,000, in some embodiments from about 50 to about 10,000, in some embodiments from about 60 to about 9,000, and in some embodiments from about 80 to about 8,000. Particularly suitable examples of ceramic materials with a high dielectric constant are those referred to as NPO (COG) (up to about 100), X7R (from about 3,000 to about 7,000), X7S, Z5U, and / or Y5V based on the standard classifications established by the Electronic Industries Alliance (EIA). Such materials may include a perovskite, such as barium titanate ceramic materials (e.g.,Barium titanate, barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate ceramic materials (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), sodium bismuth titanate, etc. In a particular embodiment, for example, barium strontium titanate ("BSTO") of the formula Ba. x Sr 1-x TiO3, where x = 0 to 1, in some embodiments about 0.15 to about 0.65, and in some embodiments about 0.25 to about 0.6. Other suitable barium titanate ceramic materials include Ba x Ca 1-x TiO3, where x is about 0.2 to about 0.8, and in some embodiments is about 0.4 to about 0.6; barium calcium zirconium titanate (BaCaZrTiO3); A[B1 1 / 3 B2 2 / 3 ]O3 materials, where A = Ba x Sr 1-x is (x can have a value from 0 to 1); B1 = Mg y Zn 1-y(y can have a value from 0 to 1) and B2 = Ta z Nb 1-z (z can have a value from 0 to 1); and so on. Other suitable ceramic materials are, for example, Pb x Zr 1-x TiO3 ("PZT"), where x ranges from about 0.05 to about 0.4; lead lanthanum zirconium titanate ("PLZT"); lead titanate (PbTiO3); and so on.

[0060] The internal electrode layers may be made of any one of a variety of different metals known in the art. The internal electrode layers may be made of a metal, such as a conductive metal. The materials may include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, as well as the respective sputtered layers of chromium, nickel, and gold, may also be suitable. In a particular embodiment, the internal electrode layers may comprise nickel or an alloy thereof. Likewise, the external terminals may be made of any one of a variety of different metals known in the art. The external terminals may be made of a metal, such as a conductive metal. The materials may include noble metals (e.g., silver, gold, palladium, platinum, etc.).), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. In a particular embodiment, the external terminals may comprise copper or an alloy thereof. The external terminals may have an average thickness of about 100 µm or less, in some embodiments, about 1 µm to about 70 µm, and in some embodiments, about 5 µm to about 50 µm.

[0061] The external terminals may be formed using any method well known in the art. The external terminals may be formed using methods such as sputtering, painting, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, propellant spraying, etc. The external terminals may be formed such that the external terminal is a thin-film metallization. Such a thin-film metallization may be formed by depositing a conductive material, such as a conductive metal, on an exposed portion of an internal electrode layer. For example, a leading edge of an internal electrode layer may be exposed to allow the formation of a metallized terminal. A metallized terminal may be formed by methods well known in the art, such as electroless plating, electroplating, or combinations thereof.When multiple layers are used to form an external terminal, the external terminal may comprise a plating layer and an electroless plating layer. For example, electroless plating may be used first to deposit an initial material layer. Then, the metallization technique may be switched to an electroplating system, which may allow for faster material buildup. When forming the metallized terminals using either metallization method, a leading edge of the terminal tabs of the internal electrode layers, which is exposed from the main body of the capacitor, is exposed to a metallization solution. This exposure allows, in one embodiment, the capacitor to be immersed in the metallization solution.

[0062] The metallization solution used in a metallization process may comprise a conductive material, such as a conductive metal. The metallization solution may be a nickel sulfamate bath solution or another nickel solution; alternatively, the metallization solution may also be a copper acid bath or another suitable copper solution. Furthermore, it should be understood that the metallization solution may also contain other additives well known in the art. For example, the additives may include other organic additives and media that can assist the metallization process. Furthermore, additives may be used to maintain the metallization solution at a desired pH.In one embodiment, resistance-reducing additives may be used in the solutions to assist in the complete metallization coverage and bonding of the metallization materials to the capacitor and the exposed leading edges of the terminal tabs of the internal electrode layers. The capacitor may be exposed to, submerged in, or immersed in the metallization solution for a predetermined period of time. This exposure time is not necessarily limited, but it may be sufficient to allow enough metallization material to deposit to form the metallized terminal.In this regard, the time should be sufficient to allow the formation of a continuous connection between the desired exposed adjacent leading edges of terminal tabs of a given polarity of the respective internal electrode layers within a set of alternating dielectric layers and internal electrode layers.

[0063] The difference between electroplating and electroless plating is that electroplating involves an electrical bias, such as using an external power source. The electroplating solution can typically be exposed to a high current density range, for example, 10 to 15 amps / ft 2(rated at 9.4 volts). A connection can be formed with a negative connection to the capacitor, which requires the formation of the metallized terminals, and a positive connection to a solid material (e.g., Cu in Cu metallizing solution) in the same metallizing solution. This means that the capacitor is biased to a polarity opposite to that of the metallizing solution. With such a process, the conductive material of the metallizing solution is attracted to the metal of the exposed leading edge of the terminal tabs of the internal electrode layers.

[0064] Before the capacitor is immersed in or exposed to a metallization solution, various pretreatment steps may be employed. Such steps may be performed for a variety of purposes, including to catalyze, accelerate, and / or improve the adhesion of the metallization materials to the leading edge of the terminal tabs. Additionally, a preliminary cleaning step may be employed prior to metallization or any other pretreatment steps. This step may be used to remove any accumulated oxide that may form on the exposed terminal tabs of the internal electrode layers. This cleaning step may be particularly useful in assisting in the removal of any nickel oxide buildup when the internal electrodes or other conductive elements are made of nickel.Cleaning of the components can be achieved by full immersion in a pre-cleaning bath, such as one containing an acid cleaner. In one embodiment, the exposure can be for a predetermined time, such as on the order of about 10 minutes. Alternatively, cleaning can also be achieved through chemical polishing or harperization steps.

[0065] Additionally, a step may also be performed to activate the exposed metallic leading edges of the terminal tabs of the internal electrode layers to facilitate the deposition of the conductive materials. Activation may be achieved by immersion in palladium salts, photopatterned palladium-organic precursors (via mask or laser), screen-printed or inkjet-deposited palladium compounds, or electrophoretic palladium deposition. It should be understood that palladium-based activation is disclosed herein merely as an example of activation solutions that often work well with activation of exposed tab portions made of nickel or an alloy thereof. However, it should be understood that other activation solutions may also be used and are therefore not necessarily limited.Furthermore, instead of or in addition to the above-mentioned activation step, the activation dopant can also be introduced into the conductive material when forming the internal electrode layers of the capacitor. For example, if the internal electrode layer comprises nickel and the activation dopant comprises palladium, the palladium dopant can be introduced into the nickel ink or composition forming the internal electrode layers. This can eliminate the palladium activation step. It should also be noted that some of the above activation methods, such as organometallic precursors, are also suitable for the co-deposition of glass formers for enhanced adhesion to the generally ceramic body of the capacitor.When activation steps are undertaken, as described above, traces of the activator material may often remain on the exposed conductive parts before and after the terminals are metallized. Furthermore, post-metallization treatment steps may also be employed if desired or necessary. Such steps may be performed for a variety of purposes, including strengthening and / or improving the adhesion of the materials. For example, a heating (or annealing) step may be employed after the metallization step. This heating can be accomplished by baking, laser irradiation, UV exposure, microwave exposure, arc welding, etc.

[0066] Thus, as described above, the external terminals employed in the capacitor may include at least one metallized layer. In one embodiment, the external terminals may include only a single metallization layer. However, it should be understood that the external terminals may also include a plurality of metallization layers. For example, the external terminals may include a first metallization layer and a second metallization layer. In addition, the external terminals may also include a third metallization layer. Furthermore, the materials for these metallization layers may be any of those mentioned above and those generally known in the art. For example, a metallization layer, such as a first metallization layer, may include copper or an alloy thereof.Another metallization layer, such as a second metallization layer, may contain nickel or an alloy thereof. Alternatively, another metallization layer, such as the second metallization layer, may contain copper or an alloy thereof. Another metallization layer, such as a third metallization layer, may comprise tin, lead, gold, or a combination thereof, such as an alloy. Alternatively, an initial metallization layer may also comprise nickel, followed by metallization layers of tin or gold. In another embodiment, an initial metallization layer of copper followed by a nickel layer may be formed.

[0067] In one embodiment, the initial or first metallization layer may consist of a conductive metal (e.g., copper). This region may be covered with a second layer containing a polymeric resistive material for sealing. The region may then be polished to selectively remove polymeric resistive material and then re-metallized with a third layer containing a conductive metallic material (e.g., copper). The above-mentioned second layer over the initial metallization layer may correspond to a solder barrier layer, for example, a nickel solder barrier layer. In some embodiments, the above-mentioned layer may be formed by electroplating an additional layer of metal (e.g., nickel or copper) over an electrolessly deposited or electroplated initial layer (e.g., deposited copper).Other exemplary materials for the above-mentioned solder barrier layer include nickel-phosphorus, gold, and silver. A third layer on the above-mentioned solder barrier layer may, in some embodiments, correspond to a conductive layer, such as deposited Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or another suitable deposited solder metal. Furthermore, a metallization layer may be formed, followed by an electroplating step to obtain a resistive alloy or a coating with a higher resistivity metal alloy, for example, an electroless Ni-P alloy, over such metallization. However, it should be understood that it is possible to use any metal coating, as will be understood by those skilled in the art from the full disclosure herein.It should be noted that each of the above steps can be performed as a volume process, such as drum metallization, fluidized bed metallization, and / or flow metallization termination methods, all of which are well known in the art. Such volume processes allow multiple components to be processed at once, resulting in an efficient and rapid termination process. This is a particular advantage over conventional termination methods, such as thick-film termination printing, which require individual processing of components. IV. Semiconductor package assembly

[0068] As is known in the art, the semiconductor package assembly can be electrically connected to and / or mounted on a circuit board (e.g., printed circuit board) to form a microelectronic assembly. Within the package assembly itself, the semiconductor structure, the package substrate, and the ceramic capacitor can generally be arranged in a variety of different configurations for connection to the circuit board. For example, when we refer to Fig. 1, an embodiment of a semiconductor package assembly 600 is illustrated including semiconductor structures 610, 620, and 630 electrically connected to an interposer 650, and a package substrate 680 electrically connected to the interposer 650. The semiconductor structures may be any type of structure as described above. In one embodiment, the structures 610 and 630 may be, for example, a high-bandwidth memory structure or a field-programmable gate array. The semiconductor structures 610, 620, and 630 may be electrically connected to the interposer 650 via first-level coupling components 611, 621, and 631, respectively, as shown. In the illustrated embodiment, the coupling components 621 may be solder balls or solder bumps, while the coupling components 611 and 631 may be a conductive adhesive or an underfill material.Although by no means required, an overmolding material 760 may also be employed. The overmolding material may be an insulating material as described above (e.g., epoxy resin material). The interposer 650 also includes conductive traces 652 formed within an insulating dielectric material 654. The conductive traces 652 enable electrical connection of the interposer 650 to the package substrate 680 via second-level coupling components 656 (e.g., solder balls or bumps). The package substrate 680, in turn, includes conductive traces 682 (e.g., vias) within an insulating dielectric material 684. The conductive traces 682 enable electrical connection of the package assembly 800 (via the package substrate 680) to a circuit board 800 (e.g., printed circuit board) via third-level coupling components 704 (e.g., solder balls).

[0069] Remarkably, a ceramic capacitor 10 (see e.g. the Fig. 3A-3B) is also electrically connected to at least one of the semiconductor structures 610, 62, and / or 630 and the package substrate 680. In particular, in the illustrated embodiment, the ceramic capacitor 10 is positioned between at least a portion of the package interposer 650 and the package substrate 680. Of course, the ceramic capacitor 10 may also be positioned at various other locations within the package, for example, between the semiconductor structures 610, 620, and / or 630 and the interposer 650. Although only a single capacitor is shown, it is of course understood that multiple ceramic capacitors may be employed. The external terminals of the ceramic capacitor(s) may be in appropriate electrical communication with current paths of the interposer and the package substrate and may be electrically connected thereto using any method well known in the art.For example, instead of solder balls 656, the ceramic capacitor 10 can either be directly electrically connected to the package substrate 680 and the interposer 650, or at least coupling components 702 (e.g., solder bumps) that are smaller than the coupling components 656 can be used. The capacitor 10 can allow the passage or transmission of an AC signal while generally blocking a DC signal. That is, it can be used to block low-frequency signals and pass high-frequency signals. Furthermore, by disposing the capacitor 10 in the manner shown, certain conductive traces directly over the capacitor can be eliminated, further improving performance. By using a ceramic capacitor in this manner, the inductance can also be significantly reduced.In particular, minimizing the distance or path for a ground connection can help reduce inductance. For example, using the ceramic capacitor can result in an inductance of about 1 nanohenry or less, in some embodiments from about 25 femtohenry to about 900 picohenry, in some embodiments from about 100 femtohenry to about 500 picohenry, and in some embodiments from about 250 femtohenry to about 100 picohenry. The ceramic capacitor can also have a low equivalent series resistance, such as about 100 mOhm or less, in some embodiments from about 0.01 mOhm to about 50 mOhm, in some embodiments from about 0.1 mOhm to about 40 mOhm, and in some embodiments from about 0.5 mOhm to about 30 mOhm.The low inductance and / or equivalent series resistance may be achieved while still having a tailored capacitance value, such as from about 1 pF to about 1000 µF, in some embodiments from about 500 pF to about 500 µF, and in some embodiments from about 1 µF to about 100 µF.

[0070] In the Fig. In the embodiment shown in Figure 1, the interposer 650 is generally considered a "passive" interposer because it does not contain any integrated electronic components. However, it should be understood that "active" interposers may also be suitably employed in the semiconductor package assembly of the present invention. For example, if we refer to Fig. 2, an embodiment of a semiconductor package assembly 800 is shown which includes an active interposer 802, which is also shown in Fig. 3. In this embodiment, the interposer 802 is electrically connected to a package substrate 832, and a semiconductor structure 310 (e.g., coprocessor) is electrically connected to the interposer 802. The semiconductor structure 310 may include an active layer 392 and a bulk semiconductor layer 390 (sometimes referred to herein as an inactive layer 390). The active layer 392 may include circuit elements and a register file 394, which may function as central on-die storage for the structure 310. The active interposer 802 may also include an active layer 806 and a bulk semiconductor layer 804 (sometimes referred to as an inactive layer 804). The active layer 806 may include a plurality of level one (L1) memory elements 808 formed on the active side that may be used as memory caches for storing configuration bit streams for configuring logic sectors in the structure 310.The active interposer 802 may be electrically connected to a package substrate 832 via coupling components 822 (e.g., solder bumps or balls), and the inactive layer 804 may include silicon vias (TSVs) 810 that may connect components such as L1 storage elements 808 in the active layer 806 to the coupling components 822. The active layer 806 may face the active layer 392 of the semiconductor structure 310 and may be electrically connected to components in the active layer 392 via coupling components 820 (e.g., solder bumps).

[0071] If desired, an additional semiconductor structure 812 (e.g., an auxiliary chip) may be directly electrically connected to the substrate 832. The structure 812 may include an active layer 816 and a bulk semiconductor layer 814 (sometimes referred to herein as an inactive layer 814). The active layer 816 may include a plurality of level two (L2) memory elements 809 formed on the active side, which may be used as memory caches for storing configuration bitstreams. For example, configuration bitstreams stored in L1 memory elements 808 on the interposer 802 may be transferred to L2 memory elements 809 to make room on L1 memory elements 808 for new incoming configuration bitstreams (received, for example, from a host processor at L1 memory elements 808). The active layer 816 may face the package substrate 832 and may be coupled to the package substrate 832 via coupling components 822 and 824 (e.g.,Solder balls or bumps) may be electrically connected thereto. A bridge 826 may also be used to connect the semiconductor structure 812 to the interposer 802. The bridge 826 may include interconnects 828 formed in a silicon substrate embedded in the package substrate 832. The interconnects 828 may electrically connect the portion of the coupling components 824 connected to the semiconductor structure 812 to the portion of the coupling components 824 connected to the interposer 802. A heat sink 830 may also be brought into contact with the semiconductor structures 310 and 812, as known in the art.

[0072] As shown, a ceramic capacitor 20 (see e.g. the Fig.5A-5B) may also be electrically connected to the semiconductor structure 310 and the package substrate 832 via the interposer 802. In particular, in the illustrated embodiment, the ceramic capacitor 20 is positioned between at least a portion of the interposer 802 and the package substrate 832. The vias 810 may electrically connect the ceramic capacitor 20 to the semiconductor structure 310 via coupling components 820. The ceramic capacitor 20 may also be electrically connected to L1 storage elements 808 in the active layer 806. The external terminals of the ceramic capacitor(s) may be in corresponding electrical communication with current paths of the interposer and the package substrate and may be electrically connected thereto using any method well known in the art.For example, instead of solder balls 824 or 822, the ceramic capacitor 20 may either be directly electrically connected to the package substrate 832 and the interposer 802, or at least coupling components 722 (e.g., solder balls) that are smaller than the coupling components 824 or 822 may be used.

[0073] These and other modifications and variations of the present invention may be practiced by those skilled in the art without departing from the spirit and scope of the present invention. Furthermore, it should be understood that aspects of the various embodiments may be substituted for one another, in whole or in part. Furthermore, those skilled in the art will appreciate that the above description is merely exemplary and is not intended to limit the invention, which is particularly described in the appended claims. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 420,761

[0001]

Claims

[1] Semiconductor package assembly comprising: a semiconductor structure; a package substrate electrically connected to the semiconductor structure; and a ceramic capacitor having a first surface and an opposite second surface, the ceramic capacitor including alternating dielectric layers and internal electrode layers, the internal electrode layers comprising first internal electrode layers and second internal electrode layers, the capacitor further comprising a first external terminal electrically connected to the first internal electrode layers and disposed on a first surface of the capacitor, a second external terminal electrically connected to the first internal electrode layers and disposed on the second surface of the capacitor, a third external terminal electrically connected to the second internal electrode layers and disposed on the first surface of the capacitor, and a fourth external terminal,which is electrically connected to the second internal electrode layers and arranged on the second surface of the capacitor, wherein the first external terminal and the third external terminal are electrically connected to the semiconductor structure and the second external terminal and the fourth external terminal are electrically connected to the package substrate., [2] The semiconductor package assembly of claim 1, wherein the semiconductor structure is an integrated circuit. [3] The semiconductor package assembly of claim 2, wherein the integrated circuit comprises a memory device, logic device, processor device, or a combination thereof. [4] A semiconductor package assembly according to claim 1, wherein the assembly includes a plurality of semiconductor structures. [5] A semiconductor package assembly according to claim 4, wherein the semiconductor structures are arranged in an array. [6] The semiconductor package assembly of claim 4, wherein the semiconductor structures are stacked. [7] The semiconductor package assembly of claim 1, wherein the package substrate comprises an insulating material through which one or more conductive traces are formed, the conductive traces being in electrical communication with the second and fourth external terminals of the ceramic capacitor. [8] The semiconductor package assembly of claim 7, wherein the insulating material comprises an organic material, an inorganic material, a semiconductor material, or a combination thereof. [9] The semiconductor package assembly of claim 1, further comprising an interposer electrically connected to the semiconductor structure and the package substrate, wherein the first external terminal and the third external terminal are electrically connected to the interposer. [10] The semiconductor package assembly of claim 9, wherein the interposer comprises an insulating material through which one or more conductive traces are formed, the conductive traces being in electrical communication with the first and third external terminals of the ceramic capacitor. [11] The semiconductor package assembly of claim 9, wherein the insulating material comprises an organic material, an inorganic material, a semiconductor material, or a combination thereof. [12] The semiconductor package assembly of claim 9, wherein an electronic component is embedded in the interposer. [13] The semiconductor package assembly of claim 12, wherein the electronic component comprises a capacitor, a resistor, an inductor, a fuse, a diode, a transformer, a sensor, an electrostatic discharger, a storage device, a radio frequency device, a power amplifier, a power management device, an antenna, a microelectromechanical system, or a combination thereof. [14] The semiconductor package assembly of claim 12, wherein the ceramic capacitor is embedded in the interposer. [15] The semiconductor package assembly of claim 1, wherein the first and second external terminals have a positive polarity and the third and fourth external terminals have a negative polarity. [16] The semiconductor package assembly according to claim 1, wherein at least one of the first, second, third, or fourth external terminal extends to an end face of the capacitor. [17] The semiconductor package assembly according to claim 1, wherein the first, second, third and fourth external terminals do not extend to an end face of the capacitor. [18] The semiconductor package assembly according to claim 1, wherein the ceramic capacitor includes only the first external terminal and the third external terminal on the first surface and only the second external terminal and the fourth external terminal on the second surface. [19] The semiconductor package assembly of claim 1, wherein the capacitor includes at least four external terminals on the first surface and at least four external terminals on the second surface. [20] The semiconductor package assembly of claim 19, wherein the external terminals are linearly arranged on the first surface and on the second surface. [21] The semiconductor package assembly of claim 19, wherein the external terminals are arranged on the first surface and on the second surface in a multi-dimensional array. [22] The semiconductor package assembly according to claim 1, wherein the first and second internal electrode layers are arranged vertically. [23] The semiconductor package assembly of claim 22, wherein the first internal electrode layers include terminal tabs extending to the first surface to contact the first external terminal and terminal tabs extending to the second surface to contact the third external terminal, and further wherein the second internal electrode layers include terminal tabs extending to the first surface to contact the second external terminal and terminal tabs extending to the second surface to contact the third external terminal. [24] The semiconductor package assembly according to claim 1, wherein the first and second internal electrode layers are arranged horizontally. [25] The semiconductor package assembly of claim 24, wherein the first and second internal electrode layers are connected to the first, second, third and fourth external terminals via conductive vias. [26] The semiconductor package assembly of claim 1, wherein the dielectric layers of the ceramic capacitor comprise a ceramic material. [27] The semiconductor package assembly of claim 26, wherein the ceramic material is a barium titanate ceramic material. [28] The semiconductor package assembly of claim 1, wherein the first, second, third and fourth external terminals include at least one metallized layer. [29] The semiconductor package assembly of claim 28, wherein the metallized layer is formed by a process comprising electroless deposition, electroplating, or a combination thereof. [30] The semiconductor package assembly of claim 1, wherein the circuit board is electrically connected to the package substrate via coupling components. [31] The semiconductor package assembly of claim 30, wherein the coupling components comprise solder. [32] The semiconductor package assembly according to claim 1, wherein the second and fourth external terminals of the ceramic capacitor are electrically connected to the package substrate via coupling components. [33] A microelectronic assembly comprising the semiconductor package assembly of claim 1 and a circuit board, wherein the package substrate is electrically connected to the circuit board.

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