PHASE CONTROL CIRCUIT

Abstract

A phase-locked system includes a phase detector to detect the phase difference between a reference signal and the output of a controllable oscillator circuit. A loop filter can filter the output signal of the loop filter, and an integrator can integrate the output signal of the loop filter. The output of the integrator can be added to the output of the loop filter and fed into the controllable oscillator circuit, modifying at least one of the two parameters of the controlled oscillator's output: phase and frequency. A loop filter can provide a roll-off of 40 dB per decade and improve the attenuation of both reference signal noise and local oscillator noise.

Description

PRIORITY

[0001] This application claims priority over U.S. patent application No. 63 / 436,931, jointly owned, dated January 4, 2023, the entire contents of which are hereby incorporated by reference for all purposes. AREA OF INVENTION

[0002] The present disclosure relates to phase control circuits, including but not limited to phase control loops (PLLs). BACKGROUND

[0003] In electronic systems, a phase-locked circuit can be used to generate a clock source. The phase-locked circuit can be a phase-locked loop (PLL). The PLL can include a phase detector, a loop filter, and a controllable oscillator circuit. The PLL can receive an input from a reference signal and generate an output at the output of the controllable oscillator circuit.

[0004] A PLL can be designed to attenuate the noise from multiple noise sources. High-frequency noise can be referred to as jitter, and low-frequency noise can be referred to as wandering. In one of several examples, a PLL can be designed to attenuate the noise in the reference signal, which can also be referred to as reference jitter. The loop filter can be designed as a low-pass filter with a low cutoff frequency to eliminate high-frequency noise in the reference signal. In another example, a PLL can be designed to attenuate noise in the local oscillator circuit. The loop filter can be designed as a high-pass filter to filter noise in the oscillator output.

[0005] A PLL can use a high-order loop filter to attenuate noise more effectively than a first-order loop filter. The system design must set the loop filter's cutoff frequency to target a specific noise source—a low-pass filter to attenuate reference jitter, or a high-pass filter to attenuate local oscillator noise, using the same cutoff frequency.

[0006] There is a need for a PLL that can significantly reduce both reference and oscillator noise. SUMMARY

[0007] The examples presented here enable a phase-controlled circuit that allows high-order attenuation of both the reference signal noise and the oscillator noise.

[0008] According to one aspect, a controllable oscillator circuit generates an oscillation signal. A phase detector circuit generates a phase difference output based on a first input and a second input, the first input being coupled to a reference signal and the second input being coupled to the oscillation signal generated by the controllable oscillator circuit. A frequency-selective slope-delay loop filter filters the phase difference output to produce a filtered phase difference output. A multiplier applies a gain setting to the filtered phase difference output. An integrator integrates the output of the multiplier, and an adder sums the filtered phase difference output and the output of the integrator, with the controllable oscillator circuit modifying at least either a phase or a frequency of the oscillation signal based on the output of the adder.

[0009] According to one aspect, a system includes a first controllable oscillator circuit for generating a phase-locked output. A first phase detector circuit generates a first phase difference output based on a first input and a second input, the first input being coupled to a reference signal and the second input being connected to the output of the first controllable oscillator circuit. A first loop filter with a frequency-selective fall-off edge filters the first phase difference output to generate a first filtered phase difference output. The first controllable oscillator circuit modifies at least one phase or frequency of a first oscillator signal based on the sum of the first filtered phase difference output and a second filtered phase difference output. A second controllable oscillator circuit generates an oscillation signal at an output of the second controllable oscillator circuit.A second phase detector circuit generates a second phase difference output based on a first input and a second input, wherein the first input receives a second oscillator signal and the second input is coupled to the output of the second controllable oscillator circuit. A second loop filter with a frequency-selective slope filters the second phase difference output to generate the second filtered phase difference output, wherein the second controllable oscillator circuit modifies at least one phase or frequency of the first oscillator signal based on the second filtered phase difference output.

[0010] According to one aspect, the examples herein enable a procedure that includes the following operations: receiving an input from a reference signal, a first oscillator signal, and a second oscillator signal; detecting a first phase difference between the reference signal and an oscillation signal of a first controllable oscillator circuit to generate a first phase difference; detecting a second phase difference between the second oscillator signal and an output oscillator signal of a second controllable oscillator circuit to generate a second phase difference; filtering the first phase difference with a first frequency-selective filter; filtering the second phase difference with a second frequency-selective filter; driving the first controllable oscillator circuit with the first oscillator signal and an output of an adder.wherein the adder adds the outputs of the first frequency-selective filter and the second frequency-selective filter, and the output of the adder modifies at least either a phase or a frequency of the output oscillator signal of the first controllable oscillator circuit, driving the second controllable oscillator circuit with the first oscillator signal and the output of the second frequency-selective filter, wherein the output signal of the second frequency-selective filter modifies at least either a phase or a frequency of the output oscillator signal of the second controllable oscillator circuit, and outputting the output oscillator signal of the first controllable oscillator circuit as a phase-locked output. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The figures illustrate examples of phase-controlled circuits. Fig. Figure 1 illustrates one of several examples of a phase control circuit. Fig. Figure 2 illustrates one of several examples of the frequency response of a phase-controlled circuit. Fig. Figure 3 illustrates one of several examples of a loop filter. Fig. Figure 4 illustrates one of several examples of the frequency response of a phase-controlled circuit. Fig. Figure 5 illustrates an enlarged view of the frequency response of Fig. 4. Fig. Figure 6 illustrates another of several examples of a loop filter. Fig. Figure 7 illustrates one of the various examples of a frequency response of a phase-controlled circuit. Fig. Figure 8 illustrates an enlarged view of the frequency response of Fig. 7. Fig. Figure 9 illustrates one of the various examples of a dual-phase control system. Fig. Figure 10 illustrates one of several examples of the frequency response of a dual-phase controlled system. Fig. Figure 11 illustrates an enlarged view of the frequency response of Fig. 10. Fig. Figure 12 illustrates a method for generating an oscillation signal. DETAILED DESCRIPTION

[0012] Fig. Figure 1 illustrates one of several examples of a phase-lock circuit 100. The phase-lock circuit 100 receives a reference signal 110. The reference signal 110 can be a periodic clock signal provided by a crystal oscillator or another signal source. The reference signal 110 can contain high-frequency noise. This noise can also be referred to as jitter. The phase detector circuit 120 can detect a phase difference between the reference signal 110 and the output of the controllable oscillator 190 of the controllable oscillator circuit 130 and generate a phase difference output based on the phase difference between the reference signal 110 and the output of the controllable oscillator 190 of the controllable oscillator circuit 130. The output of the controllable oscillator 190 can be an oscillation signal. The local oscillator 135 can provide an input for the controllable oscillator circuit 130.

[0013] The loop filter 140 can receive the phase difference output of the phase detector circuit 120 and filter the phase difference output of the phase detector circuit 120 to generate a filtered phase difference output as the loop filter output. The loop filter 140 can be a finite impulse response (FIR) or infinite impulse response (IIR) filter. The loop filter 140 can be a frequency-selective filter. The filter order and coefficients of the loop filter 140 can set a specific frequency-selective slope and determine the bandwidth of the phase-lock circuit 100. The gain setting 155 can be applied to the output of the loop filter 140. The integrator 150 can integrate the output of the gain setting 155 and generate an integrated signal. The integrator 150 can apply a low-pass filter response to the output of the loop filter 140.The output of the integrator 150 can be a first input of the adder 160, with the output of the integrator 150 being used as the second input of the adder 160. The output of the adder 160 can provide an input for the controllable oscillator circuit 130. The controllable oscillator circuit 130 can generate the output of the controllable oscillator 190, and the controllable oscillator circuit 130 can modify at least the phase or the frequency of the output of the controllable oscillator 190 based on the output of the adder 160.

[0014] The controllable oscillator circuit 130 can be implemented as a chain of low-current inverters, as a chain of CMOS inverters with switched shunt capacitors, as selectable multiplexers, or as another architecture not explicitly mentioned. The output of the controllable oscillator 190 can be a signal that is phase-locked to the reference signal 110 by the phase-lock circuit 100.

[0015] In one of the various examples, the loop response of the phase-lock circuit 100 can be a low-pass response. Based on the design of the phase-lock circuit 100, a low-pass response can attenuate high-frequency noise from the reference signal 110. Based on the design of the phase-lock circuit 100, a high-pass response can attenuate the low-frequency noise of the local oscillator 135, which provides the clock signal for the entire circuit.

[0016] Fig. Figure 2 illustrates one of several examples of the frequency response 200 of a first-order phase-locked circuit 100 according to the one in Fig. 1 illustrated example.

[0017] Curve 210 illustrates the frequency response of the noise from the local oscillator 135 to the controllable oscillator circuit 130, measured at the output of the controllable oscillator 190. The phase-locked circuit 100 can apply a high-pass response and attenuate the low-frequency noise of the local oscillator 135.

[0018] Curve 220 illustrates a frequency response of the noise from the reference signal 110, measured at the output of the controllable oscillator 190. The phase-lock circuit 100 can apply a low-pass response to the reference signal 110 and attenuate high-frequency noise.

[0019] The in Fig. The illustrated frequency response represents the response of a first-order loop filter. The frequency response rolls off at 20 dB per decade, as shown at points 221 and 222 in Figure 2. Fig. 2. Point 221 illustrates the response of curve 220 at a frequency of 1 Hz (10°), and point 222 illustrates the response of curve 220 at a frequency one decade higher, at 10 Hz (10 1 ). The response is approximately -19dB at point 221 and approximately -39dB at point 222, illustrating the 20dB per decade roll-off of a first-order loop filter.

[0020] The frequency responses illustrated in curves 210 and 220 are for illustrative purposes only and are not intended as a limitation. A different design of the loop filter 140 or a different value of the gain setting 155 may result in responses with corner frequencies at positions other than those shown. Fig. 2 illustrated corner frequencies lead to.

[0021] Fig. Figure 3 illustrates one of several examples of a Loop Filter 300. The Loop Filter 300 can represent one of several examples of the Loop Filter 140, as shown in Fig. Figure 1 illustrates this. The input signal 305 can be supplied to the loop filter 140. The input signal 305 can be coupled to a variety of amplification circuits. In the [reference to diagram] Fig. In the 3 illustrated example, the input signal 305 can be coupled with three amplification circuits, but this should not be understood as a limitation.

[0022] In the Fig. In the illustrated example 3, the first amplification circuit 310 can have a gain setting of C. p Apply. The output of the first amplification circuit 310 can be input into the first adder 370. The second amplification circuit 320 can be used to set a gain of C. p2The output of the second amplification circuit 320 can be fed into the first input of the second adder 360. The third amplification circuit 330 can be used to set a gain of C. p *C p2 Apply. The output of the third amplifier circuit 330 can be fed into the first input of the third adder 340. The value of C p2 can define a second pole in the response of the loop filter 300 and can define a frequency at which the loop filter 300 rolls off at a rate of 40dB / decade.

[0023] The output of the third amplifier circuit 330 can be fed into the first input of the third adder 340. The second input of the third adder 340 can be coupled to the output of the delay circuit 350. The output of the third adder 340 can be coupled to the input of the delay circuit 350 and to a second input of the second adder 360. The feedback path from the output of the third adder 340 to the delay circuit 350 to the second input of the third adder 340 can implement an integration function.

[0024] The output of the second amplification circuit 320 can be coupled to a second input of the second adder 360.

[0025] The output of the first amplification circuit 310 can be coupled to a first input of the first adder 370. The output of the second adder 360 can be coupled to a second input of the first adder 370. The output of the first adder 370 can be the loop filter output 390.

[0026] Fig. Figure 4 illustrates one of several examples of a frequency response of 400. A frequency response of 400 can be the response of one of several examples of the phase-locked circuit 100, as referenced in Fig. 1 described, include phase control circuit 100 including loop filter 300, as described with reference to Fig. 3 described.

[0027] Curves 410, 411, 412, and 413 illustrate the frequency response of the noise of the controllable oscillator circuit 130, measured at the output of the controllable oscillator 190, for different implementations of the loop filter 300. Curves 410, 411, 412, and 413 illustrate the frequency response for a loop filter 300 with different values ​​of the coefficients C. p and C p2 The loop filter 300 can apply a high-pass response to noise from the local oscillator 135 and attenuate low-frequency noise from the local oscillator 135. Curves 420, 421, 422, and 423 illustrate a frequency response of the noise from the reference signal 110, measured at the output of the controllable oscillator 190, for different implementations of the loop filter 300. Curves 420, 421, 422, and 423 can illustrate a frequency response for a loop filter 300 with different values ​​of the coefficients C. p and C p2To illustrate, loop filter 300 can apply a low-pass response to noise from reference signal 110 and attenuate high-frequency noise from reference signal 110.

[0028] The loop filter 300 can apply attenuation with a slope of 40 dB per decade to the noise of the local oscillator 135, as described in points 417 and 418 in Fig. 4 is given. Point 417 illustrates the response of curve 410 at a frequency of 5*10 -1 Hz, and point 418 illustrates the response of curve 410 at a frequency one decade lower, at 5*10 -2 Hz. The response is approximately -13 dB at point 417 and approximately -53 dB at point 418, illustrating the 40 dB per decade roll-off of loop filter 300. A similar roll-off can be observed for curves 420, 421, 422, and 423.

[0029] Fig. Figure 5 illustrates an enlarged view of the frequency response. Note that the vertical axis in Fig. 5 ranges from -0.5 dB to 1 dB, while the vertical axis in Fig. 4 ranges from -70 dB to 0 dB. Curves 520, 521, 522, and 523 illustrate different levels of overshoot in the frequency response for noise from controllable oscillator circuits 130 for different implementations of the loop filter 300. Curves 510 and 511 illustrate different levels of fall-off in the frequency response for noise from reference signal 110 for different implementations of the loop filter 300. Different values ​​for the gain settings in the first gain circuit 310, the second gain circuit 320, and the third gain circuit 330 can lead to different overshoot and fall-off characteristics.

[0030] Fig. Figure 6 illustrates one of several examples of a Loop Filter 600. The Loop Filter 600 can represent one of the various examples of the Loop Filter 140, as shown in Fig. Figure 1 illustrates the input signal 605, which can be the phase difference output of the phase detector 120, as shown in Fig. As illustrated in Figure 1, the input signal can be supplied to the loop filter 600. The input signal 605 can be coupled to a first amplification circuit 610. The output of the first amplification circuit 610 can be coupled to the second amplification circuit 620. The output of the second amplification circuit 620 can be coupled to a first input of the adder 640. The adder 640 can be part of an integrator, wherein the integrator includes the adder 640 and a feedback path comprising the delay circuit 650 and the third amplification circuit 660. The output of the adder 640 can be coupled to the input of the delay circuit 650. The output of the delay circuit 650 can be coupled to the third amplification circuit 660, and the output of the third amplification circuit 660 can be coupled to a second input of the adder 640. The output of adder 640 can be the loop filter output 690.

[0031] The adder 640, the delay circuit 650 and the third amplification circuit 660 can include the integrator 680.

[0032] In the Fig. In the illustrated example 6, the first amplification circuit 610 can have a gain setting C. p Apply. The second amplification circuit 620 can be used to adjust the gain C. p2 / (1+C p +C p2 ) apply. The third amplification circuit 660 can have a gain setting of 1 / (1+C). p +C p2 ) apply. The value of C p2 can define a second pole in the response of loop filter 600 and can define a frequency at which the loop filter 600 rolls off at a rate of 40dB / decade.

[0033] Fig. Figure 7 illustrates one of the various examples of a frequency response 700. Frequency response 700 can represent the response of one of several examples of the phase-locked circuit 100, as referenced in Fig. 1 described, wherein the phase control circuit 100 includes the loop filter 600, as described with reference to Fig. 6 described.

[0034] Curves 710, 711, 712, and 713 illustrate a frequency response of the noise of the controllable oscillator circuit 130, measured at the output of the controllable oscillator 190, for different implementations of the loop filter 600. Curves 710, 711, 712, and 713 illustrate a frequency response for a loop filter 600 with different values ​​of the coefficients C. p and C p2The loop filter 600 can apply a high-pass response to noise from the local oscillator 135 and attenuate low-frequency noise from the local oscillator 135. Curves 720, 721, 722, and 723 illustrate a frequency response of the noise from the reference signal 110, measured at the output of the controllable oscillator 190, for different implementations of the loop filter 600. Curves 720, 721, 722, and 723 can show a frequency response for loop filter 600 with different values ​​of the coefficients C. p and C p2 To illustrate, loop filter 600 can apply a low-pass response to noise from reference signal 110 and attenuate high-frequency noise from reference signal 110.

[0035] The loop filter 600 can apply attenuation with a slope of 40 dB per decade at the output of the controllable oscillator 190 to noise from reference signal 110, as described in points 717 and 718 in Fig. Point 717 illustrates the response of curve 721 at a frequency of 3*10 -1 Hz, and point 718 illustrates the response of curve 721 at a frequency one decade higher, at 3*10 0 Hz. The response is approximately -18dB at point 717 and approximately -58dB at point 718, illustrating the slope of 40dB per decade of the loop filter 600.

[0036] Fig. Figure 8 illustrates an enlarged view of the frequency response at 800 Hz. It should be noted that the vertical axis in Fig. 8 ranges from -0.5 dB to 1 dB, while the vertical axis in Fig. 7 ranges from -70 dB to +2 dB. Curves 820 and 821 illustrate different levels of the slope in the frequency response for noise from the local oscillator 135 for different implementations of the loop filter 600. Curves 810, 811, 812, and 813 illustrate different levels of overshoot in the frequency response for noise from the controllable oscillator circuit 130 for different implementations of the loop filter 600. Different values ​​for the gain settings in the first gain circuit 610, the second gain circuit 620, and the third gain circuit 660 can lead to different overshoot and slope characteristics.

[0037] Fig. Figure 9 illustrates one of several examples of a dual-phase locking system 900, which includes a first phase-lock circuit 970 and a second phase-lock circuit 975. The first phase-lock circuit 970 can receive a reference signal 910 as an input signal. The reference signal 910 can be input to the positive input of the first phase detector circuit 920. The output of the first controllable oscillator circuit 930 can be input to the negative input of the first phase detector circuit 920. The output of the first phase detector circuit 920 can be coupled to the input of the first loop filter 940. The output of the first phase detector circuit 920 can be a first phase difference output. The first loop filter 940 can be a loop filter, as described in Figure 930. Fig. 3 or Fig. As described in section 6, the first loop filter 940 can be another implementation of a loop filter. The first loop filter 940 can be a frequency-selective filter. The filter order and coefficients of the first loop filter 940 can set a specific frequency-selective slope and determine the bandwidth of the dual-phase control system 900.

[0038] The output of the first loop filter 940 can be coupled to a first input of the adder 950. The output of the adder 950 can be coupled to a first input of the first controllable oscillator circuit 930. The second input of the first controllable oscillator circuit 930 can be coupled to a first oscillator signal 901. The first oscillator signal 901 can also be called a local oscillator signal. The first oscillator signal 901 can be generated by an inexpensive crystal oscillator (XO). The output of the first controllable oscillator circuit 930 can be the dual-phase-locked output 990. The dual-phase-locked output 990 can also be called a phase-locked output.

[0039] The second phase-lock circuit 975 can receive the second oscillator signal 911 as an input signal. The second oscillator signal 911 can be generated by a stable oven-controlled crystal oscillator (OCXO), a temperature-controlled oscillator (TCXO), or some other type of stable oscillator not explicitly mentioned. The second oscillator signal 911 can be fed into the positive input of the second phase detector circuit 921. The output of the second controllable oscillator circuit 931 can be fed into the negative input of the second phase detector circuit 921. The output of the second controllable oscillator 931 can be an oscillation signal. The output of the second phase detector circuit 921 can be coupled to the input of the second loop filter 941. The second loop filter 941 can be a loop filter, as described in the following section. Fig. 3 or Fig. As described in section 6, the second loop filter 941 can be another implementation of a loop filter. The second loop filter 941 can be a frequency-selective filter. The filter order and coefficients of the second loop filter 941 can set a specific frequency-selective slope and determine the bandwidth of the dual-phase control system 900.

[0040] The output of the second loop filter 941 can be coupled to the first input of the second controllable oscillator circuit 931. The second input of the second controllable oscillator circuit 931 can be coupled to the first oscillator signal 901. The output of the second loop filter 941 can be coupled to the second input of the adder 950.

[0041] In operation, the first loop filter 940 can be a loop filter with a predefined frequency response. In operation, the second loop filter 941 can be a loop filter with a predefined frequency response. The dual-phase locking system 900 can apply low-pass filtering to the noise of the reference signal 910. The dual-phase locking system 900 can apply high-pass filtering to the noise of the first oscillator signal 901. The dual-phase locking system 900 can apply band-pass filtering to the noise of the second oscillator signal 911.

[0042] Fig. Figure 10 illustrates one of several examples of a frequency response 1000. Frequency response 1000 can represent the response of one of the various examples of the dual-phase controlled system 900, as referenced in Fig. 9 described.

[0043] Curves 1020, 1021, 1022, and 1023 illustrate a frequency response of the noise from the reference signal 910, as measured at the dual-phase-controlled system output 990, for different implementations of the first loop filter 940 and the second loop filter 941. The first loop filter 940 and the second loop filter 941 can apply a low-pass response to the noise of the reference signal 910 and attenuate the high-frequency noise of the reference signal 910.

[0044] Curves 1010, 1011, 1012, and 1013 illustrate the frequency response of the noise of the first oscillator signal 901, measured at the dual-phase-controlled system output 990, for different implementations of the first loop filter 940 and the second loop filter 941. The first loop filter 940 and the second loop filter 941 can apply a high-pass response to the noise of the first oscillator signal 901 and attenuate the low-frequency noise of the first oscillator signal 901.

[0045] Curves 1030, 1031, and 1032 illustrate the frequency response of the noise of the second oscillator signal 911, measured at the dual-phase-controlled system output 990, for different implementations of the first loop filter 940 and the second loop filter 941. The first loop filter 940 and the second loop filter 941 can apply a bandpass response to noise from the second oscillator signal 911 and attenuate high-frequency and low-frequency noise from the second oscillator signal 911.

[0046] The first loop filter 940 and the second loop filter 941 can apply attenuation with a slope of 40 dB per decade for noise from the reference signal 910, as described in points 1017 and 1018 in Fig. Point 10 is given. Point 1017 illustrates the response of curve 1023 at a frequency of 3*10 -1Hz, and point 1018 illustrates the response of curve 1023 at a frequency one decade higher, at 3*10 0 Hz. The response is approximately -18 dB at point 1017 and approximately -58 dB at point 1018, illustrating the 40 dB per decade roll-off of the combined response of the first loop filter 940 and the second loop filter 941. A similar 40 dB per decade roll-off in curve 1011 is illustrated between points 1027 and 1028 for the noise of the first oscillator signal 901. Dashed lines from points 1027 and 1028 to the axes of the figure have been omitted to improve the figure's readability.

[0047] Fig. Figure 11 illustrates an enlarged view of the frequency response. Note that the vertical axis in Fig. 11 ranges from -0.5 dB to 1 dB, while the vertical axis in Fig. 7 ranges from -70 dB to +2 dB. Curves 1120 and 1121 illustrate different levels of the slope in the frequency response for noise from the reference signal 910 for different implementations of the first loop filter 940 and the second loop filter 941. Curves 1130, 1131, 1132, 1133, and 1134 illustrate different levels of overshoot in the frequency response for noise from the second oscillator signal 911 for different implementations of the first loop filter 940 and the second loop filter 941. Curves 1110, 1111, 1112, and 1113 illustrate different levels of the slope in the frequency response for noise from the first oscillator signal 901 for different implementations of the first loop filter 940 and the second loop filter 941.

[0048] Fig. Figure 12 illustrates a method for generating an oscillation signal.

[0049] Operation 1205 can receive a reference signal, a first oscillator signal and a second oscillator signal as inputs.

[0050] In operation 1210, a first phase difference between the reference signal and the output of a first controllable oscillator circuit can be detected in order to generate a first phase difference, e.g. by the first phase detector circuit 920.

[0051] In operation 1220, a second phase difference between the second oscillator signal and the output of a second controllable oscillator circuit can be detected to generate a second phase difference, e.g. by the second phase detector circuit 921.

[0052] In operation 1230, the first phase difference can be filtered with a first frequency-selective filter, e.g., with the first loop filter 940. In operation 1235, the second phase difference can be filtered with a second frequency-selective filter, e.g., by the second loop filter 941.

[0053] In operation 1240, the first controllable oscillator circuit can be driven by the first oscillator signal and the output of an adder; for example, the first controllable oscillator circuit 930 can be driven by the output of the adder 950. The adder can add the output of the first frequency-selective filter and the output of the second frequency-selective filter. The output signal of the adder can modify at least the phase or the frequency of the oscillator signal of the first controllable oscillator circuit.

[0054] In operation 1250, the second controllable oscillator circuit can be driven by the first oscillator signal and the output of the second frequency-selective filter; for example, the second controllable oscillator circuit 931 can be driven by the first oscillator signal 901 and the output of the second loop filter 941. The output of the second frequency-selective filter can modify at least the phase or the frequency of the oscillator signal of the second controllable oscillator circuit.

[0055] In operation 1260, the output of the first controllable oscillator circuit can be provided as a phase control output. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 436,931

[0001]

Claims

[1] Device comprising: a controllable oscillator circuit for generating an oscillation signal, wherein the controllable oscillator circuit receives an input from a local oscillator; a phase detector circuit for generating a phase difference output based on a first input and a second input, wherein the first input is coupled to a reference signal and the second input is coupled to the oscillation signal generated by the controllable oscillator circuit; a loop filter with a frequency-selective slope for filtering the phase difference output to generate a filtered phase difference output; a multiplier to apply a gain setting to the filtered phase difference output; a first integrator to integrate an output of the multiplier, and an adder to sum the filtered phase difference output and an output of the first integrator, wherein: The controllable oscillator circuit is designed to modify at least one phase or one frequency of the oscillation signal based on the output of the adder. [2] Device according to claim 1, wherein: The loop filter is designed to receive an input signal; the input signal is coupled to a first amplification circuit, a second amplification circuit, and a third amplification circuit; the output of the first amplification circuit is coupled to a first input of a first adder; the output of the second amplification circuit is coupled to a first input of a second adder; the output of the third amplification circuit is coupled to an input of an integrator; the output of the integrator is coupled to a second input of the second adder; the output of the second adder is coupled to a second input of the first adder; and the output of the first adder is coupled to the output of the loop filter. [3] Device according to claim 2, wherein the loop filter is provided to attenuate the noise in the reference signal. [4] Device according to one of claims 2 to 3, wherein the loop filter is provided to attenuate noise in the input signal of the local oscillator. [5] Device according to one of claims 2 to 4, wherein the first amplification circuit is provided to apply a first amplification setting, the second amplification circuit is provided to apply a second amplification setting, and the third amplification circuit is provided to apply a third amplification setting. [6] Device according to any one of claims 1 to 5, wherein: The loop filter is designed to receive an input signal; the input signal is coupled to a first amplification circuit; the output of the first amplification circuit is coupled to a second amplification circuit; the output of the second amplification circuit is coupled to a second integrator; the second integrator has a third adder; a feedback path has a delay circuit in series with a third amplification circuit; the output of the second amplification circuit is coupled to a first input of the third adder; the output of the third amplification circuit is coupled to the second input of the third adder; and The loop filter output is coupled to the output of the third adder. [7] System that exhibits: a first controllable oscillator circuit for generating a phase-controlled output; a first phase detector circuit for generating a first phase difference output based on a first input and a second input, wherein the first input is coupled to a reference signal and the second input is coupled to the output of the first controllable oscillator circuit; a first loop filter with a frequency-selective slope to filter the first phase difference output in order to generate a first filtered phase difference output, and wherein the first controllable oscillator circuit modifies at least either a phase or a frequency of a first oscillator signal based on a sum of the first filtered phase difference output and a second filtered phase difference output; a second controllable oscillator circuit generates an oscillation signal at an output of the second controllable oscillator circuit; A second phase detector circuit generates a second phase difference output based on a first input and a second input, wherein the first input receives a second oscillator signal and the second input is coupled to the output of the second controllable oscillator circuit, and A second loop filter with a frequency-selective slope filters the second phase difference output to generate the second filtered phase difference output, wherein: The second controllable oscillator circuit is designed to modify at least either a phase or a frequency of the first oscillator signal based on the second filtered phase difference output. [8] System according to claim 7, wherein the first frequency-selective filter comprises a low-pass filter and the second frequency-selective filter comprises a low-pass filter. [9] Device according to one of claims 7 to 8, wherein the first loop filter receives an input signal and the input signal is coupled to a first amplification circuit, a second amplification circuit and a third amplification circuit, wherein the output of the first amplification circuit is coupled to a first input of a first adder, the output of the second amplification circuit is coupled to a first input of a second adder, and the output of the third amplification circuit is coupled to an integrator input, wherein the integrator output is coupled to a second input of the second adder, the output of the second adder is coupled to a second input of the first adder, and the output of the first adder is coupled to the output of the first loop filter. [10] Device according to one of claims 7 to 9, wherein the second loop filter receives an input signal, the input signal is coupled to a first amplification circuit, the output of the first amplification circuit is coupled to a second amplification circuit, the output of the second amplification circuit is coupled to an integrator, wherein the integrator has an adder, a feedback path comprising a delay circuit in series with a third amplification circuit, wherein the output of the second amplification circuit is coupled to a first input of the adder, the output of the third amplification circuit is coupled to the second input of the adder, and the output of the second loop filter is coupled to the output of the adder. [11] Method which features: Receiving an input from a reference signal, a first oscillator signal, and a second oscillator signal; Detecting a first phase difference between the reference signal and an output oscillator signal of a first controllable oscillator circuit to generate a first phase difference; Detecting a second phase difference between the second oscillator signal and an output oscillator signal of a second controllable oscillator circuit to generate a second phase difference; Filtering the first phase difference with a first frequency-selective filter; Filtering the second phase difference with a second frequency-selective filter; Driving the first controllable oscillator circuit with the first oscillator signal and an output of an adder, wherein the adder adds the outputs of the first frequency-selective filter and the second frequency-selective filter, and the output of the adder modifies at least either a phase or a frequency of the output oscillator signal of the first controllable oscillator circuit; Driving the second controllable oscillator circuit with the first oscillator signal and the output of the second frequency-selective filter, wherein the output of the second frequency-selective filter modifies at least one phase or one frequency of the output oscillation signal of the second controllable oscillator circuit, and Output of the output oscillation signal of the first controllable oscillator circuit as a phase control output. [12] Method according to claim 11, wherein the first frequency-selective filter comprises a low-pass filter. [13] Method according to one of claims 11 to 12, wherein the second frequency-selective filter comprises a low-pass filter.

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