Symmetrical amplifier

Abstract

A symmetrical amplifier is configured to include: a signal divider circuit (2) to divide a gain target signal into two signals, output a first signal as one of the two divided signals, and output a second signal as another of the two divided signals; a first amplifier (3) to amplify the first signal output by the signal divider circuit (2); a second amplifier (6) to amplify the second signal output by the signal divider circuit (2); and a synthesis circuit (7) to synthesize the first signal, which is amplified by the first amplifier (3), and the second signal, which is amplified by the second amplifier (6).Furthermore, the first amplifier (3) of the balanced amplifier includes a first matching circuit to match the output impedance of the first amplifier (3) to a first impedance that differs from the impedance of a load connected to an output side of the synthesis circuit (7). The second amplifier (6) of the balanced amplifier includes a second matching circuit to match the output impedance of the second amplifier (6) to a second impedance that differs from the impedance of the load. One of the first and second impedances is higher than the impedance of the load, and the other of the first and second impedances is lower than the impedance of the load.

Description

AREA OF TECHNOLOGY

[0001] The present disclosure relates to a symmetrical amplifier or balanced amplifier. TECHNICAL BACKGROUND

[0002] For example, among amplifiers for wireless communication, there is a symmetrical amplifier with two amplifiers.

[0003] As an example of such a symmetrical amplifier, patent literature 1 describes a high-frequency circuit which includes a 90° hybrid circuit, a first amplifier, a second amplifier, a 90° phase shifter and an isolator module.

[0004] The 90° hybrid circuit splits a high-frequency signal into two signals. One of the split signals is output to the first amplifier, and the other is output to the second amplifier. The first amplifier amplifies the first high-frequency signal and outputs the amplified signal to the 90° phase shifter. The 90° phase shifter delays the phase of the amplified first high-frequency signal by 90° and outputs the phase-shifted signal to the isolator module. The second amplifier amplifies the second high-frequency signal and outputs the amplified signal to the isolator module.The isolator module synthesizes the first high-frequency signal output by the 90° phase shifter and the second high-frequency signal output by the second amplifier, and outputs a synthesis signal of the first high-frequency signal and the second high-frequency signal to a load. REFERENCE LIST PATENT LITERATURE

[0005] Patent Literature 1: JP 2013-236144 A SUMMARY OF THE INVENTIONAL PROBLEM

[0006] The high-frequency circuit described in patent literature 1 has the problem that the electrical output power and efficiency decrease due to the change in the impedance of the load connected to the output side of the insulator module.

[0007] The present disclosure was made to solve the above problem, and one objective of the present disclosure is to obtain a symmetrical amplifier that can suppress a decrease in electrical output power and efficiency even when the impedance of a load changes. SOLUTION TO THE TASK

[0008] A symmetrical amplifier according to the present disclosure comprises: a signal isolator circuit for splitting an amplification target signal into two separate signals, including a first signal and a second signal, and outputting the first signal and the second signal; a first amplifier for amplifying the first signal output by the signal isolator circuit; a second amplifier for amplifying the second signal output by the signal isolator circuit; and a synthesis circuit for synthesizing the first signal amplified by the first amplifier and the second signal amplified by the second amplifier. The first amplifier of the symmetrical amplifier includes a first matching circuit for matching an output impedance of the first amplifier to a first impedance that differs from the impedance of a load connected to an output side of the synthesis circuit.The second amplifier stage of the symmetrical amplifier incorporates a second matching circuit to match the output impedance of the second amplifier to a second impedance that differs from the load impedance. One of the first and second impedances is higher than the load impedance, and the other is lower than the load impedance. ADVANTAGEOUS EFFECTS OF THE INVENTION

[0009] According to the present disclosure, it is possible to prevent a reduction in electrical output power and efficiency, even if the impedance of a load changes. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram showing a symmetrical amplifier according to embodiment 1. Fig. 2A is a block diagram showing the interior of a first amplifier 3, and Fig. 2B is a block diagram showing the inside of a second amplifier 6. Fig. Figure 3A is a Smith chart illustrating the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 after a load impedance Z0 was changed from 50 Ω to 25 Ω, and Fig. Figure 3B is a Smith chart illustrating the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 after the load impedance Z0 was changed from 50 Ω to 75 Ω. Fig. Figure 4A is a Smith chart showing the output impedance of a first amplifier and the output impedance of a second amplifier in a general symmetrical amplifier after changing the load impedance Z0 from 50 Ω to 25 Ω, and Fig. Figure 4B is a Smith chart showing the output impedance of the first amplifier and the output impedance of the second amplifier in the general symmetrical amplifier after the load impedance Z0 was changed from 50 Ω to 75 Ω. Fig. Figure 5 is a Smith chart showing the load impedance dependence of the efficiency in the diagram. Fig. Figure 1 shows the symmetrical amplifier and the general symmetrical amplifier as contours. Fig. Figure 6 is a Smith chart showing the load impedance dependence of the electrical output power in the diagram. Fig. Figure 1 shows the symmetrical amplifier and the general symmetrical amplifier as contours. Fig. Figure 7 is a block diagram showing a symmetrical amplifier according to embodiment 2. Fig. Figure 8 is a block diagram showing a symmetrical amplifier according to embodiment 3. Fig. Figure 9 is a block diagram showing a symmetrical amplifier according to embodiment 4. Fig. Figure 10 is a block diagram showing a symmetrical amplifier according to embodiment 5. Fig. Figure 11 is a block diagram showing a symmetrical amplifier according to embodiment 6. Fig. Figure 12 is a block diagram showing a symmetrical amplifier according to embodiment 7. DESCRIPTION OF THE EXAMPLES OF EXECUTION

[0010] The following describes a method for carrying out the present disclosure with reference to the accompanying drawings in order to further explain the present disclosure. Example 1.

[0011] Fig. Figure 1 is a block diagram showing a symmetrical amplifier according to embodiment 1.

[0012] The in Fig. The symmetrical amplifier shown in Figure 1 comprises a signal input terminal 1, a signal divider circuit 2, a first amplifier 3, an output phaser circuit 4, an input phaser circuit 5, a second amplifier 6, a synthesis circuit 7 and a signal output terminal 8.

[0013] A high-frequency signal is fed to signal input terminal 1 as the amplification target signal.

[0014] The signal divider circuit 2 includes a first terminal 2a, a second terminal 2b and a third terminal 2c.

[0015] The high-frequency signal present at signal input terminal 1 is fed to the first terminal 2a of the signal divider circuit 2.

[0016] The signal divider circuit 2 splits the high-frequency signal into two signals.

[0017] The signal divider circuit 2 outputs a first signal as one of the two split signals from the second terminal 2b to the first amplifier 3 and outputs a second signal as the other of the two split signals from the third terminal 2c to the input phaser circuit 5.

[0018] The first amplifier 3, for example, is designed as a semi-discrete amplifier in a high-frequency package or as a monolithic integrated microwave amplifier (MMIC) on a semiconductor substrate.

[0019] The first amplifier 3 includes a first matching circuit for matching an output impedance of the first amplifier 3 to a first impedance that differs from the impedance of a load (hereinafter referred to as "load impedance Z0") connected to an output side of the synthesis circuit 7.

[0020] At the in Fig. In the symmetrical amplifier shown in Figure 1, the first impedance is higher than the load impedance Z0.

[0021] The first amplifier 3 amplifies the first output signal of the second terminal 2b of the signal divider circuit 2.

[0022] The first amplifier 3 outputs the amplified first signal to the output phase circuit 4.

[0023] One end of the output phase circuit 4 is connected to an output side of the first amplifier 3.

[0024] The other end of the output phase circuit 4 is connected to a first terminal 7a, which is a terminal on the input side of the synthesis circuit 7.

[0025] The output phase circuit 4 is a circuit with an electrical length of 90 degrees. When the first signal, amplified by the first amplifier 3, passes through the output phase circuit 4, the phase of the amplified first signal is delayed by 90 degrees.

[0026] The first signal that is subjected to a phase shift by the output phase circuit 4 is fed to the first terminal 7a of the synthesis circuit 7.

[0027] One end of the input phase circuit 5 is connected to the third terminal 2c of the signal divider circuit 2.

[0028] The other end of the input phase circuit 5 is connected to an input side of the second amplifier 6.

[0029] The input phaser 5 changes the phase of the second signal output by the third terminal 2c of the signal divider circuit 2 such that the phase of the amplified first signal and the phase of the amplified second signal are in phase at a synthesis point of the first signal amplified by the first amplifier 3 and the second signal amplified by the second amplifier 6 in the synthesis circuit 7. A third terminal 7c of the synthesis circuit 7 corresponds to the synthesis point of the synthesis circuit 7.

[0030] The second amplifier 6, for example, is implemented as a semi-discrete amplifier in a high-frequency package or as an MMIC amplifier on a semiconductor substrate.

[0031] The second amplifier 6 contains a second matching circuit that matches an output impedance of the second amplifier 6 to a second impedance that differs from the load impedance Z0.

[0032] At the in Fig. In the symmetrical amplifier shown in Figure 1, the second impedance is lower than the load impedance Z0.

[0033] The second amplifier 6 amplifies the second signal output by the input phaser 5.

[0034] The second amplifier 6 outputs the amplified second signal to a second terminal 7b, which is a terminal on the input side of the synthesis circuit 7.

[0035] Synthesis circuit 7, for example, is implemented as a 90-degree hybrid circuit.

[0036] The synthesis circuit 7 includes the first connection 7a, the second connection 7b, the third connection 7c and a fourth connection 7d.

[0037] The first terminal 7a and the second terminal 7b are each an input terminal, the third terminal 7c is an output terminal and the fourth terminal 7d is an isolation terminal which is grounded via a resistor.

[0038] The first signal output by the output phase circuit 4 is fed to the first terminal 7a of the synthesis circuit 7.

[0039] The second signal, amplified by the second amplifier 6, is routed to the second terminal 7b of the synthesis circuit 7.

[0040] Synthesis circuit 7 synthesizes the first signal and the second signal.

[0041] The synthesis circuit 7 outputs the synthesis signal of the first signal and the second signal from the third terminal 7c to the signal output terminal 8.

[0042] Signal output terminal 8 is connected to a load not shown.

[0043] The load impedance Z0 can, for example, deviate from 50 Ω.

[0044] Fig. 2A is a block diagram showing the inside of the first amplifier 3.

[0045] The in Fig. The first amplifier 3 shown in Figure 2A comprises an input matching circuit 3a, a first amplification element 3b and an output matching circuit 3c.

[0046] One end of the input matching circuit 3a is connected to the second terminal 2b of the signal divider circuit 2.

[0047] The other end of the input matching circuit 3a is connected to an input terminal of the first amplification element 3b.

[0048] The input matching circuit 3a matches an input impedance of the first amplification element 3b to an impedance of an input side of the signal input terminal 1.

[0049] The input terminal of the first amplification element 3b is connected to the other end of the input matching circuit 3a.

[0050] An output terminal of the first amplifier element 3b is connected to one end of the output matching circuit 3c.

[0051] The first amplifying element 3b is, for example, a silicon semiconductor transistor, an LDMOS semiconductor transistor (Lateral Double Diffused MOS), a gallium arsenide semiconductor transistor or a gallium nitride semiconductor transistor.

[0052] The first amplification element 3b amplifies the first signal that has passed through the input matching circuit 3a.

[0053] The first amplification element 3b outputs the amplified first signal to the output matching circuit 3c.

[0054] One end of the output matching circuit 3c is connected to the output terminal of the first amplifying element 3b.

[0055] The other end of the output matching circuit 3c is connected to one end of the output phasing circuit 4.

[0056] The output matching circuit 3c acts as a first matching circuit to match an output impedance of the first amplification element 3b with a first impedance that is higher than the load impedance Z0.

[0057] Since the load impedance Z0 is generally 50 Ω, the output matching circuit 3c matches the output impedance of the first amplifying element 3b to the first impedance that is higher than 50 Ω.

[0058] Fig. 2B is a block diagram showing the inside of the second amplifier 6.

[0059] The in Fig. The second amplifier 6 shown in 2B comprises an input matching circuit 6a, a second amplification element 6b and an output matching circuit 6c.

[0060] One end of the input matching circuit 6a is connected to the other end of the input phasing circuit 5.

[0061] The other end of the input matching circuit 6a is connected to an input terminal of the second amplifying element 6b.

[0062] The input matching circuit 6a matches an input impedance of the second amplification element 6b to the impedance of the input side of the signal input terminal 1.

[0063] The input terminal of the second amplifier element 6b is connected to the other end of the input matching circuit 6a.

[0064] One output terminal of the second amplifier element 6b is connected to one end of the output matching circuit 6c.

[0065] The second amplifying element 6b is, for example, a silicon semiconductor transistor, an LDMOS semiconductor transistor, a gallium arsenide semiconductor transistor or a gallium nitride semiconductor transistor.

[0066] The second amplification element 6b amplifies the second signal that has passed through the input matching circuit 6a.

[0067] The second amplification element 6b outputs the amplified second signal to the output matching circuit 6c.

[0068] One end of the output matching circuit 6c is connected to the output terminal of the second amplifier element 6b.

[0069] The other end of the output matching circuit 6c is connected to the second terminal 7b of the synthesis circuit 7.

[0070] The output matching circuit 6c serves as a second matching circuit to match an output impedance of the second amplification element 6b with a second impedance that is lower than the load impedance Z0.

[0071] Since the load impedance Z0 is generally 50 Ω, the output matching circuit 6c adapts the output impedance of the second amplifier element 6b to the second impedance, which is less than 50 Ω.

[0072] The following describes how the in Fig. 1 symmetrical amplifier described.

[0073] The signal divider circuit 2 splits the high-frequency signal applied to the signal input terminal 1 into two signals.

[0074] The signal divider circuit 2 outputs the first signal as one of the two divided signals from the second terminal 2b to the first amplifier 3.

[0075] The signal divider circuit 2 outputs the second signal as the other signal of the two divided signals from the third terminal 2c to the input phase circuit 5.

[0076] The first amplification element 3b of the first amplifier 3 amplifies the first output signal of the second terminal 2b of the signal divider circuit 2.

[0077] At this point, the output matching circuit 3c of the first amplifier 3 adjusts the output impedance of the first gain element 3b, where the first impedance is higher than the load impedance Z0. If the load impedance Z0 is 50 Ω, the output matching circuit 3c adjusts the output impedance of the first gain element 3b to the first impedance that is higher than 50 Ω.

[0078] The first amplifier 3 outputs the amplified first signal to the output phase circuit 4.

[0079] The output phase circuit 4 delays the phase of the first signal amplified by the first amplifier 3 by 90 degrees.

[0080] The first signal that is subjected to a phase shift by the output phase circuit 4 is fed to the first terminal 7a of the synthesis circuit 7.

[0081] The phase of the first signal, which is applied to the first terminal 7a of the synthesis circuit 7, is further delayed by 90 degrees by the synthesis circuit 7. Thus, the phase of the first signal is delayed by a total of 180 degrees, and the first signal, delayed by 180 degrees, is applied to the third terminal 7c of the synthesis circuit 7.

[0082] The input phase circuit 5 changes the phase of the second signal output at the third terminal 2c of the signal divider circuit 2 such that the phase of the first signal amplified by the first amplifier 3 and the phase of the second signal amplified by the second amplifier 6 are in phase at the third terminal 7c of the synthesis circuit 7.

[0083] More precisely, if the phase of the first signal, which is amplified by the third terminal 7c, is θ1, and in a case where the input phaser 5 is not present, the phase of the second signal, which is amplified by the third terminal 7c, is θ2, and the phase, which is delayed by the input phaser 5, is θ3, then the phase θ3, which is delayed by the input phaser 5, is expressed, for example, by the following equation (1) or equation (2). θ3=360−|θ1+θ2| θ3=0−|θ1+θ2|

[0084] For example, if the phase θ1 of the first signal is -180 degrees and the phase θ2 of the second signal is 0 degrees, the input phase circuit 5 has such an electrical length that the phase changes from -180 degrees, or such an electrical length that the phase changes from +180 degrees, so that the phase of the first signal and the phase of the second signal are in phase at the third terminal 7c.

[0085] Here, the phase θ3 delayed by the input phaser 5 is expressed by equation (1) or equation (2). The phase of the first signal and the phase of the second signal only need to be in phase at the third terminal 7c, and the phase θ3 is not limited to a phase expressed by equation (1) or equation (2).

[0086] The second amplification element 6b of the second amplifier 6 amplifies the second output signal of the input phase circuit 5.

[0087] At this point, the output matching circuit 6c of the second amplifier 6 adapts the output impedance of the second amplifier element 6b to the second impedance that is lower than the load impedance Z0. If the load impedance Z0 is 50 Ω, the output matching circuit 6c adapts the output impedance of the second amplifier element 6b to the second impedance that is less than 50 Ω.

[0088] The second amplifier 6 outputs the amplified second signal to the second terminal 7b of the synthesis circuit 7.

[0089] The first signal output by the output phase circuit 4 is fed to the first terminal 7a of the synthesis circuit 7.

[0090] The second signal, amplified by the second amplifier 6, is routed to the second terminal 7b of the synthesis circuit 7.

[0091] The synthesis circuit 7 synthesizes the first signal and the second signal in phase after delaying the phase of the first signal, which is fed to the first terminal 7a, by 90 degrees.

[0092] The synthesis circuit 7 outputs the synthesis signal of the first signal and the second signal from the third terminal 7c via the signal output terminal 8 to the load not shown.

[0093] Next, an effect of the in Fig. 1 symmetrical amplifier described.

[0094] Fig. Figure 3A is a Smith chart showing the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 after the load impedance Z0 has changed from 50 Ω to 25 Ω. Fig. 3A represents a marker ◯ the output impedance of the first amplifier 3 and a marker □ the output impedance of the second amplifier 6.

[0095] Fig. Figure 4A is a Smith chart showing the output impedance of the first amplifier and the output impedance of the second amplifier in a general symmetrical amplifier after changing the load impedance Z0 from 50 Ω to 25 Ω. The general symmetrical amplifier corresponds to a high-frequency circuit disclosed in patent reference 1.

[0096] The output impedance of the first amplifier in a generally symmetrical amplifier is matched to the load impedance Z0, and the output impedance of the second amplifier in a generally symmetrical amplifier is matched to the load impedance Z0. Fig. 4A represents a marker ◯ the output impedance of the first amplifier and a black marker □ the output impedance of the second amplifier.

[0097] If the load impedance Z0 in a generally symmetrical amplifier changes from 50 Ω to 25 Ω, as in Fig. As shown in Figure 4A, the output impedance of the first amplifier and the output impedance of the second amplifier change in opposite directions. That is, the output impedance of the first amplifier changes in the same direction as the load impedance Z0, and the output impedance of the second amplifier changes in the opposite direction to that of the load impedance Z0. If the load impedance Z0 changes from 50 Ω to 25 Ω, the difference between the output impedance of the first amplifier and the output impedance of the second amplifier becomes larger.

[0098] In contrast, the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 change in the same direction when the load impedance Z0 changes in the Fig. The symmetrical amplifier shown in section 1 changes from 50 Ω to 25 Ω, as shown in Fig. Figure 3A illustrates this. That is, the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 change in the same direction as the load impedance Z0. Consequently, the difference between the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 will not be greater than the difference between the output impedance of the first amplifier and the output impedance of the second amplifier in a general symmetrical amplifier, even if the load impedance Z0 changes from 50 Ω to 25 Ω.

[0099] Here, the difference between the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 is described in more detail. For the sake of simplicity, the difference is described by ignoring the functions in the output matching circuit 3c of the first amplifier 3 and the output matching circuit 6c of the second amplifier 6.

[0100] A case is assumed in which a change in the reflection coefficient Γ is expressed as a change in the output impedance at each of the signal output terminals of the general symmetrical amplifier and the signal output terminal 8 of the in Fig. 1 symmetrical amplifier shown.

[0101] In a case where the reflection coefficient of the first amplifier is Γ1, the reflection phase of the first amplifier is θ1, the reflection coefficient of the second amplifier is Γ2, and the reflection phase of the second amplifier is θ2 in the general symmetrical amplifier, since the symmetrical amplifier contains a 90-degree hybrid circuit as the synthesis circuit, the following equations (3) and equations (4) apply. Γ1=Γ2 θ1=θ2+180

[0102] Equations (3) and (4) each mean that if the output impedance of the signal output terminal changes, the reflection coefficient Γ1 of the first amplifier and the reflection coefficient Γ2 of the second amplifier will move out of phase by the same amplitude. Therefore, if the load impedance Z0 changes, the difference between the output impedance of the first amplifier and the output impedance of the second amplifier will increase. As this difference increases and the synthesis circuit synthesizes two signals, losses occur, reducing the electrical output power and efficiency.

[0103] Since the in Fig. In contrast, equation (5) and equation (6) apply to the symmetrical amplifier shown in Figure 1, which contains the output phase circuit 4 and the input phase circuit 5. Γ1=Γ2 θ1=θ2

[0104] Equations (5) and (6) each mean that if the output impedance of the signal output terminal 8 changes, the reflection coefficient Γ1 of the first amplifier 3 and the reflection coefficient Γ2 of the second amplifier 6 move in phase with the same amplitude. Therefore, the difference between the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 does not increase, even if the load impedance Z0 changes. This difference remains constant, thus reducing losses during the synthesis of two signals by the synthesis circuit 7 and improving the electrical output power and efficiency.

[0105] Fig. Figure 3B is a Smith chart showing the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 after the load impedance Z0 has changed from 50 Ω to 75 Ω. Fig. 3B represents the output impedance of the first amplifier 3 with a marker ◯ and the output impedance of the second amplifier 6 with a marker □.

[0106] Fig. Figure 4B is a Smith chart showing the output impedance of the first amplifier and the output impedance of the second amplifier in the general symmetrical amplifier after changing the load impedance Z0 from 50 Ω to 75 Ω. The output impedance of the first amplifier in the general symmetrical amplifier is matched to the load impedance Z0, and the output impedance of the second amplifier in the general symmetrical amplifier is matched to the load impedance Z0. Fig. 4B represents the output impedance of the first amplifier with a marker ◯ and the output impedance of the second amplifier with a marker □.

[0107] If the load impedance Z0 of a general symmetrical amplifier changes from 50 Ω to 75 Ω, the output impedance of the first amplifier and the output impedance of the second amplifier change in opposite directions, as shown in Fig. Figure 4B illustrates this. That is, the output impedance of the first amplifier changes in the same direction as the load impedance Z0, and the output impedance of the second amplifier changes in the opposite direction to that of the load impedance Z0. If the load impedance Z0 changes from 50 Ω to 75 Ω, the difference between the output impedance of the first amplifier and the output impedance of the second amplifier will increase.

[0108] In contrast, the changes in Fig. In the symmetrical amplifier shown in Figure 1, the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 change in the same direction when the load impedance Z0 changes from 50 Ω to 75 Ω, as shown in Figure 1. Fig. Figure 3B illustrates this. That is, the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 change in the same direction as the load impedance Z0. Consequently, the difference between the output impedance of the first amplifier 3 and the output impedance of the second amplifier 6 will not be greater than the difference between the output impedance of the first amplifier and the output impedance of the second amplifier in a general symmetrical amplifier, even if the load impedance Z0 changes from 50 Ω to 75 Ω.

[0109] Fig. Figure 5 is a Smith chart showing the load impedance dependence of the efficiency in the diagram. Fig. Figure 1 shows the symmetrical amplifier and the general symmetrical amplifier as contours.

[0110] In Fig. 5 shows the contours of the efficiency as contours of 10 pt.

[0111] A contour area of ​​efficiency of 10 pt in which in Fig. The symmetrical amplifier shown in Figure 1 is wider than that of the general symmetrical amplifier, as shown in Figure 1. Fig. 5 shown. Consequently, it is determined that the in Fig. The symmetrical amplifier shown in Figure 1 can achieve high efficiency with a load impedance Z0 that differs from 50 Ω.

[0112] Fig. Figure 6 is a Smith chart showing the load impedance dependence of the electrical output power in the diagram. Fig. Figure 1 shows the symmetrical amplifier and the general symmetrical amplifier as contours.

[0113] In Fig. Figure 6 shows the contours of the electrical output power as contours of 2 dB.

[0114] A contour range of electrical output power of 2 dB in which in Fig. The symmetrical amplifier or balanced amplifier shown in Figure 1 is wider than the one in Figure 2. Fig. 6 general symmetrical amplifier shown. Consequently, it is found that the in Fig. The symmetrical amplifier shown in Figure 1 can achieve a high electrical output power with a load impedance Z0 that differs from 50 Ω.

[0115] In the above embodiment 1, the symmetrical amplifier is configured to include the signal divider circuit 2, which divides a gain target signal into two signals, outputs the first signal as one of the two divided signals and outputs the second signal as the other of the two divided signals, the first amplifier 3, which amplifies the first signal output by the signal divider circuit 2, the second amplifier 6, which amplifies the second signal output by the signal divider circuit 2, and the synthesis circuit 7, which synthesizes the first signal amplified by the first amplifier 3 and the second signal amplified by the second amplifier 6.Furthermore, the first amplifier 3 of the balanced amplifier contains the first matching circuit, which adapts the output impedance of the first amplifier 3 to the first impedance, which differs from the impedance of the load connected to the output side of the synthesis circuit 7. The second amplifier 6 of the balanced amplifier contains the second matching circuit, which adapts the output impedance of the second amplifier 6 to the second impedance, which differs from the impedance of the load. One impedance of the first and second amplifiers is higher than the impedance of the load, and the other impedance of the first and second amplifiers is lower than the impedance of the load. Accordingly, the balanced amplifier can prevent a reduction in electrical output power and efficiency, even if the impedance of the load changes.

[0116] In the Fig. In the symmetrical amplifier shown in Figure 1, the output matching circuit 3c of the first amplifier 3 matches the output impedance of the first gain element 3b to an impedance higher than the load impedance Z0, and the output matching circuit 6c of the second amplifier 6 matches the output impedance of the second gain element 6b to an impedance lower than the load impedance Z0. However, this is only an example, and the output matching circuit 3c of the first amplifier 3 matches the output impedance of the first gain element 3b to an impedance lower than the load impedance Z0, and the output matching circuit 6c of the second amplifier 6 matches the output impedance of the second gain element 6b to an impedance higher than the load impedance Z0.In this case too, the symmetrical amplifier can prevent a reduction in electrical output power and efficiency, even if the impedance of the load changes. Example 2.

[0117] In embodiment 2, a symmetrical amplifier is described in which the output phase circuit 4 is provided between the second amplifier 6 and the synthesis circuit 7 and the input phase circuit 5 is provided between the signal divider circuit 2 and the first amplifier 3.

[0118] Fig. Figure 7 is a block diagram showing the symmetrical amplifier according to embodiment 2. It should be noted that in Fig. 7 the same reference symbols as in Fig. 1. Identify identical or corresponding parts, so that a detailed description is omitted.

[0119] At the in Fig. In the symmetrical amplifier shown in Figure 7, the output phase circuit 4 is arranged between the second amplifier 6 and the synthesis circuit 7.

[0120] Furthermore, in the Fig. The input phase circuit 5 is provided between the signal divider circuit 2 and the first amplifier 3 in the symmetrical amplifier shown in Figure 7.

[0121] The input phaser 5 changes the phase of the first signal output from the second terminal 2b of the signal divider circuit 2, such that the phase of the amplified first signal and the phase of the amplified second signal are in phase at a synthesis point of the first signal amplified by the first amplifier 3 and the second signal amplified by the second amplifier 6 in the synthesis circuit 7. The third terminal 7c of the synthesis circuit 7 corresponds to the synthesis point of the synthesis circuit 7.

[0122] Also in the Fig. In the symmetrical amplifier shown in Figure 7, one of the first and second impedances is higher than the load impedance Z0, and the other of the first and second impedances is lower than the load impedance Z0, similar to the one in Fig. 1 symmetrical amplifier shown. Accordingly, the one in Fig. The symmetrical amplifiers shown in Figure 7 prevent a reduction in electrical output power and efficiency, even if the load impedance Z0 changes. Example 3.

[0123] In embodiment 3, a symmetrical amplifier is described in which the signal divider circuit 2 contains a 90-degree hybrid circuit 9.

[0124] Fig. Figure 8 is a block diagram showing the symmetrical amplifier according to embodiment 3. It should be noted that in Fig. 8 the same reference symbols as in Fig. 1. Designate identical or corresponding parts, so that a detailed description of these parts is unnecessary.

[0125] The 90-degree hybrid circuit 9 includes a first terminal 9a, a second terminal 9b, a third terminal 9c and a fourth terminal 9d.

[0126] The first terminal 9a is an input terminal to which a high-frequency signal, which is a gain target signal, is applied, and the second terminal 9b is an isolation terminal which is grounded via a resistor.

[0127] The third terminal 9c is an output terminal that outputs a first signal, and the fourth terminal 9d is an output terminal that outputs a second signal.

[0128] When the high-frequency signal is applied to the first terminal 9a, the 90-degree hybrid circuit 9 splits the high-frequency signal into two signals.

[0129] The 90-degree hybrid circuit 9 outputs the first signal as one of the two split signals from the third terminal 9c to the first amplifier 3 and outputs the second signal as the other of the two split signals from the fourth terminal 9d to the input phaser circuit 5.

[0130] At the in Fig. The symmetrical amplifier shown in Figure 8 is combined with the 90-degree hybrid circuit in Figure 9. Fig. The symmetrical amplifier shown in Figure 1 is used. However, this is only one example, and the 90-degree hybrid circuit 9 can also be applied to the circuit shown in Figure 1. Fig. The symmetrical amplifiers shown in the 7 diagrams are used.

[0131] Also in the Fig. In the 8 symmetrical amplifiers shown, the input phase circuit 5 changes the phase of the second signal output at the fourth terminal 9d of the 90-degree hybrid circuit 9 such that the phase of the first signal amplified by the first amplifier 3 and the phase of the second signal amplified by the second amplifier 6 are in phase at the third terminal 7c of the synthesis circuit 7.

[0132] More precisely, if the phase of the first signal, which is amplified by the third terminal 7c, is θ1, and in a case where the input phaser 5 is not present, the phase of the second signal, which is amplified by the third terminal 7c, is θ1, and the phase, which is delayed by the input phaser 5, is θ3, then the phase θ3, which is delayed by the input phaser 5, is expressed, for example, by equation (1) or equation (2).

[0133] Even the symmetrical amplifier, in which the signal divider circuit 2 contains the 90-degree hybrid circuit 9, can suppress a reduction in electrical output power and efficiency, even if the load impedance Z0 is similar to that in the Fig. The symmetrical amplifier shown in 1 changes. Example 4.

[0134] In embodiment 4, a symmetrical amplifier is described in which the signal divider circuit 2 contains a Wilkinson divider circuit 10.

[0135] Fig. Figure 9 is a block diagram showing the symmetrical amplifier according to embodiment 4. It should be noted that in Fig. 9 the same reference symbols as in Fig. 1. Identical or corresponding parts are designated, therefore a detailed description is omitted.

[0136] The Wilkinson divider circuit 10 comprises a first terminal 10a, a second terminal 10b and a third terminal 10c.

[0137] The first terminal 10a is an input terminal to which a high-frequency signal, which is a gain target signal, is applied.

[0138] The second terminal 10b is an output terminal that outputs a first signal, and the third terminal 10c is an output terminal that outputs a second signal.

[0139] When the high-frequency signal is applied to the first terminal 10a, the Wilkinson divider circuit 10 splits the high-frequency signal into two signals.

[0140] The Wilkinson divider circuit 10 outputs the first signal as one of the two split signals from the second terminal 10b to the first amplifier 3 and the second signal as the other of the two split signals from the third terminal 10c to the input phaser circuit 5.

[0141] At the in Fig. The Wilkinson divider circuit 10 is applied to the symmetrical amplifier shown in 9. Fig. The symmetrical amplifier shown in Figure 1 is applied. However, this is only one example, and the Wilkinson divider circuit 10 can also be applied to the circuit shown in Figure 1. Fig. The symmetrical amplifiers shown in the 7 diagrams are used.

[0142] Also in the Fig. In the 9 symmetrical amplifiers shown, the input phase circuit 5 changes the phase of the second signal, which is output at the third terminal 10c of the Wilkinson divider circuit 10, such that the phase of the first signal, which is amplified by the first amplifier 3, and the phase of the second signal, which is amplified by the second amplifier 6, are in phase at the third terminal 7c of the synthesis circuit 7.

[0143] More precisely, if the phase of the first signal, which is amplified by the third terminal 7c, is θ1, and in the case where the input phaser 5 is not present, the phase of the second signal, which is amplified by the third terminal 7c, is θ2, and the phase, which is delayed by the input phaser 5, is θ3, then the phase θ3, which is delayed by the input phaser 5, can be expressed, for example, by equation (1) or equation (2).

[0144] Even the symmetrical amplifier, in which the signal divider circuit 2 contains the Wilkinson divider circuit 10, can suppress a reduction in electrical output power and efficiency, even if the load impedance Z0 is similar to that in the Fig. The symmetrical amplifier shown in 1 changes. Example 5.

[0145] In embodiment 5, a symmetrical amplifier is described which includes a third amplifier 11 and a fourth amplifier 12.

[0146] Fig. Figure 10 is a block diagram showing the symmetrical amplifier according to embodiment 5. It should be noted that in Fig. 10 the same reference symbols as in Fig. 1. Identical or corresponding parts are designated, therefore a detailed description is omitted.

[0147] The in Fig. The 10 symmetrical amplifiers shown comprise the signal input terminal 1, the signal divider circuit 2, the third amplifier 11, the first amplifier 3, the output phaser circuit 4, the input phaser circuit 5, the fourth amplifier 12, the second amplifier 6, the synthesis circuit 7 and the signal output terminal 8.

[0148] The third amplifier 11 is implemented, for example, as a semi-discrete amplifier in a high-frequency package or as an MMIC amplifier on a semiconductor substrate.

[0149] The third amplifier 11 is connected in series with the first amplifier 3. In the case of the Fig. In the symmetrical amplifier shown in Figure 10, the third amplifier 11 is connected to an input side of the first amplifier 3. However, this is only an example, and the third amplifier 11 can be connected to the output side of the first amplifier 3. When the third amplifier 11 is connected to the output side of the first amplifier 3, the output impedance of the third amplifier 11 is matched to the impedance of the first.

[0150] The third amplifier 11 amplifies the first output signal of the second terminal 2b of the signal divider circuit 2.

[0151] The third amplifier 11 outputs the amplified first signal to the first amplifier 3.

[0152] The fourth amplifier 12 is implemented, for example, as a semi-discrete amplifier in a high-frequency package or as an MMIC amplifier on a semiconductor substrate.

[0153] The fourth amplifier 12 is connected in series with the second amplifier 6. In the case of the Fig. In the symmetrical amplifier shown in Figure 10, the fourth amplifier 12 is connected to the input side of the second amplifier 6. However, this is only an example, and the fourth amplifier 12 can also be connected to the output side of the second amplifier 6. When the fourth amplifier 12 is connected to the output side of the second amplifier 6, the output impedance of the fourth amplifier 12 is matched to the impedance of the second amplifier 6.

[0154] The fourth amplifier 12 amplifies the second signal output by the input phaser 5.

[0155] The fourth amplifier 12 outputs the amplified second signal to the second amplifier 6.

[0156] At the in Fig. Of the symmetrical amplifiers shown in 10, the third amplifier 11 and the fourth amplifier 12 are connected to the ones shown in Fig. The symmetrical amplifier shown in 1 is connected. However, this is only an example, and the third amplifier 11 and the fourth amplifier 12 can also be used for the one shown in Fig. The symmetrical amplifiers shown in the diagram are used.

[0157] Even in the case where the symmetrical amplifier includes the third amplifier 11, which is connected in series with the first amplifier 3, and the fourth amplifier 12, which is connected in series with the second amplifier 6, the symmetrical amplifier can suppress a reduction in electrical output power and efficiency, even if the load impedance Z0 is similar to that in the Fig. The symmetrical amplifier shown in 1 changes. Example 6.

[0158] In embodiment 6, a symmetrical amplifier is described which includes a fifth amplifier 13.

[0159] Fig. Figure 11 is a block diagram showing the symmetrical amplifier according to embodiment 6. It should be noted that in Fig. 11 the same reference symbols as in Fig. 1. Identify identical or corresponding parts, so that a detailed description is omitted.

[0160] The in Fig. The symmetrical amplifier shown in Figure 11 includes the signal input terminal 1, the fifth amplifier 13, the signal divider circuit 2, the first amplifier 3, the output phaser circuit 4, the input phaser circuit 5, the second amplifier 6, the synthesis circuit 7 and the signal output terminal 8.

[0161] The fifth amplifier 13 is implemented, for example, as a semi-discrete amplifier in a high-frequency package or as an MMIC amplifier on a semiconductor substrate.

[0162] The fifth amplifier 13 amplifies a high-frequency signal, which is a target gain signal, that is fed to the signal input terminal 1.

[0163] The fifth amplifier 13 outputs the amplified high-frequency signal to the first terminal 2a of the signal divider circuit 2.

[0164] At the in Fig. The fifth amplifier 13 is connected to the symmetrical amplifier shown in 11. Fig. 1. The symmetrical amplifier shown is connected. However, this is only one example, and the fifth amplifier 13 can also be used for the one shown in Fig. The symmetrical amplifiers shown in the diagram are used.

[0165] Even in the case where the symmetrical amplifier includes the fifth amplifier 13, the symmetrical amplifier can suppress a reduction in electrical output power and efficiency, even if the load impedance Z0 behaves similarly to that in the Fig. The symmetrical amplifier shown in 1 changes. Example 7.

[0166] In embodiment 7, a symmetrical amplifier is described which includes a sixth amplifier 14.

[0167] Fig. Figure 12 is a block diagram showing the symmetrical amplifier according to embodiment 7. It should be noted that in Fig. 12 the same reference symbols as in Fig. 1. Identify identical or corresponding parts, so that a detailed description is omitted.

[0168] The in Fig. The symmetrical amplifier shown comprises the signal input terminal 1, the signal divider circuit 2, the first amplifier 3, the sixth amplifier 14, the output phaser circuit 4, the input phaser circuit 5, the second amplifier 6, the synthesis circuit 7 and the signal output terminal 8.

[0169] The sixth amplifier 14 is implemented, for example, as a semi-discrete amplifier in a high-frequency package or as an MMIC amplifier on a semiconductor substrate.

[0170] The sixth amplifier 14 is connected in parallel to the first amplifier 3.

[0171] The sixth amplifier 14 amplifies the first output signal of the second terminal 2b of the signal divider circuit 2.

[0172] The sixth amplifier 14 outputs the amplified first signal to the output phase circuit 4.

[0173] When the first amplifier 3 and the sixth amplifier 14 are connected in parallel, the output impedance of the first amplifier 3 and the output impedance of the sixth amplifier 14 are each matched to the first impedance.

[0174] At the in Fig. In the symmetrical amplifier shown in Figure 12, the sixth amplifier 14 is connected in parallel to the first amplifier 3. However, this is only an example, and the sixth amplifier 14 can be connected in parallel to the second amplifier 6. When the second amplifier 6 and the sixth amplifier 14 are connected in parallel, the output impedance of the second amplifier 6 and the output impedance of the sixth amplifier 14 are each matched to the second impedance.

[0175] At the in Fig. The sixth amplifier, 14, is located on the symmetrical amplifier shown in 12. Fig. The symmetrical amplifier shown in 1 is used. However, this is only one example, and the sixth amplifier 14 can also be used for the one shown in Fig. The symmetrical amplifiers shown in the diagram are used.

[0176] Even in the case where the symmetrical amplifier includes the sixth amplifier 14, the symmetrical amplifier can suppress a reduction in electrical output power and efficiency, even if the load impedance Z0 is similar to that in the Fig. The symmetrical amplifier shown in 1 changes.

[0177] In the symmetrical amplifiers according to embodiments 1 to 7, the output impedance of the first amplifier 3 is matched to the first impedance, and the output impedance of the second amplifier 6 is matched to the second impedance. However, this is only an example, and the output matching circuit 3c and the output matching circuit 6c can be configured as adjustable matching circuits such that the output impedance of the first amplifier 3 is matched to the first impedance, which corresponds to the load impedance Z0 before the change, and the output impedance of the second amplifier 6 is matched to the second impedance, which corresponds to the load impedance Z0 before the change.

[0178] For example, if the load impedance Z0 before the modification is 60 Ω, the output matching circuit 3c is adjusted so that the output impedance of the first amplifier 3 is greater than 60 Ω, and the output matching circuit 6c is adjusted so that the output impedance of the second amplifier 6 is less than 60 Ω. If the load impedance Z0 before the modification is 70 Ω, the output matching circuit 3c is adjusted so that the output impedance of the first amplifier 3 is greater than 70 Ω, and the output matching circuit 6c is adjusted so that the output impedance of the second amplifier 6 is less than 70 Ω.

[0179] It should be noted that the present disclosure permits free combinations of the embodiments, changes to the components of the embodiments, or the omission of components of the embodiments. COMMERCIAL APPLICABILITY

[0180] The present disclosure is suitable for a symmetrical amplifier. REFERENCE MARK LIST

[0181] 1: Signal input terminal, 2: Signal distribution circuit, 2a: First terminal, 2b: Second terminal, 2c: Third terminal, 3: First amplifier, 3a: Input matching circuit, 3b: First gain element, 3c: Output matching circuit, 4: Output phaser circuit, 5: Input phaser circuit, 6: Second amplifier, 6a: Input matching circuit, 6b: Second gain element, 6c: Output matching circuit, 7: Synthesis circuit, 7a: First terminal, 7b: Second terminal, 7c: Third terminal, 7d: Fourth terminal, 8: Signal output terminal, 9: 90-degree hybrid circuit, 9a: First terminal, 9b: Second terminal, 9c: Third terminal, 9d: Fourth terminal, 10: Wilkinson divider circuit, 10a: First terminal, 10b: Second terminal 10c: Third connection, 11: Third amplifier, 12: Fourth amplifier, 13: Fifth amplifier, 14: Sixth amplifier QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2013-236144 A

[0005]

Claims

[1] Symmetrical amplifier comprising: a signal divider circuit to split an amplification target signal into two split signals, including a first signal and a second signal, and to output the first signal and the second signal; a first amplifier to amplify the first signal output by the signal divider circuit; a second amplifier to amplify the second output signal of the signal divider circuit; and a synthesis circuit for synthesizing the first signal, amplified by the first amplifier, and the second signal, amplified by the second amplifier, wherein The first amplifier contains a first matching circuit to match the output impedance of the first amplifier to a first impedance that differs from the impedance of a load connected to an output side of the synthesis circuit. The second amplifier contains a second matching circuit to match the output impedance of the second amplifier to a second impedance that differs from the impedance of the load, and One impedance is higher than the impedance of the load, and another impedance is lower than the impedance of the load. [2] Symmetrical amplifier according to claim 1, wherein An output phase circuit with an electrical length of 90 degrees is provided between the first amplifier and the synthesis circuit, and An input phase circuit is provided between the signal divider circuit and the second amplifier, wherein the input phase circuit performs a phase shift of a phase of the second signal output by the signal divider circuit in such a way that a phase of the first signal amplified by the first amplifier and the phase of the second signal amplified by the second amplifier are in phase at a point in the synthesis circuit of the first signal amplified by the first amplifier and the second signal amplified by the second amplifier. [3] Symmetrical amplifier according to claim 2, wherein the first amplifier comprises a first amplification element to amplify the first signal output by the signal divider circuit, and an output matching circuit for matching an output impedance of the first amplifying element to the first impedance, wherein the output matching circuit is the first matching circuit and one end is connected to an output side of the first amplifying element and another end to an input side of the output phaser, and the second amplifier includes a second amplification element to amplify the second signal, which is subject to the phase shift introduced by the input phase circuit, and an output matching circuit for matching an output impedance of the second amplification element to the second impedance, wherein the output matching circuit is the second matching circuit and one end is connected to an output side of the second amplification element and another end to an input side of the synthesis circuit. [4] Symmetrical amplifier according to claim 1, wherein An output phase circuit with an electrical length of 90 degrees is provided between the second amplifier and the synthesis circuit, and An input phase circuit is provided between the signal divider circuit and the first amplifier, wherein the input phase circuit performs a phase shift of the phase of the first signal output by the signal divider circuit such that the phase of the first signal amplified by the first amplifier and a phase of the second signal amplified by the second amplifier are in phase at a point in the synthesis circuit of the first signal amplified by the first amplifier and the second signal amplified by the second amplifier. [5] Symmetrical amplifier according to claim 4, wherein the first amplifier comprises a first amplification element to amplify the first signal, which is subject to the phase shift performed by the input phase circuit, and an output matching circuit for matching an output impedance of the first amplification element to the first impedance, wherein the output matching circuit is the first matching circuit and one end is connected to an output side of the first amplification element and another end to an input side of the synthesis circuit, and the second amplifier includes a second amplification element to amplify the second output signal of the signal divider circuit, and an output matching circuit for matching an output impedance of the second amplifying element to the second impedance, wherein the output matching circuit is the second matching circuit and one end is connected to an output side of the second amplifying element and another end to an input side of the output phase circuit. [6] Symmetrical amplifier according to claim 1, wherein The synthesis circuit contains a 90-degree hybrid circuit that includes: a first connection to which the first signal, amplified by the first amplifier, is supplied, a second connection to which the second signal, amplified by the second amplifier, is supplied; and a third connection for outputting a synthesis signal from the first signal, amplified by the first amplifier, and the second signal, amplified by the second amplifier. [7] Symmetrical amplifier according to claim 1, wherein The signal divider circuit contains a 90-degree hybrid circuit that includes: a first connection to which the amplification target signal is fed; a second terminal for outputting the first signal, which is one of the two split signals; and a third connection for the output of the second signal, which is one of the two split signals. [8] Symmetrical amplifier according to claim 1, wherein The signal divider circuit contains a Wilkinson divider circuit, which includes: a first connection to which the amplification target signal is fed; a second terminal for outputting the first signal, which is one of the two split signals; and a third connection for the output of the second signal, which is one of the two split signals. [9] Symmetrical amplifier according to claim 1, further comprising: a third amplifier connected in series with the first amplifier; and a fourth amplifier, which is connected in series with the second amplifier. [10] Symmetrical amplifier according to claim 1, further comprising a fifth amplifier for amplifying the target gain signal and for outputting the amplified target gain signal to the signal divider circuit. [11] Symmetrical amplifier according to claim 1, further comprising a sixth amplifier connected in parallel to one of the first and second amplifiers.

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