PIXEL CIRCUITS, THEIR DRIVE METHODS AND DISPLAY PANELS

Abstract

A pixel circuit, its drive methods and display panels, wherein the pixel circuit comprises a driver module, a signal source, a compensation module and a coupling module, wherein the compensation module is configured to compensate for the threshold voltage of the driver module in the compensation phase; wherein the signal source provides a fixed voltage to the coupling module in the initialization phase and provides a data voltage to the coupling module in the data write phase, wherein the coupling module is configured to couple the voltage with the information of the data voltage via the compensation module to the control terminal of the driver module, wherein the data write phase occurs after the compensation phase.

Description

[0001] The present application claims the priority right of the Chinese patent application filed with the Chinese Patent Office on May 31, 2023, under application number 202310637058.6, and the priority right of the patent application filed with the Chinese Patent Office on September 28, 2023, under application number 202311282413.9. The entire content of the aforementioned applications is incorporated into this application by reference. Technical field

[0002] The present application relates to the field of display technology, in particular pixel switching, its drive methods and display panels. State of the art

[0003] As display technology continues to develop, the demands on display quality are constantly increasing.

[0004] A display panel typically comprises several pixel circuits, each containing a driver transistor that generates a driver signal to excite the light source to emit light. However, display panels often suffer from display irregularities that significantly impair image quality. Content of the present invention

[0005] The embodiment of the present application provides a pixel circuit, its drive methods and display panels to improve the display quality.

[0006] According to one aspect of the present application, a pixel circuit is provided, comprising: a driver module, a signal source, a compensation module and a coupling module; wherein the compensation module is configured to compensate for the threshold voltage of the driver module during the compensation phase; wherein the signal source provides a fixed voltage to the coupling module during the initialization phase and supplies a data voltage to the coupling module during the data write phase, wherein the coupling module is configured to couple the voltage with the data voltage information via the compensation module to the control terminal of the driver module, wherein the data write phase occurs after the compensation phase.

[0007] According to another aspect of the present application, a pixel circuit is provided, comprising: a driver module, a signal source, a compensation module and a coupling module; wherein the compensation module is connected between the control terminal and the first terminal of the driver module and is configured to compensate for the threshold voltage of the driver module; wherein the coupling module is connected between the first terminal of the driver module and the signal source, wherein the signal source is configured to provide a fixed voltage and a data voltage, and wherein the coupling module is configured to couple the voltage containing the data voltage information to the control terminal of the driver module via the compensation module.

[0008] According to another aspect of the present application, a pixel circuit is provided, comprising: a driver module, a voltage writing module, a compensation module and a coupling module; wherein the compensation module is connected between the control terminal and the first terminal of the driver module and is configured to compensate for the threshold voltage of the driver module; wherein the coupling module is connected between the first terminal of the driver module and the voltage write module, wherein the voltage write module is configured to output a fixed voltage and a data voltage to the coupling module, wherein the coupling module is configured to couple the voltage containing the data voltage information to the control terminal of the driver module via the compensation module.

[0009] According to another aspect of the present application, a pixel circuit is provided, comprising: a driver module, a data write module, a first initialization module, a compensation module and a coupling module; wherein the compensation module is connected between the control terminal and the first terminal of the driver module and is configured to compensate for the threshold voltage of the driver module; where the data write module and the first initialization module are connected to the first node; wherein the coupling module is connected between the first terminal of the driver module and the first node, wherein the first initialization module is configured to transmit a fixed voltage to the coupling module, wherein the coupling module is configured to couple the voltage transmitted by the data write module with information of the data voltage via the compensation module to the control terminal of the driver module.

[0010] According to another aspect of the present application, a pixel-switching drive method is provided, comprising: where a fixed voltage is applied to the coupling module during the initialization phase; wherein in the compensation phase the compensation module is controlled to compensate the threshold voltage of the driver module; wherein in the data writing phase a data voltage is supplied to the coupling module, whereby the coupling module is controlled to couple the voltage with the information of the data voltage via the compensation module to the control terminal of the driver module.

[0011] The technical solution presented in this application involves scheduling the data write phase after the compensation phase, thus preventing the threshold compensation of the driver module and the data write from occurring simultaneously. Threshold compensation is performed before the data voltage is written to the control pin of the driver module, ensuring that the compensation and data write phases do not interfere with each other. This prevents the data write phase from affecting the time available for threshold compensation. Even at high refresh rates, the threshold voltage of the driver module can be fully compensated, reducing differences in the characteristics of the driver modules of different pixels. This contributes to improved brightness variations and increased uniformity of image quality.

[0012] It should be understood that the content described in this section is neither intended to identify the essential or important features of the embodiments of this application, nor to limit the scope of this application. Further features of this application are made easily understandable by the following description. Illustration of the attached figures Fig. 1 is a signal flow diagram of a pixel circuit provided by an embodiment of the present application; Fig. 2 is a signal flow diagram of another pixel circuit provided by an embodiment of the present application; Fig. 3 is a signal flow diagram of another pixel circuit provided by an embodiment of the present application; Fig. Figure 4 is a schematic representation of the structure of a pixel circuit provided by an embodiment of the present application; Fig. Figure 5 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application; Fig. Figure 6 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application; Fig. 7 is a schematic diagram of the drive timing sequence of a pixel circuit provided by an embodiment of the present application; Fig. Figure 8 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application; Fig. Figure 9 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application; Fig. 10 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application; Fig. 11 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application; Fig. Figure 12 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application; Fig. 13 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application; Fig. 14 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application; Fig. 15 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application; Fig. Figure 16 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application; Fig. 17 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application; Fig. Figure 18 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application; Fig. Figure 19 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application; Fig. 20 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application; Fig. Figure 21 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application; Fig. 22 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application; Fig. Figure 23 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application; Fig. 24 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application; Fig. Figure 25 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application; Fig. 26 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application; Fig. 27 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application; Fig. 28 is a flowchart of a drive method of a pixel circuit provided by an embodiment of the present application; Fig. 29 is a flowchart of a driving procedure of another pixel circuit provided by an embodiment of the present application; Fig. 30 is a flowchart of a drive method of another pixel circuit provided by an embodiment of the present application; Fig. Figure 31 is a schematic representation of the structure of a display panel provided by an embodiment of the present application. Specific embodiments

[0013] As described in the prior art, display panels experience image quality problems. The inventors have determined that the cause lies in the fact that the driver transistors in the pixel circuits exhibit a threshold voltage shift due to their inherent characteristics. Since the threshold shift of the driver transistors varies in magnitude across different pixel circuits, this leads to differences in the driver current, which in turn causes uneven display and a reduction in display homogeneity. Threshold compensation is typically employed to minimize the effects of the driver transistor threshold shift. However, the compensation time is either too short to completely compensate for the driver transistor threshold voltage, or compensation losses occur due to potential coupling.As a result, the overall compensation effectiveness is low, and problems such as poor brightness homogeneity and pronounced afterimages persist.

[0014] To solve the aforementioned problem, the present application provides a pixel circuit. Fig. 1 is a signal flow diagram of a pixel circuit provided by an embodiment of the present application, wherein in Fig. 1. Only the signal flow directions between the modules are shown and do not represent any connection relationships. With reference to Fig. 1 The pixel circuit provided in the embodiment of the present application comprises a driver module 110, a signal source, a compensation module 130 and a coupling module 140; wherein the compensation module 130 is configured to compensate the threshold voltage Vth1 of the driver module 110 during the compensation phase; wherein the signal source provides a fixed voltage Vcom to the coupling module 140 during the initialization phase and supplies a data voltage to the coupling module 140 during the data write phase, wherein the coupling module 140 is configured to couple the voltage with the information of the data voltage Vdata via the compensation module 130 to the control terminal of the driver module 110, wherein the data write phase occurs after the compensation phase.

[0015] In particular, the working process of the pixel circuit provided in this embodiment includes at least a compensation phase and a data writing phase.

[0016] During the compensation phase, the signal source supplies a fixed voltage Vcom to the first terminal of the coupling module 140, so that the voltage at the first terminal of the coupling module 140 remains constant. The compensation module 130 transfers the voltage at the first terminal of the driver module 110 to the control terminal of the driver module. The driver module 110 generates a current that flows from the first terminal to the second terminal until the voltage difference between the control terminal and the second terminal of the driver module 110 equals the threshold voltage Vth of the driver module 110, at which point the driver module 110 is switched off.A voltage associated with the threshold voltage Vth of the driver module 110 is stored at the second terminal of the coupling module 140, and the compensation module 130 transfers this voltage to the control terminal of the driver module 110, so that the voltage at the control terminal of the driver module 110 corresponds to the voltage associated with its threshold voltage Vth, thereby realizing a threshold compensation of the driver module 110.

[0017] During the data write phase, the signal source supplies the data voltage Vdata to the first terminal of the coupling module 140. The voltage at the first terminal of the coupling module 140 switches from the fixed voltage Vcom to the data voltage Vdata. The coupling module 140 couples the voltage containing the data voltage Vdata information to the control terminal of the driver module 110 via the compensation module 130, so that the voltage at the control terminal of the driver module 110 is correlated with the data voltage Vdata, thus enabling data writing. The voltage containing the data voltage Vdata information can be defined as the difference between the data voltage Vdata and the fixed voltage Vcom.

[0018] In this embodiment, the data write phase occurs after the compensation phase. This means that the threshold compensation of the driver module and the data write do not happen simultaneously. The threshold compensation is performed before the data voltage is written to the control terminal of the driver module, thus preventing the compensation and data write phases from interfering with each other. As a result, the time required for threshold compensation is not affected by the data write phase. Even at high refresh rates, the threshold voltage of the driver module can be fully compensated, which reduces the differences in the characteristics of the driver modules of different pixels and thus contributes to improved brightness variations and increased uniformity of image quality.

[0019] In this embodiment, the data write phase occurs after the compensation phase, thus completely separating the two. This prevents the compensation and data write phases from influencing each other, ensuring that the time for threshold compensation is not limited by the line time.

[0020] Fig. 2 is a signal flow diagram of another pixel circuit provided by an embodiment of the present application. With reference to Fig. 2 The pixel circuit based on the above technique further optionally includes a second initialization module 180, wherein the second initialization module 180 is configured to discharge the first terminal of the driver module 110 via the driver module 110 and the second initialization module 180 during the compensation phase, wherein the compensation module 130 is configured to compensate the threshold voltage Vth of the driver module 110 during the compensation phase based on the voltage measured after the discharge of the first terminal of the driver module 110.

[0021] The second initialization module 180 is switched on during the compensation phase and provides a discharge path for discharging the driver module 110. Specifically, the control terminal of the driver module 110 is connected to the first terminal, with the first terminal of the driver module 110 discharging through the driver module 110 and the second initialization module 180 until the voltage difference between the control terminal and the second terminal of the driver module 110 equals the threshold voltage Vth of the driver module 110. The driver module 110 is then switched off, thus completing the compensation of the threshold voltage of the driver module 110.

[0022] With reference to Fig. 2 The pixel circuit further includes a light module 150. The second initialization module 180 also serves to transfer an initialization voltage Vref to the light module 150 at least during the initialization phase in order to initialize the residual voltage remaining on the light module 150.

[0023] Fig. 3 is a signal flow diagram of another pixel circuit provided by an embodiment of the present application. With reference to Fig. 3 The pixel circuit based on the above technical scheme optionally further includes a first lighting control module 161 and a second lighting control module 162. The first lighting control module 161 serves to transmit the first supply voltage VDD to the first terminal of the driver module 110 during the initialization phase and the lighting phase, and to stop the transmission of the first supply voltage VDD to the first terminal of the driver module 110 during the compensation phase, so that the voltage stored at the first terminal of the driver module 110 can be discharged via the driver module 110 and the second initialization module 180.

[0024] The second lighting control module 162 serves to transfer the voltage at the first terminal of the driver module 110 to the second initialization module 180 during the compensation phase in order to perform a discharge; wherein the second lighting control module 162 is further configured to transfer the driver current I generated by the driver module 110 to the lighting module 150 during the lighting phase in order to make the lighting module 150 light up.

[0025] In a further alternative embodiment provided in the present application, Fig. 4 A schematic representation of the structure of a pixel circuit provided by an embodiment of the present application. With reference to Fig. Figure 4 of the pixel circuit provided in this embodiment comprises a driver module 110, a signal source, a compensation module 130, and a coupling module 140. The compensation module 130 is connected between the control terminal G and the first terminal D of the driver module 110 and serves to compensate the threshold voltage Vth of the driver module 110. The coupling module 140 is connected between the first terminal D of the driver module 110 and the signal source. The signal source provides a fixed voltage Vcom and a data voltage Vdata. The coupling module 140 couples the voltage containing the data voltage Vdata information to the control terminal G of the driver module 110 via the compensation module 130.

[0026] Using the example of the in Fig. The working process of the pixel circuit shown in Figure 4 includes at least the initialization phase, the compensation phase, the data writing phase and the illumination phase.

[0027] During the initialization phase, the compensation module 130 is switched on, the first supply voltage VDD initializes the first terminal D and the control terminal G of the driver module 110. At the same time, the signal supply source provides a fixed voltage Vcom to the first terminal of the coupling module 140 to initialize the first terminal of the coupling module 140.

[0028] During the compensation phase, the compensation module 130 remains continuously conductive. The compensation module 130 connects the control terminal G and the first terminal D of the driver module 110. Under the influence of the first supply voltage VDD, the driver module 110 generates a current that flows from the first terminal D to the second terminal S until the voltage difference between the control terminal G and the second terminal S of the driver module 110 equals the threshold voltage Vth of the driver module 110, at which point the driver module 110 switches off. Consequently, the voltage at the control terminal G of the driver module 110 corresponds to the voltage associated with its threshold voltage Vth, thus achieving threshold compensation of the driver module 110. During this process, the signal source continues to supply the fixed voltage Vcom.

[0029] During the data write phase, the signal source supplies the data voltage Vdata to the first terminal of the coupling module 140. The voltage at the first terminal of the coupling module 140 switches from the fixed voltage Vcom to the data voltage Vdata. The coupling module 140 couples the voltage associated with the data voltage Vdata to the control terminal of the driver module 110 via the compensation module 130, so that the voltage at the control terminal G of the driver module 110 is correlated with the data voltage Vdata and the data write operation is performed.

[0030] During the illumination phase, the driver module 110 generates a driver current according to the voltage at its control terminal G, which makes the lighting module 150 light up.

[0031] In this embodiment of the present application, a compensation module is switched to conduction during the compensation phase by being arranged between the control terminal and the first terminal of the driver module. The compensation module compensates the threshold voltage of the driver module based on the voltage at the first terminal of the driver module after discharge by the driver module. During the data write phase, the signal source is controlled so that the voltage transmitted to the first terminal of the coupling module is switched from a fixed voltage to the data voltage. Via the coupling module, the data voltage is coupled to the control terminal of the driver module via the compensation module, thereby writing the data voltage. In this embodiment, the threshold compensation of the driver module and the data writing do not occur simultaneously.Threshold compensation is therefore performed before the data voltage is written to the control pin of the driver module, ensuring that the compensation phase and the data write phase do not interfere with each other. This prevents the time required for threshold compensation from being affected by the data write phase. Even at high refresh rates, the threshold voltage of the driver module can be fully compensated, reducing differences in the characteristics of the driver modules of different pixels. This contributes to improved brightness variations and increased uniformity of image quality.

[0032] Furthermore, with reference to Fig. In this embodiment, the pixel circuit optionally includes a lighting control module 160. The lighting control module 160, the driver module 110, and the lighting module 150 are connected between the first supply voltage terminal and the second supply voltage terminal. The lighting control module 160 serves to interrupt the connection between the first terminal D of the driver module 110 and the first supply voltage terminal during the compensation phase, so that the voltage at the first terminal D of the driver module 110 can be discharged through the driver module 110. Of course, in other embodiments, the lighting control module 160 can be omitted between the first terminal D of the driver module 110 and the first supply voltage terminal.The voltage at the first terminal D of the driver module 110 can instead be controlled by controlling the application of the first supply voltage VDD at the first supply voltage terminal, which achieves the same effect.

[0033] Optionally, the pixel circuit further includes a second initialization module 180, wherein the second initialization module 180 is connected between the initialization signal line and the first terminal of the light module 150 and serves to initialize the potential at the first terminal of the light module 150. During the compensation phase, it also controls the line of the second initialization module 180 to provide a discharge path to the first terminal D of the driver module 110.

[0034] In particular, the second initialization module 180 serves to transmit the initialization voltage Vref to the first terminal of the lighting module 150 during the initialization phase, in order to initialize the potential at the first terminal of the lighting module 150. The initialization voltage Vref is below the ignition voltage of the lighting module 150; for example, the initialization voltage Vref can be a negative voltage. During the compensation phase, the second initialization module 180 and the compensation module 130 maintain the line state, connecting the control terminal G and the first terminal D of the driver module 110. The voltage at the first terminal D of the driver module 110 is discharged via the driver module 110 and the second initialization module 180 until the voltage between control terminal G and first terminal D of the driver module 110 reaches Vref+Vth. Then the driver module 110 switches off.This not only completes the compensation of the threshold voltage of the driver module 110, but also the initialization of the control terminal G of the driver module 110. Furthermore, by maintaining the potential at the first terminal of the lighting module 150 at the initialization voltage Vref during the initialization and compensation phases, the lighting module 150 is prevented from exhibiting "unintentional illumination" in the non-illumination phase.

[0035] In the specific embodiment described in the present application, Fig. 5 a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application. With reference to Fig. Figure 5 of the pixel circuit, based on the respective technical solutions mentioned above, optionally includes a first lighting control module 161 and a second lighting control module 162. The first lighting control module 161 is connected between the first supply voltage terminal and the first terminal D of the driver module 110. The second lighting control module 162 is connected between the second terminal S of the driver module 110 and the first terminal of the lighting module 150, with the second terminal of the lighting module 150 being connected to the second supply voltage terminal. The control terminal of the first lighting control module 161 is connected to the first lighting control signal line, and the control terminal of the second lighting control module 162 is connected to the second lighting control signal line.The first lighting control module 161 serves to be conductive at least during the lighting phase in response to the first lighting control signal EM1 on the first lighting control signal line and to be switched off during the compensation phase and the data write phase; the second lighting control module 162 serves to be conductive at least during the compensation phase and the lighting phase in response to the second lighting control signal EM2 on the second lighting control signal line.

[0036] Optionally, the pixel circuit further includes a memory module 170, wherein the memory module 170 is connected between the control terminal G of the driver module 110 and the first terminal of the light module 150 and serves to store the voltage difference between the control terminal G of the driver module 110 and the first terminal of the light module 150.

[0037] Fig. 6 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application, in particular a detailed representation of the Fig. 5 pixel circuit shown at the device level. The control terminal of the second initialization module 180 is connected to the third scan line, and the control terminal of the compensation module 130 is also connected to the third scan line. Referring to Fig. 6 The driver module 110 comprises a first transistor T1, the first lighting control module 161 comprises a fourth transistor T4, the second lighting control module 162 comprises a fifth transistor T5, the lighting module 150 comprises a light-emitting diode D1, the gate of the fourth transistor T4 is connected to the first lighting control signal line, the first terminal of the fourth transistor T4 is connected to the first supply voltage terminal, the second terminal of the fourth transistor T4 is connected to the first terminal of the first transistor T1, the second terminal of the first transistor T1 is connected to the first terminal of the fifth transistor T5, the second terminal of the fifth transistor T5 is connected to the first terminal of the light-emitting diode D1, and the second terminal of the light-emitting diode D1 is connected to the second supply voltage terminal.where the gate of the fifth transistor T5 is connected to the second light control signal line.

[0038] The coupling module 140 comprises a first capacitor C1, the compensation module 130 comprises a sixth transistor T6, and the second initialization module 180 comprises a seventh transistor T7;wherein the first electrode of the first capacitor C1 is connected to the signal source, wherein the second electrode of the first capacitor C1 is connected to the first terminal of the first transistor T1, wherein the first terminal of the sixth transistor T6 is connected to the first terminal of the first transistor T1, wherein the second terminal of the sixth transistor T6 is connected to the gate of the first transistor T1, wherein the gate of the sixth transistor T6 is connected to the third scan line, wherein the first terminal of the seventh transistor T7 is connected to the initialization signal line, wherein the second terminal of the seventh transistor T7 is connected to the first terminal of the LED D1, wherein the gate of the seventh transistor T7 is connected to the third scan line.

[0039] The storage module 170 includes a second capacitor C2, wherein the first electrode of the second capacitor C2 is connected to the control terminal of the driver module 110, and wherein the second electrode of the second capacitor C2 is connected to the first terminal of the lighting module 150.

[0040] Fig. 7 is a schematic diagram of the drive timing sequence of a pixel circuit provided by an embodiment of the present application and for which in Fig. The pixel circuit shown in section 6 is applicable. For example, all in Fig. The specific operating process of the pixel circuit provided in the present application is explained, in connection with the six transistors shown, which are N-channel types. Fig. 6 and Fig. 7 The working process of the pixel circuit provided in this embodiment comprises the initialization phase t1, the compensation phase t2, the data writing phase t3 and the illumination phase t4.

[0041] During the initialization phase t1, the third scan signal S3 is at a conducting level, for example, a high level; the first light control signal EM1 is at a conducting level, for example, a high level; and the second light control signal EM2 is at an off level, for example, a low level. Therefore, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are conducting. The signal source supplies a fixed voltage Vcom to the first electrode of the first capacitor C1. The initial supply voltage VDD is passed through the fourth transistor T4 to point D and then through the sixth transistor T6 to point G. The initialization voltage Vref is passed through the seventh transistor T7 to the second electrode of the second capacitor C2.Consequently, the voltage at the first electrode of the first capacitor C1 is Vcom, and at the second electrode is VDD; the voltage at the first electrode of the second capacitor C2 is VDD, and at the second electrode is Vref. The voltages at the first terminal and at the gate of the first transistor T1 are each VDD, thereby initializing the first capacitor C1, the second capacitor C2, and the LED D1.

[0042] During the compensation phase t2, the third scan signal S3 is at a conducting level, for example, a high level; the first light control signal EM1 is at a cut-off level, for example, a low level; and the second light control signal EM2 is at a conducting level, for example, a high level. Therefore, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are conducting. The gate and the first terminal of the first transistor T1 are short-circuited, forming a diode structure. A discharge path is created between point D and the seventh transistor T7. When the voltage at point D drops to Vref + Vth1, the first transistor T1 switches off, where Vth1 is the threshold voltage of the first transistor T1 (equivalent to the threshold voltage Vth of the driver module 110). At this point, the voltage at the gate of the first transistor T1 (point G) is also Vref + Vth1.This not only implements threshold compensation but also transfers the initialization voltage Vref to the gate of the first transistor T1, thus initializing its gate. Furthermore, during the compensation phase t2, the voltage at the first electrode of the LED D1 remains at the initialization voltage Vref to prevent the LED D1 from lighting up. The second capacitor C2 stores the gate voltage of the first transistor T1.

[0043] During the data write phase t3, the third scan signal S3 is conducting, for example, a high level; the first indicator signal EM1 is off, for example, a low level; and the second indicator signal EM2 is off, for example, a low level. Therefore, the sixth transistor T6 and the seventh transistor T7 are conducting. The signal source supplies the data voltage Vdata to the first electrode of the first capacitor C1. The voltage at the first electrode of the first capacitor C1 changes from the fixed voltage Vcom to the data voltage Vdata; the voltage change at the first electrode of the first capacitor C1 is Vdata - Vcom. Since the sixth transistor T6 is conducting, the gate voltage of the first transistor T1 is converted to Vref + Vth + c1(Vdata - Vcom) / (c1 + c2 + cgs) by coupling the first capacitor C1 and stored in the second capacitor C2.The voltage at the second electrode of the second capacitor C2 is held at the initialization voltage Vref by the holding effect of the seventh transistor T7. The voltage difference across the second capacitor C2 is Vth1 + c1(Vdata - Vcom) / (c1 + c2 + cgs).

[0044] When the third scan signal S3 transitions from a conducting level to a switched-off level, it capacitively affects the gate of the first transistor T1, lowering the gate voltage of the first transistor T1 and promoting the maintenance of a low potential at the gate of the first transistor T1. This prevents a loss of threshold compensation and avoids a voltage drop at the gate of the driver transistor due to potential coupling.

[0045] During the illumination phase t4, the third scan signal S3 is at a switched-off level, for example, a low level; the first illumination control signal EM1 is at a conducting level, for example, a high level; and the second illumination control signal EM2 is at a conducting level, for example, a high level. Therefore, the fourth transistor T4 and the fifth transistor T5 are conducting. The first supply voltage VDD is transmitted to point D via the fourth transistor T4. Since the sixth transistor T6 is in the switched-off state, the gate voltage of the first transistor T1 does not change. The first transistor T1 generates the drive current I, corresponding to the voltage at its gate and at point D, which illuminates the LED D1. The drive current I can be represented as: I=12μCoxWL(Vgs−Vth1)2=12μCoxWL[Vth1+c1(Vdata−Vcom) / (c1+c2+cgs)−Vth1]2=12μCoxW2L[c1(Vdata−Vcom) / (c1+c2+cgs)]2∘

[0046] Here, µ denotes the electron mobility of the first transistor T1, Cox the channel capacitance per unit area of ​​the first transistor T1, W / L the width-to-length ratio of the first transistor T1, Vth1 the threshold voltage of the first transistor T1, c1 the capacitance of the first capacitor C1, c2 the capacitance of the second capacitor C2, and cgs the parasitic capacitance between the gate of the first transistor T1 and the second terminal.

[0047] According to the formula for the driver current I, the driver current I is independent of the first supply voltage VDD, the second supply voltage VSS, and the threshold voltage Vth1 of the first transistor T1. Therefore, the pixel circuit provided in this embodiment can compensate for display irregularities caused by the threshold voltage of the first transistor T1 and by voltage drops (IR drops) across the first supply voltage VDD and the second supply voltage VSS, thus improving display quality. Since the data write phase t3 occurs after the compensation phase t2, it is completely separated from the compensation phase t2. This prevents the compensation phase t2 and the data write phase t3 from interfering with each other, meaning the time for threshold compensation is not limited by the line time, thus improving compensation efficiency.

[0048] Optionally, the display panel can be operated at either a low or high refresh rate. The low refresh rate is achieved through frame skipping based on the high refresh rate. A display cycle comprises write frames and hold frames. For example, at a refresh rate of 120 Hz, all 120 data frames consist of write frames, with data being written in each write frame. At a refresh rate of 1 Hz, however, one data frame is used as a write frame based on 120 Hz, while the remaining data frames function as hold frames. Data is only written in the write frames, not in the hold frames, making the pixel circuit suitable for low-frequency operation.

[0049] Fig. Figure 8 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application. The difference to the one in Fig. The difference in the pixel circuit shown in Figure 6 is that the signal line connected to the gate of the sixth transistor T6 is different. Referring to Fig. At point 8, the gate of the sixth transistor T6 is connected to the first scan line to receive the first scan signal S1 output by the first scan line. By configuring the sixth transistor T6 and the seventh transistor T7 with different signal lines, the pixel circuit can operate under low-frequency conditions while simultaneously achieving a high-frequency reset of the first electrode of the LED D1, thus improving the low-frequency flicker phenomenon.

[0050] Fig. 9 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application and for which in Fig. The pixel circuit shown in section 8 is applicable. With reference to Fig. 8 and Fig. 9 The work process of the pixel circuit provided in this embodiment comprises the following: In the write frame during the initialization phase t1, the first scan signal S1 is at a conducting level, for example, a high level; the third scan signal S3 is at a conducting level, for example, a high level; the first light control signal EM1 is at a conducting level, for example, a high level; and the second light control signal EM2 is at an off level, for example, a low level. This corresponds to the operating process of the drive timing sequence in the initialization phase t1 according to the Fig. 7.

[0051] During the compensation phase t2, the first scan signal S1 is at a conducting level, for example, a high level; the third scan signal S3 is at a conducting level, for example, a high level; the first light control signal EM1 is at a switched-off level, for example, a low level; and the second light control signal EM2 is at a conducting level, for example, a high level. Therefore, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are conducting. This corresponds to the operating process of the drive timing sequence in the compensation phase t2 after the Fig. 7.

[0052] During the data write phase t3, the first scan signal S1 is at a conducting level, for example, a high level; the third scan signal S3 is at a conducting level, for example, a high level; the first light control signal EM1 is at an off level, for example, a low level; and the second light control signal EM2 is at an off level, for example, a low level. This corresponds to the operating process of the drive timing sequence in the data write phase t3 according to the Fig. 7.

[0053] During the illumination phase t4, the first scan signal S1 is at a switched-off level, for example, a low level; the third scan signal S3 is at a switched-off level, for example, a low level; the first illumination control signal EM1 is at a conducting level, for example, a high level; and the second illumination control signal EM2 is at a conducting level, for example, a high level. This corresponds to the operating process of the drive timing sequence in the illumination phase t4 according to the Fig. 7.

[0054] During the hold frame, the first scan signal S1 remains at a cutoff level, and the sixth transistor T6 is permanently in the cutoff state. In the initialization phase t5 of the hold frame, the first scan signal S1 is at a cutoff level, for example, a low level; the third scan signal S3 is at a conducting level, for example, a high level; the first light control signal EM1 is at a conducting level, for example, a high level; and the second light control signal EM2 is at a cutoff level, for example, a low level. Therefore, the fourth transistor T4 and the seventh transistor T7 are conducting.The first supply voltage VDD is transmitted to point D via the fourth transistor T4, and the initialization voltage Vref is fed via the seventh transistor T7 to the second electrode of the second capacitor C2 and to the first electrode of the LED D1, thus initializing the first electrode of the LED D1. During this process, the signal source can apply a fixed voltage Vcom to the first electrode of the first capacitor C1.

[0055] During the illumination phase t6 of the holding frame, the work process corresponds to that in the illumination phase t4 of the writing frame.

[0056] The pixel circuit provided in this embodiment also exhibits the advantageous effects described in the above embodiments.

[0057] In a further embodiment of the present application, the fixed voltage Vcom provided by the signal source and the data voltage Vdata can be provided by a specific module and / or a power supply line. Fig. Figure 10 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application. With reference to Fig. In this embodiment, the pixel circuit comprises a driver module 110, a voltage write module 120, a compensation module 130, and a coupling module 140. The compensation module 130 is connected between the control terminal G and the first terminal D of the driver module 110 and serves to compensate the threshold voltage Vth of the driver module 110. The coupling module 140 is connected between the first terminal D of the driver module 110 and the voltage write module 120. The voltage write module 120 is designed to output the fixed voltage Vcom to the coupling module 140 and the data voltage Vdata to the coupling module 140. The coupling module 140 couples the voltage, which contains the data voltage information Vdata, via the compensation module 130 to the control terminal G of the driver module 110.

[0058] Specifically, the driver module 110 and the lighting module 150 are connected between the first and second supply voltage terminals. The driver module 110 serves to control the lighting module 150 during the illumination phase. The first supply voltage terminal is for connecting the first supply voltage VDD, and the second supply voltage terminal is for connecting the second supply voltage VSS. The first supply voltage VDD can be a positive voltage, while the second supply voltage VSS can be a negative voltage.

[0059] Using the example of the in Fig. The working process of the pixel circuit shown in 10 includes at least the initialization phase, the compensation phase, the data writing phase and the illumination phase.

[0060] During the initialization phase, the compensation module 130 is switched on, and the first supply voltage VDD initializes the first terminal D and the control terminal G of the driver module 110. Simultaneously, the voltage write module 120 transmits the fixed voltage Vcom to the first terminal of the coupling module 140 to initialize its first terminal. The first supply voltage VDD is a voltage that makes the driver module 110 conductive.

[0061] During the compensation phase, the compensation module 130 remains continuously conductive. The compensation module 130 connects the control terminal G and the first terminal D of the driver module 110. Under the influence of the first supply voltage VDD, the driver module 110 generates a current that flows from the first terminal D to the second terminal S until the voltage difference between the control terminal G and the second terminal S of the driver module 110 equals the threshold voltage Vth of the driver module 110, at which point the driver module 110 switches off. Consequently, the voltage at the control terminal G of the driver module 110 corresponds to the voltage associated with its threshold voltage Vth, thus achieving threshold compensation of the driver module 110. During this process, the voltage recorder module 120 continues to transmit the fixed voltage Vcom.

[0062] During the data write phase, the voltage write module 120 is controlled to transfer the data voltage Vdata to the first terminal of the coupling module 140. The voltage at the first terminal of the coupling module 140 switches from the fixed voltage Vcom to the data voltage Vdata. The coupling module couples the voltage associated with the data voltage Vdata to the control terminal of the driver module 110 via the compensation module 130, so that the voltage at the control terminal G of the driver module 110 is correlated with the data voltage Vdata.

[0063] During the illumination phase, the driver module 110 generates a driver current according to the voltage at its control terminal G, which makes the lighting module 150 light up.

[0064] In the technical solution of the embodiment of the present application, a compensation module is arranged between the control terminal and the first terminal of the driver module. During the compensation phase, the compensation module is switched to conduction, so that the first supply voltage is transferred from the first supply voltage terminal to the control terminal of the driver module, thus making the driver module conductive. The compensation module compensates the threshold voltage of the driver module based on the voltage at the first terminal of the driver module. During the data write phase, the first terminal of the coupling module is controlled to switch from a fixed voltage to the data voltage. The data voltage is coupled to the control terminal of the driver module via the coupling module, thereby writing the data voltage. In this solution, the threshold compensation of the driver module and the data writing do not occur simultaneously.Threshold compensation is therefore performed before the data voltage is written to the control pin of the driver module, ensuring that the compensation phase and the data write phase do not interfere with each other. This prevents the time required for threshold compensation from being affected by the data write phase. Even at high refresh rates, the threshold voltage of the driver module can be fully compensated, reducing differences in the characteristics of the driver modules of different pixels. This contributes to improved brightness variations and increased uniformity of image quality.

[0065] Furthermore, with reference to Fig. The pixel circuit optionally includes a second initialization module 180, which is connected to the first terminal of the light module 150 and serves to initialize the potential at the first terminal of the light module 150. During the compensation phase, the conduction of the second initialization module 180 is still controlled, so that the voltage at the first terminal D of the driver module 110 is discharged via the driver module 110 and the second initialization module 180, thereby achieving threshold compensation of the driver module 110.

[0066] Furthermore, with reference to Fig. In this embodiment, the pixel circuit optionally includes a lighting control module 160. The lighting control module 160, the driver module 110, and the lighting module 150 are connected between the first supply voltage terminal and the second supply voltage terminal. During the compensation phase, the lighting control module 160 serves to interrupt the connection between the first terminal D of the driver module 110 and the first supply voltage terminal, allowing the voltage at the first terminal D of the driver module 110 to be discharged via the driver module 110 and the second initialization module 180. Of course, in other embodiments, the lighting control module 160 can be omitted between the first terminal D of the driver module 110 and the first supply voltage terminal.The voltage at the first terminal D of the driver module 110 can instead be controlled by controlling the application of the first supply voltage at the first supply voltage terminal, which achieves the same effect.

[0067] In the specific embodiment described in the present application, Fig. 11 a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application. With reference to Fig. According to this embodiment, the pixel circuit optionally comprises a first lighting control module 161 and a second lighting control module 162, based on the respective technical solutions mentioned above. The first lighting control module 161 is connected between the first supply voltage terminal and the first terminal D of the driver module 110. The second lighting control module 162 is connected between the second terminal S of the driver module 110 and the first terminal of the lighting module 150, with the second terminal of the lighting module 150 being connected to the second supply voltage terminal. The control terminal of the first lighting control module 161 is connected to the first lighting control signal line, and the control terminal of the second lighting control module 162 is connected to the second lighting control signal line.The first lighting control module 161 serves to be conductive at least during the lighting phase in response to the first lighting control signal EM1 on the first lighting control signal line and to be switched off during the compensation phase and the data write phase; the second lighting control module 162 serves to be conductive at least during the compensation phase and the lighting phase in response to the second lighting control signal EM2 on the second lighting control signal line.

[0068] Furthermore, with reference to Fig. 11 is the control terminal of the voltage write module 120 connected to the first scan line, wherein the first terminal of the voltage write module 120 is connected to the data line DATA, wherein the second terminal of the voltage write module 120 is connected to the first terminal of the coupling module 140, and wherein the second terminal of the coupling module 140 is connected to the first terminal D of the driver module 110; wherein the data line DATA serves to transmit at least the fixed voltage Vcom during the compensation phase and the data voltage Vdata during the data write phase. For example, during the initialization phase, the voltage write module 120 is switched on by the first scan signal S1 transmitted on the first scan line, thereby outputting the fixed voltage Vcom transmitted on the data line DATA to the first terminal of the coupling module 140.

[0069] Simultaneously, the first supply voltage VDD is transferred to the second terminal of the coupling module 140 (i.e., the first terminal D of the driver module 110) to maintain a stable voltage at both terminals of the coupling module 140. During the initialization phase, the first supply voltage VDD is further transferred via the conducting compensation module 130 to the control terminal of the driver module 110, thus making the driver module 110 conducting in order to compensate for the threshold voltage of the driver module 110 during the compensation phase.

[0070] During the compensation phase, the DATA line continues to transmit the fixed voltage Vcom. The compensation module 130 compensates the threshold voltage Vth of the driver module 110 based on the voltage measured after the discharge of the first terminal D of the driver module 110.

[0071] During the data write phase, the voltage on the DATA line changes to the data voltage Vdata. In response to the first scan signal S1, transmitted via the first scan line, the voltage write module 120 maintains the line state and outputs the data voltage Vdata, transmitted on the DATA line, to the first terminal of the coupling module 140. The voltage at the first terminal of the coupling module 140 undergoes a step change. Due to the coupling action of the coupling module 140, the difference between the data voltage Vdata and the fixed voltage Vcom is coupled to the control terminal G of the driver module 110, thus writing the data voltage Vdata to the control terminal G of the driver module 110.

[0072] In this design, time-division multiplexing of the DATA data line enables both the fixed voltage Vcom and the data voltage Vdata to be written to the control terminal G of the driver module 110 during the data write phase. This contributes to reducing the number of signal lines and allows for a high PPI (pixels per inch, pixel density).

[0073] Furthermore, with reference to Fig. 11 The pixel circuit can optionally also include a memory module 170, wherein the memory module 170 is connected between the control terminal G of the driver module 110 and the first terminal of the light module 150; wherein the second light control module 162 further serves to be switched off in response to the second light control signal EM2 during the data write phase in order to improve the charging efficiency of the driver module 110. The specific operating principle is explained in detail in the following exemplary embodiments.

[0074] In an optional embodiment of this exemplary embodiment, the control terminal of the compensation module 130 and the control terminal of the second initialization module 180 can be connected to the same scan line. Fig. 12 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application, in particular a detailed representation of the Fig. 11 pixel circuits shown at the device level. With reference to Fig. 12 The driver module 110 comprises a first transistor T1, wherein the first terminal of the first transistor T1 forms the first terminal D of the driver module 110, wherein the second terminal of the first transistor T1 forms the second terminal S of the driver module 110, wherein the gate of the first transistor T1 represents the control terminal G of the driver module 110, wherein the data write module 120 comprises a second transistor T2, wherein the coupling module 140 comprises a first capacitor C1, wherein the gate of the second transistor T2 is connected to the first scan line, wherein the first terminal of the second transistor T2 is connected to the data line DATA, wherein the second terminal of the second transistor T2 is connected to the first electrode of the first capacitor C1, wherein the second electrode of the first capacitor C1 is connected to the first terminal of the first transistor T1.

[0075] The first lighting control module 161 comprises a fourth transistor T4, the second lighting control module 162 comprises a fifth transistor T5, the lighting module 150 comprises a light-emitting diode D1, the gate of the fourth transistor T4 is connected to the first lighting control signal line, the first terminal of the fourth transistor T4 is connected to the first supply voltage terminal, the second terminal of the fourth transistor T4 is connected to the first terminal of the first driver module 110, the second terminal of the first driver module 110 is connected to the first terminal of the fifth transistor T5, the second terminal of the fifth transistor T5 is connected to the first terminal of the light-emitting diode D1, and the second terminal of the light-emitting diode D1 is connected to the second supply voltage terminal.where the gate of the fifth transistor T5 is connected to the second light control signal line.

[0076] The storage module 170 includes a second capacitor C2, wherein the first electrode of the second capacitor C2 is connected to the control terminal of the driver module 110, and wherein the second electrode of the second capacitor C2 is connected to the first terminal of the lighting module 150.

[0077] Optionally, the control terminal of the compensation module 130 is connected to the third scan line. The sixth transistor T6, which is included in the compensation module 130, remains conductive during the initialization, compensation, and data write phases in response to the third scan signal S3 transmitted on the third scan line.

[0078] The control terminal of the second initialization module 180 can also be connected to the third scan line and can be conductive simultaneously with the compensation module 130. The first terminal of the second initialization module 180 is connected to the initialization signal line, which is used to transmit the initialization voltage Vref. The second terminal of the second initialization module 180 is connected to the first terminal of the illumination module 150. The second initialization module 180 serves to transmit the initialization voltage Vref from the initialization signal line to the first terminal of the illumination module 150 during the initialization phase. The second initialization module 180 includes the seventh transistor T7; the gate terminals of the sixth transistor T6 and the seventh transistor T7 are both connected to the third scan line.The first terminal of the sixth transistor T6 is connected to the first terminal D of the driver module 110, the second terminal of the sixth transistor T6 is connected to the control terminal G of the driver module 110. The first terminal of the seventh transistor T7 is connected to the initialization signal line, the second terminal of the seventh transistor T7 is connected to the first terminal of the light module 150.

[0079] Fig. 13 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application and for which in Fig. The pixel circuit shown in section 12 is applicable. For example, all of the pixels shown in... Fig. The specific operating process of the pixel circuit provided in the present application is explained, in connection with the 12 transistors shown, which are N-channel types. Fig. 12 and Fig. 13 The working process of the pixel circuit provided in this embodiment comprises the initialization phase t1, the compensation phase t2, the data writing phase t3 and the illumination phase t4.

[0080] During the initialization phase t1, the first scan signal S1 is at a conducting level, for example, a high level; the third scan signal S3 is at a conducting level, for example, a high level; the first light control signal EM1 is at a conducting level, for example, a high level; and the second light control signal EM2 is off, for example, a low level. Therefore, the second transistor T2, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are conducting. The fixed voltage Vcom, transmitted via the DATA line, is passed through the second transistor T2 to the first electrode of the first capacitor C1, and the first supply voltage VDD is passed through the fourth transistor T4 to point D and through the sixth transistor T6 to point G. The initialization voltage Vref is passed through the seventh transistor T7 to the second electrode of the second capacitor C2.Consequently, the voltage across the first electrode of the first capacitor C1 is Vcom, and across the second electrode is VDD; the voltage across the first electrode of the second capacitor C2 is VDD, and across the second electrode is Vref. The voltages across the first terminal and gate of the first transistor T1 are each VDD, with the first transistor T1 conducting.

[0081] During the compensation phase t2, the first scan signal S1 is at a conducting level, for example, a high level; the third scan signal S3 is at a conducting level, for example, a high level; the first light control signal EM1 is at a cut-off level, for example, a low level; and the second light control signal EM2 is at a conducting level, for example, a high level. Therefore, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are conducting. The gate and the first terminal of the first transistor T1 are short-circuited, forming a diode structure. A discharge path is created between point D and the seventh transistor T7. When the voltage at point D drops to Vref + Vth1, the first transistor T1 turns off, where Vth1 is the threshold voltage of the first transistor T1. At this point, the voltage at the gate of the first transistor T1 (point G) is also Vref + Vth1.This not only implements threshold compensation but also transfers the initialization voltage Vref to the gate of the first transistor T1, thus initializing its gate. Furthermore, during the compensation phase t2, the voltage at the first electrode of the LED D1 remains at the initialization voltage Vref to prevent the LED D1 from lighting up. The second capacitor C2 stores the gate voltage of the first transistor T1.

[0082] During the data write phase t3, the first scan signal S1 is at a conducting level, for example, a high level; the third scan signal S3 is at a conducting level, for example, a high level; the first indicator light signal EM1 is at a cut-off level, for example, a low level; and the second indicator light signal EM2 is at a cut-off level, for example, a low level. Therefore, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are conducting. The data voltage Vdata on the DATA line is transmitted via the second transistor T2 to the first electrode of the first capacitor C1. The voltage at the first electrode of the first capacitor C1 changes from the fixed voltage Vcom to the data voltage Vdata; the voltage change at the first electrode of the first capacitor C1 is Vdata - Vcom.Since the sixth transistor T6 is conducting, the gate voltage of the first transistor T1 is converted to Vref + Vth1 + c1(Vdata - Vcom) / (c1 + c2 + cgs) by coupling the first capacitor C1 and stored in the second capacitor C2. The voltage at the second electrode of the second capacitor C2 is held at the initialization voltage Vref by the holding effect of the seventh transistor T7. The voltage difference across the second capacitor C2 is Vth1 + c1(Vdata - Vcom) / (c1 + c2 + cgs), where c1 is the capacitance of the first capacitor C1, c2 is the capacitance of the second capacitor C2, and cgs is the parasitic capacitance between the gate and the second electrode of the first transistor T1.

[0083] Furthermore, during the data write phase t3, the fifth transistor T5, contained in the second lighting control module 162, is in the switched-off state. Therefore, the first capacitor C1 and the second capacitor C2 are arranged in series, which improves the charging efficiency of the first transistor T1 during the data write phase and thus ensures the display quality of the pixel circuit at high frequencies.

[0084] During the illumination phase t4, the first scan signal S1 is at a low level; the third scan signal S3 is also at a low level; the first illumination control signal EM1 is at a high level; and the second illumination control signal EM2 is at a high level. Therefore, the fourth transistor T4 and the fifth transistor T5 are conducting. The first supply voltage VDD is transmitted to point D via the fourth transistor T4. Since the sixth transistor T6 is permanently off, the gate voltage of the first transistor T1 does not change. The first transistor T1 generates the drive current I, corresponding to the voltage across its gate and at point D, which illuminates the LED D1. The drive current I can be represented as: I=12μCoxWL(Vgs−Vth1)2=12μCoxWL[Vth1+c1(Vdata−Vcom) / (c1+c2+cgs)−Vth1]2=12μCoxW2L[c1(Vdata−Vcom) / (c1+c2+cgs)]2∘

[0085] Here, µ denotes the electron mobility of the first transistor T1, Cox the channel capacitance per unit area of ​​the first transistor T1, W / L the width-to-length ratio of the first transistor T1, and Vth1 the threshold voltage of the first transistor T1.

[0086] According to the formula for the driver current I, the driver current I is independent of the first supply voltage VDD, the second supply voltage VSS, and the threshold voltage Vth1 of the first transistor T1. Therefore, the pixel circuit provided in this embodiment can compensate for display irregularities caused by the threshold voltage Vth1 of the first transistor T1 and by voltage drops (IR drop) across the first supply voltage VDD and the second supply voltage VSS, thus improving display quality.

[0087] Fig. Figure 14 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application. The control terminal of the compensation module 130 and the control terminal of the voltage write module 120 can be connected to the same first scan line, while the control terminal of the second initialization module 180 is connected to a third scan line to ensure the display performance of the pixel circuit when driven at low frequency.

[0088] Fig. 15 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application, which is intended for the Fig. The pixel circuit shown in section 14 is applicable, with reference to Fig. 14 and Fig. 15 is the drive timing sequence shown in the writing frame in Fig. 15 identical to the one in Fig. The drive sequence shown in section 13 is therefore not explained again.

[0089] During the hold frame, the first scan signal S1 remains at a low level, while the second transistor T2 and the sixth transistor T6 are permanently in the off state. In the initialization phase t5 of the hold frame, the first scan signal S1 is at a low level; the third scan signal S3 is also at a low level; the first LED control signal EM1 is at a high level; and the second LED control signal EM2 is at a low level. Therefore, the fourth transistor T4 and the seventh transistor T7 are conducting.The first supply voltage VDD is transferred to point D via the fourth transistor T4, the initialization voltage Vref is passed via the seventh transistor T7 to the second electrode of the second capacitor C2 and to the first electrode of the LED D1, thereby realizing a high frequency reset at the first electrode of the LED D1, which contributes to improving the flicker of the LED D1.

[0090] During the illumination phase t6 of the holding frame, the work process corresponds to that in the illumination phase t4 of the writing frame.

[0091] The pixel circuit provided in this embodiment also exhibits the advantageous effects described in the above embodiments.

[0092] In another alternative embodiment of this application, the data voltage Vdata and the fixed voltage Vcom can be transmitted over different signal lines to avoid interference between the two. Fig. Figure 16 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application. With reference to Fig. In this embodiment, the pixel circuit comprises a driver module 110, a data write module 121, a first initialization module 122, a compensation module 130, and a coupling module 140. The compensation module 130 is connected between the control terminal G and the first terminal D of the driver module 110 and serves to compensate for the threshold voltage Vth of the driver module 110. The data write module 121 and the first initialization module 122 are connected to the first node N1. The coupling module 140 is connected between the first terminal D of the driver module 110 and the first node N1. The first initialization module 122 transmits the fixed voltage Vcom to the coupling module 140, and the coupling module 140 couples the voltage transmitted by the data write module 121 with the data voltage information Vdata via the compensation module 130 to the control terminal G of the driver module 110.

[0093] The first terminal of the first initialization module 122 is connected to the fixed voltage Vcom, the second terminal of the first initialization module 122 is connected to the first terminal of the coupling module 140, the second terminal of the coupling module 140 is connected to the first terminal of the driver module 110. The first terminal of the coupling module 140 is also connected to the second terminal of the data write module 121, the first terminal of the data write module 121 is connected to the data line DATA, and the control terminal of the data write module 121 is connected to the first scan line. The control terminal of the first initialization module 122 is connected to the second scan line.The first initialization module 122 serves to transmit the fixed voltage Vcom to the first terminal of the coupling module 140 during the initialization phase. The compensation module 130 further serves to transmit the first supply voltage VDD from the first supply voltage terminal to the control terminal G of the driver module 110 during the initialization phase. The first scan line is used to transmit the first scan signal S1, and the second scan line to transmit the second scan signal S2. The fixed voltage Vcom can be supplied from the supply line, while the data line DATA is used exclusively for transmitting the data voltage Vdata and transmits this voltage at least during the data write phase.

[0094] Fig. Figure 17 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application. With reference to Fig. Optionally, the first supply voltage VDD applied to the first supply voltage terminal can be identical to the fixed voltage Vcom. That is, the first terminal of the first initialization unit 122 is connected to the first supply voltage terminal, with the first supply voltage VDD being multiplexed as the fixed voltage Vcom, thus reducing the number of supply lines.

[0095] In the specific embodiment described in the present application, Fig. 18 A schematic representation of the structure of another pixel circuit provided by an embodiment of the present application. With reference to Fig. According to this embodiment, the pixel circuit optionally comprises a first lighting control module 161 and a second lighting control module 162, based on the respective technical solutions mentioned above. The first lighting control module 161 is connected between the first supply voltage terminal and the first terminal D of the driver module 110. The second lighting control module 162 is connected between the second terminal S of the driver module 110 and the first terminal of the lighting module 150, with the second terminal of the lighting module 150 being connected to the second supply voltage terminal. The control terminal of the first lighting control module 161 is connected to the first lighting control signal line, and the control terminal of the second lighting control module 162 is connected to the second lighting control signal line.The first lighting control module 161 serves to be conductive at least during the lighting phase in response to the first lighting control signal EM1 on the first lighting control signal line and to be switched off during the compensation phase and the data write phase; the second lighting control module 162 serves to be conductive at least during the compensation phase and the lighting phase in response to the second lighting control signal EM2 on the second lighting control signal line.

[0096] Specifically, the first initialization module 122 switches on during the initialization phase in response to the second scan signal S2, while the data write module 121 switches off in response to the first scan signal S1. The fixed voltage Vcom is transmitted via the first initialization module 122 to the first terminal of the coupling module 140. The first lighting control module 161 switches on in response to the first lighting control signal EM1, and the second lighting control module 162 switches off in response to the second lighting control signal EM2. The first supply voltage VDD is transmitted via the first lighting control module 161 to the first terminal D of the driver module 110, thereby initializing the coupling module 140.Simultaneously, the compensation module 130 can be switched on, so that the control terminal G and the first terminal D of the driver module 110 are connected and have the same voltage, thus making the driver module 110 conductive. Furthermore, the second initialization module 180 can be switched on to transmit the initialization voltage Vref to the first terminal of the light module 150, thereby initializing the first terminal of the light module 150.

[0097] During the compensation phase, the first initialization module 122 and the compensation module 130 remain conducting. The data write module 121 is switched off in response to the first scan signal S1, the first lighting control module 161 is switched off in response to the first lighting control signal EM1, and the second lighting control module 162 is switched on in response to the second lighting control signal EM2. A discharge path is formed between the first terminal D of the driver module 110 and the second initialization module 180. When the voltage at the first terminal D of the driver module 110 drops to Vref+Vth, the driver module 110 is switched off, where Vth represents the threshold voltage of the driver module 110. At this point, the voltage at the control terminal G of the driver module 110 is also Vref+Vth.This not only implements threshold compensation but also transmits the initialization voltage Vref to the control terminal of the driver module 110, thereby initializing the control terminal of the driver module 110. In this embodiment, no separate module is required for initializing the control terminal G of the driver module 110, which reduces the number of transistors in the pixel circuit.

[0098] During the data write phase, the first initialization module 122 switches off in response to the second scan signal S2, and the data write module 121 switches on in response to the first scan signal S1. Both the first light control module 161 and the second light control module 162 switch off in response to their respective light control signals, while the compensation module 130 remains conductive. The data write module 121 transmits the data voltage Vdata via the DATA line to the first terminal of the coupling module 140. The voltage at the first terminal of the coupling module 140 changes from the fixed voltage Vcom to the data voltage Vdata. The coupling module 140 couples the voltage associated with the data voltage Vdata to the control terminal of the driver module 110 via the compensation module 130, so that the voltage at the control terminal G of the driver module 110 is correlated with the data voltage Vdata.

[0099] During the illumination phase, both the first illumination control module 161 and the second illumination control module 162 respond to the corresponding illumination control signals and switch on. The driver module 110 generates a driver current corresponding to the voltage at its control terminal G, which causes the illumination module 150 to illuminate.

[0100] Fig. 19 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application, in particular a detailed representation of the Fig. 18 pixel circuits shown at the device level. With reference to Fig. 19 comprises the driver module 110 according to this embodiment based on the respective above.Technical solutions optionally include a first transistor T1, wherein the first terminal of the first transistor T1 forms the first connection D of the driver module 110, wherein the second terminal of the first transistor T1 forms the second connection S of the driver module 110, wherein the gate of the first transistor T1 represents the control connection G of the driver module 110, wherein the data write module 121 comprises a second transistor T2, wherein the coupling module 140 comprises a first capacitor C1, wherein the gate of the second transistor T2 is connected to the first scan line, wherein the first terminal of the second transistor T2 is connected to the data line DATA, wherein the second terminal of the second transistor T2 is connected to the first electrode of the first capacitor C1, wherein the second electrode of the first capacitor C1 is connected to the first terminal of the first transistor T1.

[0101] The first initialization module 122 includes a third transistor T3, wherein the gate of the third transistor T3 is connected to the second scan line, wherein the first terminal of the third transistor T3 is connected to the fixed voltage Vcom, wherein the second terminal of the third transistor T3 is connected to the first terminal of the coupling module 140 (i.e., to the first electrode of the first capacitor C1).

[0102] The first lighting control module 161 comprises a fourth transistor T4, the second lighting control module 162 comprises a fifth transistor T5, the lighting module 150 comprises a light-emitting diode D1, the gate of the fourth transistor T4 is connected to the first lighting control signal line, the first terminal of the fourth transistor T4 is connected to the first supply voltage terminal, the second terminal of the fourth transistor T4 is connected to the first terminal of the first driver module 110, the second terminal of the first driver module 110 is connected to the first terminal of the fifth transistor T5, the second terminal of the fifth transistor T5 is connected to the first terminal of the light-emitting diode D1, and the second terminal of the light-emitting diode D1 is connected to the second supply voltage terminal.where the gate of the fifth transistor T5 is connected to the second light control signal line.

[0103] Optionally, the pixel circuit can also include a memory module 170, wherein the memory module 170 is connected between the control terminal G of the driver module 110 and the first terminal of the light module 150; wherein the second light control module 162 further serves to be switched off in response to the second light control signal EM2 during the data write phase.

[0104] The storage module 170 includes a second capacitor C2, wherein the first electrode of the second capacitor C2 is connected to the control terminal of the driver module 110, and the second electrode of the second capacitor C2 is connected to the first terminal of the lighting module 150.

[0105] Fig. 20 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application and for which in Fig. The pixel circuit shown in 19 is applicable. For example, all in Fig. The specific operating process of the pixel circuit provided in the present application is explained, in connection with the 19 transistors shown, which are N-channel types. Fig. 19 and Fig. 20 The working process of the pixel circuit provided in this embodiment comprises the initialization phase t1, the compensation phase t2, the data writing phase t3 and the illumination phase t4.

[0106] In the initialization phase 11, the first scan signal S1 is at a low level; the second scan signal S2 is at a high level; the third scan signal S3 is at a high level; the first light control signal EM1 is at a high level; and the second light control signal EM2 is at a low level. Therefore, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are conducting. The fixed voltage Vcom is applied via the third transistor T3 to the first electrode of the first capacitor C1, and the first supply voltage VDD is applied via the fourth transistor T4 to point D and passed on via the sixth transistor T6 to point G.The initialization voltage Vref is transferred via the seventh transistor T7 to the second electrode of the second capacitor C2. Consequently, the voltage at the first electrode of the first capacitor C1 is Vcom, and at the second electrode is VDD; where the voltage at the first electrode of the second capacitor C2 is VDD, and at the second electrode is Vref, the voltages at the first terminal and at the gate of the first transistor T1 are each VDD, with the first transistor T1 conducting.

[0107] During the compensation phase t2, the first scan signal S1 is at a low level; the second scan signal S2 is at a high level; the third scan signal S3 is at a high level; the first light control signal EM1 is at a low level; and the second light control signal EM2 is at a high level. Therefore, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are conducting. The gate and the first terminal of the first transistor T1 are short-circuited, forming a diode structure. A discharge path is created between point D and the seventh transistor T7. When the voltage at point D drops to Vref + Vth1, the first transistor T1 turns off, where Vth1 is the threshold voltage of the first transistor T1.At this point, the voltage at the gate of the first transistor T1 (point G) is also Vref + Vth. This not only implements the threshold compensation but also applies the initialization voltage Vref to the gate of the first transistor T1, thus initializing its gate. Furthermore, during the compensation phase t2, the voltage at the first electrode of the LED D1 remains at the initialization voltage Vref to prevent the LED D1 from lighting up. The second capacitor C2 stores the gate voltage of the first transistor T1.

[0108] During the data write phase t3, the first scan signal S1 is at a conducting level, for example, a high level; the second scan signal S2 is at a cut-off level, for example, a low level; the third scan signal S3 is at a conducting level, for example, a high level; the first indicator light signal EM1 is at a cut-off level, for example, a low level; and the second indicator light signal EM2 is at a cut-off level, for example, a low level. Therefore, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are conducting. The data voltage Vdata on the DATA line is transmitted via the second transistor T2 to the first electrode of the first capacitor C1. The voltage at the first electrode of the first capacitor C1 changes from the fixed voltage Vcom to the data voltage Vdata; the voltage change at the first electrode of the first capacitor C1 is Vdata - Vcom.Since the sixth transistor T6 is conducting, the gate voltage of the first transistor T1 is converted to Vref + Vth + c1(Vdata - Vcom) / (c1 + c2 + cgs) by coupling the first capacitor C1 and stored in the second capacitor C2. The voltage at the second electrode of the second capacitor C2 is held at the initialization voltage Vref by the holding effect of the seventh transistor T7. The voltage difference across the second capacitor C2 is Vth + c1(Vdata - Vcom) / (c1 + c2 + cgs).

[0109] When the third scan signal S3 transitions from a conducting level to a switched-off level, it capacitively affects the gate of the first transistor T1, lowering the gate voltage of the first transistor T1 and promoting the maintenance of a low potential at the gate of the first transistor T1. This prevents a loss of threshold compensation and avoids a voltage drop at the gate of the driver transistor due to potential coupling.

[0110] During the illumination phase t4, the first scan signal S1 is at a low level; the second scan signal S2 is at a low level; the third scan signal S3 is at a low level; the first illumination control signal EM1 is at a high level; and the second illumination control signal EM2 is at a high level. Therefore, the fourth transistor T4 and the fifth transistor T5 are conducting. The first supply voltage VDD is passed to point D via the fourth transistor T4. Since the sixth transistor T6 is permanently off, the gate voltage of the first transistor T1 does not change. The first transistor T1 generates the drive current I, corresponding to the voltage across its gate and at point D, which illuminates the LED D1.The drive current I can be represented as:. I=12μCoxWL(Vgs−Vth1)2=12μCoxWL[Vth1+c1(Vdata−Vcom) / (c1+c2+cgs)−Vth1]2=12μCoxW2L[c1(Vdata−Vcom) / (c1+c2+cgs)]2∘

[0111] Here, µ denotes the electron mobility of the first transistor T1, Cox the channel capacitance per unit area of ​​the first transistor T1, W / L the width-to-length ratio of the first transistor T1, Vth1 the threshold voltage of the first transistor T1, c1 the capacitance of the first capacitor C1, c2 the capacitance of the second capacitor C2, and cgs the parasitic capacitance between the gate of the first transistor T1 and the second terminal.

[0112] According to the formula for the driver current I, the driver current I is independent of the first supply voltage VDD, the second supply voltage VSS, and the threshold voltage Vth1 of the first transistor T1. Therefore, the pixel circuit provided in this embodiment can compensate for display irregularities caused by the threshold voltage Vth1 of the first transistor T1 and by voltage drops (IR drop) across the first supply voltage VDD and the second supply voltage VSS, thus improving display quality.

[0113] As a further alternative embodiment provided in the present application, the second light control signal line can be used as a second scan line connected to the control terminal of the first initialization module 122 in order to reduce the number of signal lines and achieve a high PPI. Fig. 21 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application. With reference to Fig. 21 The gate of the third transistor T3 and the gate of the fifth transistor T5 are both connected to the second light control signal EM2, allowing the initialization phase to overlap with the light phase to extend the threshold compensation time and ensure that the first transistor T1 is fully compensated. Fig. 22 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application, which is intended for the Fig. The pixel circuit shown in section 21 is applicable. With reference to Fig. 21 and Fig. 22 The working process of this pixel circuit comprises the compensation phase t2, the data writing phase t3 and the illumination phase t4.

[0114] In the initial phase t0, the light-emitting diode D1 is in the illuminated state, the voltage at the first electrode of the first capacitor C1 is the fixed voltage Vcom, while the voltage at the second electrode corresponds to the first supply voltage VDD.

[0115] The compensation phase t2 and the data writing phase t3 correspond to that in Fig. The pixel switching process shown in 19 is not explained further here.

[0116] During the illumination phase t4, the first scan signal S1 is at a cutoff level, for example, a low level; the third scan signal S3 is also at a cutoff level, for example, a low level; the first illumination control signal EM1 is at a conducting level, for example, a high level; and the second illumination control signal EM2 is at a conducting level, for example, a high level. Therefore, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are conducting. The first supply voltage VDD is passed through the fourth transistor T4 to point D, and the first transistor T1 generates the driver current I, corresponding to the voltage across its gate and at point D, which illuminates the LED D1. Simultaneously, the third transistor T3 applies the fixed voltage Vcom to the first terminal of the first capacitor C1, thus initializing the first capacitor C1.

[0117] In this embodiment, when the display panel is operated at a low refresh rate, no data is written and no threshold compensation is performed during the hold frame. Therefore, the seventh transistor T7 and the sixth transistor T6 are in the off state during the hold frame, preventing the first electrode of LED D1 from resetting, which can lead to flickering during the illuminated phase. To avoid this situation and make the pixel circuit suitable for low-frequency driving, the first electrode of LED D1 can be reset separately by another module, or the scan signal applied to the gate of the seventh transistor T7 can be modified.

[0118] Fig. Figure 23 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application. With reference to Fig. Optionally, the control terminal of the second initialization module 180 can be connected to the fifth scan line, meaning that the gate of the seventh transistor T7 is connected to the fifth scan line to insert the fifth scan signal, which is transmitted via the fifth scan line. The fifth scan signal S5 differs from the third scan signal S3. Fig. 24 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application, which is intended for the Fig. The pixel circuit shown in section 23 is applicable. With reference to Fig. 23 and Fig. 24 The work process of this pixel circuit comprises the following: During the initialization phase t1 of the write frame, the first scan signal S1 is at a low level; the third scan signal S3 is at a low level; the fifth scan signal S5 is at a high level; the first LED control signal EM1 is at a low level; and the second LED control signal EM2 is at a low level. Therefore, the seventh transistor T7 is conducting. The initialization voltage Vref is applied via the seventh transistor T7 to the first electrode of LED D1, thus initializing the first electrode of LED D1.

[0119] During the compensation phase t2, the first scan signal S1 is at a switched-off level, for example, a low level; the third scan signal S3 is at a conducting level, for example, a high level; the fifth scan signal S5 is at a conducting level, for example, a high level; the first light control signal EM1 is at a switched-off level, for example, a low level; and the second light control signal EM2 is at a conducting level, for example, a high level. Therefore, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are conducting. The compensation phase t2 can be determined based on the process associated with the operation of the circuit. Fig. The details described in the pixel circuit shown in section 19 can be traced, which is why they will not be discussed further here.

[0120] During the data write phase t3, the first scan signal S1 is at a conducting level, for example, a high level; the third scan signal S3 is at a conducting level, for example, a high level; the fifth scan signal S5 is at a conducting level, for example, a high level; the first LED control signal EM1 is at a cutoff level, for example, a low level; and the second LED control signal EM2 is at a cutoff level, for example, a low level. Therefore, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are conducting. While the data voltage Vdata is being written to the gate of the first transistor T1, the first electrode of the LED D1 is simultaneously initialized via the seventh transistor T7.

[0121] During the illumination phase t4, the first scan signal S1 is at a cutoff level, for example, a low level; the third scan signal S3 is at a cutoff level, for example, a low level; the fifth scan signal S5 is at a cutoff level, for example, a low level; the first illumination control signal EM1 is at a conducting level, for example, a high level; and the second illumination control signal EM2 is at a conducting level, for example, a high level. The first transistor T1 generates a drive current I, corresponding to the voltage across its gate and point D, which illuminates the LED D1. Simultaneously, the third transistor T3 applies the fixed voltage Vcom to the first terminal of the first capacitor C1, thus initializing the first capacitor C1.

[0122] During the initialization phase t5 of the hold frame, the first scan signal S1 is at a low level; the third scan signal S3 is at a low level; the fifth scan signal S5 is at a high level; the first LED control signal EM1 is at a low level; and the second LED control signal EM2 is at a low level. Therefore, the seventh transistor T7 is conducting. The initialization voltage Vref is applied via the seventh transistor T7 to the first electrode of LED D1, thus initializing the first electrode of LED D1.

[0123] During the illumination phase t6 of the holding frame, the work process corresponds to that in the illumination phase t4 of the writing frame.

[0124] This solution enables a high-frequency reset of the first electrode of the LED D1 within the holding frame, which helps to improve the flicker that often occurs during the illumination phase.

[0125] Fig. Figure 25 is a schematic representation of the structure of another pixel circuit provided by an embodiment of the present application. With reference to Fig. 25. In the event that the control terminal of the compensation module 130 and the control terminal of the second initialization module 180 are connected to the same scan line, the pixel circuit optionally further includes a third initialization module 190. The control terminal of the third initialization module 190 is connected to a fourth scan line, the first terminal of the third initialization module 190 being connected to the initialization signal line, and the second terminal of the third initialization module 190 being connected to the first terminal of the light module 150. The third initialization module 190 serves to transmit the initialization voltage Vref to the first terminal of the light module 150 during the write frame of a display cycle, and also during the hold frame of the same display cycle.

[0126] The third initialization module 190 includes the eighth transistor T8, wherein the gate of the eighth transistor T8 is connected to the fourth scan line, wherein the first terminal of the eighth transistor T8 is connected to the initialization signal line, and wherein the second terminal of the eighth transistor T8 is connected to the first terminal of the light module 150.

[0127] Fig. 26 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application, which is intended for the Fig. The pixel circuit shown in section 25 is applicable. With reference to Fig. 25 and Fig. 26 The write operation includes the initialization phase t1, the compensation phase t2, the data write phase t3 and the illumination phase t4, while the hold frame includes the initialization phase t5 and the illumination phase t6.

[0128] During the initialization phase t1 of the write frame, the first scan signal S1 is at a low level; the third scan signal S3 is at a low level; the fourth scan signal S4 is at a high level; the first LED control signal EM1 is at a low level; and the second LED control signal EM2 is at a low level. Therefore, the eighth transistor T8 is conducting. The initialization voltage Vref is applied via the eighth transistor T8 to the first electrode of LED D1, thus initializing the first electrode of LED D1.

[0129] During the compensation phase t2, the first scan signal S1 is at a cutoff level, for example, a low level; the third scan signal S3 is at a conducting level, for example, a high level; the fourth scan signal S4 is at a cutoff level, for example, a low level; the first light control signal EM1 is at a cutoff level, for example, a low level; and the second light control signal EM2 is at a conducting level, for example, a high level. Therefore, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are conducting.

[0130] During the data write phase t3, the first scan signal S1 is at a conducting level, for example, a high level; the third scan signal S3 is at a conducting level, for example, a high level; the fourth scan signal S4 is at a cut-off level, for example, a low level; the first light control signal EM1 is at a cut-off level, for example, a low level; and the second light control signal EM2 is at a cut-off level, for example, a low level. Therefore, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are conducting.

[0131] The compensation phase t2 and the data writing phase t3 can be described based on the work process in the Fig. The details described in the pixel circuit shown in section 19 can be traced, which is why they will not be discussed further here.

[0132] During the illumination phase t4, the first scan signal S1 is at a cutoff level, for example, a low level; the third scan signal S3 is at a cutoff level, for example, a low level; the fourth scan signal S4 is at a cutoff level, for example, a low level; the first illumination control signal EM1 is at a conducting level, for example, a high level; and the second illumination control signal EM2 is at a conducting level, for example, a high level. Therefore, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are conducting. The first supply voltage VDD is passed through the fourth transistor T4 to point D, and the first transistor T1 generates the driver current I, corresponding to the voltage across its gate and at point D, which illuminates the LED D1.At the same time, the third transistor T3 transmits the fixed voltage Vcom to the first terminal of the first capacitor C1, thereby initializing the first capacitor C1.

[0133] During the initialization phase t5 of the hold frame, the first scan signal S1 is at a low level; the third scan signal S3 is at a low level; the fourth scan signal S4 is at a high level; the first LED control signal EM1 is at a low level; and the second LED control signal EM2 is at a low level. Therefore, the eighth transistor T8 is conducting. The initialization voltage Vref is applied via the eighth transistor T8 to the first electrode of LED D1, thus initializing the first electrode of LED D1.

[0134] During the illumination phase t6 of the hold frame, the first scan signal S1 is at a low level; the third scan signal S3 is at a low level; the fourth scan signal S4 is at a low level; the first illumination control signal EM1 is at a high level; and the second illumination control signal EM2 is at a high level. Therefore, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are conducting. The first supply voltage VDD is passed through the fourth transistor T4 to point D, and the first transistor T1 illuminates the LED D1 again. Simultaneously, the third transistor T3 applies the fixed voltage Vcom to the first terminal of the first capacitor C1, thus initializing the first capacitor C1.

[0135] Optionally, with further reference to Fig. 25, the gate of the eighth transistor T8 is also connected to the first scan signal S1, so that it shares the first scan line with the gate of the second transistor T2. Fig. 27 is a schematic diagram of the drive timing sequence of another pixel circuit provided by an embodiment of the present application, which is used for the Fig. The pixel circuit shown in section 25 is suitable, with the first scan line being multiplexed as the fourth scan line.

[0136] In the write frame during the initialization phase t1, the first scan signal S1 is conducting, for example, a high level; the third scan signal S3 is off, for example, a low level; the first LED control signal EM1 is off, for example, a low level; and the second LED control signal EM2 is off, for example, a low level. Therefore, the second transistor T2 and the eighth transistor T8 are conducting. The initialization voltage Vref is applied via the eighth transistor T8 to the first electrode of LED D1, thus initializing the first electrode of LED D1. Since the sixth transistor T6 is off, even with the second transistor T2 conducting, the potential of the first transistor T1's gate is not affected.

[0137] During the data write phase t3, the first scan signal S1 is at a conducting level, for example, a high level; the third scan signal S3 is at a conducting level, for example, a high level; the first LED control signal EM1 is at a cutoff level, for example, a low level; and the second LED control signal EM2 is at a cutoff level, for example, a low level. Therefore, the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are conducting. While the data voltage Vdata is being written to the gate of the first transistor T1, the first electrode of the LED D1 is simultaneously initialized via the eighth transistor T8.

[0138] The work process of the other stages can be described accordingly in the drive time sequence according to the Fig. 26 refers to this, and is not repeated. The pixel circuit provided in this embodiment also exhibits the advantageous effects described in the aforementioned embodiments.

[0139] Through experimental validation by the inventors, it was determined that the data voltage Vdata lies in the range of 1–7 V. The pixel circuitry, arbitrarily provided in the aforementioned embodiments, can cover the driver current for the grayscale levels from 0 to 255, thus enabling an advantageous expansion of the grayscale levels.

[0140] The pixel circuit driving method provided in this embodiment can be used to drive the pixel circuits provided in any embodiment. Fig. 28 is a flowchart of a drive method of another pixel circuit provided by an embodiment of the present application. With reference to Fig. 28 The pixel circuitry driving process includes the following: S110: During the initialization phase, a fixed voltage is applied to the coupling module. S120: During the compensation phase, the compensation module is controlled to compensate for the threshold voltage of the driver module. S130: During the data writing phase, a data voltage is supplied to the coupling module, whereby the coupling module is controlled to couple the voltage with the information of the data voltage via the compensation module to the control terminal of the driver module.

[0141] In this embodiment of the present application, the pixel circuit drive method controls the compensation module during the compensation phase such that the compensation module compensates the threshold voltage of the driver module based on the voltage at the first terminal of the driver module after discharge by the driver module. During the data write phase, the signal supply source is controlled so that the voltage transmitted to the first terminal of the coupling module is switched from a fixed voltage to the data voltage. The data voltage is coupled via the coupling module to the control terminal of the driver module via the compensation module, thereby writing the data voltage. In this solution, the threshold compensation of the driver module and the data writing do not occur simultaneously.Threshold compensation is therefore performed before the data voltage is written to the control pin of the driver module, ensuring that the compensation phase and the data write phase do not interfere with each other. This prevents the time required for threshold compensation from being affected by the data write phase. Even at high refresh rates, the threshold voltage of the driver module can be fully compensated, reducing differences in the characteristics of the driver modules of different pixels. This contributes to improved brightness variations and increased uniformity of image quality.

[0142] With reference to Fig. 19 The pixel circuit further optionally includes a second initialization module 180 and a light module 150, wherein the drive method further includes the following: wherein at least in the compensation phase the second initialization module 180 is controlled to transmit the initialization voltage Vref to the first terminal of the light module 150.

[0143] Optionally, the pixel circuit includes a data write module 121 and a first initialization module 122. Fig. 29 is a flowchart of a drive method of another pixel circuit provided by an embodiment of the present application. With reference to Fig. 28 and Fig. Step S110, number 29, continues to include the following: S1101: During the initialization phase, the first initialization module is controlled to supply a fixed voltage to the first terminal of the coupling module, the second initialization module is controlled to transfer the second initialization voltage to the first terminal of the lighting module, and the compensation module is controlled to transfer the potential of the first terminal of the driver module to the control terminal of the driver module.

[0144] In particular, step S120 includes the following: S1201: During the compensation phase, the compensation module is controlled to compensate the threshold voltage of the driver module based on the voltage at the first terminal of the driver module after discharge at the driver module and second initialization module, whereby the first initialization module is controlled to continue to transmit a fixed voltage to the first terminal of the coupling module.

[0145] Specifically, the first terminal of the driver module is controlled to discharge via the driver module, the second lighting control module, and the second initialization module until the driver module is switched off. The compensation module transfers the voltage remaining at the first terminal of the driver module after discharge to the control terminal of the driver module to compensate for the threshold voltage of the driver module.

[0146] In particular, step S130 includes the following: S1301: During the data write phase, the data write module is controlled to supply a data voltage to the first terminal of the coupling module, the coupling module is controlled to couple the voltage with the information of the data voltage via the compensation module to the control terminal of the driver module, and the second initialization module is controlled to transfer the initialization voltage to the first terminal of the light module.

[0147] Fig. 30 is a flowchart of a drive method of another pixel circuit provided by an embodiment of the present application. With reference to Fig. According to step 30, the process after step S 130 continues to include the following: S140: During the illumination phase, the driver module is controlled to illuminate the lighting module based on the voltage at its own control terminal.

[0148] The pixel circuit drive method provided in this embodiment can be used to drive the pixel circuits described in the aforementioned embodiments. Therefore, the pixel circuit drive method also exhibits the advantageous effects described in the aforementioned embodiments.

[0149] The present application further provides a display panel comprising the pixel circuitry described in the aforementioned embodiments. This display panel thus also exhibits the advantageous effects described in those embodiments. Fig. Figure 31 shows a schematic representation of the structure of a display panel according to the present embodiment. In this embodiment, the display panel 200 can be used in mobile phones, as well as in any electronic products with a display function, including, but not limited to, the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, vehicle displays, medical devices, industrial control devices, touch interaction terminals, etc. The present embodiment does not further restrict this.

[0150] It should be understood that the various forms of processes described above can be used to rearrange, add, or remove steps. For example, the individual steps described in this application can be executed in parallel, sequentially, or in a different order, as long as the desired result of the technical solution of this application is achieved; no restriction is imposed here.

[0151] The embodiments mentioned above do not constitute a limitation of the scope of protection of this application. Depending on design requirements and other factors, various modifications, combinations, partial combinations, and substitutions may be made. Any changes, equivalent substitutions, and improvements made in the spirit and according to the principles of this application are also included within the scope of protection of this application. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] CN 202310637058.6

[0001] CN 202311282413.9

[0001]

Claims

[1] Pixel circuit comprising: a driver module, a signal source, a compensation module and a coupling module; wherein the compensation module is configured to compensate for the threshold voltage of the driver module during the compensation phase; wherein the signal source provides a fixed voltage to the coupling module during the initialization phase and supplies a data voltage to the coupling module during the data write phase, wherein the coupling module is configured to couple the voltage with the data voltage information via the compensation module to the control terminal of the driver module, wherein the data write phase occurs after the compensation phase. [2] Pixel circuit according to claim 1, wherein the start of the data writing phase is after the connection of the compensation phase. [3] Pixel circuit according to claim 1, wherein it further comprises a second initialization module, wherein the second initialization module is configured to discharge the first terminal of the driver module via the driver module and the second initialization module during the compensation phase, wherein the compensation module is configured to compensate the threshold voltage of the driver module during the compensation phase based on the voltage measured after the discharge of the first terminal of the driver module. [4] Pixel circuit according to claim 3, further comprising a first lighting control module and a second lighting control module, wherein the first lighting control module is configured to transfer the first supply voltage to the first terminal of the driver module during the initialization phase and the lighting phase; wherein the second lighting control module is configured to transfer the voltage at the first terminal of the driver module to the second initialization module in order to perform a discharge during the compensation phase; wherein the second lighting control module is further configured to transfer the driver current generated by the driver module to the lighting module during the lighting phase. [5] Pixel circuit according to claim 3, further comprising a light module: wherein the second initialization module is further configured to transmit an initialization voltage to the lighting module at least during the initialization phase; and / or wherein the pixel circuit further comprises a memory module, wherein the memory module is configured to store the voltage between the control terminal of the driver module and the first terminal of the light module. [6] Pixel circuit comprising: a driver module, a signal source, a compensation module and a coupling module; wherein the compensation module is connected between the control terminal and the first terminal of the driver module and is configured to compensate for the threshold voltage of the driver module; wherein the coupling module is connected between the first terminal of the driver module and the signal source, wherein the signal source is configured to provide a fixed voltage and a data voltage, and wherein the coupling module is configured to couple the voltage containing the data voltage information to the control terminal of the driver module via the compensation module. [7] Pixel circuit according to claim 6, further comprising a first light control module, a second light control module and a light module; wherein the first light control module is connected between the first supply voltage terminal and the first terminal of the driver module, wherein the second light control module is connected between the second terminal of the driver module and the first terminal of the light module, wherein the second terminal of the light module is connected to the second supply voltage terminal; wherein the control terminal of the first light control module is connected to the first light control signal line, wherein the control terminal of the second light control module is connected to the second light control signal line. [8] Pixel circuit according to claim 7, further comprising a second initialization module, wherein the second initialization module is connected between the initialization signal line and the first terminal of the light module, wherein the control terminal of the second initialization module is connected to the third scan line: wherein the control port of the compensation module is connected to the first scan line; and / or wherein the control port of the compensation module is connected to the third scan line; and / or wherein the pixel circuit further comprises a memory module, wherein the memory module is configured such that the memory module is connected between the control port of the driver module and the first port of the light module. [9] Pixel circuit according to claim 8, wherein the driver module comprises a first transistor, wherein the first lighting control module comprises a fourth transistor, wherein the second lighting control module comprises a fifth transistor, and wherein the lighting module comprises a light-emitting diode: wherein the gate of the fourth transistor is connected to the first light control signal line, wherein the first terminal of the fourth transistor is connected to the first supply voltage terminal, wherein the second terminal of the fourth transistor is connected to the first terminal of the first transistor, wherein the second terminal of the first transistor is connected to the first terminal of the fifth transistor, wherein the second terminal of the fifth transistor is connected to the first terminal of the LED, wherein the second terminal of the LED is connected to the second supply voltage terminal, wherein the gate of the fifth transistor is connected to the second light control signal line; and / or wherein the coupling module comprises a first capacitor, wherein the compensation module comprises a sixth transistor, and wherein the second initialization module comprises a seventh transistor;wherein the first electrode of the first capacitor is connected to the signal source, wherein the second electrode of the first capacitor is connected to the first terminal of the first transistor, wherein the first terminal of the sixth transistor is connected to the first terminal of the first transistor, wherein the second terminal of the sixth transistor is connected to the gate of the first transistor, wherein the gate of the sixth transistor is connected to the first scan line, wherein the first terminal of the seventh transistor is connected to the initialization signal line, wherein the second terminal of the seventh transistor is connected to the first terminal of the LED, wherein the gate of the seventh transistor is connected to the third scan line; and / or; wherein the storage module includes a second capacitor, wherein the first electrode of the second capacitor is connected to the control terminal of the driver module, and wherein the second electrode of the second capacitor is connected to the first terminal of the lighting module. [10] Pixel circuit comprising: a driver module, a voltage writing module, a compensation module and a coupling module; wherein the compensation module is connected between the control terminal and the first terminal of the driver module and is configured to compensate for the threshold voltage of the driver module; wherein the coupling module is connected between the first terminal of the driver module and the voltage write module, wherein the voltage write module is configured to output a fixed voltage and a data voltage to the coupling module, wherein the coupling module is configured to couple the voltage containing the data voltage information to the control terminal of the driver module via the compensation module. [11] Pixel circuit according to claim 10, wherein the control terminal of the voltage write module is connected to the first scan line, wherein the first terminal of the voltage write module is connected to the data line, wherein the second terminal of the voltage write module is connected to the first terminal of the coupling module, wherein the second terminal of the coupling module is connected to the first terminal of the driver module; wherein the data line is configured such that it transmits the fixed voltage at least during the compensation phase and transmits the data voltage during the data write phase. [12] Pixel circuit according to claim 10, further comprising a first light control module, a second light control module and a light module; wherein the first light control module is connected between the first supply voltage terminal and the first terminal of the driver module, wherein the second light control module is connected between the second terminal of the driver module and the first terminal of the light module, wherein the second terminal of the light module is connected to the second supply voltage terminal; wherein the control terminal of the first light control module is connected to the first light control signal line, wherein the control terminal of the second light control module is connected to the second light control signal line. [13] Pixel circuit according to claim 12, further comprising a second initialization module, wherein the second initialization module is connected between the initialization signal line and the first terminal of the light module, wherein the control terminal of the second initialization module is connected to the third scan line, wherein the second initialization module is configured to control the first terminal of the driver module via the discharge of the driver module; wherein the control port of the compensation module is connected to the third scan line; and / or wherein the control terminal of the compensation module is connected to the first scan line, as is the control terminal of the voltage record module; and / or wherein the pixel circuit further comprises a memory module, wherein the memory module is configured such that the memory module is connected between the control port of the driver module and the first port of the light module. [14] Pixel circuit according to claim 13, wherein the driver module comprises a first transistor, wherein the first terminal of the first transistor forms the first connection of the driver module, wherein the second terminal of the first transistor forms the second connection of the driver module, wherein the gate of the first transistor represents the control connection of the driver module, wherein the voltage write module comprises a second transistor, wherein the coupling module comprises a first capacitor, wherein the gate of the second transistor is connected to the first scan line, wherein the first terminal of the second transistor is connected to the data line, wherein the second terminal of the second transistor is connected to the first electrode of the first capacitor, wherein the second electrode of the first capacitor is connected to the first terminal of the first transistor; and / or wherein the first lighting control module comprises a fourth transistor, wherein the second lighting control module comprises a fifth transistor, wherein the lighting module comprises a light-emitting diode (LED), wherein the gate of the fourth transistor is connected to the first lighting control signal line, wherein the first terminal of the fourth transistor is connected to the first supply voltage terminal, wherein the second terminal of the fourth transistor is connected to the first terminal of the driver module, wherein the first terminal of the fifth transistor is connected to the second terminal of the driver module, wherein the second terminal of the fifth transistor is connected to the first terminal of the LED, wherein the second terminal of the LED is connected to the second supply voltage terminal, and wherein the gate of the fifth transistor is connected to the second lighting control signal line; and / or wherein the storage module comprises a second capacitor, wherein the first electrode of the second capacitor is connected to the control terminal of the driver module, and wherein the second electrode of the second capacitor is connected to the first terminal of the lighting module;and / or wherein the compensation module comprises a sixth transistor, wherein the second initialization module comprises a seventh transistor, wherein the gate of the sixth transistor serves as the control terminal of the compensation module, wherein the first terminal of the sixth transistor is connected to the first terminal of the driver module, wherein the second terminal of the sixth transistor is connected to the control terminal of the driver module, wherein the control terminal of the seventh transistor is connected to the third scan line, wherein the first terminal of the seventh transistor is connected to the initialization signal line, and wherein the second terminal of the seventh transistor is connected to the first terminal of the light module. [15] Pixel circuit comprising: a driver module, a data write module, a first initialization module, a compensation module and a coupling module; wherein the compensation module is connected between the control terminal and the first terminal of the driver module and is configured to compensate for the threshold voltage of the driver module; where the data write module and the first initialization module are connected to the first node; wherein the coupling module is connected between the first terminal of the driver module and the first node, wherein the first initialization module is configured to transmit a fixed voltage to the coupling module, wherein the coupling module is configured to couple the voltage transmitted by the data write module with the data voltage information via the compensation module to the control terminal of the driver module. [16] Pixel circuit according to claim 15, wherein the data write module comprises a second transistor, wherein the gate of the second transistor is connected to the first scan line, wherein the first terminal of the second transistor is connected to the data line, and wherein the second terminal of the second transistor is connected to the first node; wherein the first initialization module comprises a third transistor, wherein the gate of the third transistor is connected to the second scan line, and wherein the first terminal of the third transistor is connected to the fixed voltage, and wherein the second terminal of the third transistor is connected to the first node. [17] Pixel circuit according to claim 16, further comprising a first light control module and a second light control module; wherein the first light control module is connected between the first supply voltage terminal and the first terminal of the driver module, wherein the second light control module is connected between the second terminal of the driver module and the first terminal of the light module, wherein the second terminal of the light module is connected to the second supply voltage terminal; wherein the control terminal of the first light control module is connected to the first light control signal line, wherein the control terminal of the second light control module is connected to the second light control signal line. [18] Pixel circuit according to claim 16, wherein the control terminal of the compensation module is connected to the third scan line: wherein the pixel circuit further comprises a second initialization module, wherein the control terminal of the second initialization module is connected to the third scan line, wherein the first terminal of the second initialization module is connected to the initialization signal line, wherein the second terminal of the second initialization module is connected to the first terminal of the light module, and wherein the second initialization module is configured to transfer the initialization voltage from the initialization signal line to the first terminal of the light module; and / or wherein the pixel circuit further comprises a second initialization module, wherein the control terminal of the second initialization module is connected to the fifth scan line, wherein the first terminal of the second initialization module is connected to the initialization signal line, wherein the second terminal of the second initialization module is connected to the first terminal of the light module, wherein the second initialization module is configured to transfer the initialization voltage from the initialization signal line to the first terminal of the light module. [19] Pixel circuit according to claim 16, wherein the pixel circuit further comprises a light module, wherein the driver module and the light module are connected between the first supply voltage terminal and the second supply voltage terminal, wherein the driver module is configured to drive the light module to light up; and / or wherein the pixel circuit further comprises a light module, wherein the driver module and the light module are connected between the first supply voltage terminal and the second supply voltage terminal, wherein the first supply voltage applied to the first supply voltage terminal is identical to the fixed voltage; and / or wherein the pixel circuit further comprises a first light control module and a second light control module, wherein the control terminal of the first light control module is connected to the first light control signal line, wherein the control terminal of the second light control module is connected to the second light control signal line, wherein the second light control signal line is multiplexed as a second scan line; and / or wherein the pixel circuit further comprises a light module, wherein the driver module and the light module are connected between the first supply voltage terminal and the second supply voltage terminal, wherein the pixel circuit further comprises a first light control module and a second light control module, wherein the control terminal of the first light control module is connected to the first light control signal line, wherein the control terminal of the second light control module is connected to the second light control signal line, wherein the driver module comprises a first transistor, wherein the first light control module comprises a fourth transistor, wherein the second light control module comprises a fifth transistor, and wherein the light module comprises a light-emitting diode;wherein the gate of the fourth transistor is connected to the first light control signal line, wherein the first terminal of the fourth transistor is connected to the first supply voltage terminal, wherein the second terminal of the fourth transistor is connected to the first terminal of the first transistor, wherein the second terminal of the first transistor is connected to the first terminal of the fifth transistor, wherein the second terminal of the fifth transistor is connected to the first terminal of the LED, wherein the second terminal of the LED is connected to the second supply voltage terminal, wherein the gate of the fifth transistor is connected to the second light control signal line; and / or; wherein the pixel circuit further comprises a light module, a second initialization module, and a third initialization module, wherein the first terminal of the second initialization module is connected to the initialization signal line, wherein the control terminal of the third initialization module is connected to the fourth scan line, wherein the first terminal of the third initialization module is connected to the initialization signal line, wherein the second terminal of the third initialization module is connected to the first terminal of the light module, wherein the third initialization module is configured to transfer the initialization voltage from the initialization signal line to the first terminal of the light module within a write frame of a display cycle, and to transfer the initialization voltage to the first terminal of the light module within a hold frame of the same display cycle; and / or wherein the pixel circuit further comprises a second initialization module, wherein the control terminal of the compensation module is connected to the third scan line, wherein the control terminal of the second initialization module is connected to the third scan line, wherein the first terminal of the second initialization module is connected to the initialization signal line, wherein the compensation module comprises a sixth transistor, wherein the second initialization module comprises a seventh transistor, wherein the gate of the sixth transistor and the gate of the seventh transistor are each connected to the third scan line, wherein the first terminal of the sixth transistor is connected to the first terminal of the driver module, wherein the second terminal of the sixth transistor is connected to the control terminal of the driver module, and wherein the first terminal of the seventh transistor is connected to the initialization signal line.wherein the second terminal of the seventh transistor is connected to the first terminal of the light module; and / or, wherein the pixel circuit further comprises a second initialization module and a third initialization module, wherein the first terminal of the second initialization module is connected to the initialization signal line, wherein the control terminal of the third initialization module is connected to the fourth scan line, wherein the third initialization module comprises an eighth transistor, wherein the gate of the eighth transistor is connected to the fourth scan line, wherein the first terminal of the eighth transistor is connected to the initialization signal line, and wherein the second terminal of the eighth transistor is connected to the first terminal of the light module; and / or wherein the pixel circuit further comprises a third initialization module, wherein the control terminal of the third initialization module is connected to the fourth scan line, the first scan line being multiplexed as the fourth scan line; and / or wherein the pixel circuit further comprises a memory module, wherein the memory module is configured such that the memory module is connected between the control terminal of the driver module and the first terminal of the light module, wherein the memory module comprises a second capacitor, wherein the first electrode of the second capacitor is connected to the control terminal of the driver module, and wherein the second electrode of the second capacitor is connected to the first terminal of the light module. [20] Pixel switching drive methods, including: where a fixed voltage is applied to the coupling module during the initialization phase; in which, during the compensation phase, the compensation module is controlled to compensate for the threshold voltage of the driver module; wherein in the data writing phase a data voltage is supplied to the coupling module, whereby the coupling module is controlled to couple the voltage with the information of the data voltage via the compensation module to the control terminal of the driver module. [21] Driving method of the pixel circuit according to claim 20, wherein the pixel circuit further comprises a second initialization module and a light module, wherein at least in the compensation phase the second initialization module is controlled to transfer the initialization voltage to the first terminal of the light module. [22] Driving method of the pixel circuit according to claim 21, wherein The control of the compensation module for compensating the threshold voltage of the driver module comprises the following: wherein the compensation module compensates the threshold voltage of the driver module based on the voltage at the first terminal of the driver module after discharge by the driver module and the second initialization module; and / or wherein, during the data writing phase, the pixel circuit drive procedure further comprises the following: control of the second initialization module to transfer the initialization voltage to the first terminal of the light module; and / or the driving method further includes: controlling the driver module in the lighting phase to make the lighting unit light up based on the voltage at its own control terminal. [23] Driving method of the pixel circuit according to claim 22, wherein the pixel circuit further comprises a data write module and a first initialization module: where providing a fixed voltage to the coupling module includes: controlling the first initialization module to provide a fixed voltage to the first terminal of the coupling module; where providing a data voltage to the coupling module includes: controlling the data write module to provide a data voltage to the first terminal of the coupling module; and / or wherein the pixel circuit drive method in the initialization phase further comprises: control of the second initialization module to transfer the initialization voltage to the first terminal of the light module, and control of the compensation module to transfer the potential of the first terminal of the driver module to the control terminal of the driver module; and / or wherein the driving procedure of the pixel circuit in the compensation phase further includes the following: control of the first initialization module for the continued transmission of the fixed voltage to the first terminal of the coupling module. [24] Display panel comprising a pixel circuit according to any one of claims 1-19.

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