Selective gate override of a transistor

Abstract

Overdriving a power field-effect transistor (PFT). In response to a detection that the PFT has entered the saturation region, the gate node of the PFT is overdriven with a higher voltage. Detection of whether the PFT is within the saturation region is performed by a sensing PFT. This sensing PFT uses the same epitaxial stack of semiconductor layers as the PFT. That is, the PFT comprises a portion of an epitaxial stack of semiconductor layers that features a heterojunction between at least two adjacent semiconductor layers, and the sensing PFT comprises another portion of this same epitaxial stack of semiconductor layers.

Description

BACKGROUND OF THE INVENTION

[0001] Electronic circuits typically include transistors, which act as electronic switches to regulate or control the flow of current in sections of the circuit. One type of transistor is a field-effect transistor (FET), in which a voltage is applied to a gate terminal to turn the transistor on and off. A semiconductor channel region is located between the drain and source terminals. When the transistor is on, current flows through the semiconductor channel region between the source and drain terminals. When the transistor is off, negligible or no current flows through the semiconductor channel region between the source and drain terminals. The gate terminal is located above the semiconductor channel region between the source and drain terminals. A voltage applied to the gate terminal creates a field that affects whether the semiconductor channel region conducts current—hence the term "field-effect transistor."

[0002] Ordinary transistors are used for amplification and switching purposes. Power transistors, on the other hand, are used to conduct larger currents and have higher voltage ratings. They are typically used in power supplies, battery charging, and similar applications. Power transistors can typically handle currents from more than 1 ampere up to 100 amperes or even more. Power transistors can also deliver power from more than 1 watt up to hundreds of watts or more.

[0003] Semiconductor power transistors typically operate in the linear region, where the current flowing between the drain and source terminals is approximately proportional to the voltage between the drain and source terminals. In other words, in the linear region, semiconductor power transistors exhibit a relatively constant resistance. This constant resistance is called the "on-resistance" and is a characteristic property of a field-effect transistor. However, when the transistor enters a saturation operating region, the drain-source voltage VDS(on) can increase significantly. DS with increases in drain current i D increase dramatically. In other words, the on-resistance increases in the saturation operating region. This means that the power dissipated by the field-effect transistor (the V) increases dramatically. DS × i D is consumed, with increases in drain current i D, when it is in the saturation region, it can increase significantly. This can generate excessive heat in the transistor.

[0004] The subject matter claimed herein is not limited to embodiments that overcome any disadvantages or that operate only in environments such as those described above. Rather, this background is provided only to illustrate an exemplary technological field in which some embodiments described herein may be practiced. BRIEF SUMMARY OF THE INVENTION

[0005] At least some embodiments described herein relate to a circuit for overdriving a power field-effect transistor. Semiconductor power field-effect transistors typically operate in the linear region, where the current conducted between the drain and source nodes is approximately proportional to the voltage between the drain and source nodes. In other words, the semiconductor power transistor exhibits a relatively constant resistance in the linear region. This constant resistance is called the "on-resistance" and is a characteristic property of a field-effect transistor. However, when the transistor enters a saturation operating region, the drain-source voltage VDS(on) can increase significantly. DS with increases in drain current I DS increase dramatically. In other words, the on-resistance increases in the saturation operating region. This means that the power dissipated by the field-effect transistor (the V) increases dramatically.DS × I DS is consumed, with increases in drain current I DS , when it is in the saturation region, it can increase significantly. This can generate excessive heat in the transistor.

[0006] According to the principles described herein, in response to a detection that the power field-effect transistor has entered the saturation region, the gate node of the power field-effect transistor is overdriven with a higher voltage. For any given gate voltage applied to the gate node of a field-effect transistor, the transistor will exhibit a different current-voltage curve. The higher the applied gate voltage, the more current the transistor can conduct in the linear region before entering the saturation region. Thus, overdriving the gate voltage has the effect of forcing the power field-effect transistor out of the saturation region and back into the linear region.While such overdriving involves increasing the gate voltage to more than the voltage at which the transistor can operate for extended periods, overdriving for shorter periods can be performed with minimal risk of damaging the transistor.

[0007] Furthermore, according to the principles described herein, the detection of whether the power field-effect transistor is within the saturation region is performed using a detection field-effect transistor. This detection field-effect transistor uses the same epitaxial stack of semiconductor layers as the power field-effect transistor. That is, the power field-effect transistor comprises a portion of an epitaxial stack of semiconductor layers that has a heterojunction between at least two adjacent semiconductor layers, and the detection field-effect transistor comprises another portion of this same epitaxial stack of semiconductor layers. Thus, the detection field-effect transistor can be fabricated at the same time as the power field-effect transistor using the same semiconductor processing steps.Furthermore, the sensing field-effect transistor exhibits the same ability to handle high drain voltages and can therefore share a drain node with the power field-effect transistor. Moreover, the sensing field-effect transistor more closely reflects the operating state of the power field-effect transistor (at smaller current scales). Thus, the use of the sensing current field-effect transistor, which employs the same epitaxial stack as the power field-effect transistor, enables accurate saturation detection at high voltages without introducing significant semiconductor processing complexity.

[0008] This summary is provided to introduce, in a simplified form, a selection of concepts that are further described in detail below. This summary is not intended to identify key features or essential characteristics of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To describe how the advantages and features of the systems and methods described herein can be obtained, a more detailed description of the embodiments briefly described above is given by reference to specific embodiments illustrated in the accompanying drawings. Under the understanding that these drawings represent only typical embodiments of the systems and methods described herein and are therefore not to be considered as limiting their scope, certain systems and methods are described and explained with additional specificity and detail by means of the accompanying drawings, in which: Fig. 1. A graphical representation of various current-voltage curves for different applied gate-source voltages V GS illustrated for a given power field-effect transistor; Fig. 2 illustrates a cross-sectional view of a semiconductor structure that has an epitaxial stack grown epitaxially on a substrate; Fig. Figure 3 illustrates a cross-sectional view of a semiconductor structure, which is the same as the semiconductor structure of Fig. 2 is, however, in a subsequent stage of processing, after two transistors have been formed; Fig. Figure 4 illustrates a top view of a finger array that includes a power field-effect transistor and a detection field-effect transistor; Fig. 5 illustrates an exemplary circuit for overdriving a power field-effect transistor according to the principles described herein; Fig. 6A illustrates an exemplary circuit that includes a power field-effect transistor and a detection field-effect transistor, wherein the detection field-effect transistor is connected in a diode configuration, with the gate node connected to the source node; Fig. Figure 6B illustrates an exemplary circuit that includes the power field-effect transistor and a detection field-effect transistor, with the gate nodes of the field-effect transistor and the detection field-effect transistor connected; Fig. Figure 7 illustrates a circuit that is an example of the circuit of Fig. 5 represents and in which the detection transistor is connected in a diode configuration; Fig. Figure 8 illustrates a circuit that is an example of the circuit of Fig. 5 represents and in which the detection transistor shares a gate with the power transistor; Fig. Figure 9 illustrates a circuit that is an extension of the circuit of Fig. 7, but with additional elements that work to perform desaturation by switching off the power transistor (with a certain delay) when the voltage becomes higher than a desaturation voltage; Fig. 10 illustrates a circuit that is an extension of the circuit of Fig. 8 represents, but with additional elements that work to perform desaturation by switching off the power transistor (with a certain delay) when the voltage becomes higher than a desaturation voltage; Fig. 11 shows a table listing exemplary data that includes a load condition, peak current, duty cycle and half-cycle operating waveforms for the operation of a dead-pole bridgeless PFC (power factor converter) for a range of load conditions; Fig. 12 another schematic graphical representation of an operating waveform for drain current I D vs. time for a half cycle is shown to illustrate the relative operating share during standby, light to medium load and full load; Fig. 13 a schematic graphical representation of the gate driver voltage V GS vs. time over a corresponding half-cycle for the operation of a gate driver that provides a selective gate voltage overdrive of a first exemplary embodiment; Fig. 14 shows a schematic graphical representation of the gate driver voltage vs. time over a corresponding half-cycle for the operation of a gate driver providing selective gate voltage overdrive of a second exemplary embodiment; Fig. 15A first exemplary schematic waveforms illustrated; Fig. 15B illustrates a second exemplary schematic waveform; and Fig. Figure 16 illustrates a flowchart of a procedure for overdriving a power field-effect transistor according to the principles described herein. DETAILED DESCRIPTION OF THE INVENTION

[0010] At least some embodiments described herein relate to a circuit for overdriving a power field-effect transistor. Semiconductor power field-effect transistors typically operate in the linear region in which the current conducted between the drain and source nodes (as I) DS (referred to as V) approximately proportional to the voltage between the drain and source nodes. DS(designated) In other words, the semiconductor power transistor exhibits a relatively constant resistance in the linear region. This constant resistance is called the "on-resistance" and is a characteristic property of a field-effect transistor. However, when the transistor enters a saturation operating region, the drain-source voltage V can DS with increases in drain current I DS increase dramatically. In other words, the on-resistance increases in the saturation operating region. This means that the power dissipated by the field-effect transistor (the V) increases dramatically. DS × I DS is consumed, with increases in drain current I DS , when it is in the saturation region, it can increase significantly. This can generate excessive heat in the transistor and thereby cause damage to the transistor.

[0011] According to the principles described herein, in response to a detection that the power field-effect transistor has entered the saturation region, the gate node of the power field-effect transistor is overdriven with a higher voltage. For any given gate-source voltage applied to the gate node of a field-effect transistor, the transistor will exhibit a different current-voltage curve. For example, illustrates Fig. 1. A graphical representation of 100 different current-voltage curves 101 to 105 for different applied gate-source voltages V GS For a given power field-effect transistor, the current (in amperes) between the drain and the source is called I. DS The voltage (in volts) between the drain and the source is represented on the vertical axis. DS shown on the horizontal axis. For each given curve 101 to 105, when the voltage V is applied, the following occurs: DS increasing from zero, the current IDS Initially, the curve increases linearly, but then it flattens out and converges to a maximum saturation current.

[0012] Compared to curve 101 to curve 105, when the gate-source voltage V GS As the current increases, so does the maximum saturation current. For example, for this particular power field-effect transistor with the characteristic curves of Fig. 1, if the gate-source voltage V GS At 6 volts, the saturation current is between 140 and 150 amperes. By increasing the gate-source voltage V GS However, at 8 volts, the saturation current is significantly higher at approximately 180 amperes.

[0013] It should be noted that a certain current I DS the saturation region for a lower gate-source voltage V GS may correspond, but a linear operating range for a higher gate-source voltage V GS This can correspond to, for example, the following: Fig. 1. At a current of 120 amperes, the transistor is at its operating threshold in saturation when the gate-source voltage V is GS 6 volts (see point 111), but is clearly in the linear range when operating at the same current of 120 amperes, but with a gate-source voltage V GS operates at 8 volts (see point 112). Fig. Figure 1 is just one example for a specific field-effect transistor. The current-voltage curves will be different for each field-effect transistor. Nevertheless, the general principle is the same: a field-effect transistor operating at a given current will increase in output by increasing the gate-source voltage V. GS from the saturation range to the linear range.

[0014] The higher the applied gate voltage, the more current the transistor can conduct in the linear region before entering saturation. Accordingly, overdriving the gate voltage forces the power field-effect transistor out of saturation and back into the linear region. While such overdriving can raise the gate voltage above the voltage at which the transistor can operate for extended periods, it can be performed for shorter periods with minimal risk of transistor damage.

[0015] Furthermore, according to the principles described herein, the detection of whether the power field-effect transistor is within the saturation region is performed using a detection field-effect transistor. This detection field-effect transistor uses the same epitaxial stack of semiconductor layers as the power field-effect transistor. This improves the accuracy of saturation detection and also allows the detection transistor to operate at high voltages with only a slight increase in manufacturing complexity.

[0016] For example, it illustrates Fig. Figure 2 shows a cross-sectional view of a semiconductor structure 200, which has an epitaxial stack 214 that has grown epitaxially on a substrate 201. For example, the substrate 201 could be a silicon substrate, or perhaps sapphire or quartz. However, the substrate 201 could be any material on which the epitaxial stack 214 could have grown epitaxially. The substrate 201 could even be made of the same material as the bottom layer 211 of the epitaxial stack 214.

[0017] The epitaxial stack comprises a lower layer 211 and an upper layer 212, composed of semiconductor materials with different band gaps. Since the band gap of the lower layer 211 differs from the band gap of the upper layer 212, a heterojunction 213 exists between the lower layer 211 and the upper layer 212. A built-in potential difference at the heterojunction 213 is induced due to the difference between the band gap of the material forming the lower layer 211 and the band gap of the material forming the upper layer 212. The presence of a heterojunction 213 enables charge carrier control. Accordingly, transistors can be fabricated that utilize a portion of the epitaxial stack 214.

[0018] Other layers may be present within the epitaxial stack 214, which are in Fig. 2 are not shown. For example, layers may be present between the lower layer 211 and the substrate 201, acting as lattice relaxation layers that reduce mechanical stress due to differences between the lattice constants of the lower layer 211 and the substrate 201. However, the principles described herein are not limited to what other layers may be present. Accordingly, only the two layers 211 and 212, which define the heterojunction 213, are shown in the stack 214 in Fig. Figure 2 illustrates this. Although the lower layer 211 and the upper layer 212 are shown to have approximately the same thickness, this is not necessary. The stack can include layers of any thickness, as appropriate given the materials and design.

[0019] As mentioned previously, transistors can be fabricated that each utilize a portion of the epitaxial stack 214. The principles described herein are not limited to this type of transistor but can encompass any type of transistor that uses an epitaxial stack. An example of such a field-effect transistor is a high-electron mobility transistor (HEMT).Further examples of field-effect transistors include gallium nitride transistors, in which layer 211 is an active layer composed of gallium nitride; silicon carbide transistors, in which layer 211 is an active layer composed of silicon carbide; gallium arsenide transistors, in which layer 211 is an active layer composed of gallium arsenide; indium gallium arsenide transistors, in which layer 211 is an active layer composed of indium gallium arsenide; and indium aluminum arsenide transistors, in which layer 211 is an active layer composed of indium aluminum arsenide. The transistor can operate in an enrichment mode or a depletion mode. However, the principles described herein are not limited to the type of field-effect transistor that uses the epitaxial stack.Nevertheless, all transistors that use the same epitaxial stack are integrated on the same chip.

[0020] Fig. Figure 3 illustrates a cross-sectional view of a semiconductor structure 300, which is the same as the semiconductor structure 200 of Fig. 2, however, in a subsequent processing stage, after two transistors 301 and 302 have been formed. Each transistor 301 and 302 is formed from a corresponding part of the epitaxial stack 214. There may be other layers and components of these transistors 301 and 302, which are in Fig. Figure 3 is not illustrated, as the principles described herein are not limited to which other structures are present. For example, there may be overlying interconnect layers that link the transistor to its various nodes (source, gate, and drain), define the field plates, define the passivation structures that provide adequate electrical insulation and mechanical protection, and so on.

[0021] Whatever these structures may be, Fig. Figure 3 illustrates that the power field-effect transistor 301 incorporates part 314A of the original epitaxial stack 214, and the sensing field-effect transistor 302 incorporates another part 314B of the original epitaxial stack 214. That is, part 314A of the epitaxial stack incorporates part 311A ​​of the original lower layer 211 and part 312A of the original upper layer 212. Part 314A incorporates a heterojunction 313A between the lower layer part 311A ​​and the upper layer part 312A. The heterojunction 313A is used by transistor 301 to control the electrical flow through transistor 301. Similarly, part 314B of the epitaxial stack includes part 311B of the original lower layer 211 and part 312B of the original upper layer 212. Part 314B includes a heterojunction 313B between the lower layer part 311B and the upper layer part 312B.The heterojunction 313B is used by transistor 302 to control the electrical flow through transistor 302.

[0022] Transistor 301 is illustrated such that it has a larger portion of the epitaxial stack than transistor 302. Accordingly, transistor 301 can be a power field-effect transistor, and transistor 302 can be a sensing field-effect transistor. The principles described herein are not limited to the relative size between power field-effect transistor 301 and sensing field-effect transistor 302. However, power field-effect transistor 301 is larger than sensing field-effect transistor 302, which is shown in Fig. 3 is symbolized by the power field-effect transistor 301, which uses a portion 314A of the epitaxial stack that has a larger cross-sectional area than the portion 314B of the epitaxial stack used by the detection field-effect transistor 302. Accordingly, the power field-effect transistor comprises a portion of an epitaxial stack of semiconductor layers that has a heterojunction between at least two adjacent semiconductor layers, and the detection field-effect transistor comprises another portion of this same epitaxial stack of semiconductor layers.

[0023] Thus, the detection field-effect transistor can be manufactured at the same time as the power field-effect transistor using the same semiconductor processing steps. For example, the power field-effect transistor 301 can be the same type of transistor as the detection field-effect transistor 302. For instance, if the power field-effect transistor 301 is a high electron mobility transistor (HEMT), then the detection field-effect transistor 302 is a HEMT detection transistor. If the power field-effect transistor 301 is a gallium nitride power transistor, then the detection field-effect transistor 302 is a gallium nitride detection transistor. If the power field-effect transistor 301 is a silicon carbide power transistor, then the detection field-effect transistor 302 is a silicon carbide detection transistor.If power field-effect transistor 301 is a gallium arsenide power transistor, then detection field-effect transistor 302 is a gallium arsenide detection transistor. If power field-effect transistor 301 is an indium gallium arsenide power transistor, then detection field-effect transistor 302 is an indium gallium arsenide detection transistor. If power field-effect transistor 301 is an indium aluminum arsenide power transistor, then detection field-effect transistor 302 is an indium aluminum arsenide detection transistor. If power field-effect transistor 301 is an enhancement-mode power transistor, then detection field-effect transistor 302 is an enhancement-mode detection transistor. If the power field-effect transistor 301 is a depletion-mode power transistor, then the detection field-effect transistor 302 is a depletion-mode detection transistor.Regardless of the type of power field-effect transistor, the detection field-effect transistor is of the same type, but smaller. This means that the characteristics, such as the threshold voltages and current-voltage curves, can be the same for both the power field-effect transistor and the detection field-effect transistor (with the caveat that the detection field-effect transistor conducts lower currents).

[0024] The power field-effect transistor 301 can operate at high voltages, potentially with drain voltages exceeding 100 volts. Since the sensing field-effect transistor 302 is fabricated with the same materials, it can likewise operate at drain voltages exceeding 100 volts. Furthermore, the sensing field-effect transistor more closely reflects the operating state of the power field-effect transistor (at smaller current scales). Thus, using the sensing current field-effect transistor, which employs the same epitaxial stack as the power field-effect transistor, allows for accurate saturation detection at high voltages without introducing significant semiconductor processing complexity.

[0025] The power field-effect transistor and the detection field-effect transistor can, for example, be manufactured in the same finger array. This illustrates an example. Fig. Figure 4 shows a top view of a finger array 400, which includes a power field-effect transistor 401 and a detection field-effect transistor 402. The power field-effect transistor 401 can, for example, be the same as the power field-effect transistor 301 of Fig. 3. The detection field-effect transistor 402 can, for example, be the same as the detection field-effect transistor of Fig. 3. Metallization is illustrated using cross-hatching. The fingers are shown within a first subarray 431 and a second subarray 432.

[0026] The first subarray 431 contains numerous (34 in the example of Fig. 4) Fingers extending downwards from a source node 411A of a power field-effect transistor 401 (see, for example, finger 441), and numerous (33 in the example of Fig. 4) Fingers extending upwards from a drain node 412 (see, for example, finger 442). The drain node 412 is shared by the power field-effect transistor 401 and a sensing field-effect transistor 402.

[0027] The second subarray 432 contains numerous (33 in the example of Fig. 3) Fingers extending downwards from drain node 412. The second subarray 432 also includes numerous (34 in the example of Fig. 4) Fingers extending upwards. Specifically, in this example, 16 fingers extend upwards from source node 411B, and 16 fingers extend upwards from source node 411C. Only 2 fingers extend upwards from source 421. Source nodes 411A, 411B, and 411C are all connected and together form a source node of the power field-effect transistor 401. On the other hand, source 421 is the source node of the detection field-effect transistor 402. Gate node 413 is the gate of the power field-effect transistor 401. Gate node 423 is the gate of the detection field-effect transistor 402.

[0028] With reference to Fig. 4. Fingers extending from a source node are called "source fingers," and fingers extending from a drain node are called "drain fingers." In Fig. The source and drain fingers are nested. A cell consists of a single source finger and an adjacent drain finger. In each cell, current flows horizontally between the adjacent fingers of the cell. For example, current can flow in the underlying semiconductor channel between the source finger 411 and the drain finger 412.

[0029] The effective channel width is proportional to the number of source fingers connected to the respective source. Fig. There are 66 source fingers for the power field-effect transistor 401 and 2 source fingers for the detection field-effect transistor 402. The channel widths and gate widths are approximately equal, and thus the ratio of the gate width of the power field-effect transistor 401 to the gate width of the detection field-effect transistor 402 is approximately 33 (i.e., 66 / 2). The principles of the finger array can be extended to create an even larger finger array to generate even larger gate width ratios. For example, gate width ratios of more than 500 or even 1000 can be achieved. This can be accomplished by having only a single cell of a source finger and a drain finger for the detection field-effect transistor and by having hundreds or thousands of similar cells for the power field-effect transistor.

[0030] By placing the power field-effect transistor and the detection field-effect transistor in the same array, the operation of the power field-effect transistor can closely mirror the operation of the detection field-effect transistor in every respect except the scale of the current flowing through the channel region. Thus, it is likely that the detection field-effect transistor and the power field-effect transistor will enter the saturation region and the linear region at approximately the same time, especially when the drain nodes are split, as in Fig. 4 shown.

[0031] Fig. Figure 5 illustrates an exemplary circuit 500 for overdriving a power field-effect transistor according to the principles described herein. The circuit 500 includes a power field-effect transistor 501, a detection field-effect transistor 502, a saturation detection circuit 503, a gate overdrive circuit 504, and optionally a desaturation circuit 505. The power field-effect transistor 501 and the detection field-effect transistor 502 are represented as simple circles, which indicates that the principles described herein are not limited to the specific type of field-effect transistor the power field-effect transistor 501 and the detection field-effect transistor 502 are. Nevertheless, as mentioned above, the power field-effect transistor 501 comprises part of an epitaxial stack of semiconductor layers that has a heterojunction between at least two adjacent semiconductor layers.Furthermore, the sensing field-effect transistor 502 comprises another part of the epitaxial stack of semiconductor layers. Furthermore, as in . Fig. Figure 5 illustrates a drain node 511 of the power field-effect transistor 501 connected to a drain node 512 of the detection field-effect transistor 502.

[0032] Circuit 500 also includes the saturation detection circuit 503, the gate overdrive circuit 504, and optionally a desaturation circuit 505. The saturation detection circuit 503 is connected to the detection field-effect transistor 502 and is configured to detect an indication that the detection field-effect transistor 502 has entered saturation. The gate overdrive circuit 504 is connected to the saturation detection circuit to respond when the saturation detection circuit 503 detects that the detection field-effect transistor 502 is entering saturation. In particular, the gate overdrive circuit 504 is also connected to the power field effect transistor 501 and is configured to increase a gate voltage applied to a gate node of the power field effect transistor 501 in response to the saturation detection circuit 503 detecting that the detection field effect transistor 502 is entering saturation.The function of the desaturation circuit 505 is described further below in relation to the . Fig. 9 and Fig. 10. More specific examples of circuit 500 are given below in relation to the Fig. 7 to Fig. 10 provided.

[0033] In some of the example circuits below, the detection field-effect transistor is configured such that a gate node of the detection field-effect transistor is connected to a source node of the detection field-effect transistor. For example, illustrated Fig. Figure 6A shows an exemplary circuit 600A comprising a power field-effect transistor 601 and a detection field-effect transistor 602A, wherein the detection field-effect transistor is connected in a diode configuration with the gate node connected to the source node. In this diode configuration, the detection field-effect transistor 602A operates as a diode in the source-to-drain direction. The drain nodes of the power field-effect transistor 601 and the detection field-effect transistor 602A are shared. The power field-effect transistor 601 is an example of the power field-effect transistor 301 from Fig. 3, the power field-effect transistor 401 from Fig. 4 and the 501 power field-effect transistor from Fig. 5. The 602A field-effect sensing transistor is an example of the 302 field-effect sensing transistor. Fig. 3, the detection field-effect transistor 402 from Fig. 4 and the sensing field-effect transistor 502 from Fig. 5. In the configuration of Fig. In 6A, the 602A field-effect transistor acts as an embedded high-voltage sensing diode for measuring the drain-source voltage V. DS of the 601 power field-effect transistor.

[0034] In other embodiments, the detection field-effect transistor is connected in a shared-gate mode. For example, illustrates Fig. Figure 6B shows an exemplary circuit 600B, which includes the power field-effect transistor 601 and a detection field-effect transistor 602B, with the gate nodes of the field-effect transistor 601 and the detection field-effect transistor 602B connected. Again, the drain nodes of the power field-effect transistor 601 and the detection field-effect transistor 602B are shared. The detection field-effect transistor 602B is an example of the detection field-effect transistor 302. Fig. 3, the detection field-effect transistor 402 from Fig. 4 and the sensing field-effect transistor 502 from Fig. 5. In the configuration of Fig. 6B will be the drain-source voltage V DS the power field effect transistor 601 is measured by the detection field effect transistor 602B.

[0035] Fig. Figure 7 illustrates a circuit 700, which is an example of the circuit 500 from Fig. 5 represents. The circuit 700 includes a power field-effect transistor 701, a detection field-effect transistor 702, a saturation detection circuit 703, and a gate overdrive circuit 704, which are examples of the power field-effect transistor 501, the detection field-effect transistor 502, the saturation detection circuit 503, and the gate overdrive circuit 504 of Fig. There are 5. In circuit 700, the detection field-effect transistor is the same as in circuit 600A. Fig. 6A diode connected. The sensing field-effect transistor 702 and the power field-effect transistor 701 are integrated in that they use different parts of the same epitaxial stack.

[0036] The gate overdrive circuit 704 includes a gate voltage generator 741, which outputs a high gate signal (to turn on the power transistor 701) when the input signal 743 is high, and a low gate signal (to turn off the power transistor 701) when the input signal 743 is low. The gate voltage generator 741 has a high-voltage supply that is at one level (e.g., 6 volts) when the transistor 742 is off, and at another level (e.g., 8 volts) when the transistor 742 is on. Assuming that the input voltage 743 is high, a signal provided by the saturation detection circuit 703 to the gate of the transistor 742 selects whether the gate of the power field-effect transistor 701 is overdriven or not.

[0037] The saturation detection circuit 703 includes a comparator 731, which is configured to measure a voltage at the source node of the detection field-effect transistor 702 with a reference voltage V. ref to compare and output a signal representing saturation detection based on the comparison. The saturation detection circuit 703 also includes a clamping circuit comprising a DC voltage source 732 and a resistor 733 connected in series between the source node of the power transistor 701 and the source node of the sensing transistor 702. With the in Fig. In the sensing transistor arrangement shown in Figure 7, the sensing field-effect transistor 702 operates as a high-voltage diode, which may be integrated or embedded within the transistor package.

[0038] If the drain-source voltage V DSSince the voltage at the source (see point 750) of the sensing transistor 702 is lower than that of the DC voltage source 732, the sensing transistor 702 acts as a forward-biased diode, and thus the voltage at the source (see point 750) of the sensing transistor 702 (and at the positive input terminal of the comparator 731) is approximately equal to V DS plus a threshold voltage across the diode. Depending on the level of V DS Comparator 731 outputs a high or low signal. However, if the drain voltage is greater than that of the DC voltage source 733, the sensing transistor 702 acts as a reverse-biased diode, and thus the voltage at the positive input terminal of comparator 731 is clamped to the voltage provided by the DC voltage source 733. This clamped voltage is greater than what would indicate saturation in the power transistor 701. The reference voltage V refis selected to be the saturation voltage of the power transistor 701 (plus a threshold voltage across the diode 702).

[0039] Fig. Figure 8 illustrates a circuit 800, which is an example of the circuit 500 from Fig. 5 represents. The circuit 800 includes a power field-effect transistor 801, a detection field-effect transistor 802, a saturation detection circuit 803, and a gate overdrive circuit 804, which are examples of the power field-effect transistor 501, the detection field-effect transistor 502, the saturation detection circuit 503, and the gate overdrive circuit 504 of Fig. 5 are. In circuit 800, the detection field-effect transistor 802 shares a gate with the power field-effect transistor 80' as in circuit 600B of Fig. 6B. The 802 sensing field-effect transistor and the 801 power field-effect transistor are integrated in that they use different parts of the same epitaxial stack.

[0040] The gate overdrive circuit 804 is the same as above for the gate overdrive circuit 704 from Fig. The structure is described in Figure 7. The gate voltage generator 841 outputs a high gate signal (to turn on the power transistor 801) when the input signal 843 is high, and outputs a low gate signal (to turn off the power transistor 801) when the input signal 843 is low. The gate voltage generator 841 has a high-voltage supply that is at one level (e.g., 6 volts) when transistor 842 is off, and at another level (e.g., 8 volts) when transistor 842 is on. Thus, a signal provided by the saturation detection circuit 803 to the gate of transistor 842 selects whether the gate of the power field-effect transistor 801 is overdriven or not.

[0041] The saturation detection circuit 803 includes a voltage detection circuit 832, which measures the drain-source voltage V DSof the power transistor 801 by detecting the drain-source voltage V DS The voltage is detected at node 850 of the detection transistor 802. The comparator 831 receives this voltage V. DS at its positive input terminal and a reference voltage V ref at its negative input terminal. The reference voltage V ref is selected to be the saturation voltage of the power transistor 801.

[0042] If the voltage V DS lower than the reference voltage V ref If the input voltage V is high, comparator 831 outputs a low signal indicating that power transistor 801 is not in saturation, and consequently transistor 842 is off, meaning the gate voltage generator outputs a normal high voltage of 6 volts (assuming the input voltage 843 is high). On the other hand, if the voltage V DS higher than the reference voltage V refWhen this happens, the comparator 831 outputs a high signal indicating that the power transistor 801 is in saturation, and accordingly the transistor 842 is switched on, which means that the gate voltage generator outputs an overdrive voltage of 8 volts (assuming that the input voltage 843 is high).

[0043] Fig. Figure 9 illustrates a circuit 900, which is an extension of circuit 700 from Fig. 7, but with additional elements (labeled in the 900s) that work to perform desaturation by switching off the power transistor 701 (with a certain delay) when the voltage at node 750 is higher than a desaturation voltage V DESAT will be. Circuit elements of Fig. Seven, which are not necessary to describe the desaturation process, are in Fig. 7 omitted, although they may be present within the 900 circuit.

[0044] The desaturation voltage V DESAT is set by a divided voltage output from the voltage divider composed of resistors 901 and 902. The divided voltage is supplied to a negative input terminal of a comparator 911. Voltage at an intermediate node of an RC delay circuit 903 (comprising a series connection of a capacitor 904 and resistor 905) is supplied to the negative input terminal of the comparator 911. The voltage at this intermediate node follows the voltage at node 750 with a certain delay. The delay is introduced to allow the overdrive process of Fig. 7 has sufficient time to attempt to remove the power transistor from the saturation region. The delay is sufficient that, if the overdrive is unsuccessful within a reasonable time, the power transistor is just switched off by the operation of comparator 911. The amount of the delay can be adjusted by measuring capacitor 904 and / or resistor 905.

[0045] If the voltage at the intermediate node of the RC delay 903 is the desaturation voltage V DESATIf the threshold is exceeded, the gate overdrive of the power transistor was unsuccessful in removing the power transistor from saturation within a reasonable time. In this case, comparator 911 outputs a high signal, which is translated into a low signal by inverter 912. This low signal is supplied to the AND gate 913, which in turn supplies a low signal to the gate overdrive circuit 741, forcing the gate of power transistor 701 low, regardless of the input signal 743.

[0046] Thus, circuit 900 includes a desaturation circuit configured to turn off the power field-effect transistor when 1) the gate overdrive circuit has already increased the gate voltage applied to the gate node in response to a previous detection that the sensing field-effect transistor has entered saturation, 2) the saturation detection circuit again detects an indication that the sensing field-effect transistor has entered saturation, and 3) the gate overdrive circuit cannot further increase the gate voltage applied to the gate node of the power field-effect transistor.

[0047] Fig. Figure 10 illustrates a circuit 1000, which is an extension of circuit 800 from Fig. 8, but with additional elements (labeled in the 1000s) that work to perform desaturation by switching off the power transistor 801 (with a certain delay) when the voltage at node 850 is higher than a desaturation voltage V DESAT will be. Circuit elements of Fig. 8, which are not necessary to describe the desaturation process, are in Fig. 8 were omitted, although they may be present within circuit 1000. Circuit elements 1001, 1002, 1003, 1004, 1005, 1011, 1012, and 1013 operate in a similar manner to circuit elements 901, 902, 903, 904, 905, 906, 911, 912, and 913 of [reference missing]. Fig. 9 described. However, the circuit elements 1001, 1002, 1003, 1004, 1005, 1011, 1012, 1013 work together to switch off the power transistor 801 (after a certain delay) independently of the input signal 843 when the voltage at node 850 exceeds the desaturation voltage VDESAT exceeds.

[0048] Thus, circuit 1000 also includes a desaturation circuit configured to turn off the power field-effect transistor when 1) the gate overdrive circuit has already increased the gate voltage applied to the gate node in response to a previous detection that the sensing field-effect transistor has entered saturation, 2) the saturation detection circuit again detects an indication that the sensing field-effect transistor has entered saturation, and 3) the gate overdrive circuit cannot further increase the gate voltage applied to the gate node of the power field-effect transistor.

[0049] As mentioned previously, the gate node of the power transistor is overdriven at a voltage higher than can be safely applied for extended periods. However, the overdrive voltage can be safely applied to the gate for short periods. There are a number of applications where overdrive for only a brief period would be beneficial. Fig. Figure 11 shows a table listing exemplary data, including load condition, peak current, duty cycle, and half-cycle operating waveforms for the operation of a dead-pole bridgeless PFC (power factor converter) for a range of load conditions. For a sinusoidal current output, as an example, the duty cycle at full load is 5%, the duty cycle at moderate load is 40%, the duty cycle at light load is 50%, and the duty cycle for standby is 5%. As a result, overdriving with a higher gate-source voltage VG may occur. GSThe current peak should only be applied for a short period. Selective overdriving at the peak current for a small percentage of the time will not significantly affect reliability or reduce the device's lifespan. For high-current applications, such as traction inverters, the inverter may only operate at full load for a small percentage of the time, e.g., ≤ 5%.

[0050] Fig. Figure 12 shows another schematic graphical representation of an operating waveform for drain current I. D vs. time for a half-cycle to illustrate the relative operating share during standby, light to medium load, and full load. By detecting the saturation point through measuring V DS or I DS A higher gate-source voltage V can GS be designed so that the device operates in a linear range outside of saturation.

[0051] Fig. Figure 13 shows a schematic graphical representation of the gate driver voltage V. GS vs. time over a corresponding half-cycle for the operation of a gate driver providing a selective gate voltage overdrive of a first exemplary embodiment providing a first gate-source voltage VGS1 during most of the cycle and V gs to a second gate-source voltage V GS2 is increased at the top of the waveform.

[0052] Fig. Figure 14 shows a schematic graphical representation of the gate driver voltage vs. time over a corresponding half-cycle for the operation of a gate driver providing selective gate voltage overdrive of a second exemplary embodiment, wherein V GS is varied over the cycle, e.g. using a variable V GS, which gradually increases towards the peak load and then decreases after the peak load, e.g., proportionally to the load. Accordingly, there can be several possible levels of the overdrive gate voltage that can be applied to the gate node of the power field-effect transistor.

[0053] Schematic graphical representations of waveforms for drain current I D , Drain-source voltage V DS and gate-source voltage V GS are in Fig. 15A and Fig. 15B shown. As shown by the schematic waveforms in Fig. 15A illustrates that the voltage rises at t0 when the gate is powered on for normal operation by an initial gate-source voltage V. GS1 e.g. 6 V, during the period from t0 to t1, the drain current I D in the direction of a first saturation current I Dsat1 Saturation is indicated by an increase in V. DS detected. If V DSWhen a threshold or limit value is reached, the gate-source voltage V is GS to a higher value V GS2 , e.g. 8 V, increased to implement an overdrive that allows the drain current I D to a higher value of the operating current I op rises, and V ds The voltage falls below the threshold. Between t1 and t2, after saturation is detected, the higher gate-source voltage V results. GS2 the device returns from saturation to a linear range. Provided that the overdrive I op If the system remains within a safe operating range, an override can be used.

[0054] As shown by the schematic waveforms in Fig. 15B illustrates the case where saturation occurs during driving at V GS2 is detected between t1 and t2 when the current I Dsat2Once a fault condition is reached, it is detected, and the transistor is deactivated by reducing the gate driver voltage to below the threshold voltage V. gs-th off.

[0055] Fig. Figure 16 illustrates a flowchart of Method 1600 for overdriving a power field-effect transistor according to the principles described herein. Method 1600 is carried out in the context in which the power field-effect transistor comprises a portion of an epitaxial stack of semiconductor layers having a heterojunction between at least two adjacent semiconductor layers, and in which there is a sensing transistor comprising another portion of the epitaxial stack of semiconductor layers, and in which a drain node of the sensing field-effect transistor is connected to a drain node of the power field-effect transistor. For example, Method 1600 can be carried out in the context of Circuit 500 of Fig.5 will be carried out.

[0056] Procedure 1600 involves monitoring a parameter of the power field-effect transistor (step 1601) and detecting whether there is an indication that the detection field-effect transistor has entered saturation (decision block 1602). If there is no such indication ("no" in decision block 1602), monitoring simply continues (step 1601). On the other hand, if there is an indication that the power field-effect transistor has entered saturation ("yes" in decision block 1602), the gate of the power transistor is overdriven (step 1603), and monitoring continues (step 1601). The cycle represented by steps 1601, 1602, and 1603 can be repeated for multiple levels of the gate overdrive voltage.If the gate overdrive is successful in removing the power transistor from saturation in a timely manner ("Yes" in decision block 1604), the power transistor continues to operate and monitoring of the indicator continues (step 1601). Conversely, if the gate overdrive is unsuccessful in removing the power transistor from saturation in a timely manner ("No" in decision block 1604), the power transistor is switched off (step 1605).

[0057] Although the subject matter has been described in a language specific to structural features and / or methodological steps, it is understood that the subject matter defined in the attached claims is not necessarily limited to the features or steps described above, or to the sequence of steps described above. Rather, the described features and steps are disclosed as exemplary ways of implementing the claims.

[0058] The present disclosure can be implemented in other specific forms without deviating from its essential characteristics. The described embodiments are to be considered in every respect merely illustrative and not limiting. All modifications that fall within the scope and equivalence of the claims are to be included within their scope.

[0059] When introducing elements into the appended claims, the articles "a", "an", "the", "a", and "a" are intended to indicate that there is one or more of the elements. The terms "comprising", "containing", and "having" are intended to be inclusive and mean that there may be other additional elements besides those listed.

Claims

[1] Circuit for overdriving a power field-effect transistor, the circuit comprising: a power field-effect transistor comprising part of an epitaxial stack of semiconductor layers having a heterojunction between at least two adjacent semiconductor layers; a detection field-effect transistor comprising another part of the epitaxial stack of semiconductor layers, wherein a drain node of the detection field-effect transistor is connected to a drain node of the power field-effect transistor; a saturation detection circuit configured to detect an indication that the sensing field-effect transistor has entered saturation; and A gate overdrive circuit configured to increase a gate voltage applied to a gate node of the power field-effect transistor when the saturation detection circuit detects the sign that the detection field-effect transistor is entering saturation. [2] Circuit according to claim 1, wherein the power field effect transistor is an enrichment-mode gallium nitride power transistor, wherein the detection field effect transistor is an enrichment-mode gallium nitride detection transistor. [3] Circuit according to claim 1, wherein the power field effect transistor is an enhancement-mode silicon carbide power transistor, wherein the detection field effect transistor is an enhancement-mode silicon carbide detection transistor. [4] Circuit according to claim 1, wherein the power field effect transistor is an enrichment-mode gallium arsenide power transistor, wherein the detection field effect transistor is an enrichment-mode gallium arsenide detection transistor. [5] Circuit according to claim 1, wherein the power field effect transistor is an enrichment-mode indium gallium arsenide power transistor, wherein the detection field effect transistor is an enrichment-mode indium gallium arsenide detection transistor. [6] Circuit according to claim 1, wherein the power field effect transistor is an enrichment-mode indium aluminum arsenide power transistor, wherein the detection field effect transistor is an enrichment-mode indium aluminum arsenide detection transistor. [7] Circuit according to claim 1, wherein the power field effect transistor is a high electron mobility transistor (HEMT), wherein part of a layer of the epitaxial stack of semiconductor layers forms an active layer of the HEMT. [8] Circuit according to claim 7, wherein the detection field effect transistor is also a high electron mobility transistor (HEMT). [9] Circuit according to claim 1, wherein the detection field-effect transistor is a finger transistor manufactured in the same finger array as the power field-effect transistor. [10] Circuit according to claim 1, wherein the detection field effect transistor is configured as a diode, wherein a gate node of the detection field effect transistor is connected to a source node of the detection field effect transistor. [11] Circuit according to claim 10, wherein the saturation detection circuit comprises a comparator configured to compare a voltage at the source node of the detection field-effect transistor with a reference voltage and output a signal representing saturation detection based on the comparison. [12] Circuit according to claim 1, wherein a gate node of the detection field-effect transistor is connected to the gate node of the power field-effect transistor. [13] Circuit according to claim 12, wherein the saturation detection circuit comprises a comparator configured to compare a voltage at the drain node of the detection field-effect transistor with a reference voltage and output a signal representing saturation detection based on the comparison. [14] Circuit according to claim 1, further comprising: A desaturation circuit configured to turn off the power field-effect transistor when 1) the gate overdrive circuit has already increased the gate voltage applied to the gate node in response to a previous detection that the sensing field-effect transistor has entered saturation, 2) the saturation detection circuit again detects an indication that the sensing field-effect transistor has entered saturation, and 3) the gate overdrive circuit cannot further increase the gate voltage applied to the gate node of the power field-effect transistor. [15] Circuit according to claim 1, which is configured such that there are multiple possible levels of the overdrive gate voltage that can be applied to the gate node of the power field-effect transistor, wherein the circuit is configured such that the saturation detection circuit is configured to repeatedly detect an indication that the sensing field-effect transistor has entered saturation; and the gate overdrive circuit is configured to increase the gate voltage applied to the gate node of the power field-effect transistor in response to each successive detection of the indication that the sensing field-effect transistor has entered saturation. [16] Circuit according to claim 1, wherein the power field-effect transistor is configured to operate with a drain voltage of more than 100 volts. [17] Method for overdriving a power field-effect transistor, wherein the power field-effect transistor comprises a part of an epitaxial stack of semiconductor layers having a heterojunction between at least two adjacent semiconductor layers, the method comprising: Detecting an indication that a detection field-effect transistor has entered saturation, wherein the detection field-effect transistor comprises another part of the epitaxial stack of semiconductor layers, with a drain node of the detection field-effect transistor being connected to a drain node of the power field-effect transistor; and Increasing a gate voltage applied to a gate node of the power field-effect transistor in response to detecting the sign that the detection field-effect transistor is entering saturation. [18] The method of claim 17, further comprising: Turning off the power field-effect transistor if 1) the gate voltage applied to the gate node has already been increased in response to a previous detection that the sensing field-effect transistor has entered saturation, 2) the procedure again involves detecting an indication that the sensing field-effect transistor has entered saturation, and 3) the gate voltage applied to the gate node of the power field-effect transistor cannot be increased further. [19] Method according to claim 17, wherein there are several possible levels of the overdrive gate voltage that can be applied to the gate node of the power field-effect transistor, the method further comprising: Repeated detection of an indication that the sensing field-effect transistor has entered saturation; and increasing the gate voltage applied to the gate node of the power field-effect transistor in response to each successive detection of the indication that the sensing field-effect transistor has entered saturation.

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