SEMICONDUCTOR COMPONENT

Abstract

A semiconductor device is provided in which a large change in the positional relationship between a plug connector and an electrode of a semiconductor chip is prevented.A semiconductor device comprises an insulating circuit substrate (1); a semiconductor chip (3) mounted on the insulating circuit substrate (1) using solder material and having an electrode (30) on an upper surface; a printed substrate (6) arranged over the semiconductor chip (3); a plug connector (51, 52) inserted into the printed substrate (6) and bonded to the electrode (30) via solder material; and a solder mask (71) and a solder resist (72) provided on an upper surface side of the insulating circuit substrate (1) and spaced apart along a first direction in which the semiconductor chip (3) is located along the first direction between the solder mask (71) and the solder resist (72).

Description

Technical field

[0001] The present invention relates to a semiconductor device (semiconductor module) on which a power semiconductor chip is mounted. Background of the technology

[0002] A semiconductor device on which a power semiconductor chip (hereinafter referred to simply as a "semiconductor chip") is mounted is primarily used for variable-speed control and power conversion applications such as motors or inverters. Additionally, a metal layer of the substrate on which the semiconductor chip is mounted can be irradiated with laser light to form a photoresist on the upper surface of the metal layer.

[0003] PTL 1 describes the process of creating a liquid-repellent layer on a circuit board made of a ceramic circuit substrate by laser irradiation. Additionally, PTL 1 describes a technology in which a liquid-repellent layer is provided between areas where a semiconductor chip or a contact component is located.

[0004] PTL 2 describes an oxide film that is provided around a solder-bonding section on the top surface of a metal circuit structure. PTL 2 describes a technology in which the oxide film is provided outside an area that is 0.5 mm or less away from a semiconductor element in a top view.

[0005] PTL 3 describes a technology in which a low wettability section, exhibiting low wettability towards solder material, is formed on an electrode pad of a semiconductor chip, a solder paste containing a flux is printed to cover a tip section of the low wettability section, a remelting treatment is performed on the solder paste to form a solder bump that is electrically connected to the electrode pad, and a gas generated from the flux touches the tip section of the low wettability section and remains there to form a cavity in the solder bump.

[0006] PTL 4 describes a technology in which a nickel plating layer (Ni plating layer) is formed on a surface of a circuit layer of a circuit substrate for a semiconductor device and a section intended for solder bonding, in which a semiconductor element is soldered, and a section degraded due to laser irradiation are arranged in the formed nickel plating layer in a state that they adjoin each other in a plane direction.

[0007] PTL 5 discloses a technology in which a substrate is bonded to a main surface of a heat dissipation plate with a solder layer, a semiconductor element is bonded to a main surface of the substrate with a solder layer, a housing is attached to a main surface of the heat dissipation plate to surround the substrate, an internal electrode electrically connected to the semiconductor element is provided on an inner circumferential side of the housing, a bonding surface of the heat dissipation plate with the housing on a main surface has a first area where a photoresist layer is formed, and a second area where the photoresist layer is not formed, and the second area is formed such that it has an area that overlaps the internal electrode in a top view.

[0008] In PTL 6, a cell unit is formed by soldering a semiconductor chip to the surface of an insulating circuit substrate, which has conductive structures on both surfaces. An inorganic layer of insulating features is formed by coupling the cell unit to a metal base, which dissipates heat generated by the semiconductor chip to an unsoldered section via a metal mask. A technology for soldering the cell unit to the metal base and sealing the cell unit with an insulating resin is then described.

[0009] PTL 7 describes a semiconductor device in which an inner surface is wired to an attached printed substrate. List of patent literature PTL 1: JP 2021-118350 A PTL 2: JP 2022-137686 A PTL 3: JP 2015-76429 A PTL 4: JP 2014-167983 A PTL 5: JP 2019-197831 A PTL 6: JP 2008-172066 A PTL 7: JP 2012-119618 A Brief description of the invention: Technical problem

[0010] A printed substrate with a plug connector can be used to connect an electrode of a semiconductor chip to an external component. Additionally, the semiconductor chip can move during a melting process to melt a soldering material.

[0011] In view of the problem described above, an objective of the present invention is to provide a semiconductor device in which a large change in the positional relationship between the plug connector and the electrode of the semiconductor chip is prevented. Solution to the problem

[0012] A key component of one aspect of the present invention is that its semiconductor device comprises the following: (a) an insulating circuit substrate; (b) a semiconductor chip mounted on the insulating circuit substrate using solder material and having an electrode on a top surface; (c) a printed substrate arranged over the semiconductor chip; (d) a plug connector inserted into the printed substrate and bonded to the electrode via solder material; and (e) a first solder mask and a second solder mask provided on a top surface side of the insulated circuit substrate and spaced apart from each other along a first direction in which (f) the semiconductor chip is located between the first solder mask and the second solder mask along the first direction.

[0013] Additionally, along the first direction, if a distance between the first solder mask and the second solder mask is designated as L1, a width of the semiconductor chip is designated as L2, a width of the electrode is designated as w1, and a width of an area occupied by the plug connector with respect to the electrode is designated as d1, a relationship of L1 - L2) < (w1 - d1) can be satisfied.

[0014] In addition, the semiconductor device may further comprise: a third solder mask and a fourth solder mask provided on the upper surface side of the insulating circuit substrate and provided such that they are spaced apart from each other along a second direction intersecting the first direction, in which the semiconductor chip may be located between the third solder mask and the fourth solder mask along the second direction.

[0015] Additionally, along the second direction, if a distance between the third solder mask and the fourth solder mask is designated L3, a width of the semiconductor chip is designated L4, a width of the electrode is designated w2, and a width of an area occupied by the plug connector with respect to the electrode is designated d2, a relationship of (L3 - L4) < (w2 - d2) can be satisfied.

[0016] Additionally, the first solder mask, the second solder mask, the third solder mask and the fourth solder mask can be joined together to form a ring.

[0017] Additionally, at least a portion of the first solder mask, the second solder mask, the third solder mask and the fourth solder mask may have a slit.

[0018] Additionally, at least part of the first solder mask, the second solder mask, the third solder mask and the fourth solder mask may be provided in a duplicate manner.

[0019] Additionally, one of the first solder mask and the second solder mask can extend along the second direction, and the other can be dot-like.

[0020] Additionally, one of the first solder mask and the second solder mask can extend along the second direction and the other can be spot-shaped, and one of the third solder mask and the fourth solder mask can extend along the first direction and the other can be spot-shaped.

[0021] Additionally, the first solder mask can only be bonded to one of the third and fourth solder masks, and the second solder mask can only be bonded to the other of the third and fourth solder masks.

[0022] Additionally, each of the first solder mask, the second solder mask, the third solder mask and the fourth solder mask can be formed from several dot-shaped solder masks.

[0023] Additionally, several of the semiconductor chips can be provided side by side, and the multiple semiconductor chips can share at least part of the first solder mask, the second solder mask, the third solder mask, and the fourth solder mask.

[0024] Additionally, each of the first solder mask, the second solder mask, the third solder mask, and the fourth solder mask can be a laser photoresist provided by irradiating the top surface of the insulating circuit substrate with laser light.

[0025] Additionally, the electrode can be a gate electrode or a source electrode.

[0026] The summary of the invention does not list all of the necessary structural elements of the present invention. Furthermore, a subcombination of these groups of structural elements may also constitute an invention. Advantageous effects of the invention

[0027] According to the present invention, it is possible to provide a semiconductor device in which a large change in the positional relationship between a plug connector and an electrode of a semiconductor chip is prevented. Brief description of the drawings Fig. 1 is a cross-sectional view of a semiconductor device according to a first embodiment; Fig. Figure 2 is a top view of a printed substrate that is incorporated in the semiconductor device according to the first embodiment; Fig. Figure 3 is an enlarged top view illustrating a positional relationship prior to the melting of a solder mask and a semiconductor chip embedded in the semiconductor device according to the first embodiment; Fig. Figure 4 is an enlarged top view illustrating a positional relationship after melting the solder mask and the semiconductor chip embedded in the semiconductor device according to the first embodiment; Fig. 5 is an enlarged top view illustrating the solder mask and the semiconductor chip incorporated in the semiconductor device according to the first embodiment; Fig. Figure 6 is an enlarged top view illustrating a semiconductor chip of a semiconductor device according to a comparative example; Fig. 7 is an enlarged top view illustrating a solder mask and a semiconductor chip incorporated in a semiconductor device according to a first modification example of the first embodiment; Fig. 8 is an enlarged top view illustrating a solder mask and a semiconductor chip incorporated in a semiconductor device according to a second modification example of the first embodiment; Fig. 9 is an enlarged top view illustrating a solder mask and a semiconductor chip incorporated in a semiconductor device according to a third modification example of the first embodiment; Fig. 10 is an enlarged top view illustrating a solder mask and a semiconductor chip incorporated in a semiconductor device according to a fourth modification example of the first embodiment; Fig. Figure 11 is an enlarged top view illustrating a solder mask and a semiconductor chip incorporated in a semiconductor device according to a fifth modification example of the first embodiment; Fig. Figure 12 is an enlarged top view illustrating a solder mask and a semiconductor chip incorporated in a semiconductor device according to a sixth modification example of the first embodiment; Fig. Figure 13 is an enlarged top view illustrating a solder mask and a semiconductor chip incorporated in a semiconductor device according to a seventh modification example of the first embodiment; and Fig. Figure 14 is an enlarged top view illustrating a solder mask and a semiconductor chip incorporated in a semiconductor device according to an eighth modification example of the first embodiment. Description of the embodiments

[0028] The following describes a first embodiment and examples of modifications with reference to the drawings. In the description of the drawings, the same or similar parts are given the same or similar reference numbers, and repeated descriptions are omitted. Here, the drawings are schematic, and the relationship between a thickness and a plane dimension, the ratio between the thicknesses of respective layers, and the like may differ from the actual representation. The drawings may also show parts that differ in a relationship or ratio between dimensions.In addition, the first embodiment and the modification examples shown below are examples of a component or a method for implementing the technical idea of ​​the present invention, and the technical idea of ​​the present invention is not limited to the materials, shapes, structures, arrangement and the like of configuration components.

[0029] Furthermore, definitions of directions, such as an up-down direction, in the following description are merely definitions to facilitate the description and do not limit the technical idea of ​​the present invention. For example, if an object is rotated by 90° and observed, the top and bottom sides are naturally replaced by right and left sides, and if the object is rotated by 180° and observed, the top and bottom sides are reversed. (First embodiment)<Konfiguration des Halbleiterbauelements>

[0030] As in Fig. Figure 1 illustrates that a semiconductor device according to a first embodiment comprises an insulating circuit substrate 1, semiconductor chips (semiconductor elements) 3a, 3b and 3c mounted on the insulating circuit substrate 1 via solder materials 2a, 2b and 2c, and a printed substrate 6 arranged over the semiconductor chips 3a, 3b and 3c to be spaced apart from them. The circumferences of the semiconductor chips 3a, 3b and 3c and of the printed substrate 6 are sealed by a sealing element 8 and electrically insulated from one circumference.

[0031] The insulating circuit substrate 1 has an insulating substrate 11, upper conductor layers 12a and 12b arranged on an upper surface of the insulating substrate 11, which is a circuit surface side, and a lower conductor layer 13 arranged on a lower surface of the insulating substrate 11, which is a cooling surface side.

[0032] The insulating circuit substrate 1 can be, for example, a direct copper bonding substrate (DCB substrate), an active metal brazing substrate (AMB substrate), or the like. The insulating substrate 11 is, for example, a ceramic substrate consisting of aluminum oxide (Al₂O₃), aluminum nitride (AlN), silicon nitride (Si₃N₄), or the like, or a resin that insulates a substrate using a polymer material or the like. The upper conductor layers 12a and 12b and the lower conductor layer 13 are, for example, a conductive foil or a conductive plate made of copper (Cu), aluminum (Al), or the like. A nickel plating layer (Ni plating layer) can be formed on the upper surfaces of the upper conductor layers 12a and 12b. The upper conductor layers 12a and 12b form a predefined circuit structure.A solder mask 7 is provided on an upper surface of the upper conductor layers 12a and 12b. The solder mask 7 is a laser photoresist.

[0033] Semiconductor chips 3a, 3b, and 3c are bonded to the upper conductor layers 12a and 12b via solder materials 2a, 2b, and 2c. Solder materials 2a, 2b, and 2c are bonding materials. For example, a tin-antimony (SnSb) or tin-silver (SnAg) solder can be used.

[0034] Semiconductor chips 3a, 3b, and 3c exhibit different types depending on the application. For example, they may incorporate a power semiconductor element such as an insulated-gate bipolar transistor (IGBT), a reverse-conducting IGBT (RC-IGBT), a field-effect transistor (FET), an electrostatic induction thyristor (SI thyristor), or a gate-turn-off thyristor (GTO thyristor), as well as a rectifying element such as a freewheeling diode (FWD). Semiconductor chips 3a, 3b, and 3c may be designed as a silicon substrate (Si substrate) or as a compound semiconductor substrate consisting of a wideband gap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga₂O₃). Semiconductor chip 3, for example, is a power semiconductor chip.

[0035] For example, if semiconductor chip 3 is a field-effect transistor, it has a control electrode (gate electrode) and a first main electrode (source electrode) on an upper surface and a second main electrode (drain electrode) on a lower surface. If semiconductor chip 3 is an IGBT or an RC-IGBT, it has a control electrode (gate electrode) and a first main electrode (emitter electrode) on the upper surface and a second main electrode (collecting electrode) on the lower surface. If semiconductor chip 3 is an electrostatic induction thyristor, a gate-off thyristor, or a freewheeling diode, it has a first main electrode (for example, an anode electrode) on the upper surface and a second electrode (for example, a cathode electrode) on the lower surface.The first main electrode is a main electrode that is to be bonded via solder to a plug connector, which will be described later, below the first and second main electrodes. In the present embodiment, the semiconductor chip 3 is described as the field-effect transistor.

[0036] Although three semiconductor chips 3a, 3b and 3c in Fig. As illustrated in Figure 1, the number of semiconductor chips is not particularly limited. For example, only one semiconductor chip may be provided, or four or more semiconductor chips may be provided. For example, as shown in Figure 1. Fig. As illustrated in Figure 2, semiconductor chips (semiconductor elements) 3d, 3e, 3f, and 3g can also be mounted on the insulating circuit substrate 1 using solder (not illustrated). In the Fig. In the illustrated example 2, a lower arm LO has four semiconductor chips of semiconductor chips 3a, 3b, 3d, and 3e, and an upper arm UP has three semiconductor chips of semiconductor chips 3c, 3f, and 3g. The lower arm LO can only have three semiconductor chips. Additionally, semiconductor chips 3b and 3c can be mounted on the insulating circuit substrate 1, so that the gate electrode is on the right side of a paper surface and the source electrode is on the left side of the paper surface, as in the other semiconductor chips. If the semiconductor chips 3a, 3b, 3c, 3d, 3e, 3f, and 3g are indistinguishable from each other, they can simply be referred to as semiconductor chip 3.

[0037] As in Fig. As illustrated in Figure 1, the printed substrate 6 is arranged over the semiconductor chips 3a, 3b, and 3c. The printed substrate 6 has an insulating layer 61, an upper wiring layer (not illustrated) arranged on an upper surface of the insulating layer 61, and a lower wiring layer (not illustrated) arranged on a lower surface of the insulating layer 61. The upper wiring layer and the lower wiring layer form a predefined circuit structure.

[0038] The insulating layer 61 is designed as an insulating material such as ceramic or a resin in which, for example, aluminum oxide (Al₂O₃), aluminum nitride (AlN), silicon nitride (Si₃N₄), or the like is a major component. The insulating layer 61 can be a resin substrate consisting of a combination of glass fiber, an epoxy resin, and the like. The upper wiring layer and the lower wiring layer are each designed, for example, as a conductive foil consisting of copper (Cu), aluminum (Al), or the like.

[0039] As in Fig. As illustrated in Figure 2, the printed substrate 6 has several through-holes (vias) 6x that penetrate the insulating layer 61, the upper wiring layer, and the lower wiring layer. Several plug connectors (pin electrodes) 51 to 59 are inserted (pressed into) or fixed to the multiple through-holes 6x of the printed substrate 6. The printed substrate 6 and the plug connectors 51 to 59 form implant substrates (6, 51 to 59). A conductive layer (not illustrated), which conducts the upper wiring layer and the lower wiring layer, can be formed on the inner surface of some of the through-holes 6x, and the conductive layer on an inner surface can be in conductive contact with the plug connector inserted therein, thus allowing the upper wiring layer and the lower wiring layer to have the same potential.

[0040] The plug connectors 51 to 59 are, for example, rod-shaped (pin-shaped) or column-shaped and can, in particular, be a cylinder, an elliptical cylinder, or a polygonal prism, such as a triangular prism or a square prism. Copper (Cu) can be used as a material for the plug connectors 51 to 59. The number of plug connectors is not limited to the one in Fig. 1 and Fig. The two illustrated examples are limited. The number of connectors is not particularly limited.

[0041] The drain electrode on the lower surface of the semiconductor chip 3 is bonded via solder to the upper conductor layers 12a and 12b of the insulating circuit substrate 1, which is located in Fig. Figure 1 illustrates this. The gate electrode of semiconductor chip 3 is bonded to connector 51. The source electrode of semiconductor chip 3 is bonded to connector 52. To distinguish between connectors 51 and 52 connected to semiconductor chip 3a, connectors 51 and 52 connected to semiconductor chip 3b, and connectors 51 and 52 connected to semiconductor chip 3c, the connectors connected to semiconductor chip 3a are designated as connectors 51a and 52a, the connectors connected to semiconductor chip 3b as connectors 51b and 52b, and the connectors connected to semiconductor chip 3c as connectors 51c and 52c. If the connectors 51a and 52a, the connectors 51b and 52b and the connectors 51c and 52c are not distinguished, the connectors can simply be referred to as connectors 51 and 52.

[0042] As in Fig. As illustrated in Figure 2, one connector 51 is provided for each semiconductor chip 3. Two connectors 52 are provided for each semiconductor chip 3. To distinguish, for example, the two connectors 52a provided on semiconductor chip 3a, the connectors 52a can be designated as connectors 52a1 and 52a2. Additionally, to distinguish, for example, two connectors 52e provided on semiconductor chip 3e, the connectors 52e can be designated as connectors 52e1 and 52e2. If connectors 52a1 and 52a2 are indistinguishable, they are simply referred to as connector 52a. If connectors 52e1 and 52e2 are indistinguishable, they are simply referred to as connector 52e. The number of connectors 52, which are provided for each semiconductor chip 3, is not limited to two.For example, one connector 52 may be provided for each semiconductor chip 3, or three or more connectors 52 may be provided.

[0043] As in Fig. As illustrated in Figure 1, the lower ends of connectors 51a and 52a are bonded to the upper surface of semiconductor chip 3a via solder materials 41a and 42a, respectively. Solder materials 41a and 42a are bonding materials. For example, a tin-antimony (SnSb) or tin-silver (SnAg) solder can be used. The lower ends of connectors 51b and 52b are bonded to the upper surface of semiconductor chip 3b via solder materials 41b and 42b, respectively. The lower ends of connectors 51c and 52c are bonded to the upper surface of semiconductor chip 3c via solder materials 41c and 42c, respectively. The lower ends of the plug connectors 54, 58 and 59 are bonded to the upper surfaces of the upper conductor layers 12a and 12b of the insulating circuit substrate 1 via the solder materials 44, 48 and 49.The lower end of connector 56 is inserted (pressed into) and secured in a hole 12x provided in the upper conductor layer 12b. Connector 56 is a positioning pin used to establish a relative position between the insulating circuit substrate 1 and the printed substrate 6. Connectors 53, 55, and 57 are not connected to the insulating circuit substrate 1.

[0044] The connectors 53, 55, 57 and 59, which are in Fig. The external connections shown in Figure 1 are external. Connector 59 is a connection on the anode side (P-side), and connector 53 is a connection on the cathode side (N-side). At least one of connectors 55 and 57 is an output connector. Connectors 53, 55, 57, and 59 protrude from the sealing component 8 and are connected to an external circuit.

[0045] If, for example, the semiconductor chip 3 is a field-effect transistor, the connector 59 can supply current to the drain electrode of the semiconductor chip 3, located in the upper arm UP, via the upper conductor layer 12b, and so on. Then, the source electrode of the semiconductor chip 3, located in the upper arm UP, can supply current to the drain electrode of the semiconductor chip 3, located in the lower arm LO, via connector 52, the circuit laid out on the printed substrate, connector 54, the upper conductor layer 12a, and so on. Finally, the source electrode of the semiconductor chip 3, located in the lower arm LO, can be output to the external circuit via connector 52, the circuit laid out on the printed substrate 6, and connector 53.A control signal for switching the semiconductor chip 3 on and off can be supplied to the gate electrode of the semiconductor chip 3 via an external connection (not illustrated), the circuit laid out on the printed substrate 6, the connector 51, and the like. At least one of the connectors 55 and 57 can be connected between the upper arm UP and the lower arm LO as the output connection. <Lötstopplack>

[0046] The semiconductor chip 3 and the solder mask 7 provided around the semiconductor chip 3 are described below with regard to Fig. 3 to 5 described. The solder mask 7 can be provided for each semiconductor chip 3. Fig. Figures 3 to 5 illustrate semiconductor chip 3a as an example of semiconductor chip 3. Since semiconductor chip 3, which is not semiconductor chip 3a, also has the same configuration as semiconductor chip 3a, its description is omitted. Additionally, one of the X-direction and Y-direction is designated as a first direction, and the other as a second direction. In the present embodiment, the X-direction is designated as the first direction and the Y-direction as the second direction. However, the Y-direction can also be designated as the first direction and the X-direction as the second direction. The X-direction and the Y-direction are directions that intersect each other. In the present embodiment, the X-direction and the Y-direction are orthogonal to each other. Additionally, solder materials 41a and 42a are shown in the drawings from [reference missing]. Fig. 5 is no longer illustrated.

[0047] Fig. Figure 3 illustrates an example of the semiconductor chip 3a before melting (heat treatment) is carried out, which is one of the manufacturing processes, and Fig. Figure 4 illustrates an example of the semiconductor chip 3a after melting. If the melting is carried out as in Fig. As illustrated in Figure 4, if the soldering process is carried out as described above, the solder material 2a can melt, soak, and spread, and the semiconductor chip 3a can move. As described above, the relative positional relationship between the plug-in terminals 51a, 52a1, and 52a2 and the insulating circuit substrate 1 is unlikely to change due to the presence of the plug-in terminal 56, which is the positioning pin. To bond the plug-in terminals 51a, 52a1, and 52a2 to the electrodes of the semiconductor chip 3a, it is desirable that the semiconductor chip 3a not move excessively. In the present technology, by providing the solder mask 7 on the upper surface of the upper conductor layers 12a and 12b, the solder material 2a is prevented from soaking and spreading excessively, and the semiconductor chip 3a is prevented from moving excessively.Therefore, the plug connectors 51a, 52a1 and 52a2 are bonded to the electrodes of the semiconductor chip 3a after melting.

[0048] As in Fig. As illustrated in Figure 3, a gate electrode 31 and a source electrode 32 are provided as electrodes on the upper surface of the semiconductor chip 3a. If the gate electrode 31 and the source electrode 32 are indistinguishable, they are simply referred to as one electrode 30. A lower end of the connector 51a is bonded to the gate electrode 31 via the solder material 41a, and a lower end of the connector 52a is bonded to the source electrode 32 via the solder material 42a. The solder mask 7 includes a solder mask 71 and a solder mask 72, which are provided spaced apart along the X-direction, and a solder mask 73 and a solder mask 74, which are provided spaced apart along the Y-direction. The solder mask 71 faces the solder mask 72 and the solder mask 73 faces the solder mask 74.Solder masks 71, 72, 73, and 74 are connected to form a ring. Semiconductor chip 3a is located between solder masks 71 and 72, and its movement along the X-direction is restricted by solder masks 71 and 72. Semiconductor chip 3a is located between solder masks 73 and 74, and its movement along the Y-direction is restricted by solder masks 73 and 74. For example, the dimensions of solder masks 71 and 72 along the X-direction (dimensions in one lateral direction) and the dimensions of solder masks 73 and 74 along the Y-direction (dimensions in the lateral direction) are approximately 150 µm or more and 1000 µm or less, respectively.

[0049] A distance between the solder mask 71 and the solder mask 72 along the X-direction is designated L1, and a width of the semiconductor chip 3a is designated L2. Then, along the X-direction, a width of the gate electrode 31 is designated w1, and a width of a region occupied by the lower end of the connector 51a with respect to the gate electrode is designated d1. Similarly, along the X-direction, a width of the source electrode 32 is designated w1, and a width of a region occupied by the lower end of the connector 52a with respect to the gate electrode 31 is designated d1. The width d1 can be any diameter of the connectors 51a and 52a. Then L1, L2, w1, and d1 satisfy a relationship of (L1 - L2) < (w1 - d1). (L1 - L2) is a distance over which the movement of the semiconductor chip 3a along the X-direction is permitted, that is, a clearance of the semiconductor chip 3a along the X-direction.(w1 - d1) is a distance over which the movement of the gate electrode 312 and the source electrode 32 is permitted with respect to the plug terminals 51a and 52a along the X-direction, that is, a clearance of the gate electrode 31 and the source electrode 32 along the X-direction. By providing the clearance of the semiconductor chip 3a to be smaller than the clearances of the gate electrode 31 and the source electrode 32, it is possible, even if the semiconductor chip 3a moves along the X-direction during melting, to prevent the bond between the plug terminal 51a and the gate electrode 31 from opening, and it is possible to prevent the bond between the plug terminal 52a and the source electrode 32 from opening.

[0050] As in Fig. As illustrated in Figure 5, along the Y-direction, a distance between the solder mask 73 and the solder mask 74 is designated L3, and a width of the semiconductor chip 3a is designated L4. Then, along the Y-direction, a width of the gate electrode 31 is designated w2, and a width of a region occupied by the lower end of the connector 51a with respect to the gate electrode 31 is designated d2. Similarly, along the Y-direction, a width of the source electrode 32 is designated w2, and a width of a region occupied by the lower end of the connector 52a with respect to the gate electrode 31 is designated d2. L3, L4, w2, and d2 then satisfy a relationship (L3 - L4) y (w2 - d2). (L3 - L4) is a distance over which the movement of the semiconductor chip 3a along the Y direction is permitted, that is, a clearance of the semiconductor chip 3a along the Y direction.(w2 - d2) is a distance over which the movement of the gate electrode 31 and the source electrode 32 is permitted with respect to the plug terminals 51a and 52a along the Y-direction, that is, a clearance of the gate electrode 31 and the source electrode 32 along the Y-direction. By providing the clearance of the semiconductor chip 4y smaller than the clearances of the gate electrode 31 and the source electrode 32, it is possible, even if the semiconductor chip 3a moves along the Y-direction during melting, to prevent the bond between the plug terminal 51a and the gate electrode 31 from opening, and it is possible to prevent the bond between the plug terminal 52a and the source electrode 32 from opening.

[0051] Two plug-in terminals 52a are provided along the Y-direction. In this way, when multiple plug-in terminals 52a are provided, the width of a region occupied by the lower ends of the multiple plug-in terminals 52a with respect to the gate electrode 31 is designated as d2. For example, the width d2 can be a distance from a tangent line to a section of a plug-in terminal closest to the solder mask 73 among the multiple plug-in terminals 52a, to a tangent line to a section of a plug-in terminal closest to the solder mask 74. Similarly, when multiple plug-in terminals 52a are provided along the X-direction, the width of the region occupied by the lower ends of the multiple plug-in terminals 52a with respect to the gate electrode 31 can be d1.The widths d1 and d2 of the areas occupied by the lower ends of the plug connectors, such as plug connectors 51a and 52a with respect to the electrodes 30, are smaller than the widths w1 and w2 of the electrodes 30 provided.

[0052] Two electrodes, gate electrode 31 and source electrode 32, are provided on the upper surface of the semiconductor chip 3a. The widths w1 and w2 and the areas of gate electrode 31 and source electrode 32 can be determined, for example, according to the number of connectors to be bonded. Generally, since a single connector is connected to the gate electrode 31, the area of ​​the gate electrode 31 is often smaller than the area of ​​the source electrode 32. Additionally, if the widths L2 and L4 of the semiconductor chip 3a are reduced, the widths w1 and w2 and the areas of gate electrode 31 and source electrode 32 can also be reduced. <Verfahren zum Herstellen von Lötstopplack>

[0053] The following describes a method for producing the solder resist 7. As in Fig. As illustrated in Figure 1, the solder mask 7 is a laser photoresist formed by irradiating the upper surfaces of the conductor layers 12a and 12b with laser light. Two examples of the wavelength, output, and frequency of the laser and the laser light sampling conditions are described below. The manufacturing conditions of the solder mask 7 can be modified depending on the material of the upper surfaces of the conductor layers 12a and 12b. The solder masks 71, 72, 73, and 74 are formed by arranging several lines created by laser irradiation, for example, along a longitudinal direction. Example condition 1 Wavelength: 1064 (nm) Issue: 5 (W) Frequency: 5 (kHz) Sampling rate: 8 (mm / s) Distance between lines: 100 (µm) Example condition 2 Wavelength: 532 (nm) Output: 4.8 (W) Frequency: 30 (kHz) Sampling rate: 300 (mm / s) Distance between lines: 10 (µm)

[0054] When the upper surfaces of the upper conductor layers 12a and 12b are irradiated with laser light, an irregularity forms on the upper surface of the upper conductor layers 12a and 12b, and the wettability of the solder material decreases. Additionally, an oxide film forms on the upper surface of the upper conductor layers 12a and 12b, further reducing the wettability of the solder material. <vergleichsbeispiel>

[0055] The following describes a Fig. The comparative example in Figure 6 illustrates this. In the semiconductor device according to the comparative example, the solder mask 6 is not formed on the upper surface of the upper conductor layers 12a and 12b. If a solder component in the solder material vaporizes during melting, the vaporized solder component can form bubbles or be expelled. The semiconductor chip 3a can be affected and displaced by the vaporized solder component. Additionally, if the solder material wettability of the upper conductor layers 12a and 12b is not uniform, the solder material can migrate to a section that is easily wetted, and the semiconductor chip 3a can also move along with the solder material.If the semiconductor chip 3a moves excessively during melting, there is a possibility that the solder material may solidify in a state where a relative positional relationship between the connector and the electrode cannot be maintained. Then there is a possibility that the bond between the connector 51a and the gate electrode 31 may open, and there is a possibility that the bond between the connector 52a and the source electrode 32 may open. In particular, if the semiconductor chip 3a is prepared with a compound semiconductor substrate such as SiC to remove crystal defects, the chip dimensions may be smaller than those of a silicon-based chip.If the chip dimensions are small, the widths w1 and w2, the area of ​​the gate electrode 31 and the source electrode 32, the extent of the electrode 30's clearance, and similar parameters may be affected. Additionally, if the gate electrode 31 and the source electrode 32 are wired via a connector, the extent of the electrode 30's clearance is more limited than if they are wire-bonded. When wire-bonding is used, even slight misalignments of the gate electrode 31 and the source electrode 32 can be detected by a camera or similar device, resulting in a greater range of electrode 30's clearance than when using a connector.

[0056] On the other hand, according to the semiconductor device according to the first embodiment of the present technology, since the solder mask 7 is applied to the upper surface of the upper conductor layers 12a and 12b as in Fig. 3 and Fig. As illustrated in Figure 5, it is possible to restrict the semiconductor chip 3a from moving excessively during melting. Consequently, it is possible to prevent a large change in the positional relationship between the connectors 51a and 52a, the gate electrode 31, and the source electrode 32. It is then possible to prevent the bond between connector 51a and the gate electrode 31 from opening, and it is possible to prevent the bond between connector 52a and the source electrode 32 from opening.

[0057] Additionally, according to the semiconductor device according to the first embodiment of the present technology, since the clearance of the semiconductor chip 3a is smaller than the clearance provided by the gate electrode 31 and the source electrode 32, it is possible to prevent the bonding between the plug connector 51a and the gate electrode 31 from opening, and it is possible to prevent the bonding between the plug connector 52a and the source electrode 32 from opening.

[0058] Additionally, according to the semiconductor device of the first embodiment of the present technology, the solder resists 71, 72, 73, and 74 are connected to each other to form a ring. Since the semiconductor chip 3a is surrounded by the solder resist 7 without a gap, it is possible to reduce the amount of solder material 2a that runs off and spreads from the circumference of the semiconductor chip 3a, and it is possible to prevent the thickness of the solder material 2a from becoming excessively thin and to prevent its shape from deteriorating.

[0059] Additionally, according to the semiconductor device of the first embodiment of the present technology, the solder resists 71, 72, 73 and 74 are the laser photoresists. Since the laser photoresist has an irregularity on its surface, the adhesion between the sealing component 8 and the upper conductor layers 12a and 12b can be improved.

[0060] In addition, according to the semiconductor device according to the first embodiment of the present technology, since the solder resists 71, 72, 73 and 74 are formed using laser light, if a design of the solder resist is changed, it is possible to cope with the change by changing numerical data, and it is possible to prevent a significant increase in production costs. <Erstes Modifikationsbeispiel der ersten Ausführungsform>

[0061] As in Fig. As illustrated in Figure 7, a semiconductor device according to a first modification example of the first embodiment differs from the semiconductor device according to the first embodiment, which is shown in Fig. Figure 1 illustrates this by showing that the solder mask 7 has only the solder masks 71 and 72 provided along the X-direction, and the solder masks 73 and 74 provided along the Y-direction. The other configurations of the semiconductor device according to the first modification example of the first embodiments are the same as those of the semiconductor device according to the first embodiment, and the repeated description is therefore omitted.

[0062] According to the semiconductor device of the first modification example of the first embodiment, it is possible to restrict the semiconductor chip 3a from moving excessively along the X-direction during melting. Consequently, it is possible to prevent a large change in the positional relationship between the plug terminals 51a and 52a, the gate electrode 31, and the source electrode 32 along the X-direction. The solder mask 7 can only have the solder masks 73 and 74. <Zweites Modifikationsbeispiel der ersten Ausführungsform>

[0063] As in Fig. As illustrated in Figure 8, a semiconductor device according to a second modification example of the first embodiment differs from the semiconductor device according to the first modification example of the first embodiment, which is shown in Figure 8. Fig. Figure 7 illustrates this by showing that one of the solder resists 71 and 72 is a linear shape extending along the Y direction, and the other is dot-like. Fig. In Figure 8, the solder mask 71 is a linear shape extending along the Y-direction, and the solder mask 72 is dot-shaped. The solder masks 71 and 72 face each other. The other configurations of the semiconductor device according to the second modification example of the first embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore repeated description is omitted. Even in the semiconductor device according to the second modification example of the first embodiment, the same effects are obtained as in the semiconductor device according to the first modification example of the first embodiment. <Drittes Modifikationsbeispiel der ersten Ausführungsform>

[0064] As in Fig. As illustrated in Figure 9, a semiconductor device according to a third modification example of the first embodiment differs from the semiconductor device according to the second modification example of the first embodiment, which is shown in Figure 9. Fig. Figure 8 illustrates that the semiconductor device has solder masks 73 and 74, one of which is a linear shape extending along the X-direction, and the other is dot-like. Since the other configurations of the semiconductor device according to the third modification example of the first embodiment are the same as those of the semiconductor device according to the second modification example of the first embodiment, the repeated description is omitted. Additionally, the drawings from [reference missing] show... Fig. Nine different dimensions are the same as those in the first embodiment, and their description is therefore omitted. Fig. Solder mask 74 is the linear form extending along the X-direction, and solder mask 73 is dot-like. Solder masks 73 and 74 face each other.

[0065] The semiconductor chip 3a has corner sections 33 and 34 along a diagonal direction. The solder masks 71 and 74 are not connected and are arranged along a side forming corner section 33. The solder masks 72 and 73 are not connected and are arranged near corner section 34. According to the semiconductor device of the third modification example of the first embodiment, it is possible to restrict the semiconductor chip 3a from moving excessively along the X and Y directions during melting. Consequently, it is possible to prevent a large change in the positional relationship between the connectors 51a and 52a, the gate electrode 31, and the source electrode 32.Then it is possible to prevent the bonding between the plug connector 51 and the gate electrode 31 from opening, and it is possible to prevent the bonding between the plug connector 52a and the source electrode 32 from opening. <Viertes Modifikationsbeispiel der ersten Ausführungsform>

[0066] As in Fig. As illustrated in 10, a semiconductor device according to a fourth modification example of the first embodiment differs from the semiconductor device according to the first embodiment, which is shown in Fig. Figure 3 illustrates this by showing that the solder mask 71 is bonded (connected) to only one of the solder masks 73 and 74, and the solder mask 72 is bonded (connected) to only the other of the solder masks 73 and 74. Fig. In Figure 10, the solder mask 71 is bonded to the solder mask 74, and the solder mask 72 is bonded to the solder mask 73. The other configurations of the semiconductor device according to the fourth modification example of the first embodiment are the same as those of the semiconductor device according to the first embodiment, and the repeated description is therefore omitted. The solder masks 71 and 72 could be oriented away from each other. The distance L1 between the solder mask 71 and the solder mask 72 along the X-direction can be obtained using a line extending from one side closer to the semiconductor chip 3a of the solder masks 71 and 72. The solder masks 73 and 74 could likewise be oriented away from each other.

[0067] According to the semiconductor device of the fourth modification example of the first embodiment, the solder mask 71 and 74 prevent the corner section 33 of the semiconductor chip 3a from moving excessively, and the solder mask 72 and 73 prevent the corner section 34 of the semiconductor chip 3a from moving excessively. As a result, it is possible to prevent a large change in the positional relationship between the plug terminals 51a and 52, the gate electrode 31, and the source electrode 32. This prevents the bond between the plug terminal 51a and the gate electrode 31 from opening, and it also prevents the bond between the plug terminal 52a and the source electrode 32 from opening. <Fünftes Modifikationsbeispiel der ersten Ausführungsform>

[0068] As in Fig. As illustrated in 11, a semiconductor device according to a fifth modification example of the first embodiment differs from the semiconductor device according to the first embodiment, which is shown in Fig. 3 is illustrated by the fact that several semiconductor chips 3 are arranged next to each other and the several semiconductor chips 3 share at least a part of the solder resists 71, 72, 73 and 74. Fig. Figure 11 illustrates semiconductor chips 3a and 3e arranged side by side. The other configurations of the semiconductor device according to the fifth modification example of the first embodiment are the same as those of the semiconductor device according to the first embodiment, and the repeated description is therefore omitted.

[0069] Semiconductor chips 3a and 3e are arranged side by side along the Y-direction. Each of the solder masks 71 and 72, provided with respect to semiconductor chips 3a and 3e, is connected in a line along the Y-direction, and the multiple semiconductor chips 3a and 3e share this line. A single solder mask 75, extending along the X-direction, is provided between semiconductor chip 3a and semiconductor chip 3e. The multiple semiconductor chips 3a and 3e share the solder mask 75. The solder mask 75 functions as solder mask 74 with respect to semiconductor chip 3a and as solder mask 73 with respect to semiconductor chip 3e.

[0070] Even in the semiconductor device according to the fifth modification example of the first embodiment, the same effects are obtained as in the semiconductor device according to the first embodiment. The solder mask 73 can be provided on the lower side of the semiconductor chip 3a. Additionally, the solder mask 74 can be provided on the upper side of the semiconductor chip 3e. <Sechstes Modifikationsbeispiel der ersten Ausführungsform>

[0071] As in Fig. As illustrated in Figure 12, a semiconductor device according to a sixth modification example of the first embodiment differs from the semiconductor device according to the first embodiment, which is shown in Figure 12. Fig. Figure 3 illustrates that at least a portion of the solder masks 71, 72, 73, and 74 are interrupted by providing slots, and at least a portion of the solder masks 71, 72, 73, and 74 are provided in a double manner. The other configurations of the semiconductor device according to the sixth modification example of the first embodiment are the same as those of the semiconductor device according to the first embodiment, and the repeated description is therefore omitted.

[0072] Solder masks 71, 72, 73, and 74 are supplied in duplicate. Inner sections supplied in duplicate are designated as solder masks 71, 72, 73, and 74, and outer sections are designated as solder masks 71A, 72A, 73A, and 74A. A portion of solder masks 71, 72, 73, and 74 is interrupted. The interrupted portions of solder masks 71, 72, 73, and 74 are designated as slots 9. Similarly, a portion of solder masks 71A, 72A, 73A, and 74A is interrupted. The interrupted portions of solder masks 71A, 72A, 73A, and 74A are designated as slots 9A. Solder masks 71A, 72A, 73A and 74A are arranged so that they face slots 9. Solder masks 71, 72, 73 and 74 are arranged so that they face slots 9a.

[0073] Even in the semiconductor device according to the sixth modification example of the first embodiment, the same effects are obtained as in the semiconductor device according to the first embodiment. Additionally, in the semiconductor device according to the sixth modification example of the first embodiment, since the solder resists 71, 72, 73, and 74 are provided in duplicate, even when slots 9 and 9A are present, the solder materials 2a and 2e are prevented from excessively saturating and spreading. Consequently, it is possible to prevent the thickness of the solder materials 2a and 2e from becoming excessively thin and to prevent their shape from deteriorating. <Siebtes Modifikationsbeispiel der ersten Ausführungsform>

[0074] As in Fig. As illustrated in Figure 13, a semiconductor device according to a seventh modification example of the first embodiment differs from the semiconductor device according to the first embodiment, which is shown in Figure 13. Fig. Figure 3 illustrates that each of the solder masks 71, 72, 73, and 74 is configured by connecting several dot-shaped solder masks in a row. The solder masks 71, 72, 73, and 74 are connected to each other to form a ring. The other configurations of the semiconductor device according to the seventh modification example of the first embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore the repeated description is omitted. Even in the semiconductor device according to the seventh modification example of the first embodiment, the same effects are obtained as in the semiconductor device according to the first embodiment. <Achtes Modifikationsbeispiel der ersten Ausführungsform>

[0075] As in Fig. As illustrated in Figure 14, a semiconductor device according to an eighth modification example of the first embodiment differs from the semiconductor device according to the sixth modification example of the first embodiment, which is shown in Figure 14. Fig. Figure 12 illustrates that each of the solder masks 71, 72, 73, and 74 is configured by arranging several dot-shaped solder masks in a row. The gaps between the dot-shaped solder masks correspond to slots 9 and 9A. Since other configurations of the semiconductor device according to the eighth modification example of the first embodiment are the same as those of the semiconductor device according to the sixth modification example of the first embodiment, the repeated description is omitted. Even in the semiconductor device according to the eighth modification example of the first embodiment, the same effects are obtained as in the semiconductor device according to the sixth modification example of the first embodiment. The solder masks 71A, 72A, 73A, and 74A could be positioned opposite slots 9. The solder masks 71, 72, 73, and 74 could be positioned opposite slots 9A. (Other embodiments)

[0076] As described above, the present invention is described according to the first embodiment and the modification examples thereof; however, it should be understood that the description and the drawings, which form part of this disclosure, do not limit the present invention. It is obvious to those skilled in the art that various alternative embodiments, examples, and operational technologies can be derived from the present disclosure.

[0077] For example, the configurations disclosed in the first embodiment and its modification examples can be suitably combined within a scope that does not cause any contradictions. In this way, the present invention naturally includes various embodiments and the like, which are not described here. Accordingly, the technical scope of the present invention is limited only by the specific structural elements of the claims that are appropriate in light of the foregoing description. Reference symbol list 1 insulating circuit substrate 3, 3a, 3b, 3c, 3d, 3e, 3f, 3g semiconductor chip 6 printed substrate 7, 71, 71A, 72, 72A, 73, 73A, 74, 74A, 75 solder mask 9, 9A slot 30 electrode 31 Gate electrode 32 Source electrode 51, 51a, 51b, 51c, 52, 52a, 52a1, 52a2 plug connection d1, d2, L2, L4, w1, w2 width L1, L3 distance QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2021-118350 A

[0009] JP 2022-137686 A

[0009] JP 2015-76429 A

[0009] JP 2014-167983 A

[0009] JP 2019-197831 A

[0009] JP 2008-172066 A

[0009] JP 2012-119618 A

[0009] < / vergleichsbeispiel>

Claims

[1] Semiconductor device comprising: an insulating circuit substrate; a semiconductor chip mounted on the insulating circuit substrate using solder material and having an electrode on a top surface; a printed substrate that is positioned over the semiconductor chip; a plug connector that is inserted into the printed substrate and bonded to the electrode via solder; and a first solder mask and a second solder mask provided on an upper surface side of the insulating circuit substrate, and provided such that they are spaced apart from each other along a first direction, where the semiconductor chip is located in the first direction between the first solder mask and the second solder mask. [2] Semiconductor device according to claim 1, wherein, along the first direction, where a distance between the first solder mask and the second solder mask is designated as L1, a width of the semiconductor chip is designated as L2, a width of the electrode is designated as w1 and a width of an area occupied by the plug connector is designated as d1 with respect to the electrode, a relationship of (L1 - L2) < (w1 - d1) is satisfied. [3] Semiconductor device according to claim 1 or 2, further comprising: a third solder mask and a fourth solder mask provided on the upper surface side of the insulating circuit substrate, and provided such that they are spaced apart from each other along a second direction that intersects the first direction, the semiconductor chip is located along the second direction between the third solder mask and the fourth solder mask. [4] Semiconductor device according to claim 3, wherein, along the second direction, where a distance between the third solder mask and the fourth solder mask is designated as L3, a width of the semiconductor chip is designated as L4, a width of the electrode is designated as w2, and a width of an area occupied by the plug connector in relation to the electrode is designated as d2, a relationship of (L3 - L4) < (w2 - d2) is satisfied. [5] Semiconductor device according to claim 3, wherein the first solder mask, the second solder mask, the third solder mask and the fourth solder mask are connected to each other to form a ring. [6] Semiconductor device according to claim 5, wherein at least a part of the first solder mask, the second solder mask, the third solder mask and the fourth solder mask has a slit. [7] Semiconductor device according to claim 6, wherein at least a part of the first solder mask, the second solder mask, the third solder mask and the fourth solder mask is provided in a double manner. [8] Semiconductor device according to claim 1 or 2, wherein one of the first solder mask and the second solder mask extends along the second direction and the other is dot-shaped. [9] Semiconductor device according to claim 3, wherein one of the first solder mask and the second solder mask extends along the second direction and the other is dot-like, and One of the third solder mask and the fourth solder mask extends along the first direction, and the other is dot-like. [10] Semiconductor device according to claim 3, where the first solder mask is bonded only to one of the third and fourth solder masks, and The second solder mask is only bonded to the others of the third and fourth solder masks. [11] Semiconductor device according to claim 3, wherein each of the first solder mask, the second solder mask, the third solder mask and the fourth solder mask consists of several dot-shaped solder masks. [12] Semiconductor device according to claim 3, where several of the semiconductor chips are placed side by side, and the multiple semiconductor chips share at least a part of the first solder mask, the second solder mask, the third solder mask and the fourth solder mask. [13] Semiconductor device according to claim 3, wherein each of the first solder resist, the second solder resist, the third solder resist and the fourth solder resist is a laser photoresist provided by irradiating the upper surface of the isolated circuit substrate with laser light. [14] Semiconductor device according to claim 1 or 2, wherein the electrode is a gate electrode or a source electrode.

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