Functional component within an interconnect structure of a semiconductor device

Abstract

Device comprising: a substrate (101); a first dielectric layer (111M) over the substrate (101); a first connection (113M, 115M) in the first dielectric layer (111M); a second dielectric layer (125, 125') over the first dielectric layer (111M) and the first interconnect (113M, 115M), the second dielectric layer (125, 125') physically contacting the first dielectric layer (111M) and the first interconnect, the second dielectric layer (125') having a thickness between about 5 nm and about 20 nm; a conductive via (501) extending through the first dielectric layer (111M), the second dielectric layer (125') and the substrate (101), wherein a top surface of the conductive via (501) is flush with a top surface of the second dielectric layer (125'); a third dielectric layer (117M+1) over the second dielectric layer (125') and the conductive via (501); a fourth dielectric layer (111M+1) over the third dielectric layer (117M+1); and a second connection (113M+1, 115M+1) in the fourth dielectric layer (111M+1), the second connection (113M+1, 115M+1) extending through the third dielectric layer (117M+1) and the second dielectric layer (125') and physically contacting the first connection (113M, 115M).

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority from U.S. Provisional Patent Application No. 62 / 773,329, filed November 30, 2018, which is hereby incorporated by reference. BACKGROUND

[0002] Semiconductor devices are used in a wide variety of electronic applications, such as PCs, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by depositing insulating or dielectric layers, conductive layers, and semiconductor material layers one after the other on a semiconductor substrate. These layers are then patterned using lithography and etching processes to form circuit components and elements.

[0003] The semiconductor industry is continually improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, and the like) by continually reducing the minimum characteristic dimensions, allowing more components to be integrated into a given area. However, with the reduction of the minimum characteristic dimensions, additional problems arise in each of the processes used, and these additional problems should be addressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood after reading the following detailed description in conjunction with the accompanying figures. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1-8 show cross-sectional views of various intermediate stages of fabricating a semiconductor device according to some embodiments. Fig. 9A and Fig. 9B show cross-sectional views of a semiconductor device according to some embodiments. Fig. 10-16 show cross-sectional views of various intermediate stages of fabricating a semiconductor device according to some embodiments. Fig. 17 shows a cross-sectional view of a semiconductor device according to some embodiments. Fig. 18 shows a flowchart illustrating a method of forming a semiconductor device, according to some embodiments. Fig. 19 shows a flowchart illustrating a method of forming a semiconductor device, according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples of implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not to be considered limiting. For example, the formation of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters throughout the various examples.This repetition is for simplicity and clarity and does not in itself dictate any relationship between the various embodiments and / or configurations.

[0006] Furthermore, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one (or more) other element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device being used or operated in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0007] Embodiments are described with reference to a specific context, namely a functional component within an interconnect structure of a semiconductor device and a method for forming the same. The functional component may be a through-substrate via (TSV) structure or a capacitor. Various embodiments discussed herein enable integration process steps for forming a functional component using process steps for forming an interconnect structure of a semiconductor device. Various embodiments discussed herein further enable avoiding warping or eroding of conductive features of the interconnect structure during the performance of a planarization process on a functional component.

[0008] Fig. 1-8 show cross-sectional views of various intermediate stages of fabricating a semiconductor device 100 according to some embodiments. Referring to Fig. 1, a portion of a semiconductor device 100 is illustrated. The semiconductor device 100 may be an intermediate structure of an integrated circuit manufacturing process. In some embodiments, the semiconductor device 100 may include a substrate 101. The substrate 101 may, for example, comprise primarily doped or undoped silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. In general, an SOI substrate includes a layer of a semiconductor material, such as silicon, formed on an insulator layer. The insulator layer may, for example, be a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is provided on a substrate, such as a silicon or glass substrate. Alternatively, the substrate 101 may include: another elemental semiconductor, such as germanium; a compound semiconductor, such asSilicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0009] In some embodiments, one or more active and / or passive devices 103 (in Fig. 1 as a single transistor) is formed on the substrate 101. The one or more active and / or passive devices 103 may include transistors, capacitors, resistors, diodes, photodiodes, fuses, or the like. The one or more active and / or passive devices 103 may be formed using any suitable methods. Those skilled in the art will appreciate that the above examples are provided for illustrative purposes only and are not intended to limit the present disclosure in any way. Other circuits may be used depending on a given application.

[0010] In some embodiments, an interconnect structure 105 is formed over one or more active and / or passive devices 103 and the substrate 101. The interconnect structure 105 electrically connects the one or more active and / or passive devices 103 to form functional electrical circuits within the semiconductor device 100. The interconnect structure 105 may include one or more metallization layers 1090 to 109 M where M+1 is the number of one or more metallization layers 1090 to 109 M In some embodiments, the value of M may vary depending on the design specifications of the semiconductor device 100. In some embodiments, the metallization layer 109 M an intermediate metallization layer of the interconnect structure 105. In such embodiments, over the metallization layer 109 Mfurther metallization layers are formed. In further embodiments, the metallization layer 109 M the last metallization layer of the interconnect structure 105. In some embodiments, M is equal to 1. In other embodiments, M is greater than 1.

[0011] In some embodiments, the one or more metallization layers 1090 to 109 M one or more dielectric layers 1110 to 111 M . The dielectric layer 1110 is an inter-layer dielectric (ILD) layer, and the dielectric layers 1111 to 111 Mare inter-metal dielectric (IMD) layers. The ILD layer and the IMD layers may comprise dielectric materials with a low k value, for example, less than about 4.0 or even 2.0, disposed between such conductive features. In some embodiments, the ILD layer and the IMD layers may be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiO x C y , spin-on glass, spin-on polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like formed by a suitable process such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), a combination thereof, or the like.

[0012] In some embodiments, etch stop layers (ESLs) 1171 to 117 M between adjacent dielectric layers 111 O up to 111 M For ESLs 1171 to 117 M a material is chosen so that the etching rates of the ESLs 1171 to 117 M are smaller than the etching rates of the corresponding dielectric layers 1110 to 111 M In some embodiments, an etching process that removes the dielectric layers 1110 to 111 M Etches faster than ESLs 1171 to 117 M , a dry etching process performed using an etchant containing a C x F y -based gas or the like. In some embodiments, an etch rate of the ESL 117 K smaller than an etching rate of the dielectric layer 111 K (with K=1,..., M). In some embodiments, each of the ESLs 1171 to 117 Mcomprise one or more layers of dielectric materials. Suitable dielectric materials may include oxides (such as silicon oxide, aluminum oxide, or the like), nitrides (such as SiN or the like), oxynitrides (such as SiON or the like), oxycarbides (such as SiOC or the like), carbonitrides (such as SiCN or the like), carbides (such as SiC or the like), combinations thereof, or the like, and may be formed using spin-on deposition, CVD, PECVD, ALD, a combination thereof, or the like.

[0013] In some embodiments, the metallization layer 1090 further comprises conductive plugs 1150 within the dielectric layer 1110, and the metallization layers 1091 to 109 M further comprise one or more conductive connections, such as conductive lines 1131 to 113 M , and conductive vias 1151 to 115 Mwithin the dielectric layers 1111 to 111 M . The conductive plugs 1150 electrically couple the one or more active and / or passive devices 103 to the conductive traces 1131 to 113 M and the conductive vias 1151 to 115 M . In some embodiments, the conductive traces 1131 to 113 M have a width between about 0.05 µm and about 12 µm.

[0014] In some embodiments, the conductive plugs 1150, the conductive traces 1131 to 113 M and the conductive vias 1151 to 115 M using any suitable process, such as a damascene process, a dual damascene process, or the like. In some embodiments, the steps of forming the conductive plugs 1150, the conductive traces 1131 to 113 M and the conductive vias 1151 to 115 Mforming openings in the respective dielectric layers 111 O up to 111 Mdepositing one or more barrier / adhesive layers 119 (not explicitly shown in the conductive plugs 1150) in the openings, depositing seed layers 121 (not explicitly shown in the conductive plugs 1150) over the one or more barrier / adhesive layers 119, and filling the openings with a conductive material 123 (not explicitly shown in the conductive plugs 1150). Chemical mechanical polishing (CMP) is then performed to remove excess materials of the one or more barrier / adhesive layers 119, the seed layers 121, and the conductive material 123 that overfill the openings. In some embodiments, the topmost surfaces of the conductive plugs 1150 are flush with a topmost surface of the dielectric layer 1110. In some embodiments, the uppermost surfaces of the conductive traces 1131 to 113 Mwith the top surface of the dielectric layers 1111 to 111 M flush.

[0015] In some embodiments, the one or more barrier / adhesive layers 119 may comprise titanium, titanium nitride, tantalum, tantalum nitride, a combination thereof, or the like, and may be formed using PVD, CVD, ALD, a combination thereof, or the like. In some embodiments, the one or more barrier / adhesive layers 119 may have a thickness between about 100 Å and about 300 Å. The one or more barrier / adhesive layers 119 protect the respective dielectric layers 111. O up to 111 Mfrom diffusion and metallic contamination. The core layers 121 may comprise copper, titanium, nickel, gold, manganese, a combination thereof, or the like, and may be formed by ALD, CVD, PVD, sputtering, a combination thereof, or the like. In some embodiments, the seed layers 121 may have a thickness between about 1000 Å and about 3000 Å. The conductive material 123 may comprise copper, aluminum, tungsten, combinations thereof, alloys thereof, or the like, and may be formed, for example, by plating or other suitable methods.

[0016] With reference to Fig. 1 is deposited over the dielectric layer 111 M and the conductor tracks 113 Ma dielectric layer 125 is formed. As described in more detail below, the dielectric layer 125 acts as a CMP stop layer, while forming a substrate via (TSV) structure 501 (see, for example, Fig. 5). In addition, as described in more detail below, the dielectric layer 125 also acts as an ESL while forming conductive vias 115 M+1 (see e.g. Fig. 6) over the conductor tracks 113 M Accordingly, the dielectric layer 125 may also be referred to as a CMP stop layer or an ESL. In some embodiments, the dielectric layer 125 may be formed using similar materials and methods as in the case of the ESLs 1171 to 117 Mformed, and the description will not be repeated here. In some embodiments, the formed dielectric layer 125 has a thickness between about 200 Å and about 500 Å, for example, about 300 Å. Such a thickness range for the dielectric layer 125 enables the dielectric layer 125 to be used as both an ESL and a CMP stop layer, and enables improved CMP uniformity and ESL control.

[0017] After forming the dielectric layer 125, a mask layer 127 is formed over the dielectric layer 125 and patterned to form an opening 129 in the mask layer 127. In some embodiments, the mask layer 127 may include one or more layers of photopatternable and non-photopatternable materials. In some embodiments, the mask layer 127 may include a photoresist that may be patterned using suitable photolithographic techniques to form the opening 129. As described in more detail below, the mask layer 127 is used as an etch mask to form an opening in the interconnect structure 105 and the substrate 101 for a subsequently formed TSV structure.

[0018] With reference to Fig. 2, the interconnect structure 105 and the substrate 101 are patterned to form an opening 201. In some embodiments, the opening 201 extends through the dielectric layer 125, the dielectric layers 111 O up to 111 M and the ESLs 1170 to 117 Mand into the substrate 101. In some embodiments, the interconnect structure 105 and the substrate 101 may be patterned using a suitable etching process while using the mask layer 127 as an etch mask. In some embodiments, the suitable etching process may include one or more dry etching processes, such as a reactive ion etching (RIE) process, a neutral beam etch (NBE) process, or the like. In some embodiments, the suitable etching process may be an anisotropic etching process. In some embodiments, the opening 201 has a width W1 between about 2 µm and about 3 µm. In some embodiments, the opening 201 has a height H1 between about 20 µm and about 50 µm.

[0019] With reference to Fig. 3, after forming the opening 201, the mask layer 127 (see Fig. 2) removed. In some embodiments, the mask layer 127 formed from a photoresist may be removed using an ashing process followed by a wet cleaning process. Subsequently, a liner layer 301 is formed along sidewalls and a bottom surface of the opening 201, as well as over a top surface of the dielectric layer 125. In some embodiments, the liner layer 301 may comprise a suitable insulating material to separate conductive portions of the subsequently formed TSV structure from surrounding layers, such as the dielectric layer 125, the dielectric layers 1110 to 111 M , the ESLs 1170 to 117 Mand the substrate 101. In some embodiments, the liner layer 301 may comprise silicon oxide, silicon nitride, a combination thereof, or the like, and may be formed using ALD, CVD, PECVD, a combination thereof, or the like. In some embodiments, the liner layer 301 has a thickness between about 1000 Å and about 2000 Å.

[0020] After forming the liner layer 301, a barrier layer 303 is formed over the liner layer 301. In some embodiments, the barrier layer 303 may comprise titanium, titanium nitride, tantalum, tantalum nitride, a combination thereof, or the like, and may be formed using PVD, CVD, ALD, a combination thereof, or the like. In some embodiments, the barrier layer 303 has a thickness between about 500 Å and about 2000 Å.

[0021] After forming the barrier layer 303, a seed layer 305 is formed over the barrier layer 303. In some embodiments, the seed layer 305 may comprise copper, titanium, nickel, gold, manganese, a combination thereof, or the like, and may be formed by ALD, CVD, PVD, sputtering, a combination thereof, or the like. In some embodiments, the seed layer 305 has a thickness between about 3000 Å and about 7000 Å.

[0022] With reference to Fig. 4, a remaining section of the opening 201 (see Fig. 3) After forming the seed layer 305, it is filled with a conductive material 401. In some embodiments, the conductive material 401 overfills the opening 201 such that a portion of the conductive material 401 extends along the top surface of the dielectric layer 125. The conductive material 401 may comprise copper, aluminum, tungsten, combinations thereof, alloys thereof, or the like, and may be formed, for example, by plating or other suitable methods.

[0023] With reference to Fig. 5, portions of the lining layer 301, the barrier layer 303, the seed layer 305 and the conductive material 401 that overfill the opening 201 (see Fig. 3), removed. The remaining portions of the liner layer 301, the barrier layer 303, the seed layer 305, and the conductive material 401 form a TSV structure 501. In some embodiments, the removal process may comprise a CMP process, a grinding process, an etching process, a combination thereof, or the like. In some embodiments where the removal process comprises a CMP process, the dielectric layer 125 acts as a CMP stop layer, and the CMP process is performed after exposing the dielectric layer 125 and before exposing the conductive material 123 of the conductive line 113. M stopped so that at least a portion of the dielectric layer 125, the conductive material 123 of the conductor track 113 MIn some embodiments, where the removal process comprises a CMP process, a ratio of a removal rate of the conductive material 401 to a removal rate of the dielectric layer 125 is greater than about 10. In some embodiments, the CMP process may also thin the dielectric layer 125 to form a thinner dielectric layer 125', such that the thinner dielectric layer 125' covers the conductive material 123 of the conductive line 113 M In some embodiments, by maintaining the thinner dielectric layer 125' over the conductive line 113 M a warping or eroding of the conductor track 113 Mduring the CMP process. In some embodiments, a top surface of the TSV structure 501 is flush with a top surface of the thinned dielectric layer 125'. In some embodiments, the thinned dielectric layer 125' has a thickness between about 50 Å and about 200 Å, for example, about 100 Å.

[0024] With reference to Fig. 6, after forming the TSV structure 501, a metallization layer 109 M+1 above the metallization layer 109 M and the TSV structure 501. In some embodiments, the metallization layer 109 comprises M+1 an ESL 117 M+1 , a dielectric layer 111 M+1 and conductive connections with conductor tracks 113 M+1 and conductive vias 11 5M+1 In some embodiments, the ESL 117 M+1using similar materials and methods as those described above with reference to Fig. 1 described ESLs 1171 to 117 M formed, and the description is not repeated here. In some embodiments, the dielectric layer 111 M+1 using similar materials and methods as those described above with reference to Fig. 1 described dielectric layers 1110 to 111 M formed, and the description is not repeated here. In some embodiments, the conductive traces 113 M+1 and the conductive vias 11 5M+1 using similar materials and processes as the conductor tracks 1131 to 113 M and the conductive vias 1151 to 11 5M , which are mentioned above with reference to Fig. 1, and the description is not repeated here. In some embodiments, the ESL 117 M+1 a thickness between about 100 Å and about 350 Å.

[0025] In some embodiments, the dielectric layer 125' and the ESL 117 M+1 as a combined ESL, which is used to form openings for the conductive vias 11 5M+1 In some embodiments, the combined ESL has a thickness between about 300 Å and about 400 Å. In some embodiments, the thickness of the ESL is 117 M+1 greater than the thickness of the dielectric layer 125'. In further embodiments, the thickness of the ESL 117 M+1 less than or equal to the thickness of the dielectric layer 125'. In some embodiments, the dielectric layer 125' is formed during the process described above with reference to Fig. 5 described CMP process to such a small thickness that the conductive vias 11 5M+1 above the conductor tracks 113 M and the conductive vias 11 5M+1 above the TSV structure 501 have similar profiles. In the Fig. 6 illustrated embodiment include the ESL 117 M+1 and the dielectric layer 125' are the same material. In such embodiments, a layer of dielectric material can be formed between the ESL 117 M+1 and the dielectric layer 125' may not detect an interface. In addition, the widths of the conductive vias 11 5M+1 not, while the conductive vias 11 5M+1 by the ESL 117 M+1 and the dielectric layer 125'. In further embodiments, the ESL 117 M+1and the dielectric layer 125' may comprise different materials. Such an embodiment is described in Fig. 9A and Fig. 9B.

[0026] With reference to Fig. 7, in some embodiments, additional metallization layers are formed over the metallization layer 109 M+1 formed until N metallization layers (the metallization layers 109 M+1 up to 109 M+N ) over the metallization layer 109 M and the TSV structure 501, wherein the metallization layer 109 M+N is the last metallization layer of the interconnect structure 105. In some embodiments, the metallization layer 109 comprises M+X an ESL 117 M+X , a dielectric layer 111 M+X and conductive connections with conductor tracks 113 M+X and conductive vias 11 5M+X (with X=2,..., N). In some embodiments, the ESL 117 M+X(with X=2,..., N) using similar materials and methods as those described above with reference to Fig. 1 described ESLs 1171 to 117 M formed, and the description is not repeated here. In some embodiments, the dielectric layer 111 M+X (with X=2,..., N) using similar materials and processes as those described above with reference to Fig. 1 described dielectric layers 111 O up to 111 M , and the description is not repeated here. In some embodiments, the conductive traces 113 M+X and the conductive vias 115 M+X (with X=2,..., N) using similar materials and processes as the conductor tracks 1131 to 113 M and the above with reference to Fig. 1 described conductive vias 1151 to 115 Mformed, and the description is not repeated here. In some embodiments, N is equal to 1. In other embodiments, N is greater than 1.

[0027] With reference to Fig. 8 can be formed after the formation of the last metallization layer 109 M+Nthe interconnect structure 105, various process steps may be performed on the semiconductor device 100. In some embodiments, a thinning process may be performed on a backside of the substrate 101 to expose the TSV structure 501. In some embodiments, the thinning process may include a CMP process, a grinding process, an etching process, a combination thereof, or the like. In some embodiments, the thinning process is stopped after the conductive material 401 of the TSV structure 501 is exposed. In further embodiments, the thinning process is stopped after the barrier layer 303 of the TSV structure 501 is exposed. In still further embodiments, the thinning process is stopped after the seed layer 305 of the TSV structure 501 is exposed.

[0028] Fig. 9A shows a cross-sectional view of a semiconductor device 900 according to some embodiments. Fig. 9B shows an enlarged cross-sectional view of a portion 901 of the Fig. 9A, according to some embodiments. In some embodiments, the semiconductor device 900 is similar to the semiconductor device 900 shown in Fig. 8, wherein similar features are designated by similar reference numerals, and the descriptions of the similar features are not repeated herein. In some embodiments, the semiconductor device 900 may be fabricated using similar materials and methods as those described above with reference to Fig. 1-8, and the description will not be repeated here.

[0029] In the Fig. 9A and Fig. 9B, the ESL 117 M+1and the dielectric layer 125' different materials. In some embodiments, an etch rate of the ESL 117 M+1 relating to an etching process that creates openings for the conductive vias 11 5M+1 forms, greater than an etch rate of the dielectric layer 125'. In some embodiments, the etching process is a dry etching process performed using an etchant that generates a gas on C x F y -Base with a fluorine (F) content that is greater than a carbon (C) content, or the like. In such embodiments, the widths of the conductive vias 11 5M+1 while the conductive vias 11 5M+1 by the ESL 117 M+1 and the dielectric layer 125'. In some embodiments, the conductive vias 11 5M+1 within the ESL 117 M+1a uniform width W2. In some embodiments, the width W2 is between about 0.2 µm and about 0.4 µm. In some embodiments, the conductive vias 11 5M+1 within the dielectric layer 125' a non-uniform width. In some embodiments, the conductive vias 11 5M+1 within the dielectric layer 125' at the top surface of the conductor track 113 M a width W3. In some embodiments, the width W3 is between about 0.12 µm and about 0.35 µm. In some embodiments, a ratio W3 / W2 is between about 0.6 and about 0.9.

[0030] Fig. 10-16 show cross-sectional views of various intermediate stages of fabricating a semiconductor device 1000 according to some embodiments. Referring to Fig. 10, a method of forming the semiconductor device 1000 begins with forming a mask layer 1001 over a dielectric layer 125 of a Fig. 1. In some embodiments, the mask layer 1001 is patterned to form an opening 1003 in the mask layer 1001. In some embodiments, the mask layer 1001 may comprise one or more layers of photopatternable and non-photopatternable materials. In some embodiments, the mask layer 1001 may comprise a photoresist that may be patterned using suitable photolithographic techniques to form the opening 1003 in the mask layer 1001. As described in more detail below, the mask layer 1001 is used as an etch mask to form an opening in the interconnect structure 105 for a subsequently formed capacitor.

[0031] With reference to Fig. 11, the interconnect structure 105 is patterned to form an opening 1101 in the interconnect structure 105. In some embodiments, the opening 1101 extends through the dielectric layer 125, the dielectric layer 111 M and the ESL 117 M . In further embodiments, the opening 1101 may also extend through one or more of the dielectric layers 111 O up to 111 M-1 and one or more of the ESLs 1171 to 117 M-1extend without extending into the substrate 101. In some embodiments, the interconnect structure 105 may be patterned using a suitable etching process while using the mask layer 1001 as an etch mask. In some embodiments, the suitable etching process may include one or more dry etching processes, such as a reactive ion etch (RIE) process, a neutral beam etch (NBE) process, or the like. In some embodiments, the suitable etching process may be an anisotropic etching process. In some embodiments, the opening 1101 has a width W4 between about 2.1 µm and about 5.2 µm. In some embodiments, the opening 1101 has a height H4 between about 1.0 µm and about 2.0 µm.

[0032] With reference to Fig. 12, after forming the opening 1101, the mask layer 1001 (see Fig. 11). In some embodiments, the mask layer 1001 formed of a photoresist may be removed using an ashing process followed by a wet cleaning process. Subsequently, a first conductive layer 1201 is formed along sidewalls and a bottom surface of the opening 1101 and over a top surface of the dielectric layer 125. In some embodiments, the first conductive layer 1201 may include one or more layers of TaN, TiN, a combination thereof, or the like, and may be formed using ALD, CVD, PECVD, a combination thereof, or the like. In some embodiments, the first conductive layer 1201 may also be referred to as a bottom electrode layer. In some embodiments, the first conductive layer 1201 has a thickness between about 400 Å and about 800 Å.

[0033] After forming the first conductive layer 1201, a dielectric layer 1203 is formed over the first conductive layer 1201. In some embodiments, the dielectric layer 1203 may comprise a material with a high dielectric constant (k), such as ZrO2, HfO2, Si3N4, barium strontium titanate (BST), a combination thereof, or the like, and may be formed using ALD, CVD, PECVD, a combination thereof, or the like. In further embodiments, the dielectric layer 1203 may comprise other suitable dielectric materials. In some embodiments, the dielectric layer 1203 has a thickness between about 50 Å and about 100 Å.

[0034] With reference to Fig. 13, a second conductive layer 1301 is formed over the dielectric layer 1203. In some embodiments, the second conductive layer 1301 overfills the remaining portion of the opening 1101 (see Fig. 12) such that a portion of the second conductive layer 1301 extends along the top surface of the dielectric layer 125. In some embodiments, the second conductive layer 1301 may include one or more layers of TiN, TaN, copper, a combination thereof, or the like. In some embodiments, the second conductive layer 1301 may include a layer of TiN or TaN formed over the dielectric layer 1203 using ALD, CVD, PECVD, a combination thereof, or the like, and a layer of copper formed over the layer of TiN or TaN using plating or other suitable methods. In some embodiments, the second conductive layer 1301 may also be referred to as a top electrode layer.

[0035] With reference to Fig. 14, portions of the first conductive layer 1201, the dielectric layer 1203 and the second conductive layer 1301 that overfill the opening 1101 (see Fig. 11). The remaining portions of the first conductive layer 1201, the dielectric layer 1203, and the second conductive layer 1301 form a capacitor 1401. In some embodiments, the capacitor 1401 may be a decoupling capacitor. The remaining portion of the first conductive layer 1201 may also be referred to as a bottom electrode, and the remaining portion of the second conductive layer 1301 may also be referred to as a top electrode. In some embodiments, the bottom electrode is electrically coupled to conductive features of the interconnect structure 105. In some embodiments, the removal process may include a CMP process, a grinding process, an etching process, a combination thereof, or the like.In some embodiments where the removal process includes a CMP process, the dielectric layer 125 acts as a CMP stop layer, and the CMP process is performed after exposing the dielectric layer 125 and before exposing the conductive material 123 of the conductive line 113. M stopped so that at least a portion of the dielectric layer 125, the conductive material 123 of the conductor track 113 M In some embodiments, the CMP process may also thin the dielectric layer 125 to form a thinner dielectric layer 125', such that the thinner dielectric layer 125' covers the conductive material 123 of the conductive line 113 M In some embodiments, by maintaining the thinner dielectric layer 125' over the conductive line 113 M a warping or eroding of the conductor track 113 Mduring the CMP process. In some embodiments, a top surface of the capacitor 1401 is flush with a top surface of the thinned dielectric layer 125'. In some embodiments, the thinned ESL 125' has a thickness between about 50 Å and about 200 Å, for example, about 100 Å.

[0036] With reference to Fig. 15, after forming the capacitor 1401, a metallization layer 109 M+1 above the metallization layer 109 M and the capacitor 1401. In some embodiments, the metallization layer 109 comprises M+1 an ESL 117 M+1 , a dielectric layer 111 M+1 and conductive connections with conductor tracks 113 M+1 and conductive vias 115 M+1 . In some embodiments, the metallization layer 109 M+1 as above with reference to Fig. 6, and the description is not repeated here. In some embodiments, the dielectric layer 125' and the ESL 117 M+1 as a combined ESL used to form openings for the conductive vias 11 5M+1 serves. In the Fig. 15 illustrated embodiment include the ESL 117 M+1 and the dielectric layer 125' are the same material. In such embodiments, a layer of dielectric material can be formed between the ESL 117 M+1 and the dielectric layer 125' may not detect an interface. In addition, the widths of the conductive vias 11 5M+1 not, while the conductive vias 11 5M+1 by the ESL 117 M+1 and the dielectric layer 125'. In further embodiments, the ESL 117 M+1and the dielectric layer 125' may comprise different materials. Such an embodiment is described in Fig. 17 shown.

[0037] With reference to Fig. 16, in some embodiments, additional metallization layers are formed over the metallization layer 109 M+1 formed until N metallization layers (the metallization layer 109 M+1 up to 109 M+N ) over the metallization layer 109 M and the capacitor 1401, wherein the metallization layer 109 M+N is the last metallization layer of the interconnect structure 105. In some embodiments, N is equal to 1. In further embodiments, N is greater than 1. In some embodiments, the additional metallization layers are formed as described above with reference to Fig. 7, and the description is not repeated here.

[0038] Fig. 17 illustrates a cross-sectional view of a semiconductor device 1700, wherein Fig. 9B illustrates an enlarged cross-sectional view of a portion 1701 of the semiconductor device 1700 according to some embodiments. In some embodiments, the semiconductor device 1700 is similar to that shown in Fig. 16, wherein similar features are designated by similar reference numerals, and the descriptions of the similar features are not repeated herein. In some embodiments, the semiconductor device 1700 may be formed using similar materials and methods as those described above with reference to Fig. 10-16, and the description will not be repeated here. In the semiconductor device 1000 described in Fig. 17 illustrated embodiment include the ESL 117 M+1and the dielectric layer 125' different materials. In some embodiments, an etch rate of the ESL 117 M+1 relating to an etching process that creates openings for the conductive vias 11 5M+1 forms, greater than an etching rate of the dielectric layer 125'. In such embodiments, the widths of the conductive vias 11 5M+1 while the conductive vias 11 5M+1 by the ESL 117 M+1 and the dielectric layer 125'.

[0039] With reference to Fig. 9B have the conductive vias 115 M+1 in some embodiments within the ESL 117 M+1 a uniform width W2. In some embodiments, the width W2 is between about 0.2 µm and about 0.4 µm. In some embodiments, the conductive vias 11 5M+1within the dielectric layer 125' a non-uniform width. In some embodiments, the conductive vias 11 5M+1 a width W3 within the dielectric layer 125' at the top surface of the conductor track 113 M In some embodiments, the width W3 is between about 0.12 µm and about 0.35 µm. In some embodiments, a ratio W3 / W2 is between about 0.6 and about 0.9.

[0040] Fig. 18 shows a flowchart illustrating a method 1800 for forming a semiconductor device according to some embodiments. The method 1800 begins with step 1801, where one or more first metallization layers (such as the one or more metallization layers 1090 to 109 M , which in Fig. 1) over a substrate (such as that shown in Fig. 1 illustrated substrate 101) as described above with reference to Fig. 1. In step 1803, a substrate via (TSV) (such as the one shown in Fig. 5 illustrated TSV structure 501) is formed as described above with reference to Fig. 2-5. In step 1805, one or more second metallization layers (such as the one or more metallization layers 109 M+1 up to 109 M+N , which in Fig. 7) formed over the TSV as described above with reference to Fig. 6 and Fig. 7. In step 1807, a backside of the substrate is thinned to expose the TSV, as described above with reference to Fig. 8 described.

[0041] Fig. 19 shows a flowchart illustrating a method 1900 for forming a semiconductor device according to some embodiments. The method 1900 begins with step 1901, where one or more first metallization layers (such as the one or more metallization layers 109 O up to 109 M , which in Fig. 10) over a substrate (such as that shown in Fig. 10 illustrated substrate 101) as described above with reference to Fig. 10. In step 1903, a capacitor (such as the one in Fig. 14) is formed within the one or more first metallization layers as described above with reference to Fig. 10-14. In step 1905, one or more second metallization layers (such as the one or more metallization layers 109 M+1 up to 109 M+N , which in Fig. 16) formed over the capacitor as described above with reference to Fig. 15 and Fig. 16 described.

[0042] According to another embodiment, a device comprises: a substrate; a first dielectric layer over the substrate; a first interconnect in the first dielectric layer; a second dielectric layer over the first dielectric layer and the first interconnect, wherein the second dielectric layer and the first dielectric layer physically contact each other, wherein the first interconnect, the second dielectric layer has a thickness between about 5 nm and about 20 nm; a conductive via extending through the first dielectric layer, the second dielectric layer, and the substrate,wherein a top surface of the conductive via is flush with a top surface of the second dielectric layer; a third dielectric layer over the second dielectric layer and the conductive via; a fourth dielectric layer over the third dielectric layer; and a second interconnect in the fourth dielectric layer, the second interconnect extending through the third dielectric layer and the second dielectric layer and physically contacting the first interconnect. In one embodiment, the second dielectric layer and the third dielectric layer comprise a same material. In one embodiment, the second dielectric layer and the third dielectric layer comprise different materials. In one embodiment, the second interconnect narrows,while the second connection extends through the second dielectric layer toward the first connection. In one embodiment, the ratio of the width of the second connection at a bottom of the second dielectric layer to the width of the second connection at a top of the second dielectric layer is between 0.6 and 0.9. In one embodiment, the second connection in the third dielectric layer has a uniform width. In one embodiment, the device further includes a third connection in the fourth dielectric layer,wherein the third connection extends through the third dielectric layer and physically contacts the conductive via. In one embodiment, a bottom surface of the conductive via is flush with a surface of the substrate. In one embodiment, the second dielectric layer and the third dielectric layer form a combined etch stop layer. In one embodiment, the via comprises a conductive material, wherein a ratio of a removal rate of the conductive material of the conductive via to a removal rate of the dielectric layer is greater than about 10. In one embodiment, the second dielectric layer physically contacts the third dielectric layer.

[0043] According to another embodiment, a device comprises: a substrate; a first dielectric layer over the substrate; a first interconnect in the first dielectric layer; a second dielectric layer over the first dielectric layer and the first interconnect, wherein the second dielectric layer and the first dielectric layer physically contact each other, the second dielectric layer having a thickness between about 5 nm and about 20 nm; a capacitor within the first dielectric layer and the second dielectric layer, the capacitor comprising a first conductive layer, a second conductive layer, and a third dielectric layer between the first conductive layer and the second conductive layer,wherein a top surface of the capacitor is flush with a top surface of the second dielectric layer; a fourth dielectric layer over the second dielectric layer and the conductive via; a fifth dielectric layer over the fourth dielectric layer; and a second interconnect in the fifth dielectric layer, the second interconnect extending through the fourth dielectric layer and the second dielectric layer and physically contacting the first interconnect. In one embodiment, the second dielectric layer and the fourth dielectric layer comprise a same material. In one embodiment, the second dielectric layer and the fourth dielectric layer comprise different materials. In one embodiment, the second interconnect narrows,while the second connection extends through the second dielectric layer toward the first connection. In one embodiment, the ratio of the width of the second connection at a bottom of the second dielectric layer to the width of the second connection at a top of the second dielectric layer is between 0.6 and 0.9. In one embodiment, the second connection in the fourth dielectric layer has a uniform width. In one embodiment, the device further includes a third connection in the fifth dielectric layer,wherein the third connection extends through the fourth dielectric layer and physically contacts the conductive via. In one embodiment, the second dielectric layer and the fourth dielectric layer form a combined etch stop layer. In one embodiment, the second dielectric layer physically contacts the fourth dielectric layer.

[0044] In the foregoing, features of several embodiments are summarized in order to better understand aspects of the present disclosure to those skilled in the art. It should be apparent to those skilled in the art that the present disclosure may be readily utilized as a basis for designing or modifying other processes and structures to accomplish the same purposes and / or achieve the same advantages of the embodiments presented herein. It should also be apparent to those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations may be made herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 62 / 773 329

[0001]

Claims

[1] Device comprising: a substrate (101); a first dielectric layer (111M) over the substrate (101); a first connection (113M, 115M) in the first dielectric layer (111M); a second dielectric layer (125, 125') over the first dielectric layer (111M) and the first interconnect (113M, 115M), the second dielectric layer (125, 125') physically contacting the first dielectric layer (111M) and the first interconnect, the second dielectric layer (125') having a thickness between about 5 nm and about 20 nm; a conductive via (501) extending through the first dielectric layer (111M), the second dielectric layer (125') and the substrate (101), wherein a top surface of the conductive via (501) is flush with a top surface of the second dielectric layer (125'); a third dielectric layer (117M+1) over the second dielectric layer (125') and the conductive via (501); a fourth dielectric layer (111M+1) over the third dielectric layer (117M+1); and a second connection (113M+1, 115M+1) in the fourth dielectric layer (111M+1), the second connection (113M+1, 115M+1) extending through the third dielectric layer (117M+1) and the second dielectric layer (125') and physically contacting the first connection (113M, 115M). [2] The device of claim 1, wherein the second dielectric layer (125') and the third dielectric layer (117M+1) comprise a same material. [3] The device of claim 1, wherein the second dielectric layer (125') and the third dielectric layer (117M+1) comprise different materials. [4] The device of claim 1 or 3, wherein the second interconnection (115M+1) narrows as the second interconnection (115M+1) extends through the second dielectric layer (125') toward the first interconnection (113M, 115M). [5] The device of claim 4, wherein the ratio of the width (W3) of the second connection (113M+1, 115M+1) at a bottom side of the second dielectric layer (125, 125') to the width (W2) of the second connection (113M+1, 115M+1) at a top side of the second dielectric layer (125, 125') is between 0.6 and 0.

9. [6] A device according to any one of the preceding claims, wherein the second connection (113M+1, 115M+1) in the third dielectric layer (117M+1) has a uniform width (W2). [7] The device of any preceding claim, further comprising a third interconnect (113M+1, 115M+1) in the fourth dielectric layer (111M+1), the third interconnect (113M+1, 115M+1) extending through the third dielectric layer (117M+1) and physically contacting the conductive via (125'). [8] The device of any preceding claim, wherein a lowermost surface of the conductive via (501) is flush with a surface of the substrate (101). [9] The device of any preceding claim, wherein the second dielectric layer (125') and the third dielectric layer (117M+1) form a combined etch stop layer. [10] The device of any preceding claim, wherein the via (501) comprises a conductive material, wherein a ratio of a removal rate of the conductive material of the conductive via (501) to a removal rate of the dielectric layer (125) is greater than about 10. [11] The device of any preceding claim, wherein the second dielectric physically contacts the third dielectric layer (117M+1). [12] Device comprising: a substrate (101); a first dielectric layer (111M) over the substrate (101); a first connection (113M, 115M) in the first dielectric layer (111M); a second dielectric layer (125, 125') over the first dielectric layer (111M) and the first interconnect (113M, 115M), the second dielectric layer (125, 125') physically contacting the first dielectric layer (111M) and the first interconnect (113M, 115M), the second dielectric layer having a thickness between about 5 nm and about 20 nm; a capacitor (1401) within the first dielectric layer (111M) and the second dielectric layer (125'), the capacitor (1401) comprising a first conductive layer (1201), a second conductive layer (1301), and a third dielectric layer (1203) between the first conductive layer (1201) and the second conductive layer (1301), a top surface of the capacitor (1401) being flush with a top surface of the second dielectric layer (125'); a fourth dielectric layer (117M+1) over the second dielectric layer (125') and the conductive via (501); a fifth dielectric layer (111M+1) over the fourth dielectric layer (117M+1); and a second connection (113M+1, 115M+1) in the fifth dielectric layer (111M+1), the second connection (113M+1, 115M+1) extending through the fourth dielectric layer (117M+1) and the second dielectric layer (125') and physically contacting the first connection (113M, 115M). [13] The device of claim 12, wherein the second dielectric layer (125') and the fourth dielectric layer (117M+1) comprise a same material. [14] The device of claim 12, wherein the second dielectric layer (125') and the fourth dielectric layer (117M+1) comprise different materials. [15] The device of claim 12 or 14, wherein the second interconnection (115M+1) narrows as the second interconnection (115M+1) extends through the second dielectric layer (125') toward the first interconnection (113M, 115M). [16] The device of claim 15, wherein the ratio of the width (W3) of the second connection (113M+1, 115M+1) at a bottom side of the second dielectric layer (125, 125') to the width (W2) of the second connection (113M+1, 115M+1) at a top side of the second dielectric layer (125, 125') is between 0.6 and 0.

9. [17] The device according to any one of claims 12 to 16, wherein the second interconnection (113M+1, 115M+1) in the fourth dielectric layer (117M+1) has a uniform width (W2). [18] The device of any one of claims 12 to 17, further comprising a third interconnect (113M+1, 115M+1) in the fifth dielectric layer (111M+1), the third interconnect (113M+1, 115M+1) extending through the fourth dielectric layer (117M+1) and physically contacting the conductive via (125'). [19] The device of any one of claims 12 to 18, wherein the second dielectric layer (125') and the fourth dielectric layer (117M+1) form a combined etch stop layer. [20] The device of any one of claims 12 to 19, wherein the second dielectric layer (125, 125') physically contacts the fourth dielectric layer (117M+1).

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