Solar cell, photovoltaic module and photovoltaic system

Abstract

Solar cell, comprising: a substrate (10) comprising a first surface (F), a second surface (S) and a plurality of first side surfaces (C1), the first surface and the second surface being opposite one another, the plurality of first side surfaces being adjacent to and located between the first and second surfaces, at least the first surface and a portion of the first side surface of the substrate comprising a textured structure (20); a doped conductive layer (30) disposed on at least the first surface and the portion of the first side surface to cover the textured structure; a first passivation layer (40) stacked on the doped conductive layer and covering the first surface and at least the portion of the first side surface, thereby covering at least the doped conductive layer; a passivating contact layer (50) disposed on the second surface; and a second passivation layer (60) stacked on the passivating contact layer and covering the second surface, thereby covering the passivating contact layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular a solar cell, a photovoltaic module and a photovoltaic system. BACKGROUND

[0002] As photovoltaic technology has rapidly advanced, the efficiency of crystalline silicon solar cells has improved year after year. Currently, tunnel oxide passivated contact solar cells (TOPCon solar cells) are gaining traction due to their advantages such as high efficiency and well-established industrial manufacturing processes. Many manufacturers in the industry have intensified their research and development efforts for TOPCon cells. State-of-the-art TOPCon cell manufacturing involves doping both the front and back surfaces of the cells to improve lateral charge transport capability. However, this approach also leads to strong recombination of charge carriers on the sides of the cells, which can lead to potential leakage problems and an overall reduction in solar cell efficiency. SUMMARY

[0003] In view of this, there is a need to provide a solar cell with relatively high efficiency, a method for its production, a photovoltaic module and a photovoltaic system.

[0004] A first aspect of embodiments of the present application provides a solar cell. The solar cell includes a substrate, a doped conductive layer, a first passivation layer, a passivating contact layer, and a second passivation layer. The substrate includes a first surface, a second surface, and a plurality of first side surfaces. The first surface and the second surface are opposite one another. The plurality of first side surfaces are adjacent to and located between the first surface and the second surface. At least the first surface and a portion of the first side surface of the substrate include a textured structure. The doped conductive layer is disposed on at least the first surface and the portion of the first side surface to cover the textured structure.The first passivation layer is stacked on the doped conductive layer and covers the first surface and at least the portion of the first side surface to cover at least the doped conductive layer. The passivating contact layer is arranged on the second surface. The second passivation layer is stacked on the passivating contact layer and covers the second surface to cover the passivating contact layer.

[0005] In some embodiments, the first side surface includes a textured region provided with the textured structure and a flat region adjacent to the textured region. On the first side surface, the first passivation layer completely covers the textured region and covers at least a portion of the flat region.

[0006] In some embodiments, an edge of the first passivation layer facing away from the first surface is flush with a surface of the passivating contact layer facing away from the substrate.

[0007] In some embodiments, the substrate further includes at least one cut-edge side surface adjacent to and located between the first and second surfaces. Only the first surface and the portion of the first side surface enclose the textured structure. The doped conductive layer is disposed only on the first surface and the portion of the first side surface to cover the textured structure.

[0008] In some embodiments, the cut edge side surface is flush in the normal direction with the edges of the doped conductive layer, the first passivation layer, the passivating contact layer, and the second passivation layer that are on the same side as the cut edge side surface.

[0009] In some embodiments, the first passivation layer also at least partially covers the cut edge side surface.

[0010] In some embodiments, the second passivation layer further at least partially covers the cut edge side surface such that it covers at least a portion of the first passivation layer located on the cut edge side surface.

[0011] In some embodiments, the substrate further includes at least one cut edge side surface adjacent to and located between the first and second surfaces. At least a portion of the cut edge side surface includes the textured structure. The doped conductive layer is disposed on the first surface, the portion of the first side surface, and the portion of the cut edge side surface to cover the textured structure. The first passivation layer further covers at least the portion of the cut edge side surface to cover at least the doped conductive layer.

[0012] In some embodiments, the second passivation layer further at least partially covers the cut edge side surface such that it covers at least a portion of the first passivation layer located on the cut edge side surface.

[0013] In some embodiments, the second passivation layer further at least partially covers the first side surface such that it covers at least a portion of the first passivation layer located on the first side surface.

[0014] In some embodiments, the first side surface includes a textured region provided with the textured structure and a flat region adjacent to the textured region. The first passivation layer includes a first portion located on the first side surface, and the first portion covers the flat region. The second passivation layer covers at least the first portion.

[0015] In some embodiments, the first passivation layer further includes a second portion located on the first side surface, and the second portion covers the textured region. The second passivation layer covers the first portion and at least a portion of the second portion.

[0016] In some embodiments, an edge of the second passivation layer facing away from the second surface is flush with an outer surface of the first passivation layer located on the first surface.

[0017] In some embodiments, the textured structure of the first surface and the textured structure of the first side surface form a continuous structure. Alternatively, the textured structure of the first surface is spaced apart from the textured structure of the first side surface.

[0018] In some embodiments, the first passivation layer includes a first passivation film and a first anti-reflection film stacked on the doped conductive layer; and / or the second passivation layer includes at least a second anti-reflection film stacked on the passivating contact layer.

[0019] A second aspect of the embodiments of the present application provides a method for manufacturing a solar cell. The method includes the following steps: Providing a wafer, the wafer including a substrate and a doped conductive layer, the substrate including a first surface, a second surface, and a plurality of first side surfaces, the first surface and the second surface being opposite each other, and the plurality of first side surfaces being adjacent to and located between the first and second surfaces, at least the first surface and a portion of the first side surface of the substrate including a textured structure, the doped conductive layer being disposed on at least the first surface and the portion of the first side surface, thereby covering the textured structure; Forming a passivating contact layer on the second surface of the substrate; Forming a first passivation layer on the doped conductive layer, the first passivation layer covering the first surface and at least the portion of the first side surface to cover at least the doped conductive layer; and Forming a second passivation layer on the passivating contact layer, thereby forming a solar cell array, wherein the second passivation layer covers the second surface so as to cover the passivating contact layer.

[0020] In some embodiments, after forming the second passivation layer on the passivating contact layer, the method further includes a step of laser cutting the solar cell matrix along the thickness direction to form at least two solar cells.

[0021] In some embodiments, the step of providing the wafer includes: Performing a texturing treatment and diffusing doping elements onto at least the first surface and the first side surface of the substrate; and Etching the substrate to expose the second surface and a first target area of ​​each first side surface; wherein the first target area is adjacent to and connected to the second surface.

[0022] In some embodiments, the step of providing the wafer includes: Cutting a substrate blank along the thickness direction to form the substrate and a cut edge side surface of the substrate; Performing a texturing treatment and diffusing doping elements onto at least the first surface, the first side surface, and the cut edge side surface of the substrate; and Etching the substrate to expose the second surface, a first target area of ​​each first side surface, and a second target area of ​​each cut edge side surface of the substrate, so as to form the textured structure and the doped conductive layer covering the textured structure on the first surface, the portion of the first side surface, and a portion of the cut edge side surface of the substrate; wherein the first target area is adjacent to the second surface and the second target area is adjacent to the second surface.

[0023] In some embodiments, the step of forming the passivating contact layer on the second surface of the substrate includes: sequentially forming a tunnel material layer, a doped polysilicon material layer, and an oxide material layer on each surface of the wafer; Etching to remove the oxide material layer on a surface of a first side of the wafer and on each side surface of the wafer; and Etching to remove the doped polysilicon material layer and the tunneling material layer on the surface of the first side of the wafer and on each side surface of the wafer; wherein the surface of the first side of the wafer corresponds to the first surface of the substrate.

[0024] In some embodiments, the step of forming the passivating contact layer on the second surface of the substrate includes: Forming a passivating contact material layer on each surface of the wafer; Cutting the wafer formed with the passivating contact material layer along the thickness direction of the substrate to form the cut edge side surface of the substrate; and Etching to remove the passivating contact material layer disposed outside the second surface of the substrate, thereby forming the passivating contact layer.

[0025] In some embodiments, after the step of forming the second passivation layer on the passivating contact layer, the method further includes a step of forming electrodes on the first passivation layer and the second passivation layer, respectively.

[0026] A third aspect of the embodiments of the present application provides a photovoltaic module including at least one cell group. The cell group includes at least two interconnected solar cells as described above.

[0027] A fourth aspect of the embodiments of the present application provides a photovoltaic system including the photovoltaic module described above.

[0028] A fifth aspect of the embodiments of the present application provides a method for manufacturing a solar cell. The method includes the following steps: Providing a wafer, the wafer including a substrate and a doped conductive layer, the substrate including a first surface, a second surface, and a plurality of first side surfaces, the first surface and the second surface being opposite each other, and the plurality of first side surfaces being adjacent to and located between the first surface and the second surface, the first surface and a portion of the first side surface of the substrate including a textured structure, the doped conductive layer being disposed on the first surface and the portion of the first side surface to cover the textured structure; Forming a passivating contact material layer on each surface of the wafer; Cutting the wafer formed with the passivating contact material layer along the thickness direction of the substrate to form at least two sub-wafers to cut the doped conductive material layer into doped conductive layers; Etching to remove the passivating contact material layer on a surface of a first side of the sub-wafer and on each side surface of the sub-wafer, thereby forming a passivating contact layer on the sub-wafer, wherein the surface of the first side of the sub-wafer corresponds to the first surface of the substrate; and Forming a first passivation layer on the doped conductive layer, wherein the first passivation layer covers the first surface and at least the part of the first side surface to cover at least the doped conductive layer, and the first passivation layer further covers at least a part of a cut edge side surface, wherein the cut edge side surface is a side surface of the sub-wafer formed by cutting the wafer.

[0029] In some embodiments, the step of providing the wafer includes: Performing a texturing treatment and diffusing doping elements onto at least the first surface and the first side surface of the substrate; and Etching the substrate to expose the second surface and a first target area of ​​each first side surface of the substrate; wherein the first target area is adjacent to and connected to the second surface.

[0030] In some embodiments, the step of etching the substrate to expose the second surface and the first target region of each first side surface of the substrate includes: Etching the substrate that has undergone the texturing treatment and the diffusion of doping elements to expose the textured structure in the second surface and the first target region; and Etching to remove the exposed textured structure to expose the second surface and the first target area of ​​each first side surface of the substrate.

[0031] In some embodiments, the step of forming the passivating contact material layer on each surface of the wafer includes a step of sequentially forming a tunnel material layer, a doped polysilicon material layer, and an oxide material layer on each surface of the wafer.

[0032] In some embodiments, the step of etching to remove the passivating contact material layer on the surface of the first side of the sub-wafer and on each side surface of the sub-wafer to form the passivating contact layer on the sub-wafer includes: Etching to remove the oxide material layer on the surface of the first side of the sub-wafer and on each side surface of the sub-wafer, Etching to remove the doped polysilicon material layer and the tunnel material layer on the surface of the first side of the sub-wafer and on each side surface of the sub-wafer; and Etching to polish the cut edge side surface of the sub-wafer.

[0033] In some embodiments, the step of etching to remove the oxide material layer is performed using a continuous machine; the step of etching to remove the doped polysilicon material layer and the tunnel material layer is performed using a trough machine.

[0034] In some embodiments, the method further includes, after the step of etching to remove the doped polysilicon material layer and the tunnel material layer on the surface of the first side of the sub-wafer and on each side surface of the sub-wafer: etching to remove the oxide material layer on a surface of a second side of the sub-wafer; wherein the surface of the second side of the sub-wafer corresponds to the second surface of the substrate.

[0035] In some embodiments, after the step of forming the first passivation layer on the doped conductive layer, the method further includes: Forming a second passivation layer on the passivating contact layer; wherein the second passivation layer covers at least the second surface, at least a portion of the first side surface, and at least a portion of the cut edge side surface so as to cover the passivating contact layer and at least a portion of the first passivation layer.

[0036] In some embodiments, after the step of forming the second passivation layer on the passivating contact layer, the method further includes: Forming electrodes on the first passivation layer and the second passivation layer, respectively, thereby forming the solar cell.

[0037] In some embodiments, the step of cutting the wafer formed with the passivating contact material layer along the thickness direction of the substrate to form the sub-wafers includes: Laser cutting the wafer formed with the passivating contact material layer along the thickness direction of the substrate to form the sub-wafer.

[0038] A sixth aspect of the embodiments of the present application provides a solar cell. The solar cell includes a substrate, a doped conductive layer, a first passivation layer, a passivating contact layer, and a second passivation layer. The substrate includes a first surface, a second surface, and at least one first side surface. The first surface and the second surface are opposite each other, and the at least one first side surface is adjacent to and located between the first surface and the second surface. At least the first surface and a portion of the first side surface of the substrate include a textured structure. The doped conductive layer is disposed on at least the first surface and the portion of the first side surface to cover the textured structure.The first passivation layer is stacked on the doped conductive layer and covers the first surface and at least the portion of the first side surface to cover at least the doped conductive layer. The passivating contact layer is arranged on the second surface. The second passivation layer is stacked on the passivating contact layer and covers the second surface to cover the passivating contact layer.

[0039] A seventh aspect of the present application provides a method for manufacturing a solar cell. The method includes the following steps: Providing a wafer, the wafer including a substrate and a doped conductive layer; the substrate including a first surface, a second surface, and at least one first side surface, the first surface and the second surface being opposite each other and the at least one first side surface being adjacent to and located between the first surface and the second surface, the first surface and at least a portion of the first side surface of the substrate including a textured structure, the doped conductive layer being disposed on at least the first surface and the portion of the first side surface to cover the textured structure; Forming a passivating contact layer on the second surface of the substrate; Forming a first passivation layer on the doped conductive layer, the first passivation layer covering the first surface and at least the portion of the first side surface to cover at least the doped conductive layer; and Forming a second passivation layer on the passivating contact layer, thereby forming a solar cell array, wherein the second passivation layer covers the second surface so as to cover the passivating contact layer.

[0040] An eighth aspect of the present application provides a method for manufacturing a solar cell. The method includes the following steps: Providing a wafer, the wafer including a substrate and a doped conductive layer, the substrate including a first surface, a second surface, and at least one first side surface, the first surface and the second surface being opposite each other, and the at least one first side surface being adjacent to and located between the first surface and the second surface, the first surface and at least a portion of the first side surface of the substrate including a textured structure, the doped conductive layer being disposed on the first surface and at least the portion of the first side surface to cover the textured structure; Forming a passivating contact material layer on each surface of the wafer; Cutting the wafer formed with the passivating contact material layer along the thickness direction of the substrate to form sub-wafers to cut the doped conductive material layer into doped conductive layers; Etching to remove the passivating contact material layer on a surface of a first side of the sub-wafer and on each side surface of the sub-wafer, thereby forming a passivating contact layer on the sub-wafer, wherein the surface of the first side of the sub-wafer corresponds to the first surface of the substrate; and Forming a first passivation layer on the doped conductive layer, wherein the first passivation layer covers the first surface and at least the part of the first side surface to cover at least the doped conductive layer; and the first passivation layer further covers at least a part of the cut edge side surface, wherein the cut edge side surface is a side surface of the sub-wafer formed by cutting the wafer.

[0041] In the solar cell according to the embodiments of the present application, the first surface and a portion of the first side surface of the substrate include a textured structure. The doped conductive layer is disposed on the first surface and the portion of the first side surface of the substrate to cover the textured structure. Since the portion of the first side surface has the textured structure and the doped conductive layer is disposed on the textured structure, the doped conductive layer in this region contributes to reducing the recombination of charge carriers at the interface on the first side surface, thereby achieving a relatively good passivation effect on the first side surface. Furthermore, the textured structure of the first side surface enlarges the light absorption area of ​​the solar cell and thus increases the light-generated current of the solar cell, which has a positive effect on the efficiency of the solar cell.

[0042] In the solar cell according to the embodiments of the present application, the first passivation layer is stacked on the doped conductive layer. The first passivation layer covers the first surface and at least a part of the first side surface to cover at least the doped conductive layer. Since the first passivation layer covers the first surface and at least a part of the first side surface, at least a part of the first side surface is protected by the first passivation layer, which not only increases the passivation effect on the first side surface but also reduces the recombination of charge carriers on the first side surface. Furthermore, the first passivation layer is an insulating layer that effectively prevents leakage currents at the first side surface, thereby increasing the output power while improving the conversion efficiency of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a structural schematic view of a solar cell provided in an embodiment of the present application. Fig. 2 is a structural schematic view of a solar cell provided in an embodiment of the present application. Fig. 3 is a structural schematic view of a solar cell provided in an embodiment of the present application. Fig. 4 is a structural schematic view of a solar cell provided in an embodiment of the present application. Fig. 5 is a structural schematic view of a solar cell provided in an embodiment of the present application. Fig. 6 is a structural schematic view of a solar cell provided in an embodiment of the present application. Fig. 7 is a structural schematic view of a solar cell provided in an embodiment of the present application. Fig. 8 is a structural schematic view of a solar cell provided in an embodiment of the present application. Fig. 9 is a structural schematic view of a solar cell provided in an embodiment of the present application. Fig. 10 is a structural schematic view of a solar cell provided in an embodiment of the present application. Fig. 11 is a structural schematic view of a solar cell provided in an embodiment of the present application. Fig. 12 is a structural schematic view of a solar cell provided in an embodiment of the present application. Fig. 13 is a flowchart of a method for manufacturing a solar cell provided in an embodiment of the present application. Fig. 14 is a structural schematic view of a substrate in the method of manufacturing a solar cell provided in an embodiment of the present application. Fig. 15 is a structural schematic view of a textured structure and a doped conductive layer formed on a substrate in the method of manufacturing a solar cell provided in one embodiment of the present application. Fig. 16A and Fig. 16B are structural schematic views of a passivating contact layer formed in the method of manufacturing a solar cell according to an embodiment of the present application. Fig. 17 is a schematic view of a first passivation layer formed in the method of manufacturing a solar cell according to an embodiment of the present application. Fig. 18 is a schematic view of a second passivation layer formed in the method of manufacturing a solar cell according to an embodiment of the present application. Fig. 19 is a schematic view of a solar cell formed in the method of manufacturing a solar cell according to an embodiment of the present application. Fig. 20 is a structural schematic view of a first side surface of a substrate in the method of manufacturing a solar cell according to an embodiment of the present application. Fig. 21 is a structural schematic view of a wafer in another method for manufacturing a solar cell provided in an embodiment of the present application. Fig. 22 is a schematic view of a passivating contact layer formed on a wafer in the other method of manufacturing a solar cell provided in an embodiment of the present application. Fig. 23 is a schematic view of a first passivation layer formed on a doped conductive layer in the other method of manufacturing a solar cell provided in an embodiment of the present application. Fig. 24 is a schematic view of a second passivation layer formed on the passivating contact layer in the other method of manufacturing a solar cell provided in an embodiment of the present application. Fig. 25 is a schematic view of electrodes formed on a first passivation layer and a second passivation layer in the other method of manufacturing a solar cell provided in an embodiment of the present application. Fig. 26 is a structural schematic view of a solar cell formed in the other method for manufacturing a solar cell provided in an embodiment of the present application. Fig. 27 is a photograph of a sectional surface of a solar cell in the other method for manufacturing a solar cell provided in an embodiment of the present application. Fig. 28 is a flowchart of a method for manufacturing a solar cell provided in an embodiment of the present application. Fig. 29A is a structural schematic view of a wafer in a method of manufacturing a solar cell according to an embodiment of the present application. Fig. 29B is a structural schematic view of a wafer having a passivating contact material layer formed in a method of manufacturing a solar cell according to an embodiment of the present application. Fig. 30 is a structural schematic view of a sub-wafer in the method of manufacturing a solar cell according to an embodiment of the present application. Fig. 31 is a schematic view of a first passivation layer formed in the method of manufacturing a solar cell according to an embodiment of the present application. Fig. 32 is a schematic view of a second passivation layer provided in the method of manufacturing a solar cell according to an embodiment of the present application. Fig. 33 is a schematic view of a solar cell formed in the method of manufacturing a solar cell according to an embodiment of the present application. Fig. 34 is a structural schematic view of a photovoltaic module provided in an embodiment of the present application. Fig. 35 is a schematic view showing a manufacturing process of a photovoltaic module provided in an embodiment of the present application. Reference symbols:

[0043] 100. Solar cell; 101, 101', wafer; 102, sub-wafer; 103, solar cell matrix; F, first surface; S, second surface; C1, first side surface; C11, first target area; C12, second target area; C2, cut edge side surface; CQ, cut surface; P, flat area; R, textured area; H, thickness direction of a substrate; 10, substrate; 11, boundary line; 20, textured structure; 30, doped conductive layer; 30', doped conductive material layer; 40, first passivation layer; 41, first part; 42, second part; 50, passivating contact layer; 51, tunnel oxide layer; 52, doped conductive polysilicon layer; 60, second passivation layer; 70, electrode; 200, photovoltaic module; 210, cell group. DETAILED DESCRIPTION

[0044] In order to make the above-mentioned objects, features, and advantages of the present application more clearly understood, specific embodiments of the present application will now be described in detail with reference to the drawings. In the following description, many specific details are set forth in order to provide a thorough understanding of the present application. However, the present application may be implemented in many ways other than those described herein. Similar improvements may be made by those skilled in the art without departing from the spirit of the present application. The present application is not limited to the specific embodiments disclosed below.

[0045] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "top", "bottom", "front", "rear", "left", "right", "vertical", "horizontal", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicate the orientations or positional relationships based on the drawings. These terms are merely used to simplify the description of the present application and to simplify the description. They do not imply that the associated devices or elements must have a particular orientation, nor that they must be constructed or operated in a particular orientation. They therefore do not constitute a limitation of the present application.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply a relative importance or to imply the quantity or order of the specified technical features. Therefore, the features modified by "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present application, "plurality" means at least two, such as two, three, etc., unless expressly defined otherwise.

[0047] In this application, the terms "installed," "connected," "coupled," "attached," and the like, unless clearly stated and defined otherwise, are to be understood in their broadest sense. For example, when an element is referred to as being "installed," "connected," "coupled," or "attached" to another element, unless expressly defined otherwise, it may be fixedly connected, detachably connected, or integrated with the other element; it may be mechanically or electrically connected to the other element; and it may be connected to the other element directly or via an intermediate medium. Those skilled in the art may understand the specific meanings of the above terms in this application depending on the specific circumstances.

[0048] Unless expressly defined otherwise, in the present application, when a first feature is referred to as being "on" or "below" a second feature, it may be in direct contact with the second feature or in indirect contact with the second feature via an intermediate medium. Furthermore, when a first feature is referred to as being "on" or "above" a second feature, it may be directly above or diagonally above the second feature, or it may merely be at a higher horizontal level than the second feature. When a first feature is referred to as being "below," "under," or "beneath" a second feature, it may be directly below or diagonally below the second feature, or it may merely be at a lower horizontal level than the second feature.

[0049] It should be noted that when an element is referred to as being "attached" or "mounted" to another element, it may be attached or mounted to the other element either directly or through an intermediate element. When an element is referred to as being "connected" to another element, it may be connected to the other element directly or through an intermediate element. The terms "vertical," "horizontal," "top," "bottom," "left," "right," and the like, as used herein, are for illustrative purposes only and do not represent the only ways to implement the present application.

[0050] The embodiments of the solar cell, the method for manufacturing the same, the photovoltaic module, and the photovoltaic system of the present application are described below with reference to the drawings. In the present application, the term "covering" means partial or complete covering unless otherwise specified.

[0051] With reference to Fig. 1, one embodiment of the present application provides a solar cell 100. The solar cell 100 includes a substrate 10, a doped conductive layer 30, a first passivation layer 40, a passivating contact layer 50, and a second passivation layer 60. The substrate 10 includes a first surface F, a second surface S, and at least one first side surface C1. The first surface F and the second surface S are opposite each other. The at least one first side surface C1 is adjacent to and located between the first surface F and the second surface S.

[0052] The substrate 10 is configured to receive incident light and generate photogenerated charge carriers. For example, the solar cell 100 may be a TOPCon cell, and both the first surface F and the second surface S of the substrate 10 may be used to receive incident light. In some embodiments, the substrate 10 further includes at least one cut-edge side surface C2 adjacent to and located between the first surface F and the second surface S. The cut-edge side surface C2 is a side surface formed by cutting a larger substrate.

[0053] In the embodiment of the present application, at least the first surface F and a part of the first side surface C1 of the substrate 10 are formed with the textured structure 20. The doped conductive layer 30 is arranged on at least the first surface F and a part of the first side surface C1 to cover the textured structure 20. For example, the doped conductive layer 30 completely covers the textured structure 20. The first passivation layer 40 is stacked on the doped conductive layer 30. The first passivation layer 40 covers at least the first surface F and a part of the first side surface C1 to cover at least the doped conductive layer 30. For example, the first passivation layer 40 completely covers the doped conductive layer 30. The passivating contact layer 50 is arranged on the second surface S.The second passivation layer 60 is stacked on the passivating contact layer 50. The second passivation layer 60 covers the second surface S to thereby cover the passivating contact layer 50. For example, the second passivation layer 60 completely covers the passivating contact layer 50.

[0054] In the embodiments of the present application, the first surface F and a part of the first side surface C1 of the substrate 10 include textured structures 20. The doped conductive layer 30 is arranged on the first surface F and a part of the first side surface C1 to cover the textured structure 20. Since a part of the first side surface C1 is formed with the textured structure 20 and the doped conductive layer 30 is arranged on the textured structure 20, the doped conductive layer 30 in this region contributes to reducing the recombination of charge carriers at the interface at the first side surface C1, thereby achieving a relatively good passivation effect on the first side surface C1.Furthermore, the textured structure 20 in the first side surface C1 increases the light absorption area of ​​the solar cell 100 and thereby increases the light-generated current of the solar cell 100, which in turn improves the efficiency of the solar cell 100.

[0055] On the other hand, the first passivation layer 40 is stacked on the doped conductive layer 30. The first passivation layer 40 covers the first surface F and at least a portion of the first side surface C1 to cover at least the doped conductive layer 30. Since the first passivation layer 40 covers the first surface F and at least a portion of the first side surface C1, the first passivation layer 40 provides protection for at least a portion of the first side surface C1, which not only increases the passivation effect on the first side surface C1 but also reduces the recombination of charge carriers at the first side surface C1. Furthermore, the first passivation layer 40 is an insulating layer that effectively prevents leakage currents at the first side surface C1, thereby increasing the output power of the solar cell 100 while improving the conversion efficiency of the solar cell 100.

[0056] In some embodiments, the solar cell 100 further includes at least two electrodes 70. The at least two electrodes 70 are each arranged on both the first surface F side and the second surface S side of the substrate 10. The electrode 70 on the first surface F side of the substrate 10 penetrates the first passivation layer 40 and is in contact with the doped conductive layer 30, such that it is electrically connected to the doped conductive layer 30 and spaced from the substrate 10. The electrode 70 on the second surface S side of the substrate 10 penetrates the second passivation layer 60 and is in contact with the passivating contact layer 50, such that it is electrically connected to the passivating contact layer 50 and spaced from the substrate 10.

[0057] In the embodiments of the present application, the first surface F and the second surface S of the substrate 10 may be, for example, two end surfaces in the thickness direction H of the substrate 10. The substrate 10 includes a plurality of side surfaces adjacent to and located between the first surface F and the second surface S. The plurality of side surfaces are arranged around the first surface F and sequentially connected one by one. The two ends of each side surface are respectively connected to the first surface F and the second surface S. One, several, or all of the plurality of side surfaces may be the first side surface(s) C1. Except for the first side surface(s) C1, the remaining side surface(s) of the substrate 10 may be the cut edge side surface(s) C2.In some embodiments, the substrate 10 includes both the first side surface(s) C1 and the cut edge side surface(s) C2. The first side surface(s) C1 and the cut edge side surface(s) C2 can be arranged around the first surface F and joined sequentially one after the other. In some embodiments, the substrate 10 is quadrangular in plan view. The total number of the first side surface(s) C1 and the cut edge side surface(s) C2 is four. The substrate 10 can have other shapes as needed. In some embodiments, the first side surface(s) C1 and the cut edge side surface(s) C2 face each other. In one example, all of the first side surfaces C1 can be joined sequentially and then joined to the cut edge side surfaces C2. In another example, the first side surfaces C1 and the cut edge side surfaces C2 can be arranged alternately.Of course, the present application is not limited to this, and the relative positions of the first side surface(s) C1 and the cutting edge side surface(s) C2 can be adjusted as needed.

[0058] The first surface F and a portion of the first side surface C1 of the substrate 10 have the textured structure 20. The textured structure 20 located in the first side surface C1 may be adjacent to the first surface F. In some embodiments, the textured structure 20 of the first surface F of the substrate 10 is connected to the textured structure 20 of the first side surface C1 of the substrate 10, forming a continuous textured structure. In some other embodiments, the textured structure 20 of the first surface F of the substrate 10 may be spaced from the textured structure 20 of the first side surface C1 of the substrate 10, forming a discontinuous textured structure.

[0059] The solar cell 100 may be an N-type cell or a P-type cell. In the N-type cell, the substrate 10 is doped with N-type elements, and the doped conductive layer 30 is doped with P-type elements. In the P-type cell, the substrate 10 is doped with P-type elements, and the doped conductive layer 30 is doped with N-type elements. The doped conductive layer 30 is configured to form a PN junction with the substrate 10. In the embodiments of the present application, the N-type substrate 10 is used as an example for description. In this case, the doped conductive layer 30 may be doped with P-type elements. For example, the doped conductive layer 30 may be doped with boron elements and is also referred to as a P+ emitter.

[0060] A portion of the doped conductive layer 30 is disposed on the first surface F, and another portion of the doped conductive layer 30 is disposed on a portion of the first side surface C1. The doped conductive layer 30 extends to cover at least the entire textured structure 20. In some embodiments, the coverage area of ​​the doped conductive layer 30 may be larger than the coverage area of ​​the textured structure 20. In some embodiments, the coverage area of ​​the doped conductive layer 30 is identical to the coverage area of ​​the textured structure 20. That is, the doped conductive layer 30 exclusively and completely covers the textured structure 20.

[0061] Still referring to Fig. 1, the passivating contact layer 50 is disposed on the second surface S of the substrate 10. For example, the passivating contact layer 50 may be stacked directly on the second surface S of the substrate 10. The passivating contact layer 50 may reduce the recombination of charge carriers at the second surface S of the substrate 10, thereby increasing the open-circuit voltage of the solar cell 100 and improving the photoelectric conversion efficiency of the solar cell 100. The passivating contact layer 50 may include a tunnel oxide layer 51 and a doped conductive polysilicon layer 52, which are sequentially stacked on the second surface S. For example, the tunnel oxide layer 51 is configured to provide interfacial passivation for the second surface S of the substrate 10, thereby achieving chemical passivation.In particular, by saturating the dangling bonds on the surface of the substrate 10 and reducing the defect state density at the interface at the second surface S of the substrate 10, the recombination center at the second surface S of the substrate 10 can be reduced and thus the recombination of charge carriers can be reduced. The material of the tunnel oxide layer 51 can be a dielectric material, such as at least one of: silicon oxide, magnesium fluoride, amorphous silicon, polysilicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. In some embodiments, the electrode 70 arranged on the second surface S of the substrate 10 can only be in contact with the doped conductive layer 52 made of polysilicon and is spaced from the substrate 10 and the tunnel oxide layer 51 by the polysilicon-doped conductive layer 52.

[0062] The first passivation layer 40 is stacked on the doped conductive layer 30. The first passivation layer 40 is configured for surface passivation and antireflection for the solar cell 100. The first passivation layer 40 can effectively chemically passivate the dangling bonds on the surface of the substrate 10 and also reduce reflection at the front side of the solar cell 100.

[0063] For example, the first passivation layer 40 includes a first passivation film (not shown) and a first anti-reflection film (not shown) which are sequentially stacked on the doped conductive layer 30.

[0064] The first anti-reflection film is located on the first surface side of the substrate 10, which is also the side of the solar cell 100 that receives incident light (also referred to as the front side or light-receiving side). The first anti-reflection film provides an anti-reflection effect on the front side of the solar cell 100. The first anti-reflection film may have a multilayer structure. In the multilayer structured first anti-reflection film, the layers may be made of one or more of the following materials: silicon oxide, silicon nitride, or silicon oxynitride.

[0065] The first passivation film may have a single-layer or multi-layer structure. The material of the first passivation film may be at least one of: aluminum oxide, silicon oxide, silicon nitride, or silicon oxynitride. Furthermore, the first passivation film may be formed by chemical deposition.

[0066] The first passivation layer 40 covers at least the first surface F and at least a portion of the first side surface C1 to cover at least the doped conductive layer 30. In particular, the first passivation layer 40 may continuously cover the first surface F and at least a portion of the first side surface C1 adjacent to the first surface F to thereby cover the doped conductive layer 30. In this case, the first passivation layer 40 includes a portion covering the first surface F and another portion extending continuously from the portion covering the first surface F to the first side surface C1.

[0067] The second passivation layer 60 is stacked on the passivating contact layer 50. The second passivation film 60 may have a single-layer or a multi-layer structure. The material of the second passivation layer 60 may be one or more of: silicon oxide, silicon nitride, or silicon oxynitride. Furthermore, the second passivation layer 60 is disposed on the backside (i.e., the side facing away from the sun) of the solar cell 100. With the advancement of the technology of the solar cell 100, the backside of the solar cell 100 can also utilize light energy, mainly from the reflected or scattered light from the environment. The second passivation layer 60 includes at least one second anti-reflection film (not shown) stacked on the passivating contact layer 50.In this way, the light reflection on the back side of the solar cell 100 can be reduced and the light absorption on the back side of the solar cell 100 can be increased, so that the second passivation layer 60 can have both a passivation effect and an anti-reflection effect.

[0068] In some embodiments relating to Fig. 1 and Fig. 2, the first side surface C1 includes a textured region R provided with a textured structure 20 and a flat region P adjacent to the textured region R. The flat region P refers here to the region of the first side surface C1 without the textured structure 20. In some embodiments, the textured region R is adjacent to the first surface F. The flat region P is facing away from the first surface F.

[0069] In some embodiments, as mentioned above, the first passivation layer 40 covers at least the first surface F and at least a portion of the first side surface C1. With respect to the coverage area of ​​the first passivation layer 40 on the first side surface C1, for example, on the first side surface C1, the edge of the first passivation layer 40 facing away from the first surface F is flush with the edge of the doped conductive layer 30, or the first passivation layer 40 extends beyond the edge of the doped conductive layer 30 along the thickness direction H of the substrate 10.

[0070] In the embodiment in which the first passivation layer 40 extends beyond the edge of the doped conductive layer 30 along the thickness direction H of the substrate 10, the first passivation layer 40 on the first side surface C1 can cover the entire textured region R and at least a portion of the flat region P. In this way, the first passivation layer 40 provides improved coverage and improved passivation effects on the first side surface C1.

[0071] The first passivation layer 40 on the first side surface C1 may cover the entire textured region R and at least a part of the flat region P, which may be due to the following facts: During the manufacturing process of the solar cell 100, a part of the first side surface C1 of the substrate 10 may be in contact with a positioning element or the like and thus be prevented from forming a film or layer thereon, so that the first passivation layer 40 does not completely cover the first side surface C1.

[0072] Fig. 2 shows an embodiment in which an edge of the first passivation layer 40, which is arranged on the first side surface C1 and faces away from the first surface F, lies within the area of ​​the flat area P. Fig. 1 shows an embodiment in which an edge of the first passivation layer 40 facing away from the first surface F is flush with the surface of the passivating contact layer 50 facing away from the substrate 10. It can be seen that the Fig. 1 compared to the embodiment shown in Fig. 2 has a better passivation effect.

[0073] In some embodiments, the edge of the first passivation layer 40 is flush with the edge of the doped conductive layer 30. For example, with reference to Fig. 3 and Fig. 4, the first passivation layer 40 does not extend to the flat region P along the thickness direction H of the substrate 10. That is, the coverage area of ​​the first passivation layer 40 coincides with the coverage area of ​​the doped conductive layer 30.

[0074] In some embodiments, the second passivation layer 60 covers at least a portion of the first side surface C1, such that it covers at least a portion of the first passivation layer 40 located on the first side surface C1. Since the first passivation layer 40 covers the first surface F and at least a portion of the first side surface C1, and the second passivation layer 60 covers at least a portion of the first passivation layer 40, the first passivation layer 40 and the second passivation layer 60 together protect at least a portion of the first side surface C1, which not only increases the passivation effect on at least a portion of the first side surface C1, but also reduces the recombination of charge carriers at the first side surface C1.Furthermore, the second passivation layer 60 is an insulating layer that can effectively prevent leakage currents at the first side surface C1, thereby increasing the output power of the solar cell 100 and simultaneously improving the conversion efficiency of the solar cell 100.

[0075] The second passivation layer 60 covers at least the second surface S and at least a portion of the first side surface C1, thereby covering the passivating contact layer 50 and at least a portion of the first passivation layer 40. In particular, the second passivation layer 60 may continuously cover the second surface S and at least a portion of the first side surface C1 adjacent to the second surface S, so that both the passivating contact layer 50 and the first passivation layer 40 may be covered. In this case, the second passivation layer 60 includes a portion covering the second surface S and another portion extending continuously from the portion covering the second surface S to the first side surface C1.

[0076] The coverage area of ​​the second passivation layer 60 on the first side surface C1 is described below with reference to Fig. 1 to 4.

[0077] In some embodiments, the first passivation layer 40 extends beyond the edge of the doped conductive layer 30 along the thickness direction H of the substrate 10. Referring to Fig. 1 and Fig. 2, the part of the first passivation layer 40 located on the first side surface C1 may include a first part 41 covering the flat region P, and the second passivation layer 60 may cover at least the first part 41. This ensures that the second passivation layer 60 reliably covers the first passivation layer 40, thus preventing the region of the first side surface C1 between the ends of the two passivation layers from being covered by no passivation layer.

[0078] Furthermore, the part of the first passivation layer 40 located on the first side surface C1 includes a second part 42 covering the textured region R. The second passivation layer 60 covers the first part 41 and at least a part of the second part 42. In this way, the coverage area of ​​the second passivation layer 60 on the first passivation layer 40 is relatively large, which improves the passivation effect on the side surface of the solar cell 100.

[0079] As in Fig. 2, in some embodiments, the second passivation layer 60 covers the entire first portion 41 and a portion of the second portion 42. In other embodiments, the second passivation layer 60 covers only the first portion 41 or the second passivation layer 60 covers only the entire second portion 42.

[0080] Referring to Fig. 1, in some embodiments, on the first side surface C1, the second passivation layer 60 extends along the thickness direction H of the substrate 10 such that the edge of the second passivation layer 60 facing away from the second surface S is flush with the outer surface of the first passivation layer 40 on the first surface F. In this way, the passivation effect on the side surface of the solar cell 100 is improved. If the first passivation layer 40 is not deposited well or evenly due to contact with a quartz boat or due to manufacturing problems, the increased coverage area of ​​the second passivation layer 60 can further improve the reliability of the passivation on the side surface of the solar cell 100.

[0081] With reference to Fig. 3 and Fig. 4, in some embodiments, on the first side surface C1, the edge of the first passivation layer 40 is flush with the edge of the doped conductive layer 30, and the part of the first passivation layer 40 arranged on the first side surface C1 covers only the textured region R. In this case, the second passivation layer 60 on the first side surface C1 covers at least a part of the textured region R. For example, as in Fig. 4, the second passivation layer 60 on the first side surface C1 forms part of the textured region R.

[0082] Alternatively, as in Fig. 3, the second passivation layer 60 is deposited on the first side surface C1 along the thickness direction H of the substrate 10, such that the edge of the second passivation layer 60 facing away from the second surface S is flush with the outer surface of the first passivation layer 40 on the first surface F. In this way, the passivation effect on the side surface of the solar cell 100 is improved. If the first passivation layer 40 is not well or uniformly deposited due to contact with a quartz boat or due to manufacturing problems, the increased coverage area of ​​the second passivation layer 60 can further improve the reliability of the passivation on the side surface of the solar cell 100.

[0083] The second passivation layer 60 on the first side surface C1 may cover a part of the textured region R, which may be due to the following facts: During the manufacturing process of the solar cell 100, a part of the first passivation layer 40 on the first side surface C1 or on the cut edge side surface C2 of the substrate 10 may be in contact with a positioning member or the like and thus be prevented from forming a film or layer thereon, so that the second passivation layer 60 does not completely cover the first passivation layer 40.

[0084] In some embodiments, the substrate 10 includes at least one cut edge side surface C2 adjacent to and located between the first surface F and the second surface S.

[0085] With reference to Fig. 1 to 4, in some embodiments, the textured structure 20 is formed only in the first surface F and a portion of the first side surface C1. The doped conductive layer 30 is disposed only on the first surface F and a portion of the first side surface C1 to cover the textured structure 20.

[0086] For example, the cut edge side surface C2 is flush in the normal direction with the edges of the doped conductive layer 30, the first passivation layer 40, the passivating contact layer 50, and the second passivation layer 60 on the same side as the cut edge side surface C2. In this case, no film or layer is formed on the surface of the solar cell 100 corresponding to the cut edge side surface C2. Such a structure can be obtained, for example, by cutting a cell structure at the end of the manufacturing process of the solar cell 100.

[0087] With reference to Fig. 5 to 8, in some embodiments of the present application, the solar cells 100 based on the above embodiments are further improved by forming a film or layer structure on the cut edge side surface C2. It should be understood that the film or layer structures and their covering areas on the first surface F and the first side surface C1 of the substrate 10 are the same as those in the above embodiments and will not be described repeatedly herein.

[0088] Fig. 5 and Fig. 6 show embodiments in which the first passivation layer 40 on the first side surface C1 extends along the thickness direction H of the substrate 10 beyond the edge of the doped conductive layer 30. Fig. 7 and Fig. 8 show embodiments in which the edge of the first passivation layer 40 on the first side surface C1 is flush with the edge of the doped conductive layer 30.

[0089] Fig. 5 and Fig. 7 show embodiments in which the second passivation layer 60 extends on the first side surface C1 along the thickness direction H of the substrate 10, so that the edge of the second passivation layer 60 is flush with the outer surface of the first passivation layer 40 on the first surface F. Fig. 6 and Fig. 8 show the embodiments in which the second passivation layer 60 partially covers the second part 42, which is the part of the first passivation layer 40 that is located on the first side surface C1 and covers the textured structure R.

[0090] The arrangement of the films or layers on the cut edge side surface C2 is as follows.

[0091] With reference to Fig. 5 to 8, in some embodiments, the textured structure 20 is formed only in the first surface F and a portion of the first side surface C1. The doped conductive layer 30 is formed only on the first surface F and a portion of the first side surface C1 to cover the textured structure 20. Therefore, the textured structure 20 and the doped conductive layer 30 are not formed on the cut-edge side surface C2.

[0092] In some embodiments, the first passivation layer 40 also covers at least a portion of the cut edge side surface C2. The cut edge side surface C2 corresponds to the cut-shaped surface of the solar cell 100, so that at least a portion of the cut edge side surface C2 is protected by the first passivation layer 40, which not only increases the passivation effect on the cut edge side surface C2 but also reduces the recombination of charge carriers at the cut edge side surface C2. Furthermore, the first passivation layer 40 is an insulating layer that effectively prevents leakage currents at the cut edge side surface C2, thereby increasing the output power while improving the conversion efficiency of the solar cell 100.

[0093] Furthermore, the coverage area of ​​the first passivation layer 40 on the cut edge side surface C2 may be as follows. For example, as shown in Fig. 5, the edge of the first passivation layer 40 may be arranged on the cut edge side surface C2 and facing away from the first surface F and may be flush with the surface of the passivating contact layer 50 facing away from the substrate 10. Alternatively, as shown in Fig. 6, Fig. 7 and Fig. 8, the edge of the first passivation layer 40, which is located on the cut edge side surface C2 and faces away from the first surface F, may lie within the area of ​​the cut edge side surface C2.

[0094] Of course, the edge of the first passivation layer 40 on the first side surface C1 may be flush with the other edge of the first passivation layer 40 on the cut edge side surface C2. Alternatively, the edge of the first passivation layer 40 on the first side surface C1 is not flush with the other edge of the first passivation layer 40 on the cut edge side surface C2.

[0095] In some embodiments, the second passivation layer 60 also covers at least a portion of the cut edge side surface C2 so as to cover at least a portion of the first passivation layer 40 on the cut edge side surface C2.

[0096] In particular, as in Fig. 5 and Fig. 7, the second passivation layer 60 is applied to the cut edge side surface C2 along the thickness direction H of the substrate 10, so that the edge of the second passivation layer 60 is flush with the outer surface of the first passivation layer 40 on the first surface F. Alternatively, as shown in Fig. 6 and Fig. 8, the second passivation layer 60 covers only a part of the first passivation layer 40 on the cut edge side surface C2.

[0097] Of course, the edge of the second passivation layer 60 on the first side surface C1 may be flush with the other edge of the second passivation layer 60 on the cut edge side surface C2. Alternatively, the edge of the second passivation layer 60 on the first side surface C1 is not flush with the other edge of the second passivation layer 60 on the cut edge side surface C2.

[0098] With reference to Fig. 9 to 12, in some embodiments of the present application, the solar cells 100 based on the above embodiments are further improved by forming a film or layer structure on the cut edge side surface C2. It should be understood that the film or layer structures and their covering areas on the first surface F and the first side surface C1 of the substrate 10 are the same as those in the above embodiments and will not be described repeatedly herein.

[0099] For example, Fig. 9 and Fig. 10 embodiments in which the first passivation layer 40 on the first side surface C1 extends along the thickness direction H of the substrate beyond the edge of the doped conductive layer 30. Fig. 11 and Fig. 12 show embodiments in which the edge of the first passivation layer 40 on the first side surface C1 is flush with the edge of the doped conductive layer 30.

[0100] Fig. 9 and Fig. 11 show embodiments in which the second passivation layer 60 extends on the first side surface C1 along the thickness direction H of the substrate 10, so that the edge of the second passivation layer 60 is flush with the outer surface of the first passivation layer 40 on the first surface F. Fig. 10 and Fig. 12 show embodiments in which the second passivation layer 60 partially covers the second portion 42.

[0101] The arrangement of the films or layers on the cut edge side surface C2 is as follows.

[0102] With reference to Fig. 9 to 12, in some embodiments, the textured structure 20 is also formed in at least a portion of the cut edge side surface C2. The doped conductive layer 30 is arranged on the first surface F, a portion of the first side surface C1, and a portion of the cut edge side surface C2 to cover the textured structure 20. The first passivation layer 40 also covers at least a portion of the cut edge side surface C2 to cover at least the doped conductive layer 30. In some embodiments, the doped conductive layer 30 completely covers the textured structure 20 on the cut edge side surface C2. The first passivation layer 40 completely covers the doped conductive layer 30 on the cut edge side surface C2.

[0103] In this way, based on increasing the passivation effect on the first side surface C1 and reducing the recombination of charge carriers at the first side surface C1, since a part of the cut edge side surface C2 also includes the textured structure 20 and the doped conductive layer 30 is arranged on the textured structure 20, the doped conductive layer 30 in this region will contribute to reducing the recombination of charge carriers at the interface at the cut edge side surface C2, thereby achieving a relatively good passivation effect on the cut edge side surface C2. Furthermore, the textured structure 20 in the cut edge side surface C2 enlarges the light absorption area of ​​the solar cell 100 and thereby increases the photogenerated current of the solar cell 100, which has a positive effect on the efficiency of the solar cell 100.

[0104] In other embodiments, the first passivation layer 40 covers at least a portion of the cut edge side surface C2 to cover at least the doped conductive layer 30, so that at least a portion of the cut edge side surface C2 is protected by the first passivation layer 40, which not only increases the passivation effect on the cut edge side surface C2 but also reduces the recombination of carriers at the cut edge side surface C2. Furthermore, the first passivation layer 40 is an insulating layer that can effectively prevent leakage currents at the cut edge side surface C2, thereby increasing the output power while improving the conversion efficiency of the solar cell 100.

[0105] Furthermore, the coverage area of ​​the first passivation layer 40 on the cut edge side surface C2 may be as follows. For example, as shown in Fig. 9, the first passivation layer 40 is applied to the cut edge side surface C2 along the thickness direction H of the substrate 10, so that the edge of the first passivation layer 40 facing away from the first surface F is flush with the surface of the passivating contact layer 50 facing away from the substrate 10. Alternatively, as shown in Fig. 11 and Fig. 12, on the cut edge side surface C2, the edge of the first passivation layer 40 facing away from the first surface F is flush with the edge of the doped conductive layer 30. Alternatively, as shown in Fig. 10, the first passivation layer 40 extends beyond the edge of the doped conductive layer 30, and the edge of the first passivation layer 40 facing away from the first surface F is located within the region of the cut edge side surface C2.

[0106] Of course, the edge of the first passivation layer 40 on the first side surface C1 may be flush with the other edge of the first passivation layer 40 on the cut edge side surface C2. Alternatively, the edge of the first passivation layer 40 on the first side surface C1 is not flush with the other edge of the first passivation layer 40 on the cut edge side surface C2.

[0107] In some embodiments, the second passivation layer 60 also covers at least a portion of the cut edge side surface C2 so as to cover at least a portion of the first passivation layer 40 on the cut edge side surface C2.

[0108] In particular, as in Fig. 9 and Fig. 11, the second passivation layer 60 is applied to the cut edge side surface C2 along the thickness direction H of the substrate, so that the edge of the second passivation layer 60 is flush with the outer surface of the first passivation layer 40 on the first surface F. Alternatively, as shown in Fig. 10 and Fig. 12, the second passivation layer 60 covers only a part of the first passivation layer 40 on the cut edge side surface C2.

[0109] Of course, the edge of the second passivation layer 60 on the first side surface C1 may be flush with the other edge of the second passivation layer 60 on the cut edge side surface C2. Alternatively, the edge of the second passivation layer 60 on the first side surface C1 is not flush with the other edge of the second passivation layer 60 on the cut edge side surface C2.

[0110] For the above description, only one first side surface C1 and one cut-edge side surface C2 are used as examples. When the substrate 10 includes a plurality of first side surfaces C1 and / or a plurality of cut-edge side surfaces C2, the plurality of first side surfaces C1 and / or the plurality of cut-edge side surfaces C2, as well as the films or layers thereon, may each have the same or different structures. The above embodiments can be arbitrarily combined and applied to the plurality of first side surfaces C1 and / or the plurality of cut-edge side surfaces C2.

[0111] It should be understood that the doped conductive layer 30 may be formed by diffusing doping elements into at least a portion of a surface of the substrate 10. Both the first passivation layer 40 and the second passivation layer 60 may be formed using a deposition process such as plasma-enhanced chemical vapor deposition. Therefore, the outer surfaces of the doped conductive layer 30, the first passivation layer 40, and the second passivation layer 60 may not be flat, but may have conformal structures that correspond to the surfaces of the substrate 10. When covering the textured structure 20, the doped conductive layer 30, the first passivation layer 40, and / or the second passivation layer 60 also have a textured structure.When covering a flat surface, for example when covering the flat region P, the doped conductive layer 30, the first passivation layer 40 and / or the second passivation layer 60 also have flat surfaces.

[0112] One embodiment of the present application provides a method for manufacturing a solar cell. The method is suitable for manufacturing the solar cell in any of the above-mentioned embodiments. The structures, functions, operating principles, etc. related to the solar cell 100 described in the above embodiments need not be repeated here.

[0113] With reference to Fig. 13 to 18, the method for manufacturing the solar cell includes steps S10 to S40.

[0114] S10, providing a wafer 101. The wafer 101 includes a substrate 10 and a doped conductive layer 30. The substrate 10 includes a first surface F, a second surface S, and at least one first side surface C1. The first surface F and the second surface S are opposite each other. The at least one first side surface C1 is adjacent to and located between the first surface F and the second surface S. At least the first surface F and a portion of the first side surface C1 of the substrate 10 have a textured structure 20. The doped conductive layer 30 is arranged at least on the first surface F and a portion of the first side surface C1 to cover the textured structure 20.

[0115] S20, forming a passivating contact layer 50 on the second surface S of the substrate 10.

[0116] S30, forming a first passivation layer 40 on the doped conductive layer 30. The first passivation layer 40 covers the first surface F and at least a part of the first side surface C1 to cover at least the doped conductive layer 30.

[0117] S40, forming a second passivation layer 60 on the passivating contact layer 50, thereby forming a solar cell array 103. The second passivation layer 60 covers the second surface S so as to cover the passivating contact layer 50.

[0118] In the above embodiment, the first surface F and a part of the first side surface C1 of the substrate 10 include a textured structure 20. The doped conductive layer 30 is disposed at least on the first surface F and at least a part of the first side surface C1 to cover the textured structure 20. Since a part of the first side surface C1 has the textured structure and the doped conductive layer 30 is disposed on the textured structure 20, the doped conductive layer 30 on the first side surface C1 contributes to reducing the recombination of charge carriers at the interface at the first side surface C1, thereby achieving a relatively good passivation effect on the first side surface C1.Furthermore, the textured structure 20 in the first side surface C1 increases the light absorption area of ​​the solar cell 100 and thereby increases the light-generated current of the solar cell 100, which in turn improves the efficiency of the solar cell 100.

[0119] On the other hand, the first passivation layer 40 is formed on the doped conductive layer 30. The first passivation layer 40 covers at least the first surface F and at least a part of the first side surface C1 to cover at least the doped conductive layer 30. Thus, at least a part of the first side surface C1 is protected by the first passivation layer 40, which not only increases the passivation effect on the first side surface C1 but also reduces the recombination of charge carriers at the first side surface C1. Furthermore, the first passivation layer 40 is an insulating layer that effectively prevents leakage currents at the first side surface C1, thereby increasing the output power and conversion efficiency of the solar cell 100.

[0120] It is understood that the structures, materials, and coverage areas of the textured structure 20, the doped conductive layer 30, the first passivation layer 40, the passivating contact layer 50, and the second passivation layer 60 have been described in detail in the above embodiments and will not be described again here.

[0121] In some embodiments relating to Fig. 16A and Fig. 16B, the step of forming the passivating contact layer 50 on the second surface S of the substrate 10 in step S20 includes the following steps: sequentially forming a tunnel material layer 51', a doped polysilicon material layer 52', and an oxide material layer 54 on each surface of the wafer 101; Etching to remove the oxide material layer 54 on a surface F' of a first side of the wafer 101 and on each side surface of the wafer 101; and Etching to remove the doped polysilicon material layer 52' ​​and the tunnel material layer 51' on the surface F' of the first side of the wafer 101 and on each side surface of the wafer 101; wherein the surface F' of the first side of the wafer corresponds to the first surface F of the substrate 10.

[0122] In this way, only the tunnel material layer, the doped polysilicon material layer, and the oxide material layer remain on the second surface S. The tunnel material layer remaining on the second surface S is the tunnel oxide layer 51. The layer of doped polysilicon material remaining on the second surface S is the doped conductive polysilicon layer 52. The oxide material layer, for example, a silicon oxide layer, can act as a mask in a subsequent manufacturing process and can be removed by a subsequent process, for example, etching. In this way, the passivating contact layer 50 can be formed on the second surface S.

[0123] For example, the oxide material layers are etched and thus removed using a continuous etching machine; the tunnel material layer and the doped polysilicon material layer are etched and thus removed using a trough etching machine.

[0124] With reference to Fig. 19, in some embodiments, in step S40, after the step of forming the second passivation layer 60 on the passivating contact layer 50, the method further includes a step of forming electrodes 70 on the first passivation layer 40 and the second passivation layer 60, respectively. The electrode 70 on the side of the first surface F of the substrate 10 penetrates the first passivation layer 40 and is electrically connected to the doped conductive layer 30. The electrode 70 on the side of the second surface S of the substrate 10 penetrates the second passivation layer 60 and is electrically connected to the passivating contact layer 50.

[0125] It is understandable that to improve the photoelectric conversion efficiency, the cell of a standard size can be halved or cut into several parts, which can then be connected in series to form a module.

[0126] In various embodiments of the method for manufacturing a solar cell of the present application, the cutting step may be performed at different stages.

[0127] For example, the cutting step may be performed in step S10. Alternatively, the cutting step may be performed after step S40. Alternatively, the cutting step may be performed between steps S10 and S40.

[0128] In the embodiment in which the cutting step is performed, for example, in step S10, the cutting step specifically refers to cutting a substrate blank into substrates 10 having sizes required for solar cells 100.

[0129] In some embodiments, the substrate blank may be cut into substrates 10 of appropriate sizes prior to doping and patterning, corresponding to the sizes of the actually required solar cells 100. Through the prior cutting and the subsequent single-side etching and interfacial passivation processes, the edge surfaces of the solar cell 100, including the cut edge side surface C2, can be effectively passivated, thereby reducing carrier recombination and improving photoelectric conversion efficiency. Furthermore, no cutting step is performed in subsequent steps, thus avoiding the formation of new cut surfaces. This, in turn, effectively prevents significant carrier recombination that occurs in the prior art at the surface formed by the cut.

[0130] In particular with reference to Fig. 14 and Fig. 15, in step S10, the step of providing the wafer 101 includes: Cutting a substrate blank along the thickness direction to form the substrates 10, wherein the cut edge side surface C2 of each substrate 10 is formed by the cutting step; Performing a texturing treatment and diffusing doping elements at least onto the first surface F, each first side surface C1 and each cut edge side surface C2 of each substrate 10; and Etching each substrate 10 to expose the second surface S, a first target area C11 of each first side surface C1, and a second target area C12 of each cut edge side surface C2 of the substrate 10, so as to form the textured structure 20 and the doped conductive layer 30 covering the textured structure 20 on the first surface F, a portion of each first side surface C1, and a portion of each cut edge side surface C2 of each substrate 10; wherein the first target area C11 is an area of ​​the first side surface C1 adjacent to the second surface S, and the second target area C12 is an area of ​​the cutting edge side surface C2 adjacent to the second surface S.

[0131] In the above-mentioned steps, in the texturing treatment, all surfaces of the substrate 10 may be textured and formed into textured surfaces. Upon diffusion of doping elements onto the substrate 10, the first surface F of the substrate 10 may be doped with the doping elements to form the doped conductive layer 30, and some of the doping elements may wrap around the substrate 10 and deposit on the first side surface C1, the cut edge side surface C2, and the second surface S of the substrate 10, so that the first side surface C1, the cut edge side surface C2, and the second surface S are also covered with the doped conductive material.In the etching step, the first side surface C1, the cut edge side surface C2, and the second surface S of the substrate 10 may be etched using a single-sided etching technique to remove the doped conductive material and the textured structure from the second surface S, the first target region C11 of the first side surface C1, and the second target region C12 of the cut edge side surface C2 of the substrate 10, thereby exposing the second surface S, the first target region C11 of the first side surface C1, and the second target region C12 of the cut edge side surface C2 of the substrate 10 to prevent leakage currents. As a result, the textured structure 20 and the doped conductive layer 30 are retained and formed on the first surface F, a portion of the first side surface C1, and a portion of the cut edge side surface C2.

[0132] Specifically, the step of etching the substrate 10 to expose the second surface S, the first target area C11 of each first side surface C1, and the second target area C12 of each cut edge side surface C2 of the substrate 10 includes step D and step E.

[0133] Step D: Etching the substrate 10 that has undergone the texturing treatment and the diffusion of doping elements to expose the textured structure in the second surface S, the first target area C11 of each first side surface C1, and the second target area C12 of each cut edge side surface C2. In some embodiments, the etching may be performed using a continuous etching machine. During the etching process, the liquid level in the continuous etching machine must be controlled to prevent the etching solution from coming into contact with the textured structure 20 and the doped conductive layer 30 on the first surface F of the substrate 10. In one embodiment, the morphology on the first side surface C1 is irregular after the etching step, as shown in Fig. 20 shown.

[0134] Step E: Etching to remove the exposed textured structure in the second surface S, the first target area C11, and the second target area C12, so as to expose the second surface S, the first target area C11 of each first side surface C1, and the second target area C12 of each cut edge side surface C2 of the substrate 10. In some embodiments, the etching may be performed using a trough machine. It should be understood that the etching to remove the exposed textured structure serves to polish the exposed textured structure to form a non-textured structure, for example, a relatively flat surface. Due to the slight variations in the surface of the etching solution and the saturation of the substrate 10 with the etching solution during the etching process, as shown in Fig. 20, the boundary line 11 between the doped conductive layer 30 and the first target region C11 may not be a straight line but has an irregular wave pattern.

[0135] In some embodiments, the step of cutting the substrate blank along the thickness direction to form the substrates 10 includes a step of laser cutting the substrate blank along the thickness direction H to form the substrates 10. In some embodiments, the substrate blank may be divided into two substrates 10 by a laser cutting step.

[0136] The following is a concrete example to illustrate the solar cell manufacturing method in which the cutting step is performed in step S10. This example is compared with a comparative example.

[0137] Example 1: A method for manufacturing a solar cell includes steps SJ to S0.

[0138] Step SJ: Referring to Fig. 14, a substrate blank is cut along the thickness direction H to form at least two substrates 10. Each substrate 10 includes a first surface F and a second surface S opposite each other, and includes a plurality of first side surfaces C1 adjacent to and located between the first surface F and the second surface S, and further includes at least one cut edge side surface C2 formed by a cutting step.

[0139] Step SK: With reference to Fig. 15, surfaces of the substrate 10 are textured and diffused with boron elements. The substrate 10 is then etched to expose the second surface S, the first target area C11 of each first side surface C1, and the second target area C12 of each cut edge side surface C2 of the substrate 10, so that the textured structure 20 remains in the first surface F, a portion of each first side surface C1, and a portion of each cut edge side surface C2 of the substrate 10, and a doped conductive layer 30 (i.e., the boron-doped conductive layer) covers the textured structure 20 of the first surface F, a portion of each first side surface C1, and a portion of each cut edge side surface C2 of the substrate 10, thereby forming a wafer 101.

[0140] Step SL: A tunnel material layer, a doped polysilicon material layer, and an oxide material layer are sequentially stacked on the surfaces of the wafer 101. The oxide material layer on the surface F' of the first side of the wafer 101 and on the side surfaces of the wafer 101 (including each first side surface C1 and each cut edge side surface C2) is etched and thereby removed. The doped polysilicon material layer and the tunnel material layer on the surface F' of the first side of the wafer 101 and on the side surfaces of the wafer 101 are etched and thereby removed. The surface F' of the first side of the wafer 101 corresponds to the first surface F of the substrate 10. In this way, only the tunnel material layer, the doped polysilicon material layer, and the oxide material layer on the second surface S remain.The tunneling material layer, for example, a silicon oxide layer, can act as a mask in a subsequent manufacturing process and can be removed by a subsequent process, for example, etching. In this way, a passivating contact layer 50 can be formed on the second surface S, as shown in FIG. Fig. 16 shown.

[0141] Step SM: With reference to Fig. 17, a first passivation layer 40 is formed on the doped conductive layer 30. The first passivation layer 40 covers at least the first surface F, at least a portion of each first side surface C1, and at least a portion of each cut edge side surface C2 to cover at least the doped conductive layer 30.

[0142] Step SN: With reference to Fig. 18, a second passivation layer 60 is formed on the passivating contact layer 50. The second passivation layer 60 covers at least the second surface S, at least a portion of each first side surface C1, and at least a portion of each cut edge side surface C2, so as to cover the passivating contact layer 50 and at least a portion of the first passivation layer 40.

[0143] Step SO: With reference to Fig. 19, electrodes 70 are formed on the first passivation layer 40 and the second passivation layer 60, respectively, thereby obtaining a solar cell 100.

[0144] The solar cell 100 manufactured in steps SJ to S0 is referred to as solar cell A1.

[0145] Comparative Example 1: A method for manufacturing a solar cell includes steps SP to SU.

[0146] Step SP: A silicon substrate is washed and textured, and then boron elements are diffused into the washed and textured front surface of the silicon substrate.

[0147] Step SQ: The borosilicate glass (BSG) formed on the back and side surfaces of the silicon substrate by circumferential boron deposition is removed, and the side surfaces and back of the silicon substrate are polished with alkali.

[0148] Step SR: A tunnel oxide layer and a doped conductive polysilicon layer are stacked on the backside of the silicon substrate.

[0149] Step SS: A passivation and anti-reflection film is applied to both the front and back of the silicon substrate.

[0150] Step ST: To obtain a solar cell, electrodes are formed on the front and back of the silicon substrate.

[0151] Step SU: The solar cell is cut into two halves using a laser.

[0152] The solar cell of the comparative example manufactured in steps SP to ST is referred to as solar cell B1. The solar cell manufactured by steps SP to SU of the comparative example is referred to as solar cell B2.

[0153] Solar cell A1 and solar cells B1 and B2 were subjected to performance tests. The test results are shown in Table 1, where Uoc is the open-circuit voltage, FF is the fill factor, Eta is the conversion efficiency, Isc is the short-circuit current, and IRev2 is the reverse current.

[0191] Table 1: Test results for the performance of solar cells Solarzelle Isc (A) Uoc (mV) FF (%) Eta (%) IRev2 (A) A1 7,79 712,9 82,95 24,13 0,05 B1 15,56 713,3 82,98 24,12 0,08 B2 7,76 712,2 82,21 23,80 0,09

[0154] From the above experimental results, it can be seen that the efficiency of the cut solar cell A1 manufactured by the method in Example 1 is substantially the same as that of the intact (uncut) solar cell B1 in Comparative Example 1. However, compared with the cut solar cell B2 in Comparative Example 2, the open circuit voltage of the solar cell A1 increased by 0.7 mV, the fill factor of the solar cell A1 increased by about 0.74%, the conversion efficiency of the solar cell A1 increased by about 0.33%, and the reverse current of the solar cell A1 decreased from 0.09 A to 0.05 A. It can be seen that the solar cell A1 manufactured by the method in Example 1 has a higher efficiency.

[0155] In the above embodiments, the cutting step is performed in step S10. In some other embodiments, the cutting step may be performed after step S40. For example, the cutting step is performed after the preparation of the films and layers.

[0156] In the embodiment in which the cutting step is performed after step S40, the method further includes step S50 after step S40 of forming the second passivation layer 60 on the passivating contact layer 50:

[0157] Step S50: Laser cutting the solar cell matrix 103 (e.g. as shown in Fig. 25) along the thickness direction to form the cut edge side surface C2 of the substrate 10.

[0158] The solar cell matrix 103 can be divided into two or more solar cells 100 by the cutting step. For example, the solar cell matrix 103 can be cut into two halves along the thickness direction H to form two solar cells 100 (e.g., as shown in Fig. 26 shown).

[0159] In some embodiments, the step of forming the electrodes 70 on the first passivation layer 40 and the second passivation layer 60 may be performed before step S50.

[0160] In step S10, the substrate 10 is not formed by cutting the substrate blank and thus includes only the first side surfaces C1, but not any cut edge side surfaces C2. In this embodiment, the step of providing the wafer 101 in step S10 includes: Performing a texturing treatment and diffusion of doping elements onto at least the first surface F and the first side surfaces C1 of the substrate 10; and Etching the substrate 10 to expose the second surface S of the substrate 10 and the first target region C11 of each first side surface C1 of the substrate 10; wherein the first target region C11 is a region of each first side surface C1 that is adjacent to and connected to the second surface S.

[0161] In the above-mentioned steps, all surfaces of the substrate 100 may be textured and formed into textured surfaces during the texturing treatment. Upon diffusion of doping elements into the substrate 10, the first surface F of the substrate 10 may be doped with the doping elements to form the doped conductive layer 30, and some of the doping elements may surround the substrate 10 and deposit on the first side surface C1 and the second surface S of the substrate 10, so that the first side surface C1 and the second surface S are also covered with the doped conductive material.In the etching step, the first side surface C1 and the second surface S of the substrate 10 may be etched using a single-sided etching technique to remove the doped conductive material and the textured structure from the second surface S and the first target region C11 of the first side surface C1 of the substrate 10, thereby exposing the second surface S and the first target region C11 of the first side surface C1 of the substrate 10 to prevent leakage current. As a result, the textured structure 20 and the doped conductive layer 30 located on the first surface F and a portion of the first side surface C1 are retained and thus formed.

[0162] In particular, the step of etching the substrate 10 to expose the second surface S and the first target region C11 of each first side surface C1 of the substrate 10 includes step D' and step E'.

[0163] Step D': Etching the substrate 10, which has undergone the texturing treatment and the diffusion of doping elements, to expose the textured structure in the second surface S and the first target region C11. In some embodiments, the etching may be performed using a continuous etching machine. During the etching process, the liquid level in the continuous etching machine must be controlled to prevent the etching solution from coming into contact with the textured structure 20 and the doped conductive layer 30 on the first surface F of the substrate 10. In one embodiment, the morphology on the first side surface C1 is irregular after the etching step, as shown in Fig. 20 shown.

[0164] Step E': Etching to remove the exposed textured structure so as to expose the second surface S and the first target area C11 of each first side surface C1 of the substrate 10. In some embodiments, the etching may be performed using a trough machine. It is understood that the etching to remove the exposed textured structure of the surface of the substrate 10 serves to polish the textured structure 20 of the first target area C11 and the second surface S of the substrate 10 to form a non-textured structure, such as a relatively flat surface. Due to the slight fluctuations in the surface of the etching solution and the saturation of the substrate 10 with the etching solution during the etching process, as shown in Fig. 20, the boundary line 11 between the doped conductive layer 30 and the first target region C11 may not be a straight line but has an irregular wave pattern.

[0165] Since in this embodiment the solar cell 100 is formed by cutting the solar cell matrix 103 in step S40, the size of the finally formed solar cell 100 (e.g., as shown in Fig. 26) smaller than the size of the solar cell matrix 103 (e.g. as shown in Fig. 25 shown).

[0166] It is understood that by cutting the solar cell matrix 103, a cutting surface CQ is formed, as shown, for example, in Fig. 27 shown.

[0167] The following is a concrete example to illustrate the method for manufacturing the solar cell, in which the cutting step is performed after step S40. This example is compared with a comparative example.

[0168] Example 2: A method for manufacturing a solar cell including steps SJ' to S0'.

[0169] Step SJ': With reference to Fig. 21, surfaces of a substrate 10 are textured and diffused with boron elements. The substrate 10 is then etched to expose the second surface S and the first target region C11 of each first side surface C1, so that the textured structure 20 remains in the first surface F and a portion of each first side surface C1 of the substrate 10, and a doped conductive layer 30 (i.e., the boron-doped conductive layer) remains covering the textured structure 20 of the first surface F and a portion of the first side surface C1, thereby forming a wafer 101.

[0170] Step SK': With reference to Fig. 22, a tunnel material layer, a doped polysilicon material layer, and a silicon oxide material layer are sequentially stacked on the surfaces of the wafer 101. The silicon oxide material layer on the surface F' of the first side of the wafer 101 and on the side surfaces of the wafer 101 is etched and thereby removed. The tunnel material layer and the doped polysilicon material layer on the surface F' of the first side of the wafer 101 and on the side surfaces of the wafer 101 are etched and thereby removed. Thus, only the tunnel material layer, the doped polysilicon material layer, and the oxide material layer on the second surface S remain. The silicon oxide material layer, for example, a silicon oxide layer, can act as a mask in a subsequent manufacturing process and can be removed by a subsequent process, for example, etching.In this way, a passivating contact layer 50 can be formed on the second surface S, as shown in . Fig. 22 shown.

[0171] Step SL': With reference to Fig. 23, a first passivation layer 40 is formed on the doped conductive layer 30. The first passivation layer 40 completely covers at least the first surface F and each first side surface C1, thereby covering the doped conductive layer 30.

[0172] Step SM': With reference to Fig. 24, a second passivation layer 60 is formed on the passivating contact layer 50 to form a solar cell array 103. The second passivation layer 60 completely covers the second surface S and each of the first side surfaces C1, so that it covers the passivating contact layer 50 and completely covers the first passivation layer 40 arranged on the first side surface C1.

[0173] Step SN': With reference to Fig. 25, electrodes 70 are formed on the first passivation layer 40 and the second passivation layer 60 of the solar cell matrix 103, respectively.

[0174] Step SO': With reference to Fig. 26, the solar cell matrix 103 is cut by a laser along the thickness direction H to form at least two solar cells 100. The solar cell 100 manufactured in steps SJ to S0 is referred to as solar cell A2.

[0175] Solar cell A2 and solar cell B1 were subjected to performance tests. The test results are shown in Table 2, where Uoc is the open-circuit voltage, FF is the fill factor, Eta is the conversion efficiency, Isc is the short-circuit current, and IRev2 is the reverse current.

[0214] Table 2: Test results for the performance of solar cells Solarzelle Isc (A) Uoc (mV) FF (%) Eta (%) IRev2 (A) A2 15,57 714,4 83,00 24,18 0,05 B1 15,56 713,3 82,98 24,12 0,08

[0176] From the above experimental results, it can be seen that, compared with solar cell B1, the open-circuit voltage of solar cell A2 increased by 1.1 mV, the fill factor of solar cell A2 increased by about 0.02%, the conversion efficiency of solar cell A2 increased by 0.06%, and the leakage current of solar cell A2 decreased from 0.08 A to 0.05 A at a bias voltage of 12 V. It can be seen that solar cell A2 manufactured by the method in Example 2 has a lower leakage current and a higher efficiency.

[0177] With the rapid development and increasing application of photovoltaic technology, the market demand for high-efficiency photovoltaic modules is increasing. Conventional photovoltaic modules are typically packaged in a full-chip design. However, with the continuous increase in output current, the impact of internal losses is becoming increasingly significant. In order to reduce internal losses and improve the output power of photovoltaic modules, encapsulation technology has gradually evolved into the current half-cell or multi-cell technology. This technology often uses a laser cutting process to divide a standard-sized solar cell into two halves or multiple cell segments.However, laser cutting technology leads to high recombination of charge carriers at the cut edges of the resulting half-cells, creating a large number of dangling bonds and defect states on the surfaces that become effective recombination centers for charge carriers. Furthermore, there is a risk of leakage at the cut edges of the half-cells, which ultimately reduces the efficiency of the solar cell.

[0178] In one embodiment of the present application, the cutting step in the solar cell manufacturing process is performed after the deposition of the passivating contact material. The cut surface is further passivated by the first passivation layer and the second passivation layer, which are subsequently applied, reducing charge carrier recombination at the cut surface and increasing the efficiency of the solar cell 100.

[0179] An embodiment of the present application provides another method for manufacturing a solar cell suitable for manufacturing the solar cell 100 in any of the above-mentioned embodiments. The structures, functions, operating principles, etc. related to the solar cell 100 described in the above embodiments need not be repeated herein. In this embodiment, the dicing step is performed during the step of forming the passivating contact layer 50.

[0180] With reference to Fig. 28 to 33, the method for manufacturing the solar cell provided in the present embodiment includes steps S100 to S500.

[0181] S100, providing a wafer 101'. The wafer 101 includes a substrate 10 and a doped conductive material layer 30. The substrate 10 includes a first surface F, a second surface S, and at least one first side surface C1. The first surface F and the second surface S are opposite each other. The at least one first side surface C1 is adjacent to and located between the first surface F and the second surface S. At least the first surface F and a portion of the first side surface C1 of the substrate 10 have a textured structure 20. The doped conductive material layer 30 is disposed on at least the first surface F and a portion of the first side surface C1 to cover the textured structure 20.

[0182] S200, forming a passivating contact material layer 50' on each surface of the wafer 101'.

[0183] S300, cutting the wafer 101' formed with the passivating contact material layer along the thickness direction H of the substrate to form a sub-wafer 102 including a cutting edge side surface C2 for cutting the doped conductive material layer 30' into a doped conductive layer 30. In some embodiments, the cutting step divides the wafer 101' into at least two sub-wafers 102.

[0184] S400, etching to remove the passivating contact material layer 50' on a surface F' of a first side of the sub-wafer 102 and side surfaces of the sub-wafer 102, thereby forming the passivating contact layer 50 on the sub-wafer 102. The surface F' of the first side of the sub-wafer 102 corresponds to the first surface F of the substrate 10.

[0185] S500, forming a first passivation layer 40 on the doped conductive layer 30. The first passivation layer 40 covers at least the first surface F and at least a portion of the first side surface C1 to cover at least the doped conductive layer 30. The first passivation layer 40 also covers at least a portion of the cut edge side surface C2. The cut edge side surface C2 is a sub-wafer side surface formed by cutting the wafer 101'.

[0186] In the above embodiment, the first surface F and a part of the first side surface C1 of the substrate 10 include a textured structure 20. The doped conductive material layer 30' is disposed at least on the first surface F and at least a part of the first side surface C1 to cover the textured structure 20. Since a part of the first side surface C1 has the textured structure and the doped conductive material layer 30' is disposed on the textured structure 20, the doped conductive material layer 30' on the first side surface C1 in the cut solar cell 100 contributes to reducing the recombination of charge carriers at the interface at the first side surface C1, thereby achieving a relatively good passivation effect on the first side surface C1.Furthermore, in the cut solar cell 100, the textured structure 20 in the first side surface C1 enlarges the light absorption area of ​​the solar cell 100, thereby increasing the light-generated current of the solar cell 100, which in turn improves the efficiency of the solar cell 100.

[0187] On the other hand, the first passivation layer 40 is formed on the doped conductive layer 30. The first passivation layer 40 covers at least a part of the cut edge side surface C2, so that at least a part of the cut edge side surface C2 is protected by the first passivation layer 40, which not only increases the passivation effect on the cut edge side surface C2 but also reduces the recombination of charge carriers generated at the cut edge side surface C2. Furthermore, the first passivation layer 40 is an insulating layer that effectively prevents leakage currents at the cut edge side surface C2, thereby increasing the output power and conversion efficiency of the solar cell 100.

[0188] Furthermore, the first passivation layer 40 covers at least the first surface F and at least a portion of the first side surface C1 to cover at least the doped conductive layer 30. Since the first passivation layer 40 covers the first surface F and at least a portion of the first side surface C1, at least a portion of the first side surface C1 is protected by the first passivation layer 40, which not only increases the passivation effect on the first side surface C1 but also reduces the recombination of charge carriers on the first side surface C1. Furthermore, the first passivation layer 40 is an insulating layer that effectively prevents leakage currents at the first side surface C1, thereby increasing the output power and conversion efficiency of the solar cell 100.

[0189] With reference to Fig. 30, in some embodiments, in step S300, the wafer 101' is cut into at least two sub-wafers 102. That is, the solar cell 100 is manufactured after the wafer 101' is cut in step S300. Therefore, the size of the substrate 10 in the wafer 101' is larger than the size of the substrate 10 in the solar cell 100. Apart from the size and area, the first surface F and the second surface S of the substrate 10 in the wafer 101' are the same as those in the finally formed solar cell 100, which will not be described again here.

[0190] The wafer 101' is cut into a plurality of sub-wafers 102 such that the size of some first side surfaces C1 of the substrate 10 of each sub-wafer 102 is reduced compared to the original substrate 10, while a new surface formed by cutting (ie, the cut edge side surface C2) is formed in the substrate 10 of the sub-wafer 102 (and the solar cell 100).

[0191] With reference to Fig. 29A, in the wafer 101', a plurality of first side surfaces C1 of the substrate 10 may be bonded together and collectively surround the first surface F. Each first side surface C1 is bonded to the first surface F and the second side S. Furthermore, the first surface F and a part of the first side surface C1 of the substrate 10 include the textured structure 20, which is similar to that in the previous embodiments. For example, the textured structure 20 of the first surface F and the textured structure 20 of the first side surface C1 may form a continuous structure or a discontinuous structure. In this way, the textured structure 20 as a whole forms a cover that wraps the first surface F of the substrate 10 when a continuous structure is formed.

[0192] In the present embodiment, the doped conductive layer 30 is formed from the doped conductive material layer 30' after the cutting step in step S300. Thus, the material, structure, and coverage area of ​​the doped conductive material layer 30' are the same as those of the doped conductive layer 30 in the previous embodiments, which will not be described again here.

[0193] The doped conductive material layer 30' is formed on the first surface F and a portion of the first side surface C1 to cover the textured structure 20. Therefore, a portion of the doped conductive material layer 30' is disposed on the first surface F, and another portion of the doped conductive material layer 30' is disposed on a portion of each first side surface C1. The coverage area of ​​the doped conductive material layer 30' covers the textured structure 20. In some embodiments, the coverage area of ​​the doped conductive material layer 30' may be larger than the coverage area of ​​the textured structure 20. In some embodiments, the coverage area of ​​the doped conductive material layer 30' is identical to the coverage area of ​​the textured structure 20. That is, the doped conductive material layer 30' exclusively and completely covers the textured structure 20.

[0194] With reference to Fig. 29B, in step S200, during the formation of the passivating contact material layer 50' on the second surface S of the substrate 10 of the wafer 101', the passivating contact material layer 50' is also formed on the surface of the first side and each side surface of the wafer 101'. In step S400, except for the passivating contact material layer 50' formed on the second surface S of the substrate 10 of the sub-wafer 102 by the dicing step, the passivating contact material layer 50' on all other surfaces is etched and thus removed, thereby forming the passivating contact layer 50. The material of the passivating contact material layer 50' is the same as that of the passivating contact layer 50 in the previous embodiments. The passivating contact material layer 50' may include a tunneling material layer 51 and a doped polysilicon layer 52', which are sequentially stacked on the second surface S.The tunnel material layers 51' and 51 have the same material and structure, and the doped polysilicon material layers 52' and 52 have the same material and structure, which will not be described again here.

[0195] With reference to Fig. 31, in step S500, the first passivation layer 40 is formed on the doped conductive layer 30. The first passivation layer 40 has been described in detail in the above embodiments and will not be described again here.

[0196] In some embodiments, in step S100, referring to Fig. 29A, the step of providing the wafer 101' includes: Performing a texturing treatment and diffusion of doping elements onto at least the first surface F and the first side surface C1 of the substrate 10; and Etching the substrate 10 to expose the second surface S and a first target area C11 of each first side surface C1 of the substrate 10.

[0197] The first target region C11 is a region of each first side surface C1 of the substrate 10 that is adjacent to and connected to the second surface S.

[0198] In the above-mentioned embodiment, during the texturing treatment, all surfaces of the substrate 10 may be textured and formed into textured surfaces. Upon diffusion of doping elements into the substrate 10, the first surface F of the substrate 10 may be doped with the doping elements to form the doped conductive material layer 30', and some of the doping elements may wrap around the substrate 10 and deposit on the first side surface C1 and the second surface S of the substrate 10, so that the first side surface C1 and the second surface S are also covered with the doped conductive material.In the etching step, the first side surface C1 and the second surface S of the substrate 10 are etched using a single-sided etching technique to remove the doped conductive material and the textured structure from the second surface S and the first target region C11 of the first side surface C1 of the substrate 10, thereby exposing the second surface S and the first target region C11 of each first side surface C1 of the substrate 10 to prevent current leakage. As a result, the textured structure 20 and the doped conductive material layer 30' located on the first surface F and a portion of the first side surface C1 are retained and thus formed.

[0199] In particular, the step of etching the substrate 10 to expose the second surface S and the first target region C11 of each first side surface C1 of the substrate 10 includes step D'' and step E''.

[0200] Step D'': Etching the substrate 10, which has undergone the texturing treatment and the diffusion of doping elements, to expose the textured structure in the second surface S and the first target region C11 of each first side surface C1. In some embodiments, the etching may be performed using a continuous etching machine. During the etching process, the liquid level in the continuous etching machine must be controlled to prevent the etching solution from coming into contact with the textured structure 20 and the doped conductive material layer 30' on the first surface F of the substrate 10, so that after the etching step, the morphology on the first side surface C1 is irregular.

[0201] Step E'': Etching to remove the exposed textured structure so as to expose the second surface S and the first target area C11 of each first side surface C1 of the substrate 10. In some embodiments, the etching may be performed using a trough machine. It is understood that the etching to remove the textured structure 20 in the surface of the substrate 10 serves to polish the textured structure 20 of the first target area C11 and the second surface S of the substrate 10 to form a non-textured structure, such as a relatively flat surface.

[0202] In some embodiments, in step S200, the step of forming the passivating contact material layer 50' on each surface of the wafer 101' includes a step of sequentially forming a tunnel material layer 51', a doped polysilicon material layer 52', and an oxide material layer (i.e., a mask layer) on each surface of the wafer 101'.

[0203] With reference to Fig. 30, in some embodiments, in step S400, the step of etching to remove the passivating contact material layer 50' on the surface of the first side and each side surface of the sub-wafer 102 to form the passivating contact layer 50 on the sub-wafer 102 includes: Etching to remove the oxide material layer on the surface F' of the first side of the sub-wafer 102 and on each side surface of the sub-wafer 102; Etching to remove the doped polysilicon material layer 52' ​​and the tunnel material layer 51' on the surface F' of the first side of the sub-wafer 102 and on each side surface of the sub-wafer 102; and Etching to polish the cut edge side surface C2 of the sub-wafer 102.

[0204] In this way, the cut edge side surface C2 formed by the cutting step can be etched and polished to remove the surface layer damaged by the laser, thereby reducing the recombination of charge carriers at the interface of the cut edge side surface C2. For example, the etching step for removing the oxide material layer is performed using a trough machine. The etching step for removing the doped polysilicon material layer 52' ​​and the tunnel material layer 51' is performed using a trough machine.

[0205] Furthermore, after the step of etching to remove the doped polysilicon material layer 52' ​​and the tunnel material layer 51' on the surface F' of the first side of the sub-wafer 102 and on each side surface of the sub-wafer 102, the method further includes: Etching to remove the oxide material layer on a surface S' of a second side of the sub-wafer 102, thereby forming the passivating contact layer 50 on the sub-wafer 102, wherein the surface S' of the second side of the sub-wafer 102 corresponds to the second surface S of the substrate 10.

[0206] In some embodiments, in step S300, the step of cutting the wafer 101 formed with the passivating contact material layer 50' along the thickness direction H of the substrate to form at least two sub-wafers 102 includes: Laser cutting the wafer 101 formed with the passivating contact material layer 50' along the thickness direction H of the substrate 10 to form the sub-wafer 102.

[0207] In some embodiments, a wafer 101 may be divided into two equally sized sub-wafers 102 by a laser cutting step. It should be understood that in sub-wafer 102, the substrate 10, the textured structure 20, and the doped conductive layer 30 may be the same as in the solar cell 100 in the above embodiments.

[0208] In some embodiments, the method includes, with reference to Fig. 32, in step S500 after the step of forming the first passivation layer 40 on the doped conductive layer 30 further insert: Forming a second passivation layer 60 on the passivating contact layer 50, wherein the second passivation layer 60 covers at least the second surface S, at least a portion of each first side surface C1, and at least a portion of each cut edge side surface C2 to cover the passivating contact layer 50 and at least a portion of the first passivation layer 40.

[0209] In this way, the first passivation layer 40 and the second passivation layer 60 together protect at least a portion of the first side surface C1 and at least a portion of the cut-edge side surface C2, which not only increases the passivation effect on the first side surface C1 and the cut-edge side surface C2, but also reduces the recombination of charge carriers on the side surface of the solar cell 100. Furthermore, the first passivation layer 40 and the second passivation layer 60 are insulating layers that can effectively prevent leakage currents at the side surfaces of the solar cell 100, thereby increasing the output power and conversion efficiency of the solar cell 100.

[0210] In some embodiments, with reference to Fig. 33, the method further includes, after the step of forming the second passivation layer 60 on the passivating contact layer 50: Forming electrodes 70 on the first passivation layer 40 and the second passivation layer 60, respectively, to form the solar cell 100.

[0211] As in Fig. As shown in Figure 33, the electrode 70 arranged on the side of the first surface F of the substrate 10 penetrates the first passivation layer 40 and is connected to the doped conductive layer 30. The electrode 70 of the substrate 10 arranged on the side of the second surface S penetrates the second passivation layer 60 and is connected to the passivating contact layer 50.

[0212] A concrete example is given below to illustrate the method for manufacturing the solar cell in the present embodiment.

[0213] Example 3: A method for manufacturing a solar cell includes steps SJ'' to S0''.

[0214] Step SJ'': With reference to Fig. 29A, surfaces of a substrate 10 are textured and diffused with boron elements. The substrate 10 is then etched to expose the second surface S and the first target region C11 of each first side surface C1 of the substrate 10, so that the textured structure 20 remains in the first surface F and a part of the first side surface C1 of the substrate 10, and a doped conductive layer 30 (i.e., the boron-doped conductive layer) remains covering the textured structure 20 of the first surface F and a part of the first side surface C1, thereby forming a wafer 101.

[0215] Step SK'': With reference to Fig. 29B, a tunnel material layer 51', a doped polysilicon material layer 52' ​​and an oxide material layer are sequentially formed on surfaces of the wafer 101'.

[0216] Step SL'': With reference to Fig. 30, the wafer 101' formed with the passivating contact material layer is cut along the thickness direction H of the substrate, thereby forming at least two sub-wafers 102. Thus, the doped conductive material layer 30' is cut into doped conductive layers 30. The oxide material layer on the surface F' of the first side of the sub-wafer 102 and on each side surface of the sub-wafer 102 is etched and thus removed. The doped polysilicon material layer 52' ​​and the tunnel material layer 51' on the surface F' of the first side of the sub-wafer 102 and on each side surface of the sub-wafer 102 are etched and thus removed. The cut edge side surface C2 of the sub-wafer 102 created by cutting is etched and polished. Thus, only the tunnel material layer 51`, the doped polysilicon material layer 52' ​​and the oxide material layer remain on the second surface S of the substrate 10 of the sub-wafer 102.The oxide material layer, for example, a silicon oxide layer, can act as a mask in a subsequent manufacturing process and can be removed by a subsequent process, for example, etching. In this way, the passivating contact layer 50 can be formed on the sub-wafer 102.

[0217] Step SM'': With reference to Fig. 31, a first passivation layer 40 is formed on the doped conductive layer 30. The first passivation layer 40 covers at least the surface F' of the first side of the sub-wafer 102 (corresponding to the first surface F of the substrate 10) and at least a portion of the first side surface C1, thereby covering at least the doped conductive layer 30. The first passivation layer 40 also covers at least a portion of the cut edge side surface C2.

[0218] Step SN'': With reference to Fig. 32, a second passivation layer 60 is formed on the passivating contact layer 50. The second passivation layer 60 covers at least the surface of the second side of the sub-wafer 102, at least a portion of the first side surface C1, and at least a portion of the cut edge side surface C2, thereby covering the passivating contact layer 50 and at least a portion of the first passivation layer 40. The surface of the second side of the sub-wafer 102 corresponds to the second surface S of the substrate 10.

[0219] Step SO'': With reference to Fig. 33, electrodes 70 are formed on the first passivation layer 40 and the second passivation layer 60, respectively.

[0220] The solar cell 100 manufactured in steps SJ'' to sSO'' is referred to as solar cell A3.

[0221] Solar cell A3 and solar cells B1 and B2 were subjected to performance tests. The test results are shown in Table 3, where Uoc is the open-circuit voltage, FF is the fill factor, Eta is the conversion efficiency, Isc is the short-circuit current, and IRev2 is the reverse current.

[0261] Table 3: Test results for the performance of solar cells Solarzelle Isc (A) Uoc (mV) FF (%) Eta (%) IRev2 (A) A3 7,77 713,9 82,94 24,10 0,07 B1 15,56 713,3 82,98 24,12 0,08 B2 7,76 712,2 82,21 23,80 0,09

[0222] From the above experimental results, it can be seen that the efficiency of the solar cell A3 (cut) manufactured by the method in Example 3 is substantially the same as that of the intact solar cell B1 (uncut) in Comparative Example 1. However, compared with the solar cell B2 cut in Comparative Example 2, the open circuit voltage of the solar cell A3 increased by 1.7 mV, the fill factor of the solar cell A3 increased by about 0.73%, the conversion efficiency of the solar cell A3 increased by about 0.3%, and the reverse current of the solar cell A3 decreased from 0.09 A to 0.07 A. It can be seen that the solar cell A3 manufactured by the method in Example 3 has a higher efficiency.

[0223] With reference to Fig. 34, an embodiment of the present application provides a photovoltaic module 200 including at least one cell group 210. The cell group 210 includes one or more solar cells 100 provided by any of the aforementioned embodiments. The solar cells 100 may be connected to each other by serial welding.

[0224] Furthermore, with reference to Fig. 35, the solar cell matrix 103 formed in step S40 is cut into halves or three parts to obtain a plurality of solar cells 100. The plurality of solar cells 100 are connected to each other by serial welding, thus forming the photovoltaic module 200.

[0225] For example, multiple solar cells 100 may be connected in series via a welding strip to collect and transmit the electrical energy generated by the individual solar cells 100. Specifically, the electrodes 70 on the front side of each solar cell 100 are electrically connected to the electrodes 70 on the back side of an adjacent solar cell 100 by conductive strips, and the electrodes 70 on the back side of each solar cell 100 are electrically connected to the electrodes 70 on the front side of another adjacent solar cell 100 by conductive strips, so that the solar cells 100 are connected in series. The solar cells 100 may be arranged at intervals or stacked in an overlapping manner.

[0226] For example, the photovoltaic module 200 further includes an encapsulation layer and a cover plate (not shown). The encapsulation layer is configured to cover the surface of the cell group 210. The cover plate is configured to cover the surface of the encapsulation layer facing away from the cell group 210. The solar cells 100 are electrically connected in one piece or in multiple pieces to form a plurality of cell groups 210. The plurality of cell groups 210 are electrically connected in series and / or parallel. In particular, in some embodiments, the plurality of cell groups 210 may be electrically connected by conductive strips. The encapsulation layer covers the surface of the solar cells 100. The encapsulation layer may be, for example, an organic encapsulation film, such as an ethylene-vinyl acetate copolymer film, a polyethylene-octene elastomer film, or a polyethylene terephthalate film.The cover plate may have a translucent function and may be, for example, a glass cover plate, a plastic cover plate or the like.

[0227] An embodiment of the present application provides a photovoltaic system including the photovoltaic module 200 in any of the above-mentioned embodiments.

[0228] The photovoltaic system can be applied to photovoltaic power plants such as ground-mounted power plants, rooftop power plants, water surface power plants, etc. Alternatively, the photovoltaic system can be applied to devices or devices that utilize solar energy to generate electricity, such as solar power supplies for users, solar streetlights, solar cars, solar buildings, etc. It should be understood that the application scenarios of the photovoltaic system are not limited to those mentioned above; that is, the photovoltaic system can be applied to any field where solar energy needs to be utilized to generate electricity. Taking a photovoltaic power generation grid as an example, the photovoltaic system may include photovoltaic arrays, a combiner box, and an inverter. The photovoltaic array may be an array composed of multiple photovoltaic modules 200. For example, the multiple photovoltaic modules 200 may constitute multiple photovoltaic arrays.The photovoltaic systems are connected to the combiner box, which combines the power generated by the photovoltaic systems. The combined power flows through the inverter and is converted into grid-compatible alternating current. It is then connected to the grid to provide solar power.

[0229] The technical features of the above embodiments can be combined arbitrarily. To keep the description concise, not all possible combinations of the technical features are described in the embodiments. However, as long as the combination of these technical features is not contradictory, the combinations of these technical features should be considered to fall within the scope of the present application.

[0230] The embodiments described above represent only some implementations of the present application, and the descriptions are relatively specific and detailed; however, they should not be construed as limiting the scope of the present application. It should be apparent to those skilled in the art that various modifications and improvements may be made without departing from the concept of the present application, and that all fall within the scope of the present application. The patent protection of the present application is therefore defined by the appended claims.

Claims

[1] Solar cell, comprising: a substrate (10) comprising a first surface (F), a second surface (S) and a plurality of first side surfaces (C1), the first surface and the second surface being opposite one another, the plurality of first side surfaces being adjacent to and located between the first and second surfaces, at least the first surface and a portion of the first side surface of the substrate comprising a textured structure (20); a doped conductive layer (30) disposed on at least the first surface and the portion of the first side surface to cover the textured structure; a first passivation layer (40) stacked on the doped conductive layer and covering the first surface and at least the portion of the first side surface, thereby covering at least the doped conductive layer; a passivating contact layer (50) disposed on the second surface; and a second passivation layer (60) stacked on the passivating contact layer and covering the second surface, thereby covering the passivating contact layer. [2] The solar cell according to claim 1, wherein the first side surface comprises a textured region (R) provided with the textured structure and a flat region (P) adjacent to the textured region; wherein, on the first side surface, the first passivation layer completely covers the textured region and covers at least a portion of the flat region; preferably, wherein an edge of the first passivation layer facing away from the first surface is flush with a surface of the passivating contact layer facing away from the substrate. [3] The solar cell according to any one of claims 1 to 2, wherein the substrate further comprises at least one cut edge side surface (C2) adjacent to and located between the first surface and the second surface; wherein only the first surface and the part of the first surface comprise the textured structure, and the doped conductive layer is arranged only on the first surface and the part of the first surface to cover the textured structure. [4] The solar cell according to claim 3, wherein in the normal direction of the cut edge side surface, the cut edge side surface is flush with edges of the doped conductive layer, the first passivation layer, the passivating contact layer, and the second passivation layer located on the same side as the cut edge side surface; or wherein the first passivation layer further at least partially covers the cut edge side surface. [5] The solar cell according to any one of claims 1 to 2, wherein the substrate further comprises at least one cut edge side surface adjacent to and located between the first surface and the second surface; wherein at least a portion of the cut edge side surface comprises the textured structure and the doped conductive layer is arranged on the first surface, the portion of the first surface and the portion of the cut edge side surface, thereby covering the textured structure; and the first passivation layer further covers at least the part of the cut edge side surface, thereby covering at least the doped conductive layer. [6] The solar cell according to any one of claims 3 to 5, wherein the second passivation layer further at least partially covers the cut edge side surfaces, thereby covering at least a part of the first passivation layer located on the cut edge side surface. [7] The solar cell according to any one of claims 1 to 6, wherein the second passivation layer further at least partially covers the cut edge side surface, thereby covering at least a part of the first passivation layer located on the cut edge side surface. [8] The solar cell of claim 7, wherein the first side surface comprises a textured region provided with the textured structure and a flat region adjacent to the textured region; wherein the first passivation layer comprises a first part (41) located on the first side surface, and the first part covers the flat area; and the second passivation layer covers at least the first portion; preferably, wherein the first passivation layer further comprises a second portion (42) located on the first side surface, the second portion covering the textured region; and the second passivation layer covers the first portion and at least a portion of the second portion; more preferably, an edge of the second passivation layer facing away from the second surface is flush with an outer surface of the first passivation layer on the first surface. [9] A photovoltaic module comprising at least one cell group (210), wherein the cell group comprises a plurality of solar cells, wherein at least one of the plurality of solar cells comprises: a substrate (10) comprising a first surface (F), a second surface (S) and a plurality of first side surfaces (C1), the first surface and the second surface being opposite one another, the plurality of first side surfaces being adjacent to and located between the first surface and the second surface, at least the first surface and a portion of the first side surface of the substrate comprising a textured structure (20); a doped conductive layer (30) disposed on at least the first surface and the portion of the first side surface to cover the textured structure; a first passivation layer (40) stacked on the doped conductive layer and covering the first surface and at least the portion of the first side surface, thereby covering at least the doped conductive layer; a passivating contact layer (50) disposed on the second surface; and a second passivation layer (60) stacked on the passivating contact layer and covering the second surface, thereby covering the passivating contact layer. [10] A photovoltaic system comprising the photovoltaic module (200) according to claim 9.

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