HIGH-RESOLUTION THERMOPILE INFRARED SENSOR ARRAY WITH MONOLITHIC INTEGRATED SIGNAL PROCESSING

Description

[0001] The invention relates to a high-resolution thermopile infrared sensor array with monolithically integrated signal processing and multiple parallel signal processing channels for the signals of pixels of a sensor array, as well as a digital port for serial output of the signals of the pixels, wherein the sensor array is located on one or more sensor chips.

[0002] To build a high-resolution infrared thermopile sensor array, the number of individual thermopile elements, i.e., the number of pixels, must increase, while the geometric dimensions of the pixels themselves must decrease. The thermopile sensor arrays originally available on the market had only a few pixels (e.g., 8x8 or 16x16 pixels), with the individual pixels being quite large (e.g., 150–300 µm x 150–300 pm). This left enough space on the sensor chip (e.g., made of silicon) to accommodate a few amplifiers or low-pass filters alongside the thermopile sensor array.

[0003] Currently common thermopile sensor arrays with larger pixel counts require a reduction in pixel dimensions to a side length of 100 µm, or even down to 25 µm. However, the smaller pixels resulting from the increased integration density have the disadvantage of generating a proportionally smaller signal. This means that with half the pixel size, only a quarter of the signal strength is available for further processing.

[0004] The resulting ever-lower signal voltages, usually in the nanovolt range down to a few microvolts, require increasingly higher gain factors to process signals without additional noise or other interference outside the actual sensor housing. The consequence, however, is a progressively lower signal-to-noise ratio.

[0005] The signal amplification required due to the low signal voltages is at least several thousand, and usually even over 10,000, to raise the signal voltage sufficiently to be passed on to other components and processed further. The analog amplifiers with high gain traditionally used for signal amplification require multi-stage amplifiers with a relatively large footprint and, moreover, these amplifiers have considerable power consumption. This means that the power dissipation and thus the self-heating increase, which in turn leads to an increase in the overall measurement error of the thermopile sensor array.

[0006] Infrared thermopile sensor arrays, fabricated on a chip using silicon micromechanics, are now known in various configurations. In these sensor arrays, some signal processing takes place on the chip, but only a few preamplifiers and a common multiplexer are present, which outputs the signals from all pixels. The thermopiles have so-called "hot" contacts on a progressively smaller infrared receiving area and so-called "cold" contacts on a heat sink at the edge of each pixel. The signal voltage generated by the thermopile depends directly on the achievable temperature difference between the "hot" and "cold" contacts.

[0007] For example, in a thermopile sensor array according to WO 2006 / 122529 A1, one preamplifier and one low-pass filter are integrated on the chip for each row of the sensor array. However, this is insufficient for high-resolution sensor arrays with many rows and columns. For instance, in a 64x64 pixel array, only 64 preamplifiers and 64 low-pass filters are used. The achievable noise bandwidth would be up to 64 times higher than necessary. However, since noise increases with the square root of the noise bandwidth, the noise could be reduced by up to 8 times, or the thermal resolution could be improved by up to 8 times.

[0008] However, no measures are specified for a power- and space-saving solution for signal amplification per signal channel.

[0009] Furthermore, JP 2004-170375 A reveals a thermopile sensor array that has only a single preamplifier.

[0010] German patent DE 103 22 860 B4 describes a circuit arrangement for reading electronic signals from high-resolution thermal sensors with preamplifiers located upstream of a multiplexer. To reduce the considerable power dissipation of the individual parallel-operating preamplifiers, they are cyclically switched off to save power.

[0011] However, this very measure prevents the desired high temperature resolution from being achieved, because the preamplifiers before the multiplexer can only deliver the expected result if the noise bandwidth of the sampled signal is simultaneously reduced proportionally to the number of parallel amplifier channels. This is not possible, however, if the amplified signal is not continuously "integrated" via the preamplifiers using a low-pass filter to limit the noise bandwidth, or smoothed, for example, via a low-pass filter.

[0012] EP 2 587 234 A1 discloses a thermopile infrared sensor with a signal processing circuit in which the signals from the individual pixels are passed on without band limiting or intermediate preamplifiers. Further prior art is disclosed in V. Kassovski et al.: "Miniaturized 4x16 Thermopile Array Sensor with Integrated Signal Conditioning on Chip", Proceedings IRS 2011, page 57.

[0013] All of the above solutions describe thermopile infrared sensor arrays, but do not propose measures for signal processing at higher integration densities on the chip. In particular, there are no proposals for reducing the noise bandwidth while simultaneously minimizing footprint and power dissipation.

[0014] The known solutions have insufficient thermal resolution because only a single or very few preamplifier channels have been integrated on the sensor chip, resulting in a high noise bandwidth and simultaneously a poor signal-to-noise ratio.

[0015] High integration density requires reducing the pixel size and the so-called pixel pitch, i.e., the center-to-center distance of the thermopile pixels, in order to fit more pixels onto the same chip area. In addition to high geometric resolution, high thermal resolution (i.e., a large signal-to-noise ratio) and low noise-limited temperature resolution (NETD) are also desirable.

[0016] Because of the smaller receiving area and the resulting small distance between the "hot" and "cold" contacts of the thermopile pixel, a reduction in pixel size also leads to a reduction in the sensor signal emitted by the thermopile pixel, resulting in a lower signal-to-noise ratio, poorer thermal resolution, and reduced measurement accuracy.

[0017] In principle, it is possible to reduce the size of thermopile cells (thermopiles) and integrate increasingly larger numbers of pixels onto the sensor chip. For example, 16x16, 32x32, 64x64, 128x128 thermopile pixels, or more, are implemented on a single sensor chip. The signal voltages of the individual thermopile pixels would be multiplexed via an mxn addressing system and MUX switches, i.e., routed to a common serial signal line leading to one amplifier per array, or via a common serial interface per row or column.

[0018] Since the minimum resolvable signals from thermopile pixels with further reduced pixel dimensions are still in the nV range for many applications, the signals must be amplified and processed sufficiently on the chip so that they cannot be affected by electrical interference from outside and inside the sensor chip.

[0019] Gain factors of typically 10,000 or more are required in known solutions to amplify the sensor signals of such small thermopile pixels to a few mV so that the sensor signals can be output from the sensor chip on a fast serial analog output after the MUX (multiplexer) - or converted into digital signals by a fast A / D converter integrated on or directly next to the sensor chip.

[0020] The disadvantage here is that the bandwidth of these preamplifiers located after the multiplexer must be very high in order to still transmit the sensor signals of many successively sampled thermopile pixels at frame rates of several Hz up to several tens of Hz.

[0021] This requires at least mx n times the frame rate for one preamplifier per array, or m times the frame rate for an array with m columns and one preamplifier per column. However, with the square root of the (noise) bandwidth, the system noise also increases, and the temperature resolution (NETD) deteriorates.

[0022] Stable and accurate amplifiers with high gain require multiple amplifier stages, need a relatively large amount of space on the sensor chip, and also have a significant power consumption with correspondingly large heat dissipation, which in turn further reduces the achievable signal voltage of the thermopile elements.

[0023] For this reason, it is not possible to fit many such large amplifiers next to the pixels in the very limited space of a sensor chip.

[0024] The invention is therefore based on the objective of providing a thermopile infrared sensor array with monolithically integrated signal processing and several parallel signal processing channels, which has a high integration density at minimal power loss and is simultaneously thermally and geometrically high-resolution.

[0025] The problem underlying the invention is solved by the subject matter of the independent claim. The dependent claims relate to embodiments.

[0026] In a high-resolution thermopile infrared sensor array of the type mentioned above, it is proposed that each signal processing channel (K1...KN) is arranged on the sensor chip (SP) and includes at least one analog-to-digital converter (ADC). The outputs of the analog-to-digital converters of each signal processing channel (K1...KN) are connected to a memory area in a memory (RAM) for storing the results of the analog-to-digital converters (ADCs), which can be read via a control circuit.

[0027] The center-to-center distance between individual pixels of the sensor array is less than 200 µm and preferably less than 100 µm.

[0028] Each signal processing channel is assigned at least one pixel and at most 16 pixels, preferably only 8, 4, 3 or 2 pixels and most preferably one pixel.

[0029] Furthermore, a signal multiplexer is provided for each signal processing channel to select the pixels of the sensor array assigned to the signal processing channel.

[0030] A preamplifier is connected upstream of the analog-to-digital converter in each signal processing channel.

[0031] The preamplifiers have a gain factor of less than 500, and preferably less than 100.

[0032] The analog-to-digital converter has a resolution of at least 10 bits and preferably at least 16 bits, wherein the analog-to-digital converter operates according to an integrating method, for example a "charge balancing" or a "delta-sigma" method.

[0033] Each signal processing channel contains a low-pass filter to limit the noise bandwidth, the cutoff frequency of which is at least the product of the frame rate of the thermopile infrared sensor array and the number of pixels per signal processing channel, but not higher than three times, preferably twice, the product.

[0034] Finally, the low-pass filter can be part of an integrating analog-to-digital converter.

[0035] The noise bandwidth of each signal processing channel is determined depending on the respective frame rate by using an integrating analog / digital converter and the specified conversion rate of the analog / digital converter, which operates, for example, according to the "charge balancing" method.

[0036] A portion of the signal processing channels is preferably arranged in the space between the pixels, i.e., near the heat sink.

[0037] Furthermore, in the interest of a uniform distribution of the resulting power loss, it is advantageous if at least part of the signal processing channels, together with other electronics, are arranged in the area surrounding the sensor array in the outer edge region of the sensor chip.

[0038] Finally, in addition to the signal processing channels and signal multiplexers, other electronic components such as reference voltage, power supply, a reset circuit, a temperature reference, a reference data memory, a clock generator, an I / O digital port and digital signal processing (e.g. a digital controller) can be integrated on the sensor chip.

[0039] An EEPROM or flash memory is particularly suitable as a reference data storage device.

[0040] In a particularly specific embodiment of the invention, at least some of the signal processing channels are arranged on a separate chip below the sensor chip containing the sensor elements. The electrical connection of the pixels to the signal processing channels and / or other electronic components is achieved via through-holes through the sensor chip or other electrical connection means, such as rewiring. The thermopile infrared sensor chip (SP) and the separate chip (ROIC) are rigidly connected to each other. This significantly reduces the surface area of ​​the sensor chip.

[0041] The invention is explained in more detail below using exemplary embodiments. The accompanying drawings show... Fig. 1: the basic structure of a thermopile infrared sensor array according to the invention; Fig. 2: a block diagram of a circuit arrangement according to the invention for integrated signal processing for thermopile infrared array sensor chips with a low-pass filter and one signal processing channel per pixel; Fig. 3: a block diagram of a circuit arrangement according to the invention for integrated signal processing for thermopile infrared array sensor chips in a second embodiment, in which the low-pass function is performed in an integrated ADC (analog-to-digital converter); Fig. 4: a block diagram of a circuit arrangement according to the invention for integrated signal processing for thermopile infrared array chips in a third embodiment, in which several pixels share one signal processing channel, with Fig. 4a : Low-pass filter after the preamplifier and Fig. 4b : an integrating analog-to-digital converter (ADC) that performs the low-pass filter function; Fig. 5: a block diagram of another circuit arrangement according to the invention for integrated signal processing for thermopile infrared sensor arrays, in which the low-pass filter function is performed in an integrating ADC; Fig. 6a: a schematic sectional view of a sensor chip with vias and a separate chip arranged below it with integrated signal processing channels and further storage and signal processing electronics; and Fig. 6b: the arrangement according to Fig. 6a , however, supplemented with a cover wafer with a radiation entry window and additional electrical connecting means, such as bond wires for connection with other functional assemblies for operation of the thermopile infrared sensor array.

[0042] Out of Fig. 1 , 2The basic structure of a thermopile infrared sensor array according to the invention is shown, comprising a thermopile infrared sensor array (TPA) arranged in matrix form with mxn pixels SE 1.1 ... SE 1.nx SE m1.1 ... SE m, n. Around the pixels SE, or around the pixel array, signal processing channels K 1 ... KN are preferably located on two sides of the same sensor chip SP, which amplify, filter, and convert the signals of the individual pixels SE into digital signals. A number of a pixels share one signal processing channel K 1 ... KN.

[0043] In principle, all signal processing channels can also be located on one side of the pixel field, in which case the thermopile infrared sensor array will have an asymmetrical heat distribution.

[0044] Essential to the function of thermopiles is that they have "hot" and "cold" contacts that are connected to each other via the longest possible conductive paths, i.e., are arranged as far apart as possible, and where the "hot" contacts are located on a radiation receiver (not shown) and the "cold" contacts are located on a heat sink at the edge of the pixel in order to generate an evaluable signal voltage depending on the temperature difference between the "hot" and "cold" contacts.

[0045] Each pixel SE of the thermopile infrared sensor array (TPA) contains a miniaturized thermopile cell of known per se, and optionally a radiation entry window with suitable optics above each thermopile cell. The individual thermopile cells have a center-to-center distance (so-called pixel pitch) of at most 400 pm, preferably less than 200 µm, and particularly preferably less than 100 µm. The smaller the pixel pitch, the smaller the entire thermopile infrared sensor array chip becomes, and the dimensions of the optics required to image the infrared radiation onto the pixel SE also decrease for the same number of pixels. A reduction in chip and optics dimensions typically also leads to lower manufacturing costs.

[0046] Optionally, a smaller pitch allows more pixel SE to be placed on a sensor chip of a given size, thus achieving a higher optical resolution.

[0047] Fig. 2 Figure 1 shows a block diagram of a circuit arrangement according to the invention for integrated signal processing for thermopile infrared sensor arrays TPA with a mirror-image structure, with a central thermopile infrared sensor array TPA with a preamplifier VV, a downstream low-pass filter TPF and an analog / digital converter ADC for each signal processing channel K 1 ...KN on two sides of the sensor array TPA per pixel SE.

[0048] The outputs of the analog-to-digital converters (ADCs) are connected to a memory array (RAM) which can be read via a control circuit (CRTL), so that the digital output signals are available for further processing at a digital input and output port (DIO).

[0049] Furthermore, each sensor chip SP contains the components necessary for operation, such as the clock generator CLK and the necessary power supply VDD, VSS and one or more reference voltages VREF or REF / PTAT, as well as additional ESD switching blocks.

[0050] According to the invention, a large number of individual signal processing channels K 1 ...KN are integrated on or under the same sensor chip SP, wherein a number a of at most 16 or 8 pixels SE share a signal processing channel K 1 ...KN, preferably, however, only a = 4, 3 or 2 pixels SE share a signal processing channel.

[0051] The corresponding number a of pixels SE is switched via multiplexer MUX, or areas of a multiplexer MUX, to the respective assigned signal processing channel K 1 ...KN ( Fig. 4a Preferably, each pixel has its own signal processing channel K 1 ...KN (i.e., a = 1); see Fig. 3 and Fig. 4b This achieves the lowest noise bandwidth, and therefore the lowest noise and best temperature resolution. Furthermore, the multiplexers upstream of the signal processing channel K1...KN can then be omitted ( Fig. 2 ).

[0052] However, since more signal processing channels K 1 ...KN also increase space requirements and power loss, it can be advantageous, especially for sensor arrays TPA with a very high number of pixels, to choose a > 1, taking into account thermal resolution and space requirements.

[0053] In order to accommodate as many signal processing channels K 1 ...KN as possible on the chip, both the area requirement and the power loss of the individual channels must be very low in order to keep chip size and costs low, as well as thermal crosstalk between the thermopile pixel SE of the sensor array TPA.

[0054] To achieve this, signal processing channels K 1 ...KN are used, each with only one small, low-noise preamplifier W with a comparatively low gain factor, i.e. less than 500 times, and a slow, power-saving analog-to-digital converter ADC with high resolution, i.e., with at least 10 bits.

[0055] Preferably, preamplifiers (VV) with a gain factor of less than 100 times are used, and the resolution of the analog-to-digital converter (ADC) should preferably be between 16 and 24 bits.

[0056] The combination of a low-gain preamplifier (VV) and a high-resolution, slow analog-to-digital converter (ADC) ensures a small footprint due to the low gain. Furthermore, low power consumption is guaranteed thanks to the ADC, which, while high-resolution, operates at a comparatively low data rate.

[0057] Furthermore, the use of a high-resolution analog-to-digital converter (ADC) without a preamplifier (VV) is conceivable. A small difference between the positive and negative reference voltages (VREF) of the ADC is advantageous because it increases the temperature resolution.

[0058] Suitable preamplifiers include, for example, so-called auto-zero (switched chopper) amplifiers, which are characterized by low offset voltages and offset voltage drift. With a gain of less than 100 to 500, a chopper amplifier can be built as a single stage, thus saving space and power.

[0059] For slow, high-resolution analog-to-digital converters (ADCs), methods such as "sigma / delta" or "charge balancing" are suitable. Since many ADCs operate in parallel on the sensor chip (SP), the conversion rate is lower compared to conventional thermopile infrared sensor arrays with only one ADC at the output. This results in the required low power dissipation and small footprint, as can be illustrated by a 64x64 sensor array (TPA).

[0060] Analog-to-digital converters operating according to the "sigma / delta" method or the "charge balancing" method are well-known and common converters in the professional world.

[0061] A state-of-the-art sensor array with 64x64 pixels and only one analog / digital converter requires an analog / digital converter (ADC) conversion rate of 64x64 pixels x 15 Hz = 61,440 Hz at a frame rate of 15 Hz.

[0062] The analog-to-digital converters (ADCs) operating in parallel according to the invention require a conversion rate of only 15 Hz (at a = 1) or 60 Hz (at a = 4). This enables the realization of high-resolution analog-to-digital converters (ADCs) with very low power consumption and space requirements.

[0063] The digitized signals of each signal processing channel K1...KN can be temporarily stored in a memory area of ​​RAM before being passed on to the serial output data stream of an I / O digital port DIO. This allows the timing for reading the data via the digital port DIO to be selected so that the entire time of an image is available for integrating and low-pass filtering the pixel signals.

[0064] The noise bandwidth of the signal processing channels K 1 ...KN should preferably be reduced to the minimum necessary amount, which results from the product of the number of pixels SE per signal processing channel K 1 ...KN and the frame rate of the sensor array TPA.

[0065] This can be easily achieved by integrating a low-pass filter (TPF) before the analog-to-digital converter (ADC), which is possible, for example, as part of the preamplifier (VV) or as an additional low-pass filter (TPF).

[0066] In the Fig. 3 and Fig. 4b A particularly space-saving variant is shown, in which the reduction of the noise bandwidth is achieved in a particularly preferred manner by the integrator behavior of a suitable analog / digital converter ADC, e.g. an analog / digital converter ADC operating according to the charge balancing method.

[0067] The new signal processing described above results in a significant overall improvement in performance.

[0068] As is well known, in the case of white noise, the noise increases with the square root of the signal or noise bandwidth of the preamplifier VV. Using a state-of-the-art 64 x 64 sensor array, the noise bandwidth would increase by a factor of 64 x 64 of the frame rate with only one preamplifier VV, and still by a factor of 64 with one signal amplifier per column.

[0069] Consequently, the overall noise and temperature resolution of a 64x64 sensor array with one preamplifier VV would be 64 times higher, and with 64 column amplifiers still about 8 times higher, than in an array where each pixel has its own signal channel.

[0070] For example, a 64x64 sensor array TPA according to the invention can achieve up to 8 times higher thermal resolution than known sensor arrays constructed according to the prior art. Similarly, a possible improvement in thermal resolution of 4 times is achieved with a 16x16 sensor array TPA according to the invention, 5.5 times with a 32x32 sensor array TPA, and 11 times with a 128x128 sensor array TPA.

[0071] If the number of signal processing channels were reduced in a 128x128 sensor array TPA, and if, for example, a = 16 pixels shared one signal processing channel, instead of an 11-fold improvement in thermal resolution, a 3-fold improvement in signal-to-noise ratio would still be achieved compared to WO 2006 / 122529 A1 and compared to the other state of the art with only one signal transmission channel by a factor of 32.

[0072] The signal processing channels K 1 ...KN designed according to the invention can be located both in the edge region of the individual pixels SE, as in Fig. 5 The pixels are shown to be arranged in the peripheral border area of ​​the sensor chip SP, i.e., outside the pixels, or distributed across both areas.

[0073] In order to achieve good thermal balance and thus a homogeneous thermal image across the entire sensor chip SE, the power losses of the various assemblies should be distributed as homogeneously and symmetrically as possible on the sensor chip SE.

[0074] In addition to the actual signal processing channels K 1 ...KN and the multiplexers MUX, further electronic components can be integrated onto the sensor chip and switched to the digital interface via the multiplexers MUX (see Fig. 1 and Fig. 5 These additional electronic components can be temperature references, voltage references, storage devices (e.g., EEPROMs for storing calibration data), and possibly also small microcontrollers, e.g., for further signal processing or temperature calculation.

[0075] Furthermore, it can be advantageous to insert additional information REF / PTAT, such as signals from image pixels or image elements, via the same signal processing channel with the serial data stream to compensate for drift effects and thereby increase measurement accuracy.

[0076] When using an integrating analog-to-digital converter (ADC), the optimal noise bandwidth for the respective frame rate can be set via the internally generated master clock and the conversion rate specified by the clock regime.

[0077] For the sake of completeness, it should be mentioned that the signal processing channels K 1 ...KN can also be arranged on a separate ROIC chip, below the actual sensor chip SP ( Fig. 6a, 6b ).

[0078] Fig. 6a Figure 1 shows a schematic cross-sectional view of a sensor chip SP with vias TSV and a separate chip ROIC arranged beneath it, the latter containing integrated signal processing channels K1...KN and the other storage and signal processing electronics as described above. The vias TSV are through-holes filled with a conductive material passing through the sensor chip SP, which are insulated from the sensor chip SP and connected at their ends to conductive traces (not shown) on the sensor chip SP and the separate chip ROIC, respectively. It is understood that a mechanically secure connection must also exist between the sensor chip SP and the separate chip ROIC.

[0079] Out of Fig. 6b The same arrangement applies as in Fig. 6a The sensor array TPA is distinguished by a cover wafer (CAP) on the sensor chip SP, which includes a radiation entry window (SEF). The cover wafer (CAP) can be made entirely of an infrared-transparent material or may only have such a region over the sensor array TPA. Furthermore, additional electrical connections, such as bond wires (BD), can be provided to connect the sensor chip SP to other functional modules on a printed circuit board or similar, which are required for the operation of the thermopile infrared sensor array TPA.

[0080] Instead of the TSV vias for the electrical connection between sensor chip SP and the separate ROIC chip, rewiring is also possible, in which conductive traces are routed around the side edge from the sensor chip SP to the separate ROIC chip. Bezugzeichenliste

[0081] TPA Sensor array VV Preamplifier TPF Low-pass filter ADCA Analog / digital converter K 1 ...KN Signal processing channel SEPixel SP Sensor chip RAM Memory array CRTL Control circuit DIO Digital port CLK Clock generator VREF Reference voltage VDDDrain voltage VSS Source voltage MUX Multiplexer REF / PTAT Temperature reference a Number of pixels TSV Via ROIC Separate chip CAP Cover wafer SEF Radiation entry window BDB Bond wire

Claims

1. High-resolution thermopile infrared sensor array (TPA) with thermopile elements of the sensor array (TPA), hereinafter referred to as pixels (SE), with monolithically integrated signal processing, a plurality of parallel signal processing channels (K1...KN ) for the signals of the pixels (SE) of the sensor array (TPA), as well as a digital port for serial output of the signals of the pixels (SE), - wherein the sensor array is located on a sensor chip (SP) - wherein each signal processing channel (K1...KN) is arranged on the sensor chip (SP) and has at least one analog / digital converter (ADC), - wherein the outputs of the analog / digital converters (ADC) of each signal processing channel (K1...KN ) are connected to a memory area in a memory (RAM), which can be read out via a control circuit, for storing the results of the analog / digital converters (ADC), - wherein a number a of at least one pixel (SE) and at most 16 pixels (SE) share a signal processing channel (K1...KN), - wherein the signal processing channels (K1...KN) are distributed in the edge area of the individual pixels (SE), in the peripheral edge area of the sensor chip (SP) or in both areas, - wherein each signal processing channel (K1...KN) contains a low-pass filter (TPF) for limiting the noise bandwidth, the cut-off frequency of which corresponds at least to the product of the frame rate of the thermopile infrared sensor array (TPA) and the number of pixels (SE) per signal processing channel (K1...KN), but at most to three times the amount of the product, - wherein the number a of pixels (SE) for 16 ≥ a > 1 is connected via multiplexers (MUX) or areas of a multiplexer (MUX) to the respectively assigned signal processing channel (K1...KN), and for each signal processing channel (K1...KN) a signal multiplexer (MUX) for selecting the pixels (SE) of the sensor array (TPA) assigned to the signal processing channel (K1...KN) is present on the sensor chip (SP) or, with a number of pixels a = 1, each pixel (SP) has its own signal processing channel (K1...KN) without a signal multiplexer (MUX), - wherein the center-to-center distance between the individual pixels (SE) of the sensor array (TPA) is less than 200 pm, - wherein the analog-to-digital converter (ADC) has a resolution of at least 10 bits and a conversion rate of at least 15 Hz and operates according to an integrating method, and - wherein a preamplifier (VV) is connected upstream of the analog / digital converter (ADC) in each signal processing channel (K1...KN) and the preamplifiers (VV) have an amplification factor of less than 500.

2. High-resolution thermopile infrared sensor array (TPA) according to claim 1, wherein the center-to-center distance between individual pixels (SE) of the sensor array (TPA) is less than 100 µm.

3. High-resolution thermopile infrared sensor array (TPA) according to claim 1 or 2, wherein a number a of at least one pixel (SE) and at most 8, preferably at most 4, more preferably at most 3, more preferably at most 2, pixels (SE) share a signal processing channel (K1...KN).

4. High-resolution thermopile infrared sensor array (TPA) according to one of the preceding claims, wherein the analog-to-digital converter (ADC) operates according to the charge balancing or delta-sigma method.

5. High-resolution thermopile infrared sensor array (TPA) according to one of the preceding claims, wherein the low-pass filter (TPF) is a component of an integrating analog-to-digital converter (ADC).

6. High-resolution thermopile infrared sensor array (TPA) according to one of the preceding claims, wherein the sensor array (TPA) has a noise bandwidth of each signal processing channel (K1...KN) as a function of the respective frame rate, which is determined by the integrating analog-to-digital converter (ADC) by the externally predetermined or internally generated master clock and the predetermined conversion rate of the analog-to-digital converter (ADC).

7. High-resolution thermopile infrared sensor array (TPA) according to one of the preceding claims, wherein a part of the signal processing channels (K1...KN) is arranged in the space between the pixels (SE).

8. High-resolution thermopile infrared sensor array (TPA) according to one of the preceding claims, wherein at least a part of the signal processing channels (K1...KN) is arranged together with further electronics in the region surrounding the sensor array (TPA) in the outer edge region of the sensor chip (SP).

9. High-resolution thermopile infrared sensor array (TPA) according to one of the preceding claims, wherein further electronic components are integrated on the sensor chip (SP) in addition to the signal processing channels (K1...KN) and the signal multiplexers (MUX).

10. High-resolution thermopile infrared sensor array (TPA) according to claim 9, wherein said further electronic components are those for a reference voltage (VREF), a voltage supply (VDD, VSS), a temperature reference, a reference data memory (REF / PTAT), a clock generator (CLK), an I / O digital port (DIO) and signal processing.