DIGITAL INPUT CIRCUIT FOR RECEIVING DIGITAL INPUT SIGNALS FROM A SIGNAL GENERATOR

Description

[0001] The present invention relates to a digital input circuit for receiving digital input signals of a signal generator according to the preamble of claim 1.

[0002] A current trend in technology is the ever-increasing miniaturization of devices and device components, particularly electrical and electronic devices and device components. This trend toward miniaturization is often accompanied by a simultaneous increase in the range of functions of the devices or device components. This results, for example, in switching devices or safety switching devices intended for safety-related applications, particularly in automated technical systems, in an increase in the number of inputs for receiving analog or digital input signals from various signal generators. These analog or digital input signals originate, for example, from sensor devices or signaling devices, such as emergency stop buttons, safety doors, pressure sensitive mats, two-hand switches, limit switches, and other position switches.

[0003] Digital input signals are binary signals and are characterized by two defined states, which can be defined, for example, by two static potentials. These binary states are characterized by different voltage states. A first state is assumed when a defined voltage threshold is reached or exceeded. This is a so-called low-level state. A second state is assumed when a defined voltage threshold is reached or exceeded. This is a so-called high-level state. Known digital input circuits are disclosed, for example, in EP1261120A1, US6043703A, or EP2506436A2.

[0004] Digital input circuits of the type mentioned above for receiving digital input signals from a signal generator with at least one input are known from the prior art in a wide variety of designs. For current-sinking digital input circuits, which are typically operated with an operating voltage of 24 V (DC), a distinction is made between three different types (Type 1, Type 2, and Type 3) according to the EN 61131-2:2007 standard. These three types of digital input circuits differ from one another, particularly in their high levels, their low levels, and their current consumption.

[0005] Type 1 digital input circuits must detect a high level at an input voltage of 15 V at the latest. In practice, this high level is therefore already detected at an input voltage of < 15 V. Type 1 digital input circuits must also detect a high level over the entire input voltage range from 15 V to 30 V. The current consumption is ≥ 2 mA in the high level range and can be up to 15 mA. Type 1 digital input circuits (as well as types 2 and 3 mentioned below) must also be able to detect a low level over the entire range from -3 V to 5 V. In practice, a low level is therefore already detected at input voltages > 5 V. In the range from -3 V to 5 V, the input current may be between 0 mA and 15 mA. A current limit of 0.5 mA is relevant when the input voltage is between 5 V and 15 V.In this range, the input must also detect a low level as long as the input current is ≤ 0.5 mA. Such Type 1 digital input circuits are used particularly for... elektromechanische They are used for switching devices such as push buttons or relay contacts, or also for 3-wire sensor devices. A typical application example for Type 1 digital input circuits is emergency stop switching devices.

[0006] Type 2 digital input circuits are suitable, for example, for 2-wire sensor devices and for semiconductor sensors that require a relatively high quiescent current for their operation. Current consumption in the high-level range, which lies between 11 V and 30 V, is typically ≥ 6 mA and can reach up to 30 mA.

[0007] Type 3 digital input circuits are characterized by lower power consumption and lower heat dissipation compared to Type 2 digital input circuits, especially at high electrical voltages, so that more digital input circuits can be combined into one digital input module than with Type 2 digital input circuits. Type 3 digital input circuits must detect a high level in the input voltage range between 11 V and 30 V. The current consumption in the high level range, which is between 11 V and 30 V, is typically ≥ 2 mA and can be up to 15 mA. In the input voltage range between -3 V and 5 V, Type 3 digital input circuits must detect a low level with a permissible current consumption between 0 mA and 15 mA. In addition, a low level must be detected if the input voltage is between 5 V and 11 V and the input current is ≤ 1.5 mA.

[0008] The aforementioned trend toward miniaturization combined with a simultaneous increase in the number of functions requires not only the use of ever smaller components but also a constant reduction in the power dissipation of the components and circuits used. This applies particularly to digital input circuits required, for example, to process sensor signals or signals from signaling devices. The goal here must therefore be to keep the input current as low as possible at input voltages corresponding to the second state (i.e., the logical high level). This is particularly important in the range of the highest input voltages encountered, since this is where the highest currents typically flow and, consequently, the greatest power dissipation occurs.At the same time, however, there are often requirements for a minimum input current that must not be undercut when the upper threshold value, which defines the beginning of the high-level range, is reached.

[0009] An optimal digital input circuit with regard to its minimum power consumption has an input current-input voltage characteristic curve as shown in Fig. 1 is shown. This figure shows the curve of the input current I IN of the digital input circuit as a function of the input voltage U IN . The low-level range is defined by an input voltage U IN ≤ U Low,max and by an input current I IN ≤ I Low,max. The high-level range is defined by an input voltage U High,min ≤ U IN ≤ U High,max and by an input current I IN = I High,min. Between the low-level range and the high-level range there is a transition range between the input voltage U IN > U Low,max and U IN < U High,min in which an input current I Low,max < I IN < I High,min flows. As already mentioned above, in practical applications the high-level state and the low-level state are already detected at input voltages that lie within the transition range.A key feature of this idealized characteristic curve is the constant input current I IN = I High,min in the high-level range of the digital input circuit. This means that, ideally, the input current I IN in the high-level range does not increase further despite increasing input voltage U IN.

[0010] Fig. 2 In contrast, shows the input current-input voltage characteristic of a real digital input circuit, which has a suboptimal power consumption, since in the second state (high-level range) a non-ideal current consumption behavior exists. The input current I IN of the digital input circuit is plotted again as a function of the input voltage U IN . The characteristic curve, as shown in Fig. 2 shown is different from that shown in Fig. 1 The idealized characteristic curve shown is essentially due to the fact that the input current I IN continues to increase (more or less strongly) even in the high-level range. With ever increasing input voltage U IN, the following applies: I IN > I High,min . The resulting increase ΔI of the electrical input current I IN leads to a significantly greater increase in electrical power loss with increasing input voltage U IN than is the case with a characteristic curve of an ideal digital input circuit, as shown in Fig.1 shown is the case.

[0011] In the prior art, for example, a circuit arrangement is used to stabilize the input current of a digital input circuit, as shown in Fig. 3 is shown. The circuit arrangement of the digital input circuit 100' has a very simply constructed voltage regulator which comprises a bipolar transistor (npn transistor) T1', a Zener diode Z1' and a series resistor R2' for the Zener diode Z1'. Voltage limitation can be achieved by means of the Zener diode Z1'. In order for the output voltage of a voltage regulator constructed in this way to be well stabilized, it is necessary for the Zener diode Z1' to be operated in its stabilization range (i.e. with a small differential resistance) or at least close to it. For this purpose, however, the series resistor R2' of the Zener diode Z1' of the voltage regulator must be selected to be sufficiently small. However, with increasing input voltage (U in > U High,min ), this has the disadvantage that the current through the series resistor R2' and the Zener diode Z1' and thus also the input current of the digital input circuit 100' itself continues to increase significantly.The current rise ΔI in the high-level range cannot be kept very small. Therefore, the desirable stabilization of the voltage regulator's output voltage results in a significantly increased internal current requirement of the voltage regulator as the input voltage increases.

[0012] However, if the series resistor R2' is increased, the stability of the voltage regulator's output voltage deteriorates to the extent that the series resistor R2' is increased. The operating point of the Zener diode Z1' used to stabilize the output voltage can then very quickly move into the blocking region of the Zener diode Z1'. In this range, the differential resistance of the Zener diode Z1' is known to be very high. This has the disadvantage that the actual output voltage of the voltage regulator depends not only relatively strongly on the input voltage U IN but also strongly on the type of Zener diode Z1' used. This in turn can lead to the output voltage of the voltage regulator not reaching the minimum value required to detect a high-level state - at least for an input voltage U IN = U High,min.The digital input circuit therefore only detects a high-level state when the input voltage is U IN > U High,min or, in extreme cases, not even then.

[0013] In addition to the lack of reliability of such an input circuit 100', the increase in the input current I IN with increasing input voltage U IN is often not negligible, despite a relatively large series resistor R2' of the Zener diode Z1'. This increase in the input current I IN with increasing input voltage U IN is particularly important when multiple digital input circuits must be housed in a single housing with a limited power dissipation capacity to form a digital input module.

[0014] In other digital input circuits known from the prior art, the input current is stabilized by means of a single current source. The disadvantages of the circuit arrangement described above (ie the current increase ΔI in the high-level range, as in Fig. 2 The problems (shown in Figure 1) and a lack of reliability also occur when using typical real-world current sources. An example of such an embodiment is known from EP 1 906 533 A1. There, an additional current source is used to set a quiescent current in the low-level range for connecting proximity switches.

[0015] EP 1 261 120 A1 discloses an input circuit that includes two current sources, an intermediate resistor, and an optocoupler as a component for galvanic isolation. The intermediate resistor and the optocoupler are connected between the two current sources. This input circuit is designed for an input voltage range of 10 volts to 72 volts. Such relatively high input voltage fluctuations occur, for example, in railway signaling technology.

[0016] In order to obtain a digital input circuit with the lowest possible electrical power loss, it should ideally have a course of its input current-input voltage characteristic in the logical high level range, which corresponds to the Fig. 1 The aim is essentially to find the input current-input voltage characteristic curve shown in Fig. 2 shown increase in input current ΔI as the input voltage U IN > U High,min increases. In addition, the minimum input current I IN in the high-level range should be as close as possible to the minimum required input current I High,min. Another objective is to implement the digital input circuit as simply and cost-effectively as possible.

[0017] The invention therefore has for its object to provide a digital input circuit of the type mentioned at the outset which enables reliable detection of high-level and low-level states of the input signal as well as particularly low-loss operation in the high-level range and is designed in a simple and cost-effective manner.

[0018] The solution to this problem is provided by a digital input circuit of the type mentioned at the outset with the features of the characterizing part of claim 1. The subclaims relate to advantageous developments of the invention.

[0019] According to the invention, the digital input circuit comprises a high-value resistor, via which the first subcircuit is connected to ground and whose resistance value is ≥ 750 kOhm. The high-value resistor forms a series resistor for the Zener diode of the first subcircuit and is directly connected to ground. This high-value resistor has the particular function of ensuring that a current can flow into the input when the input voltage U IN increases (starting from 0 V). This resistor thus serves, in a sense, as a "start-up" or "starting resistor." Specifically, this resistor enables a current to flow in the control circuit of the current-stabilizing element of the first subcircuit during the "switch-on phase." This current, in turn, is a prerequisite for the first subcircuit to be able to supply a current.This current is a prerequisite for a current flow in the control circuit of the current stabilizing element of the second subcircuit, which ultimately enables a current flow into the second subcircuit.

[0020] In the digital input circuit, it is further provided that the first subcircuit and the second subcircuit are designed and interconnected in such a way that, at least in the second state, an electrical current flowing through the voltage-stabilizing element of the first subcircuit consists almost entirely of a stabilized current of the second subcircuit and an electrical current flowing through the voltage-stabilizing element of the second subcircuit consists almost entirely of a stabilized current of the first subcircuit, so that the non-ideal current output behavior of the first subcircuit and the non-ideal current output behavior of the second subcircuit at least partially compensate each other, at least in the second state.The circuit architecture of the digital input circuit is thus characterized by the use of at least two subcircuits that form current sources, wherein these subcircuits are preferably connected crosswise in series such that, at least for input signals in the high-level range (or at least in a part of the high-level range), which defines the second state of the digital input circuit, the electrical current flowing through the voltage-stabilizing element of the first subcircuit essentially consists of the stabilized current of the second subcircuit, and the electrical current flowing through the voltage-stabilizing element of the second subcircuit essentially consists of a stabilized current of the first subcircuit. This ensures that two parallel constant or essentially constant currents flow in the region of the first and second subcircuits.With this circuit architecture, a digital input circuit can be realized in a surprisingly simple and cost-effective manner, the input current-input voltage characteristic of which in the region of the second state, which is formed by the high-level region, almost has the optimal curve according to . Fig. 1 The currents of the two control circuits in the second state (high-level range) only make up a small part of the currents of the two subcircuits. The current increase ΔI according to Fig. 2 tends toward zero even at input voltages U IN > U High,min, so that the electrical power loss in the second state of the digital circuit arrangement can be advantageously minimized. The digital input circuit is particularly suitable for digital input modules that comprise multiple digital input circuits housed in a single housing with a limited power loss capacity.

[0021] The voltage-stabilizing elements of the first and second subcircuits are Zener diodes, which are operated in their stabilization range in the second state. The circuit architecture allows for the use of Zener diodes for both the first and second subcircuits, allowing their dimensions to be easily selected such that, at least for input signals in the high-level range, a sufficiently large current flows through both Zener diodes to operate them in, or at least close to, their stabilization range. The good mutual stabilization of the currents of the two subcircuits (and thus of the total input current) in this circuit architecture is based on the fact that the currents of the Zener diodes, and consequently also the voltages of the Zener diodes, are kept stable. The mutual stabilization of the currents of the two subcircuits is greatest when the Zener diodes are in their stabilization range.This is advantageously achieved without a disadvantageous significant increase in the input current I IN in the high-level range, as is the case with the digital input circuit 100' according to . Fig. 3 and operation of the Z-diode Z1' of the voltage regulator provided there in the stabilization range would be the case.

[0022] It has been shown that a further advantage of operating the Zener diodes of the first subcircuit and the second subcircuit within their stabilization range is that this minimizes their influence on the component-dependent tolerance of the currents of the first subcircuit and the second subcircuit. The current rise ΔI is thus minimized when the Zener diodes of the two subcircuits are operated within their respective stabilization ranges and the high-ohm resistance is as large as possible—according to a preferred embodiment, for example, ≥ 1 MOhm.

[0023] As an alternative to Zener diodes, other voltage stabilizing elements are also possible, such as conventional diodes, light-emitting diodes, or reference diodes (one or more diodes connected in series or in series with, for example, one or more Zener diodes). Limiting the current rise ΔI according to Fig. 2 This is almost as possible even with conventional diodes as with Zener diodes, since the differential resistance of diodes in the forward region can have similar values to some Zener diodes in the stabilization region after reaching the breakdown voltage. Only the dispersion of the diode voltage at a given current is generally larger than with Zener diodes. Consequently, the dispersion of the absolute current of subcircuits in which Zener diodes are used as voltage stabilizing elements is generally smaller.

[0024] In a particularly preferred embodiment, the current-stabilizing element of the first subcircuit can be formed by a bipolar transistor, in particular a PNP transistor, with a base, an emitter, and a collector. This allows the current-stabilizing element of the first subcircuit to be implemented relatively simply and cost-effectively.

[0025] Preferably, the current-stabilizing element of the second subcircuit can be formed by a bipolar transistor, in particular an NPN transistor, with a base, an emitter, and a collector. This measure also allows the current-stabilizing element of the second subcircuit to be implemented relatively simply and cost-effectively.

[0026] In an advantageous embodiment, it is proposed that the two subcircuits are interconnected in such a way that the base of the bipolar transistor of the first subcircuit is connected to the collector of the bipolar transistor of the second subcircuit.

[0027] In a further advantageous embodiment, the two subcircuits can be interconnected in such a way that the base of the bipolar transistor of the second subcircuit is connected to the collector of the bipolar transistor of the first subcircuit.

[0028] In a preferred embodiment, it can be provided that the digital input circuit has a third subcircuit which is configured to detect the logical state of the digital input circuit and which is connected to an output via which an output signal can be output. In a further embodiment, it is also possible to accommodate this third subcircuit in a separate device unit. However, this third subcircuit is not absolutely necessary. For example, the digital input circuit can be used to visually display the logical states of the input signal. This display can in particular be integrated into the second subcircuit by replacing the Zener diode for this purpose, for example, with an LED or with an LED connected in series with a Zener diode or in series with a normal diode.

[0029] In a particularly preferred embodiment, it is possible for the third subcircuit to have a coupling element configured to couple the input to the output, and a threshold element connected in parallel thereto, wherein the threshold element is designed to provide the coupling element with a switching threshold and is in particular embodied as a resistor. With the aid of the coupling element and the threshold element, it can be checked whether the digital input circuit is in the first state (in the low-level range) or in the second state (in the high-level range). Preferably, the coupling element can be designed such that it is only conductive and couples the input to the output when the digital input circuit is in the second state (in the high-level range).The coupling element can in particular be designed as an optocoupler in order to achieve galvanic isolation of a primary side of the digital input circuit, which comprises the input, from a secondary side, which comprises the output. This galvanic isolation has the advantage that the output or components connected to it can be protected from damage and resulting errors in the event of an overvoltage. The threshold element, which is preferably designed as a resistor, ensures the required switching threshold of the coupling element and, in the high-level range, also limits the current through the LED of the optocoupler, which preferably forms the coupling element, to the value for which the optocoupler is specified (e.g., 1 mA). Finally, the current flow through the resistor also contributes to the fact that the input circuit does not yet detect a high state at an input current I IN of 1.5 mA.This is required according to the IEC61131-2 standard for a DC 24 V Type 3 input, provided the input voltage is between 5 V and 11 V.

[0030] In an alternative embodiment, it is also possible, for example, to implement the coupling element as a transistor stage. This creates a digital input circuit in a non-isolated form.

[0031] It has been shown that the temperature influence of the input current can be minimized by a suitable design of the first subcircuit and the second subcircuit. In a particularly advantageous embodiment, it is proposed that the Zener diodes of the first and second subcircuits have a negative temperature coefficient. If such Zener diodes are used, which have a negative temperature coefficient, these can at least partially cancel each other out with the likewise negative temperature coefficients of the base-emitter voltages of the transistors. In other words, this means that the temperature-dependent voltage changes of the Zener diodes and the base-emitter voltages of the transistors of the two subcircuits can compensate each other relatively well.

[0032] The main advantages of the circuit architecture described above are a simple and cost-effective implementation, their suitability for all types of digital input circuits 100 according to IEC61131-2 (Type 1, 2 and 3), their suitability for current-sinking and current-sourcing digital input circuits 100, their suitability for digital input circuits 100 with and without potential isolation, as well as their suitability for safety-related applications, in particular in safety switching devices for the fail-safe shutdown of a technical system, or in I / O modules.

[0033] The digital input circuit with the circuit architecture described above can be implemented, in particular, using discrete components. Alternatively, a digital input circuit with this circuit architecture can also be implemented using an integrated circuit in an IC, in particular an ASIC.

[0034] The digital input circuit described here itself is not inherently low-loss. The actual electrical power dissipation ultimately depends on the circuit's dimensions. Dimensioning options are possible that minimize power dissipation (especially in the high-level range, of course). Dimensioning options that result in greater or higher power dissipation are equally possible. For a Type 2 digital input circuit, for example, the IEC 61131-2 standard requires a minimum current of 6 mA for a 24 V DC input in the high-level range, three times as much as for a Type 1 or Type 3 digital input circuit (at least 2 mA).

[0035] Accordingly, in a Type 2 digital input circuit, the power loss in the high-level range is at least three times as high as in a Type 1 or Type 3 digital input circuit. Nevertheless, even in a Type 2 digital input circuit, the power loss can of course be kept to a minimum using the circuit architecture described here.

[0036] Further features and advantages of the present invention will become clear from the following description of a preferred embodiment with reference to the accompanying drawings. Fig. 1 shows an idealized profile of an input current-input voltage characteristic curve of a digital input circuit, Fig. 2 shows a real profile of an input current-input voltage characteristic curve of a digital input circuit, Fig. 3 shows a digital input circuit according to the prior art, Fig. 4 shows a digital input circuit which is designed according to a preferred embodiment of the present invention.

[0037] With reference to Fig. 4 The structure of a digital input circuit 100, which is designed according to a preferred embodiment of the present invention, will be explained in more detail below. The digital input circuit 100 has an input 1, by means of which the digital input circuit 100 can be connected to a signal generator. The signal generator, which can provide the input circuit with a digital input signal, can in particular be a sensor device or a signaling device, such as an emergency stop button, an emergency stop button, a safety door, a safety mat, a two-hand switch, a limit switch, or a position switch. The signaling device can, for example, also operate contactlessly and be designed, for example, as a light grid or light barrier or comprise these.These digital input signals provided by the signal generator are binary signals and are characterized by two defined states, which can in particular be provided by two static potentials. As already explained above, these two states are characterized by different voltage levels. This is a first state in which the input voltage U IN falls below a defined threshold and is often referred to as the low-level state, and a second state in which the input voltage U IN exceeds a defined threshold and is often referred to as the high-level state. The low-level range is characterized by an input voltage U IN ≤ U Low,max and by an input current I IN ≤ I Low,max. The high-level range is defined by an input voltage U High,min ≤ U IN ≤ U High,max and by an input current I IN ≥ I High,min.

[0038] From a functional point of view, the circuit structure of the digital input circuit 100 presented here can be roughly divided into three subcircuits 3, 4, 5, which will be explained in more detail below.

[0039] The digital input circuit 100 comprises an input filter 6, which is connected to the input 1 on the one hand and to the first subcircuit 3 on the other. The input filter 6 comprises a resistor R1 and a capacitor C1 connected downstream of the resistor, one electrode of which is connected to ground GND1. The capacitor C1 serves in particular to smooth the input voltage U IN and also improves the electromagnetic compatibility of the digital input circuit 100. For example, the resistor R1 of the input filter 6 can have a resistance value of 1.5 kOhm.

[0040] The first subcircuit 3 comprises a first transistor T1, which forms a first current-stabilizing element of the digital input circuit 100 and has a drive circuit A1, as well as a first Zener diode Z1, which forms a first voltage-stabilizing element of the digital input circuit 100. In the exemplary embodiment shown here, the first transistor T1 is embodied as a pnp transistor. Furthermore, the first subcircuit 3 comprises a resistor R2, which is provided between an emitter of the first (pnp) transistor T1 and the input filter means 6 and is thus connected to the input 1 of the digital input circuit 100. For example, the resistor R2 can have a resistance value of 1.1 kOhm. This first subcircuit 3 exhibits a non-ideal current output behavior.Thus, (at least) in the second state (high-level state) it does not provide a constant output current, but an output current that continues to increase with increasing input voltage U IN and would consequently also result in an increase in the input current I IN.

[0041] The second subcircuit 4 comprises a second transistor T2, which forms a second current-stabilizing element of the digital input circuit 100 and has a drive circuit A2, as well as a second Zener diode Z2, which forms a second voltage-stabilizing element of the digital input circuit 100. In the exemplary embodiment shown here, the second transistor T2 is embodied as an npn transistor. Furthermore, the second subcircuit 4 comprises a resistor R5, which connects an emitter of the second (npn) transistor T1 to ground GND1. For example, the resistor R5 can have a resistance value of 1.1 kOhm, so that it is dimensioned like the resistor R2 of the first subcircuit 3. The second subcircuit 4 also exhibits a non-ideal current output behavior.Thus, (at least) in the second state (high-level state) it does not deliver a constant output current, but an output current that continues to increase with increasing input voltage U IN and would consequently also result in an increase in the input current I IN.

[0042] The digital input circuit 100 further comprises a high-resistance resistor R3, via which the first subcircuit 3 is connected to ground GND1 and whose resistance is preferably ≥ 1 MOhm. This high-resistance resistor R3, which connects the first subcircuit 3 to ground GND1, has the function in the present exemplary embodiment of ensuring that (starting from 0 V) an electrical current can flow into the input circuit 100 when the input voltage U IN increases. The resistor R3 thus serves, in a sense, as a "start-up" or "starting resistor." Specifically, this resistor R3 enables a current to flow in the control circuit A1 of the first transistor T1 during this "switch-on phase." This current, in turn, is a prerequisite for the first subcircuit 3 to be able to supply a current (via the collector of the first transistor T1).This current, in turn, is a prerequisite for a current flow in the control circuit A2 of the second transistor T2, which ultimately enables a current flow into the second subcircuit 4 (via the collector-emitter path of the second transistor T2). Consequently, the resistor R3 is necessary for reliable operation of the digital input circuit 100 of the embodiment shown in FIG. Fig. 4 required. Under certain circumstances, leakage currents can ensure that a current flows in the control circuit A1 of the first transistor T1 during the "switch-on phase" described above, even without resistor R3, but this is generally not reliable and therefore not practical.

[0043] The third subcircuit 5 is configured here to determine the logic state of the input signal supplied to the digital input circuit 100 via input 1, and thus also the logic state of the digital input circuit 100. The third subcircuit 5 of the input circuit 100 is connected to an output 2, via which an output voltage U OUT can be output. This third subcircuit 5 comprises a first resistor R4, which is connected to the collector of the first transistor T1, and a second resistor R6. The second resistor R6 has a first terminal connected to the output 2 and a second terminal connected to ground GND2. Furthermore, the third subcircuit 5 comprises a coupling element 7 to separate the first subcircuit 3, the second subcircuit 4, and the resistor R4 of the third subcircuit 5 from the resistor R6 and the output 2.In the exemplary embodiment shown here, this coupling element 7 is designed to bring about complete galvanic isolation (i.e., potential separation) of the first subcircuit 3, the second subcircuit 4, and the first resistor R4 of the third subcircuit 5, on the one hand, from the second resistor R6 of the third subcircuit 5 and the output 2, on the other hand. The first subcircuit 3, the second subcircuit 4, and the first resistor R4 of the third subcircuit 5 are thus formed on a primary side of the digital input circuit 100, whereas the output 2 and the second resistor R6 are provided on a secondary side of the digital input circuit 100.

[0044] In the embodiment shown here, the coupling element 7, which enables signal transmission from the primary side to the secondary side, is designed as an optocoupler having a light-emitting diode 70 on the primary side and a phototransistor 71 on the secondary side. The phototransistor 71 has, in a conventional manner, an emitter connected to ground GND2 via the resistor R6 and also to output 2 of the digital input circuit 100.

[0045] The first resistor R4 of the third subcircuit 5 ensures, on the one hand, the required switching threshold of the coupling element 7, which is embodied here as an optocoupler, and, on the other hand, limits the current through the optocoupler's LED 70 (in the high-level range) to the value for which the optocoupler is designed (for example, a current of 1 mA). Finally, the current flowing through the resistor R4 also contributes to the digital input circuit 100 not detecting a high-level state at an input current I IN of 1.5 mA. This is required by the IEC 61131-2 standard for a DC 24 V Type 3 input, provided the input voltage is between 5 V and 11 V.

[0046] The detection of whether the input voltage U IN is in the low-level range (first state of the digital input circuit 100) or in the high-level range (second state of the digital input circuit 100) is carried out by means of the coupling element 7 and the resistor R4 connected in parallel, which from a functional point of view forms a threshold element. From a functional point of view, the resistor R4 and the Zener diode Z2 of the second subcircuit 4 together form a voltage divider, with the Zener diode Z2 providing a voltage reference. The resistor R4 is dimensioned such that a current only flows through the LED 70 of the coupling element 7, which is designed as an optocoupler in this case, when the following applies to the input voltage U IN: U IN ≥ U High,min . For example, the resistor R4 can have a resistance value of 2 kOhm. The high-level state must be detected at the latest when U IN = U High,min.To ensure this, in practice, the high-level state is already detected when U IN < U High,min (i.e., within the transition region). The collector-emitter path of phototransistor 71 then becomes conductive, so that a corresponding output signal U OUT can be provided at output 2, representing the second state (high-level state). Otherwise, a corresponding output signal U OUT is provided at output 2, representing the first state (low-level state).

[0047] The galvanic isolation explained above has the advantage that the output 2 or components connected to it can be protected from damage and resulting errors in the event of an overvoltage. In an alternative embodiment, it is also possible, for example, to replace the coupling element 7, which is here designed as an optocoupler, with a transistor stage. This creates a digital input circuit 100 in a non-isolated embodiment.

[0048] The first and second subcircuits 3, 4 form two current sources (the second subcircuit 4 could also be referred to as a current sink) which are designed and interconnected in such a way that the non-ideal current output behavior of the first subcircuit 3 and the non-ideal current output behavior of the second subcircuit 4 in the second state (i.e. in the high-level range or at least in part of the high-level range) can at least partially compensate for one another. The first subcircuit 3 and the second subcircuit 4 are connected crosswise in series. The base of the transistor T1 of the first subcircuit 3, which forms part of the drive circuit A1 of the transistor T1, is connected to the collector of the bipolar transistor T2 of the second subcircuit 4.In addition, the base of the bipolar transistor T2 of the second subcircuit 4, which forms part of the control circuit A2 of the transistor T2, is connected via the resistor R4 to the collector of the bipolar transistor T1 of the first subcircuit 3.

[0049] During operation of the digital input circuit 100 and the reception of input signals in the high-level range or at least in a part of the high-level range, a current flows from the first subcircuit 3 into the third subcircuit 5, by means of which the logic state of the input signal U IN can be determined. Compensation for the non-ideal current output behavior of the two subcircuits 3, 4 is achieved in that the current flowing through the first Zener diode Z1 essentially consists of the stabilized current of the second subcircuit 4 and the current flowing through the second Zener diode Z2 essentially consists of the stabilized current of the first subcircuit 3.The good mutual stabilization of the currents of the two subcircuits 3, 4 and thus of the total input current of the input circuit 100 is based on this circuit architecture by keeping the currents of the Zener diodes Z1, Z2 and, consequently, also the voltages of the Zener diodes Z1, Z2 stable. The mutual stabilization of the currents of the two subcircuits 3, 4 is greatest when the Zener diodes Z1, Z2 are in their respective stabilization ranges. In the second state (high-level range), the currents of the two control circuits A1, A2 only account for a small portion of the currents of the two subcircuits 3, 4. In the low-level range, the transistor T2 of the second subcircuit 4 can control a base current IB,T1 of the transistor T1 of the first subcircuit 3. Conversely, the transistor T1 of the first subcircuit 3 can control a base current IB,T2 of the transistor T2 of the second subcircuit 4 in the low-level range.In the high-level range, the transistors T1, T2 primarily control the currents through the Zener diodes Z1, Z2 of the other subcircuits 3, 4.

[0050] In the logic high-level range, which characterizes the second state of the digital input circuit 100, the Zener diode Z1 of the first subcircuit 3 and the Zener diode Z2 of the second subcircuit 4 are each operated in their stabilization range. This means that in this state, the current of the first subcircuit 3 essentially flows through the Zener diode Z2 of the second subcircuit 4. In this state, the electrical current through the Zener diode Z1 of the first subcircuit 3 flows almost entirely into the second subcircuit 4, provided that the resistor R3 is selected to be sufficiently large. For example, the resistor R3 can have a resistance value of 1 MOhm.However, the currents of the two subcircuits 3, 4 already flow almost completely through the Zener diodes Z1, Z2 of the respective other subcircuit 3, 4 before the two Zener diodes Z1, Z2 are operated in their respective stabilization range, in particular at the transition of the Zener diodes Z1, Z2 from the blocking range to the conducting range. Due to the cross-series connection of the first subcircuit 3 and the second subcircuit 4, at least for input signals U IN in the high-level range (second state of the digital input circuit 100), the essentially constant currents of the respective other subcircuit 3, 4 flow through both Zener diodes Z1, Z2 of the first and second subcircuits 3, 4. Overall, the total input current I IN also remains essentially constant.By this measure, it is possible to minimize the current rise ΔI in the high-level range, so that an input current-input voltage characteristic curve of the digital input circuit 100 can be obtained which almost corresponds to the ideal characteristic curve according to . Fig. 1 By minimizing the current rise ΔI in the high-level range, which preferably tends toward zero with the circuit architecture described here, the power loss of the digital input circuit 100 can be advantageously minimized.

[0051] A significant advantage of the circuit architecture described here is that when using Zener diodes Z1, Z2 for the first subcircuit 3 and for the second subcircuit 4, their dimensioning can be very easily selected such that, at least for input signals U IN in the high-level range, a sufficiently large current flows through both Zener diodes Z1, Z2 to operate them in their stabilization range or at least close to it. This is achieved without a disadvantageous, significant increase in the input current I IN in the high-level range, as is the case with the digital input circuit 100' according to Fig. 3 and operation of the Z-diode Z1' of the voltage regulator provided there in the stabilization range would be the case.

[0052] A further advantage of operating the Zener diodes Z1, Z2 of the first subcircuit 3 and the second subcircuit 4 in their stabilization range is that their influence on the component-dependent tolerance of the currents of the first subcircuit 3 and the second subcircuit 4 is minimized. The current rise ΔI is thus minimal when the Zener diodes Z1, Z2 of the two subcircuits 3, 4 are operated in their stabilization range and the series resistor R3 of the Zener diode Z1 of the first subcircuit 3 is chosen to be as large as possible (for example - as already mentioned above - R3 = 1 MOhm or higher). The two Zener diodes Z1, Z2 can, for example, have a breakdown voltage of 2.7 V.

[0053] The temperature influence of the input current I IN can be minimized by a suitable design of the first subcircuit 3 and the second subcircuit 4. For example, Zener diodes Z1, Z2 can be used for this purpose, which have a negative temperature coefficient so that they at least partially cancel each other out with the equally negative temperature coefficients of the base-emitter voltages of the transistors T1, T2. In other words, this means that the temperature-dependent voltage changes of the Zener diodes Z1, Z2 and the base-emitter voltages of the transistors T1, T2 of the first and second subcircuits 3, 4 can compensate each other relatively well.

[0054] Alternatively, it is possible to also obtain a compensation of the temperature coefficients of the base-emitter voltages of the transistors T1, T2 by adding a conventional diode in series to the Zener diode Z1 of the first subcircuit 3 and to the Zener diode Z2 of the second subcircuit 4.

[0055] The advantages of the circuit architecture described here are particularly a simple and cost-effective implementation, their suitability for all types of digital input circuits 100 according to IEC61131-2 (Type 1, 2 and 3), their suitability for current-sinking and current-sourcing digital input circuits 100, their suitability for digital input circuits 100 with and without potential isolation, as well as their suitability for safety-related applications, in particular in safety switching devices for the fail-safe shutdown of a technical system, or in I / O modules.

[0056] Above, a digital input circuit 100 was explained that was implemented using discrete components. Alternatively, a digital input circuit 100 with this circuit architecture can also be implemented using an integrated circuit in an IC, in particular an ASIC.

[0057] In a further embodiment, it is also possible to accommodate the third subcircuit 5, which is provided for detecting the logical state of the input signal U IN, in a separate device unit.

Claims

1. Digital input circuit (100) for receiving digital input signals from a signal generator, comprising - an input (1) via which the input signal is able to be supplied to the input circuit (100), wherein the input circuit (100) assumes a first logic state, constituting a low-level state, when the input signal reaches or falls below a lower threshold value, and wherein the input circuit (100) assumes a second logic state, constituting a high-level state, when the input signal reaches or exceeds an upper threshold value, - a first subcircuit (3) which has at least one current-stabilizing element (T1) comprising a control circuit (A1) and at least one voltage-stabilizing element, wherein the first subcircuit (3), at least in the second state, exhibits non-ideal current output behaviour and does not deliver a constant output current but rather an output current which increases further as the input voltage (UIN) increases, and - a second subcircuit (4) which has at least one current-stabilizing element (T2) comprising a control circuit (A2) and at least one voltage-stabilizing element, wherein the second subcircuit (4), at least in the second state, exhibits non-ideal current output behaviour and does not deliver a constant output current but rather an output current which increases further as the input voltage (UIN) increases, wherein the first subcircuit (3) and the second subcircuit (4) are embodied and connected to one another in such a way that, at least in the second state, an electrical current flowing through the voltage-stabilizing element of the first subcircuit (3) consists virtually completely of a stabilized current from the second subcircuit (4), and an electrical current flowing through the voltage-stabilizing element of the second subcircuit (4) consists virtually completely of a stabilized current from the first subcircuit (3), such that the non-ideal current output behaviour of the first subcircuit (3) and the non-ideal current output behaviour of the second subcircuit (4) at least partially compensate for one another at least in the second state, wherein the voltage-stabilizing elements of the first and second subcircuit (3, 4) are Zener diodes (Z1, Z2) which are operated in their stabilization range in the second state, wherein the digital input circuit (100) has a high-impedance resistor (R3) via which the first subcircuit (3) is connected to earth (GND1) and the resistance value of which is ≥ 750 kOhm, wherein the high-impedance resistor (R3) forms a series resistor with the Zener diode (Z1) of the first subcircuit (3) and is connected directly to earth (GND1).

2. Digital input circuit (100) according to Claim 1, characterized in that the resistance value of the high-impedance resistor (R3) is ≥ 1 MOhm.

3. Digital input circuit (100) according to either of Claims 1 and 2, characterized in that the current-stabilizing element (T1) of the first subcircuit (3) is formed by a bipolar transistor (T1), in particular by a pnp transistor, comprising a base, an emitter and a collector.

4. Digital input circuit (100) according to one of Claims 1 to 3, characterized in that the current-stabilizing element (T2) of the second subcircuit (4) is formed by a bipolar transistor (T2), in particular by an npn transistor, comprising a base, an emitter and a collector.

5. Digital input circuit (100) according to Claim 4, characterized in that the two subcircuits (3, 4) are connected to one another in such a way that the base of the bipolar transistor (T1) of the first subcircuit (3) is connected to the collector of the bipolar transistor (T2) of the second subcircuit (4).

6. Digital input circuit (100) according to either of Claims 4 and 5, characterized in that the two subcircuits (3, 4) are connected to one another in such a way that the base of the bipolar transistor (T2) of the second subcircuit (4) is connected to the collector of the bipolar transistor (T1) of the first subcircuit (3).

7. Digital input circuit (100) according to one of Claims 1 to 6, characterized in that the digital input circuit (100) has a third subcircuit (5) which is configured to identify the logic state of the digital input circuit (100) and which is connected to an output (2) via which an output signal can be output.

8. Digital input circuit (100) according to Claim 7, characterized in that the third subcircuit (5) has a coupling element (7), which is configured to couple the input (1) to the output (2), and a threshold value element connected in parallel therewith, wherein the threshold value element is designed to provide the coupling element (7) with a switching threshold and is embodied in particular as a resistor (R4).

9. Digital input circuit (100) according to one of Claims 2 to 8, characterized in that the Zener diodes (Z1, Z2) of the first and of the second subcircuit (3, 4) have a negative temperature coefficient.