FIELD EFFECT TRANSITOR ARRANGEMENT AND METHOD FOR ADJUSTING A DRAIN FLOW OF A FIELD EFFECT TRANSITOR

Description

[0001] The present invention relates to a field-effect transistor arrangement and a method for adjusting a drain current of a field-effect transistor. State of the art

[0002] Due to parasitic effects, the drain current ID of field-effect transistors in the saturation region, also known as the pinch-off region, increases with increasing drain-source voltage V DS. This undesirable behavior increases in CMOS processes with increasing transistor scaling, causing the output characteristics of, for example, modern CMOS field-effect transistors to exhibit a considerable increase. See also the Figure 1 the state of the art.

[0003] The described effect adversely leads to a reduction in the small-signal drain-source resistance r DS and thus also to a reduction in the intrinsic gain A i of the field-effect transistor. The intrinsic gain of the field-effect transistor describes the maximum voltage gain that a field-effect transistor can achieve at a specific operating point. For a common-source field-effect transistor with a high-impedance load, this is calculated from the product of the so-called small-signal transconductance gm and the small-signal drain-source resistance r DS . High values ​​of this quantity are important for applications requiring high gain or high precision.

[0004] Complex circuit topologies with multiple field-effect transistors allow amplifier circuits with high voltage gain to be designed even with field-effect transistors with low intrinsic gain. However, this requires the stacking of multiple field-effect transistors, which is difficult or even impossible in scaled CMOS technologies due to the low supply voltage. The combination of both effects, the strong ID (V DS ) dependence, and the low supply voltage ensure that high voltage gain in scaled CMOS processes is not achievable or only with considerable effort. US 2009 / 0146723 A1 and US 5 132 752 A provide an amplifier circuit with a transistor whose backgate voltage is controlled via an operational amplifier.US 2010 / 0026391 A1 discloses a circuit arrangement comprising two transistors connected in series and a control unit which controls the intermediate current between the transistors via backgates. Disclosure of the invention

[0005] According to the invention, a field effect transistor arrangement according to claim 1 is provided.

[0006] The invention has the advantage that unwanted parasitic effects can be compensated by regulating the backgate voltage. This allows, for example, output characteristics with a largely constant drain current to be generated in a saturation region of the field-effect transistor; for example, see Figure 4, thereby increasing the small-signal drain-source resistance and thus improving the intrinsic gain of the field-effect transistor. The invention implements a control system or a control loop in which at least the gate-source voltage acts as an input variable to regulate the backgate voltage acting as a manipulated variable and thus adjust the drain current to a target current. The invention is particularly suitable for field-effect transistors with a strong impact of the backgate voltage on the drain current, which is the case, for example, with SOI or FDSOI CMOS technologies. However, other field-effect transistors in which the drain current can be sensitively changed by changing the backgate voltage can also be used preferably within the meaning of the invention.A field-effect transistor can be, for example, an IGFET such as a MOSFET or a JFET, although the invention is not limited to a specific field-effect transistor. For example, both normally-on and normally-off field-effect transistors are possible. The field-effect transistor arrangement can also be connected or integrated into electrical circuits instead of a prior-art field-effect transistor.

[0007] The control unit is also configured to regulate the backgate voltage depending on the drain-source voltage at the field-effect transistor. This can be used, for example, to determine the operating range of the field-effect transistor, such as the linear range or the saturation range. The control unit can thus generate a backgate voltage control suitable for the respective range.

[0008] The target current in a saturation region of the field-effect transistor is independent of the drain-source voltage. In other words, the backgate voltage is controlled by the control unit such that the drain current is constant as a function of the drain-source voltage. This maximizes the intrinsic gain of the field-effect transistor arrangement.

[0009] The control unit is configured to control the backgate voltage of the field-effect transistor based on its known electrical behavior. The advantage of this design is that the drain current of the field-effect transistor does not need to be explicitly determined. Furthermore, the control unit can perform additional calibration tasks, for example, to compensate for process fluctuations. The known electrical behavior of the field-effect transistor is provided to the control unit in the form of data sets stored in a memory. From this, a corresponding correction value for the backgate voltage can then be determined using the data as well as the drain-source voltage and gate-source voltage.

[0010] In an embodiment not covered by the claims, the control unit can be configured to control the backgate voltage depending on the drain current flowing through the field-effect transistor. Thus, all electrical information—i.e., drain current, gate-source voltage, and drain-source voltage—is available for implementing a control loop with a reference element.

[0011] According to a preferred embodiment, the field-effect transistor arrangement comprises a reference field-effect transistor, to which a gate-source voltage identical to the gate-source voltage of the field-effect transistor is applied, and wherein a constant drain-source voltage and a constant backgate voltage are also applied to the reference field-effect transistor. As a result, the drain current flowing through the reference field-effect transistor is advantageously independent of the drain-source voltage.

[0012] The control unit can be configured to regulate the backgate voltage at the field-effect transistor such that the drain current through the reference field-effect transistor is identical to the drain current through the field-effect transistor. The drain current through the reference field-effect transistor thus serves as the target value for the drain current through the field-effect transistor. Thus, the reference field-effect transistor sets an independent drain current through the field-effect transistor that is independent of the drain-source voltage.

[0013] Furthermore, an electrical circuit, in particular an amplifier circuit, comprising one or more field-effect transistor arrangements according to one of the preceding claims is proposed. Electrical circuits, in particular amplifier circuits, can exhibit improved performance by eliminating or compensating for parasitic effects of the field-effect transistor.

[0014] The method according to the invention for adjusting a drain current of a field-effect transistor basically comprises the steps according to claim 3.

[0015] The advantages of the method correspond to the advantages of the field effect transistor arrangement described above.

[0016] The backgate voltage is also regulated depending on the drain-source voltage.

[0017] The target current is independent of the drain-source voltage in a saturation region of the field-effect transistor.

[0018] The backgate voltage can be controlled by the control unit based on a known electrical behavior of the field-effect transistor.

[0019] Furthermore, in an embodiment not covered by the claims, the method may comprise regulating the backgate voltage as a function of the drain current flowing through the field effect transistor.

[0020] Preferably, the method may comprise providing a reference field-effect transistor to which a gate-source voltage equal to the gate-source voltage on the field-effect transistor is applied, and wherein a constant drain-source voltage and a constant backgate voltage are applied to the reference field-effect transistor.

[0021] In a further preferred embodiment, the backgate voltage can be controlled by the control unit in such a way that the drain current through the reference field-effect transistor is identical to the drain current through the field-effect transistor.

[0022] Advantageous further developments of the invention are specified in the subclaims and described in the description. Drawings

[0023] Embodiments of the invention are explained in more detail with reference to the drawings and the following description. They show: Figure 1an output characteristic field of a field-effect transistor of the state of the art, Figure 2 a field effect transistor arrangement according to the invention according to a first embodiment, Figure 3 a field effect transistor arrangement which is not covered by the claims, and Figure 4 an exemplary output characteristic field of a field effect transistor arrangement according to the invention. Embodiments of the invention

[0024] In the Figure 1is shown an output characteristic field of a field-effect transistor of the prior art, in which a drain current ID flowing through a field-effect transistor is plotted as a function of the drain-source voltage V DS for a plurality of different gate-source voltages V GS . On the field-effect transistor according to the prior art, an adjustable but constant backgate voltage is set at its backgate terminal, which is not explicitly shown here. The functional curve of the drain current ID for each associated gate-source voltage V GS shows, as a function of the drain-source voltage V DS , a linear region 40 for sufficiently small drain-source voltages V DS and a saturation region 50 for sufficiently large drain-source voltages V DS , wherein the regions are separated from one another by a dividing line for illustrative purposes. The Figure 1The plot of the drain current ID as a function of the drain-source voltage V DS shows that in the saturation region 50, also called the pinch-off region, the drain current continues to increase as a function of the drain-source voltage, which is undesirable and is due to parasitic effects. This effect adversely leads to a lower small-signal drain-source resistance and thus to lower intrinsic gain.

[0025] In the Figure 2 A field-effect transistor arrangement 1 according to a first embodiment of the invention is described. The field-effect transistor arrangement 1 is integrated, for example, in an electrical circuit, in this specific case in an amplifier circuit 100.

[0026] The field-effect transistor arrangement 1 comprises a field-effect transistor T with a backgate terminal BG that can be adjusted with a backgate voltage V BG . Furthermore, a gate-source voltage V GS and a drain-source voltage V DS are applied to the field-effect transistor T, and a drain current ID also flows through the field-effect transistor T. Purely by way of example, in the present embodiment, a source terminal S of the field-effect transistor T is grounded, so that the voltage applied to a gate terminal G of the field-effect transistor T corresponds to the gate-source voltage V GS . However, the invention is not limited to grounding the source terminal S.

[0027] The field-effect transistor arrangement 1 further comprises a control unit 10, which is connected to the backgate terminal BG of the field-effect transistor T. The control unit 10 is configured to adjust the drain current ID flowing through the field-effect transistor T to a desired current by controlling the backgate voltage V BG at the backgate terminal BG. The backgate voltage V BC is controlled as a function of at least the gate-source voltage V GS .

[0028] The field-effect transistor arrangement 1 has the advantage that unwanted parasitic effects can be compensated for by regulating the backgate voltage V BG . For example, the target current can be selected such that the small-signal drain-source resistance is increased accordingly, thus improving the intrinsic gain of the field-effect transistor T.

[0029] The invention describes a feedback control system or a control loop in which at least the gate-source voltage V GS acts as an input variable to control the backgate voltage V BG , which acts as a manipulated variable, and thus to adjust the drain current to a desired current.

[0030] The control unit 10 also controls the backgate voltage V SG as a function of the drain-source voltage V DS at the field-effect transistor T.

[0031] By means of the drain-source voltage V DS at a given gate-source voltage V GS , it can be determined, for example, in which operating range the field-effect transistor T is located, i.e., for example, whether the field-effect transistor T is in the saturation region 50 or in the linear region 40.

[0032] The control unit 10 can, for example, be configured to directly detect or record the drain-source voltage V DS and the gate-source voltage V GS applied to the field-effect transistor T. Alternatively, these can also be recorded by a corresponding measuring unit, which is not explicitly shown, and transferred to the control unit 10.

[0033] In particular, the target current in the saturation region 50 of the field-effect transistor T is independent of the drain-source voltage V DS . Thus, the backgate voltage V BG is regulated as a function of the input variable such that the drain current ID corresponds to this constant target current. This allows the intrinsic gain to be maximized.

[0034] In this specific embodiment, the regulation of the backgate voltage V BG is only dependent on the gate-source voltage V GS and the backgate voltage V SG , although the invention is not limited thereto.

[0035] In this embodiment, the control unit 10 is further configured to control the backgate voltage V BG of the field-effect transistor T from a known electrical behavior of the field-effect transistor T. For this purpose, data sets from the field-effect transistor T, which describe the electrical behavior of the field-effect transistor T, are stored in a memory 15. The control unit 10 can then access this memory 15. For example, the control unit 10 can comprise an internal memory 15 in which corresponding data about the electrical behavior of the field-effect transistor T are stored. For example, the data can describe the output characteristics in the form of an ID (V DS ) dependency for different values ​​of gate-source voltages V GS similar to Figure 1 have.

[0036] The control unit 10 can then determine a suitable correction value for the backgate voltage V BG by detecting the gate-source voltage V GS and the drain-source voltage V DS and comparing it with the known behavior. This then sets a desired target current, which is constant in the saturation region 50, through the field-effect transistor 1 using the backgate voltage V BC. In this embodiment, the drain current ID does not have to be explicitly determined as an input variable. Compared to the Figure 3 However, the design described requires increased design effort and complicated control technology for the control unit 10.

[0037] An exemplary output characteristic field of such a field effect transistor arrangement 1 can, for example, be Figure 4 be taken.

[0038] Such a field effect transistor arrangement 1 can, as exemplified in the present Figure 2shown, be integrated in an electrical circuit. In the present example, the electrical circuit is designed as an amplifier circuit 100. This amplifier circuit 100 is constructed in the form of a typical source circuit, although the invention is not restricted to a specific circuit. The amplifier circuit 100 in this embodiment comprises an operating voltage V DD , which is connected via a load resistor R1 to the drain terminal D of the field-effect transistor T. A portion of the operating voltage V DD is therefore always dropped across the load resistor R1. The load resistor R1 also limits the drain current ID . The input voltage of this amplifier circuit 100 in this embodiment is applied to the gate terminal G of the field-effect transistor T. An amplified output voltage V out of the amplifier circuit 100 can then be tapped off at the drain terminal D.The field effect transistor arrangement 1 can thus be used instead of a conventional field effect transistor of the prior art, wherein the electrical circuit, here the amplifier circuit, has no or reduced parasitic behavior compared to a circuit of the prior art.

[0039] In the Figure 3 A field effect transistor arrangement 1 is shown which does not fall under the claims. The differences to the one in Figure 2 described embodiment in more detail. For the similarities, please refer to the description content Figure 2 referred to.

[0040] As in the embodiment in Figure 2the field-effect transistor arrangement 1 comprises a control unit 10 which is connected to the backgate terminal BG of the field-effect transistor T. The control unit 10 is configured to set the drain current ID flowing through the field-effect transistor T to a target current by controlling the backgate voltage V BG at the backgate terminal BG. In this embodiment, the backgate voltage V BG is controlled as a function of the gate-source voltage V GS and additionally as a function of the drain current ID through the field-effect transistor T. Optionally, in this embodiment, the control can also be controlled as a function of the drain-source voltage V DS. The drain current ID can, for example, be detected by the control unit 10 or measured by another measuring unit and transferred to the control unit 10.As a result, all electrical information, namely the gate-source voltage V GS and the drain-source voltage V DS and the drain current ID , are available to the control unit 10 for the realization of a control loop with a reference element.

[0041] In this preferred embodiment, a reference field-effect transistor T1 is used as the reference element. In this embodiment, a gate-source voltage V GS1 is applied to the reference field-effect transistor T1, which is identical to the gate-source voltage V GS of the field-effect transistor T.

[0042] This correspondence is realized in the present exemplary embodiment by a source terminal S1 of the reference field-effect transistor T1, which, like the source terminal S, is grounded and is further connected to a potential by an electrical connection from the gate terminal G of the field-effect transistor T to a gate terminal G1 of the reference field-effect transistor T1. Due to the coupling of the gates G, G1, their electrical potentials are thus always identical. Since the source terminals S, S1 are also at the same potential, since both are grounded, the same gate-source voltage V GS = V GS1 is always present at the reference field-effect transistor T1 as at the field-effect transistor T.

[0043] In this embodiment, a constant drain-source voltage V DS1 and a constant backgate voltage V SG1 are also applied to the reference field-effect transistor T1. As a result, a drain current I D1 , which depends only on the gate-source voltage V GS , flows through the reference field-effect transistor T1 to the source terminal S1. This drain current I D1 is thus independent of the drain-source voltage V DS .

[0044] The control unit 10 can then control the backgate voltage V BG at the field-effect transistor T such that the drain current ID through the reference field-effect transistor T1 is identical to the drain current I D1 through the field-effect transistor T. Furthermore, the drain current ID also becomes independent of the drain-source voltage V DS . The drain current I D1 thus corresponds to the target current of the control loop.

[0045] By this implementation, the output characteristics in the saturation region 50 of the field effect transistor 1 can be kept constant, see also for example Figure 4 .

[0046] The field effect transistor arrangement 1 can be analogous to Figure 1 be integrated in an electrical circuit, such as an amplifier circuit 100, see the design in the description of Figure 2 .

[0047] In the Figure 4 An exemplary output characteristic field of a field-effect transistor arrangement 1 according to the invention is shown. A drain current ID is plotted as a function of the drain-source voltage V DS for a plurality of different gate-source voltages V GS .

[0048] The functional course of the drain current ID to each gate-source voltage V GS shows as in the Figure 1of the prior art, a linear region 40 for sufficiently small drain-source voltages V DS and a saturation region 50 for sufficiently large drain-source voltages V DS , the respective regions being separated by a dividing line for illustrative purposes.

[0049] In contrast to the Figure 1 In the illustrated output characteristics, the output characteristics in the saturation region 50 exhibit a nearly constant profile as a function of the drain-source voltage V DS , or at least a significantly reduced slope. In other words, the drain current ID is independent of the drain-source voltage V DS . This advantageously results in a correspondingly increased small-signal drain-source resistance r DS and thus also an improved intrinsic gain A i .

[0050] Although the invention has been illustrated and described in detail by means of preferred embodiments, the invention is not limited by the disclosed examples and other variations can be derived therefrom by those skilled in the art without departing from the scope of the invention as defined by the claims.

Claims

1. Field-effect transistor arrangement (1), comprising: - a field-effect transistor (T) having a back gate terminal (BG) that can be adjusted using a back gate voltage (VBG), wherein a gate source voltage (VGS) and a drain source voltage (VDS) are also applied at the field-effect transistor (T) and a drain current (ID) flows through the field-effect transistor (T); - a control unit (10) that is connected to the back gate terminal (BG) and is configured to adjust the drain current (ID) flowing through the field-effect transistor (T) to a setpoint current by means of controlling the back gate voltage (VBG) at the back gate terminal (BG), characterized by - a memory (15) in which data about a known electrical behaviour of the field-effect transistor (T) are stored; and the control unit (10) is configured to control the back gate voltage (VBG) as a function of the gate source voltage (VGS), the drain source voltage (VDS) and from the data stored in the memory (15) about the known electrical behaviour of the field-effect transistor (T) as input variables so that the drain current is independent of the drain source voltage (VDS) in a saturation range (50) of the field-effect transistor (T).

2. Electrical circuit, in particular an amplifier circuit (100), comprising one or more field-effect transistor arrangements (1) according to Claim 1.

3. Method for adjusting a drain current of a field-effect transistor (T), comprising the steps of: - providing a field-effect transistor (T) having a back gate terminal (BG) that can be adjusted using a back gate voltage (VBG), wherein a gate source voltage (VGS) and a drain source voltage (VDS) are also applied at the field-effect transistor (T) and a drain current (ID) flows through the field-effect transistor (T); - adjusting the drain current (ID) flowing through the field-effect transistor (T) to a setpoint current by means of controlling the back gate voltage (VBG) at the back gate terminal (BG) by means of a control unit (10) that is connected to the back gate terminal (BG), characterized in that data about a known electrical behaviour of the field-effect transistor (T) are stored in a memory (15), and the back gate voltage (VBG) is controlled as a function of the gate source voltage (VGS), the drain source voltage (VDS) and the data stored in the memory (15) about the known electrical behaviour of the field-effect transistor (T) as input variables so that the drain current is independent of the drain source voltage (VDS) in a saturation range (50) of the field-effect transistor (T).