PRECHARGE OF AN INTERMEDIATE CIRCUIT

Description

[0001] The present invention relates to a method for operating a three-phase inverter which comprises an intermediate circuit, a DC / AC bridge and a control unit, wherein half bridges of the DC / AC bridge are controlled by the control unit in order to convert an input DC voltage of a DC voltage side into an output AC voltage via the intermediate circuit and the DC / AC bridge in normal operation, wherein the inverter is switched into a pre-charging mode before activation of the normal operation, in which an intermediate circuit voltage of the intermediate circuit is pre-charged to a predetermined bias voltage.Furthermore, the present invention relates to a three-phase inverter comprising an intermediate circuit, a DC / AC bridge and a control unit, wherein the control unit is designed to control half bridges of the DC / AC bridge in order to convert an input DC voltage of a DC input stage into an output AC voltage via the intermediate circuit and the DC / AC bridge in normal operation.

[0002] A typical inverter converts an input DC voltage into an output AC voltage and thus connects a DC voltage source applied to an input via a DC voltage input stage and a DC / AC bridge at the output to an AC voltage network, e.g., an n-phase power grid. In this way, an n-phase output AC voltage can be fed into n mains voltages of the power grid. The DC / AC bridge is usually formed by two half-bridges per phase of the power grid, with each half-bridge comprising two power switches, e.g., IGBTs or MOSFETs. A first half-bridge per phase is used to provide the positive half-waves of the AC voltage, and a second half-bridge is used to provide the negative half-waves.An intermediate circuit consisting of intermediate circuit capacitors is typically provided between the DC input stage and the DC / AC bridge. A photovoltaic system in generator mode, for example, can serve as the DC voltage source. A filter can also be provided in the inverter on the output side, i.e., upstream of the AC grid. Switching elements, such as relays, and / or additional filters, such as an EMC filter, can also be provided between the inverter and the AC grid.

[0003] In normal operation, the inverter is designed to transfer energy from a DC voltage source at the input to the output and thus feed it into an AC voltage grid. However, before the inverter begins normal operation, the DC link capacitors installed in the DC link must be pre-charged to a bias voltage. If the inverter were to be connected directly to the power grid at the output without a pre-charged DC link, the DC link capacitors would charge from the output side via the parasitic diodes of the power switches in the half-bridges of the DC / AC bridge. Since the DC link represents a very low-impedance load when discharged, the resulting currents can be so high that the components of the inverter, in particular the power switches, could be damaged.The pre-charging of the intermediate circuit capacitors to the bias voltage must therefore be carried out before the power switches of the DC / AC bridge are connected to the power supply network in normal operation.

[0004] Known solutions for precharging the DC link capacitors involve using the energy available at the DC voltage input stage. This energy can be made available, for example, by appropriately designing the components of the DC voltage source connected to the DC voltage input stage. For example, photovoltaic cells are connected in series to achieve a sufficiently high DC input voltage, which is then applied as the DC link voltage to the DC link capacitors and precharges them. However, particularly with photovoltaic cells, the problem can arise that no or insufficient DC input voltage is generated, which makes precharging impossible.

[0005] If the available input DC voltage is not sufficiently high, it can be increased using boost converters additionally attached to the inverter in order to generate a sufficiently high intermediate circuit voltage. DE 10 2010 060 633 A1 discloses precharging the intermediate circuit of an inverter by coupling it to the DC voltage input side, wherein the intermediate circuit capacitors are precharged to a high value in a first step without additional circuitry. The DC voltage input side is then switched off and the voltage drops to a value that roughly corresponds to the desired intermediate circuit voltage. The intermediate circuit voltage is set to the desired value in a subsequent step by operating the inverter in boost converter mode. This makes it possible to achieve a sufficient intermediate circuit voltage without providing an additional inverter.The disadvantage of this method, however, is that it only works if a DC input voltage is applied to the input during the initial step, which requires sunlight. Thus, reliable pre-charging is only possible in sunshine. Furthermore, the DC input voltage must be sufficient to approximately reach the desired intermediate circuit voltage, as the inverter's semiconductor switches could otherwise be damaged again if the intermediate circuit voltage is too low at the beginning of boost converter operation due to the insufficient impedance and the associated high current flows.

[0006] External power storage devices, such as batteries, can also be used to precharge the DC link capacitors, especially when no DC voltage sources are available, for example, when inverters are used to couple AC grids for reactive power compensation. However, using external power storage devices to charge the DC link capacitors carries the risk that precharging is not possible, as the respective power storage devices may be completely discharged or, for example, in standby mode. This also makes reliable precharging impossible. Furthermore, an additional power storage device naturally entails additional effort and costs.

[0007] US 2005 / 231172 A1 describes the use of series resistors to charge the intermediate circuit, with capacitors also being connected. EP 3 098 953 A2 describes a precharging of an intermediate circuit, with capacitors and a current limiting unit being provided.

[0008] It is an object of the present invention to enable reliable charging of the intermediate circuit capacitors of an inverter.

[0009] This object is achieved according to the invention in that, in pre-charging mode, the intermediate circuit voltage is pre-charged via output-side clock filters and mains filters, which form a current-limiting capacitive voltage divider, via a power supply network connected to the output. The object is also achieved by a capacitive circuit, preferably a capacitive voltage divider, via which the intermediate circuit can be connected in pre-charging mode to a power supply network connected to the output in order to pre-charge an intermediate circuit voltage of the intermediate circuit. Thus, according to the invention, the energy required for pre-charging can be obtained from the power supply network, and there is no dependency on an input-side or additionally provided DC voltage source. An external circuit with suitable capacitors can serve as the capacitive circuit, for example.The capacitive circuit serves as a current-limiting series resistor and can, for example, connect the n phases of the power supply network that are connected to the output of the inverter to the intermediate circuit.

[0010] Output-side clock filters and line filters serve as capacitive circuits. Clock filters and line filters typically comprise clock filter capacitors and line filter capacitors connected in a star configuration between the phases, forming a current-limiting capacitive voltage divider through which the intermediate circuit capacitors are charged via a charging curve.

[0011] Without current limitation, as mentioned at the beginning, components, especially circuit breakers, could be damaged or destroyed when connecting the power supply network to the DC / AC bridge because the DC link capacitors are initially insufficiently charged. By using the clock filters and mains filters that are already present, the DC link capacitors are charged directly via the power supply network, i.e. without additional, external components or series resistors. This eliminates the need for additional hardware, which also reduces the overall cost of the inverter and can subsequently increase its service life, as fewer installed electronic components also means a lower probability of failure. Clock filters and / or mains filters can of course also be not part of the inverter and instead be formed by additional elements.Of course, despite using the clock filters and mains filters as capacitive circuits, further circuitry can also be used, e.g. to expand the capacitive circuit.

[0012] Advantageously, the intermediate circuit voltage is precharged via the output-side clock filters and mains filters via the power supply network to a threshold voltage lower than the bias voltage and then half bridges of the DC / AC bridge are clocked by the control unit in accordance with a boost converter in order to further increase the intermediate circuit voltage via the power supply network until the specified bias voltage is reached.

[0013] By operating the DC / AC bridge as a boost converter, the pre-charging of the intermediate circuit capacitor can be controlled via the existing control unit, thus avoiding additional hardware expenditure.

[0014] The threshold voltage can advantageously correspond to a value just below half the peak voltage of the power grid and can be adjusted by dimensioning the clock filter and line filter. The threshold voltage can usually not quite reach half the peak voltage, since a voltage drop occurs due to pre-charging via the capacitive voltage divider, even after a longer charging time. Advantageously, the intermediate circuit voltage is first pre-charged via the output-side clock filters and line filters via one phase of the power grid, and the intermediate circuit voltage is further increased in boost converter mode via the output-side clock filters and line filters via one phase of the power grid, whereby particularly advantageously the same phase is used in each case.

[0015] The half-bridges of the DC / AC bridge can also be clocked by the control unit like a boost converter to precharge the intermediate circuit voltage to the specified bias voltage via the power grid. This eliminates the need for a preliminary step involving precharging to a threshold voltage, and boost converter operation can begin immediately. This is possible because the capacitive circuit connecting the DC / AC bridge to the power grid has a current-limiting effect. Without the capacitive circuit or another type of current limiting, boost converter operation with uncharged intermediate circuit capacitors would lead to component damage.

[0016] In addition, the object is achieved according to the invention by an inverter comprising an intermediate circuit, a DC / AC bridge and a control unit, wherein the control unit is designed to control half bridges of the DC / AC bridge in order to convert an input DC voltage of a DC input stage into an output AC voltage via the intermediate circuit and the DC / AC bridge in normal operation, wherein the inverter is operated in a pre-charging mode according to the method according to the invention before activation of the normal operation.

[0017] The present invention is described below with reference to the Figuren 1 bis 10 which show exemplary, schematic and non-limiting advantageous embodiments of the invention. Fig.1 a schematically illustrated inverter, Fig.2 an inverter with two DC link capacitors in normal operation, Fig.3 the inverter in pre-charging mode, Fig.4a an effective circuit for an upper half-wave in the first step, Fig.4b an effective circuit for a lower half-wave in the first step, Fig.5a an effective circuit for an upper half-wave in boost converter operation, Fig.5b an effective circuit for a lower half-wave in boost converter operation, Fig.6 an inverter with an intermediate circuit capacitor in normal operation, Fig.7 the inverter in pre-charging mode, Fig.8a an effective circuit for an upper half-wave in the first step, Fig.8b an effective circuit for a lower half-wave in the first step, Fig.9a the effective circuit for an upper half-wave in boost converter operation, Fig.9b the effective circuit for a lower half-wave in boost converter operation, Fig.10 the course of an intermediate circuit voltage in pre-charging mode.

[0018] In Fig. 1 A schematic inverter 1 is shown, which connects a DC input stage 20 via a DC / AC bridge 3 to a power supply network 4. In the DC input stage 20, a capacitive intermediate circuit Z is provided upstream of the DC / AC bridge 3. The power supply network 4 has n phases, here n=3 phases L1, L2, L3, as well as a neutral conductor N (in Fig.1 not shown). The DC voltage input stage 20 is connected via an input switch Se to a DC voltage source 2, for example a photovoltaic system, and has a first pole A and a second pole B. The first pole A and the second pole B are also connected to the intermediate circuit Z. The intermediate circuit voltage Uz is present at the intermediate circuit Z, ie between the first pole A and the second pole B.

[0019] The DC / AC bridge 3 comprises an upper half-bridge HB1+, HB2+, HB3+ and a corresponding lower half-bridge HB1-, HB2-, HB3- per phase L1, L2, L3. For n=3 phases, three upper half-bridges HB1+, HB2+, HB3+ and three lower half-bridges HB1-, HB2-, HB3- are provided, in Fig. 1 only indicated. The half-bridges HB1+, HB2+, HB3+, HB1-, HB2-, HB3- are controlled in normal operation by a control circuit 5 such that an input DC voltage Ue applied to the DC voltage input stage 20 is converted via the intermediate circuit and the DC / AC bridge 3 into an output AC voltage uL1, uL2, uL3 per phase L1, L2, L3. The output AC voltages uL1, uL2, uL3 are then fed into the mains voltages U1, U2, U3 of the power supply network 4 in normal operation. According to the invention, however, before activating normal operation, a pre-charging operation is carried out, in which the intermediate circuit voltage Uz (which corresponds to the input voltage Ue in normal operation) of the intermediate circuit is pre-charged to a predetermined bias voltage Uv via a capacitive circuit C via the power supply network 4, as shown in Fig. 1 is indicated schematically by the dashed arrow.

[0020] In Fig. 2 As a first exemplary embodiment, a first possible circuit arrangement of the inverter 1 is shown in more detail. The intermediate circuit Z of the DC voltage input stage 20 comprises an upper intermediate circuit capacitor C+ and a lower intermediate circuit capacitor C- connected in series. The first pole A and the second pole B connect the series connection of the two intermediate circuit capacitors C+, C-, with an intermediate circuit center point M located between the upper intermediate circuit capacitor C+ and the lower intermediate circuit capacitor C-. The upper intermediate circuit capacitor C+ and the lower intermediate circuit capacitor C- thus form the intermediate circuit Z, although of course further serial and / or parallel capacitors can also be provided in the intermediate circuit.The first pole A is connected to the second pole B via the upper half-bridge HB1+, HB2+, HB3+ and the corresponding lower half-bridge HB1-, HB2-, HB3- connected in series, whereby the intermediate circuit voltage Uz is applied to the series connection of the upper half-bridges HB1+, HB2+, HB3+ and the corresponding lower half-bridges HB1-, HB2-, HB3- of each phase n. The first, second, and third center points M1, M2, and M3 are located between the upper half-bridges HB1+, HB2+, HB3+ and the corresponding lower half-bridges HB1-, HB2-, HB3-.

[0021] In the first exemplary embodiment shown here, the upper half-bridges HB1+, HB2+, and HB3+ each comprise an upper power switch S11+, S21+, and S31+ and a lower power switch S12+, S22+, and S32+ connected in series, with a first upper center point M1+, a second upper center point M2+, and a third upper center point M3+ located between the upper power switches S11+, S21+, and S31+ and the associated lower power switches S12+, S22+, and S32+, respectively. Freewheeling diodes D are arranged in the upper half-bridges HB1+, HB2+, and HB3+ in parallel with the upper power switches S11+, S21+, and S31+ and the lower power switches S12+, S22+, and S32+, respectively, and are polarized to be permeable in the direction of the first pole A. The intermediate circuit center point M is also connected to the upper centers M1+, M2+, M3+ via upper diodes D1+, D2+, D3+, which are polarized in a permeable manner towards the upper centers M1+, M2+, M3+.

[0022] In the first exemplary embodiment shown here, the lower half-bridges HB1-, HB2-, HB3- comprise, in an analogous manner, an upper power switch S11-, S21-, S31- and a lower power switch S12-, S22-, S32-, each connected in series, with a first lower center point M1-, a second lower center point M2-, and a third lower center point M3- being located between the upper power switches S11-, S21-, S31- and the associated lower power switches S12-, S22-, S32-. Freewheeling diodes D are arranged in parallel with the upper power switches S11-, S21-, S31- and the lower power switches S12-, S22-, S32- and are polarized in a permeable manner towards the associated first, second, or third center point M1, M2, M3, or towards the first pole A.The lower center points M1-, M2-, M3- are connected to the intermediate circuit center point M via lower diodes D1-, D2-, D3-, whereby the lower diodes D1-, D2-, D3- are polarized to be conductive towards the intermediate circuit center point M. The upper diodes D1+, D2+, D3+ and lower diodes D1-, D2-, D3- are used in normal operation of the inverter 1 shown in the first embodiment and are therefore already present in the inverter. At least the upper diodes D1+, D2+, D3+ and lower diodes D1-, D2-, D3-, which belong to phase L1, L2, L3, via which the inverter 1 is connected to the power grid 4 in pre-charging mode, can thus also be used during operation of the inverter 1 as a boost converter.

[0023] The power supply network comprises a number n of phases L1, L2, L3, each having a phase-shifted mains voltage U1, U2, U3 (e.g. 230 volts) with a mains frequency f (e.g. 50 Hz). The output AC voltage uL1, uL2, uL3 is of course synchronized with the mains voltage U1, U2, U3 in order to enable feeding into the power supply network 4. The first phase L1 of the power supply network 4 is preferably connected to the first center point M1 via a first inductance X1 (choke). Analogously, the second phase L2 of the power supply network 4 is preferably connected to the second center point M2 via a second inductance X2, and the third phase L3 of the power supply network 4 is preferably connected to the third center point M3 via a third inductance X3. The n=3 phases L1, L2, L3 are also connected to one another via a clock filter TF.The clock filter TF comprises a star connection of at least three clock filter capacitors CF1, CF2, CF3, with the star point of the clock filter being connected to the neutral conductor N of the power supply network. Furthermore, the n=3 phases L1, L2, L3 are connected to one another via a line filter NF (EMC filter), which, similar to the clock filter TF, in turn consists of a star connection of at least three line filter capacitors C41, C42, C43, with the star point being connected to the neutral conductor N of the power supply network 4. The clock filter TF and line filter NF do not have to be part of the inverter 1 and can also be configured externally. In the present embodiment, the clock filters TF and line filter NF are used as capacitive circuits C for precharging the intermediate circuit voltage Uz to the bias voltage Uv.Alternatively or additionally, a different / further capacitive circuit C can of course be provided to create a capacitive series resistor for current limitation during the pre-charging of the intermediate circuit capacitors C+, C-.

[0024] Inverter 2 can be disconnected from and connected to the supply network 4 via the first, second, and third phase filter switches SF1, SF2, SF3 provided in phases L1, L2, and L3 between the clock filter TF and the mains filter NF, as well as a neutral conductor filter switch SFN provided in the neutral conductor L between the clock filter TF and the mains filter NF. If the phase filter switches SF1, SF2, SF3 and the neutral conductor filter switch SFN are open, the DC / AC bridge 3 and thus the inverter are disconnected from the power supply network 4.

[0025] Furthermore, a first, second, and third phase switch S41, S42, S43, as well as a neutral conductor switch S4N, are provided between the NF mains filter and the power supply network 4, via which the NF mains filter can be disconnected from or connected to the power supply network 4. If the phase switches S41, S42, S43, and the neutral conductor switch S4N are open, the clock filter TF and thus also the DC / AC bridge 3 are also disconnected from the power supply network 4.

[0026] The upper power switches S11+, S21+, S31+ and lower power switches S12+, S22+, S32+ of the upper half-bridges HB1+, HB2+, HB3+, as well as the upper power switches S11-, S21-, S31- and lower power switches S12-, S22-, S32- of the lower half-bridges HB1-, HB2-, HB3- can further be controlled via a control circuit 5, which is only indicated in the figures for reasons of clarity.

[0027] Since inverter 1 is in Fig. 2 is in normal operation, with the input switch Se closed, the DC voltage source 2 acts as a generator at the DC voltage input stage 20 and generates an input DC voltage Ue between the first pole A and the second pole B, whereby the input DC voltage Ue corresponds to the intermediate circuit voltage Uz. The phase filter switches SF1, SF2, SF3, or the neutral conductor filter switch SFN, the phase switches S41, S42, S43, or neutral conductor switch S4N are closed, whereby the DC / AC bridge 3 is connected to the power supply network 4. An input DC voltage Ue corresponds to the intermediate circuit voltage Uz and is present between the first pole A and the second pole B. The control circuit 5 switches the upper half-bridges HB1+, HB2+, HB3+ in such a way that positive half-waves are generated at the first, second and third center points M1, M2, M3.The control circuit 5 switches the lower half-bridges HB1-, HB2-, HB3- in a similar manner such that negative half-waves are generated at the first, second, and third midpoints M1, M2, and M3, respectively. The upper half-bridges HB1+, HB2+, HB3+ and the corresponding lower half-bridges HB1-, HB2-, HB3- are alternately switched. This creates a phase-shifted rectangular alternating voltage at the first, second, and third midpoints M1, M2, and M3, which is smoothed via the inductors X1, X2, and X3 and then fed into the corresponding phases L1, L2, and L3 of the power supply network 4. These positive and negative half-waves of the generated voltages must, of course, be synchronized by the control circuit 5 to the half-waves of the respectively connected phases L1, L2, and L3 in order to enable feeding into the power supply network.The DC / AC bridge 3 thus generates square-wave voltages at the first, second, and third center points M1, M2, and M3, respectively. By filtering these square-wave voltages via clock filters TF and line filters NF, or via the inductors X1, X2, and X3, sinusoidal output AC voltages uL1, uL2, and uL3 are generated, which are then fed into the line voltages U1, U2, and U3 of the power supply network 4. Preferably, the power switches S11+, S21+, S31+, S12+, S22+, S32+, S11-, S21+, S31-, S12-, S22-, and S32- of the DC / AC bridge 3 are clocked at a frequency higher than the line frequency of 50 Hz, for example, 20 kHz.

[0028] Since the operation of inverters 1 in normal operation is well known, it will not be discussed in detail here.

[0029] As is known, before normal operation of the inverter 1, the intermediate circuit capacitors C+, C- of the intermediate circuit must be precharged to a suitable intermediate circuit voltage Uz in a precharging mode. This is achieved according to the invention by precharging the intermediate circuit voltage Uz via the power supply network 4 to a bias voltage Uv, as shown in Fig. 3 is shown as an example.

[0030] This precharging operation can be carried out in two steps, whereby in a first step the intermediate circuit voltage Uz is precharged via the power supply network 4 to a threshold voltage Us, less than a bias voltage Uv, and then in a boost converter operation the power switches S11+, S21+, S31+ S12+, S22+, S32+, S11-, S21+, S31-, S12-, S22-, S32- of the inverter 1 are clocked according to a boost converter until the intermediate circuit voltage Uz reaches the specified bias voltage Uv. However, it is also possible to skip the first step and charge the intermediate circuit voltage to the bias voltage Uv purely in boost converter operation, without taking a threshold voltage Us into account beforehand, which can therefore also be regarded as a threshold voltage Us of zero.

[0031] During pre-charging operation, the DC voltage source 2 cannot be connected to the inverter 1, which results in Fig. 3 is symbolized by an open input switch Se. However, the DC voltage source 2 could also be connected to the inverter 1 via a closed input switch Se. If the input DC voltage Ue were higher than the bias voltage Uv, no precharging is necessary. If the input DC voltage Ue is lower, precharging according to the invention can be carried out, although of course less time is required for precharging than if the intermediate circuit voltage Uz had to be charged from zero to the bias voltage Uv.

[0032] The pre-charging operation can be activated by means of a switch position, as in Fig. 3 The neutral conductor switch S4N on the output side and one of the phase switches on the output side, in this case the third phase switch S43, are closed. The other phase switches, in this case the first phase switch S41 and the second phase switch S42, are opened. Furthermore, the front phase filter switches SF1, SF2, and SF3 located between the mains filter NF and the clock filter TF are closed (if present), although the neutral conductor filter switch SFN remains open. In this switch position, there can be no direct current flow via the parasitic diodes of the circuit breakers S11+, S21+, S31+ S12+, S22+, S32+, S11-, S21+, S31-, S12-, S22-, S32- and a capacitive voltage divider is created which is formed via the line filter capacitors C41, C42, C43 and the clock filter capacitors CF1, CF2.At the third center point M3, which is connected to the upper intermediate circuit capacitor C+ via the third inductor X3 and the diodes D of the third upper half-bridge HB3+, a sinusoidal voltage is present with a frequency corresponding to the mains frequency f. However, the magnitude of this sinusoidal voltage at the third center point M3 is reduced by the capacitive voltage divider and is also phase-shifted relative to the mains frequency.

[0033] To describe the capacitive voltage divider, the circuit that effectively results in the above-mentioned switch positions in the first step for positive half-waves of the mains voltage U3 of the selected phase L3 is Fig. 4a shown, the circuit for negative half-waves of the mains voltage in Fig. 4b . In the Fig. 4a and 4bThe open circuit breakers are not shown, but the parallel freewheeling diodes D are shown, in this case the freewheeling diodes of the third upper half-bridge HB3+ and the third lower half-bridge HB3-, since the respective semiconductor switches S31+, S32+ and S31-, S32- are open. It can be seen that the capacitive voltage divider divides the (here third) mains voltage U3, which is applied to the third mains filter capacitor C43, into a first partial voltage uT1 and a second partial voltage uT2. The first partial voltage uT1 is applied to the third clock filter capacitor CF3, the second partial voltage uT2 to a parallel connection of two branches. One of the branches is formed from a series connection of the first clock filter capacitor CF1 and the first mains filter capacitor C41 and the other branch from a series connection of the second clock filter capacitor FC1 and the second mains filter capacitor C42.The first partial voltage uT1 is thus applied in the positive half-wave via the third coil X3 and the freewheeling diodes D of the third upper half-bridge HB3+ to the upper intermediate circuit capacitor C+ (. Fig.4a ). In the negative half-wave, the first partial voltage uT1 is applied via the third coil X3 and the freewheeling diodes D of the third lower half-bridge HB3- to the lower intermediate circuit capacitor C- ( Fig.4b ). Of course, only one of the branches could be used for the capacitive voltage divider, which can be achieved by opening the first phase filter switch SF1 or the second phase filter switch SF2. However, the remaining first or second branch would then have a higher resistance, changing the capacitive voltage divider and increasing the second partial voltage uT2 and thus decreasing the first partial voltage uT1.

[0034] A continuous current flow is created toward the intermediate circuit capacitors C+, C-, with the clock filter capacitors CF1, CF2, and CF3 acting as current limiters. The resulting intermediate circuit voltage Uz depends on the voltage across the clock filter capacitors CF1, CF2, and CF3, which in turn depends on the capacitance of the clock filter capacitors CF1, CF2, and CF3.

[0035] This allows the intermediate circuit voltage Uz to be precharged up to a threshold voltage Us, which, due to the capacitive voltage divider, does not occur abruptly but according to a charging curve, as shown in Fig. 10 is shown.

[0036] The threshold voltage Us can correspond to a value just below half the peak voltage of the mains voltage U1, U2, U3 of the power supply network 4. For a power supply network 4 with a mains voltage U1, U2, U3 of 230 volts, the peak voltage is 325 V, which means that the threshold voltage Us, as half the peak voltage, is 162.5 V. Since the theoretically possible threshold voltage Us cannot usually be reached, e.g. due to losses, the threshold voltage Us should be selected to be somewhat lower than the maximum possible value, i.e. half the peak voltage, in order to ensure that the threshold voltage Us is reached and the boost converter operation can be reliably activated.

[0037] In order to avoid damage to the components, the intermediate circuit voltage Uz for an inverter 1 should usually be charged to a bias voltage Uv that corresponds to at least twice the peak voltage (here 650 V) before activating normal operation, which is done in boost converter mode.

[0038] If the first step described above is executed until the intermediate circuit voltage Uz reaches or exceeds a threshold voltage Us, the second step can be initiated. If the first step is skipped, boost converter operation can also be started immediately, as mentioned above.

[0039] In this boost converter operation, the inverter 1 can be connected to a phase L1, L2, L3 of the power supply network 4, whereby circuit breakers S11+, S21+, S31+ S12+, S22+, S32+, S11-, S21+, S31-, S12-, S22-, S32- of the inverter 1 are clocked according to a boost converter until the intermediate circuit voltage reaches the specified bias voltage. The voltage curve of a phase L1, L2, L3 is considered, and the power switches S11+, S21+, S31+ S12+, S22+, S32+, S11-, S21+, S31-, S12-, S22-, S32- of the half-bridge HB1+, HB2+, HB3+ HB1-, HB2-, HB3- corresponding to the considered phase L1, L2, L3 are clocked synchronously with the AC voltage uL1, uL2, uL3 on the selected phase L1, L2, L3 according to a boost converter, as shown in Fig. 5a and 5b indicated on the control unit 5. It is in Fig.5a the circuit that effectively results in the above-mentioned switch positions in boost converter operation for positive half-waves of the mains voltage, and in Fig. 5b the circuit for negative half-waves of the mains voltage.

[0040] In the illustrated embodiment, the voltage curve of the third phase L3 is considered, since this was already connected in the first step via the third phase switch S43. This means that the phase filter switches SF1, SF2, SF3, neutral conductor filter switch SFN, phase switches S41, S42, S43, and neutral conductor switch S4N remain in the same position as in the first step, i.e. the neutral conductor switch S4N and one of the output-side phase switches, here the third phase switch S43, and phase filter switches SF1, SF2, SF3 remain closed and the neutral conductor filter switch SFN as well as the first phase switch S41 and the second phase switch S42 remain open.

[0041] This allows the switch position to Fig. 3 be retained for the second step as well. If the first phase L1 were to be used in the second step, the first phase switch S41 would naturally have to be closed and the second phase switch S42, as well as the third phase switch S43, would have to be opened. If the second phase L2 were to be used in the second step, the second phase switch S42 would have to be closed and the first phase switch S41, as well as the third phase switch S43 would have to be opened. The power switches S31, S32+ of the upper third half-bridge HB3+ and the power switches S31-, S32- of the third lower half-bridge HB3- are clocked accordingly.

[0042] In the Figuren 5a and 5bOpen circuit breakers are not shown, but the parallel freewheeling diodes D are. Closed circuit breakers are also not shown, as are the parallel freewheeling diodes, as these are short-circuited by the closed circuit breakers. The circuit breakers shown are shown in Fig. 5a and Fig. 5b each clocked with a PWM.

[0043] The clocking process begins during a voltage zero crossing of the selected phase, in this case the third phase L3. In the positive half-wave of the third phase voltage UL3 on the third phase L3, the lower semiconductor switch S32+ of the third upper half-bridge HB3+ is switched on (in Fig. 5a therefore not shown), accordingly the lower semiconductor switch S32- and the upper semiconductor switch S31- of the third lower half-bridge HB3- are switched off (in Fig. 5a therefore only the parallel freewheeling diode D is shown) and the upper semiconductor switch S31+ of the upper half-bridge HB3+ is clocked by the control unit 5 with a PWM signal PWM with a certain pulse-pause ratio, whereby the clock frequency of the PWM signal PWM is, for example, 20 kHz. The frequency of the signal resulting from the PWM signal can be derived from the current phase voltage of the corresponding phase of the power supply network. However, the upper semiconductor switch S31- of the third lower half-bridge HB3- could also not be switched off, but clocked inversely to the upper semiconductor switch S31+ of the upper half-bridge HB3+.

[0044] In the negative half-wave of the third phase voltage UL3, the lower semiconductor switch S32+ and the upper semiconductor switch S31+ of the third upper half-bridge HB3+ are switched off (in Fig. 5b therefore only the parallel freewheeling diode D is shown), the lower semiconductor switch S32- of the lower third half-bridge HB3- is switched on (in Fig. 5b (therefore not shown) and the upper semiconductor switch S31- of the lower third half-bridge HB3- are also clocked at high frequency by the control unit 5 with a PWM signal PWM with a pulse-pause ratio, whereby the frequency can in turn be derived from the current value of the associated third phase voltage U3. The upper semiconductor switch S31+ of the third upper half-bridge HB3+ does not have to be switched off, but can also be clocked inversely to the lower semiconductor switch S31- of the upper half-bridge HB3+.

[0045] The power switches S31+ S31- are clocked synchronously with the sinusoidal voltage applied to the third center point M3, whereby a square wave voltage is generated at the third center point M3. The current flow into the intermediate circuit can be regulated via the duty cycle of the PWM, whereby the duty cycle can be derived from the amplitude of the voltage at the third center point M3, with a suitable scaling factor for the amplitude being selected. This boost converter operation creates a self-stabilizing control loop. It is necessary that the current flowing into the intermediate circuit is not higher than the current flowing through the capacitive voltage divider, otherwise the voltage at the third center point M3 would collapse. The duty cycle is therefore automatically reduced when the voltage at the third center point 3 decreases and increased when it increases. In control terms, the scaling factor corresponds to a P component and limits the maximum current.Due to the described switching pattern, the DC / AC bridge 3 behaves like a boost converter and energy is taken in a controlled manner from the supply network 4, or from the mains voltage U3 of the selected phase, here the third phase L3, and charged into the intermediate circuit capacitors C+, C-, which results in a further increase in the intermediate circuit voltage Uz.

[0046] The described method can of course not only be used in an inverter 1 with two intermediate circuit capacitors C+, C- and tapped center point M, as in the first embodiment shown above, but also in an analogous manner, for example, for an inverter 1 with only one intermediate circuit capacitor Cz in the intermediate circuit Z. Such an inverter 1 is shown here as a second embodiment as a B6 bridge inverter, where Fig. 6 normal operation and Fig. 7 shows the precharging operation. The intermediate circuit Z can, of course, also have several intermediate circuit capacitors Cz, but no center point M is tapped.

[0047] As in the first exemplary embodiment, the first pole A is connected to the second pole B via the upper half-bridge HB1+, HB2+, HB3+ and the associated lower half-bridge HB1-, HB2-, HB3- connected in series, whereby the intermediate circuit voltage Uz is applied to the series connection of the upper half-bridges HB1+, HB2+, HB3+ and the associated lower half-bridges HB1-, HB2-, HB3- of each phase n. The first, second and third midpoints M1, M2, M3 are also located between the upper half-bridges HB1+, HB2+, HB3+ and the associated lower half-bridges HB1-, HB2-, HB3-. In the second exemplary embodiment, inverter 1, the upper half-bridges HB1+, HB2+, HB3+ each comprise only one power switch S1+, S2+, S3+ with parallel freewheeling diodes D, which are polarized to be permeable in the direction of the first pole A. There are therefore no lower circuit breakers S12+, S22+, S32+ connected in series and therefore no upper center points M1+, M2+, M3+.

[0048] Since the neutral conductor is not connected to any center point M and there are no upper center points M1+, M2+, M3+, there are no upper diodes D1+, D2+, D3+ and lower diodes D1-, D2-, D3-.

[0049] The lower half-bridges HB1-, HB2-, HB3- comprise, in a similar manner, a power switch S1-, S2-, S3- with freewheeling diodes D arranged in parallel, which are polarized to conduct toward the corresponding first, second, and third center points M1, M2, M3, respectively. There are also no lower center points M1-, M2-, M3- and no lower diodes D1-, D2-, D3-.

[0050] In normal operation after Fig. 6 the input switch Se is closed. The DC voltage source 2 generates an input DC voltage Ue between the first pole A and the second pole B, whereby the input DC voltage Ue corresponds to the intermediate circuit voltage Uz. The phase filter switches SF1, SF2, SF3, or the neutral conductor filter switch SFN, the phase switches S41, S42, S43, or neutral conductor switch S4N are closed, whereby the DC / AC bridge 3 is connected to the power supply network 4. An input DC voltage Ue corresponds to the intermediate circuit voltage Uz in normal operation and is present between the first pole A and the second pole B. The control circuit 5 switches the upper half-bridges HB1+, HB2+, HB3+ in such a way that positive half-waves are generated at the first, second and third center points M1, M2, M3.The control circuit 5 switches the lower half-bridges HB1-, HB2-, HB3- in a similar manner, such that negative half-waves are generated at the first, second, and third midpoints M1, M2, and M3, respectively. In this case, the upper half-bridges HB1+, HB2+, HB3+ and the corresponding lower half-bridges HB1-, HB2-, HB3- are switched alternately. Operation in normal mode is therefore fundamentally the same as in the first embodiment.

[0051] The precharging of the intermediate circuit capacitor Cz to a bias voltage Uv is carried out in the same basic way as in the first embodiment in precharging mode, which can again be carried out in two steps. In the first step, the intermediate circuit voltage Uz is precharged via the power supply network 4 to a threshold voltage Us, less than the bias voltage Uv, and then in boost converter mode the (here only six) power switches S1+, S2+, S3+, S1-, S2-, S3- of the inverter 1 are clocked like a boost converter until the intermediate circuit voltage Uz reaches the specified bias voltage Uv. However, it is also possible to skip the first step and charge the intermediate circuit voltage to the bias voltage Uv purely in boost converter mode, without taking a threshold voltage Us into account beforehand.

[0052] During pre-charging operation, the DC voltage source 2 can be connected to the inverter as in the first embodiment, or it can be separated, as in Fig. 7 symbolized by an open input switch Se.

[0053] The pre-charging operation of the second embodiment can be carried out with the same position of the phase filter switches SF1, SF2, SF3, or the neutral wire filter switch SFN and the phase switches S41, S42, S43, or the neutral wire switch S4N, as in the first embodiment to form a capacitive voltage divider.

[0054] The capacitive voltage divider is obtained for positive half-waves of the mains voltage as in Fig. 8a and for negative half-waves as in Fig. 8b shown. Analogously to the first embodiment, the intermediate circuit voltage Uz can be precharged up to the threshold voltage Us.

[0055] If the first step is executed until the intermediate circuit voltage Uz reaches or exceeds a threshold voltage Us, the second step can be initiated. If the first step is skipped, boost converter operation can also begin immediately.

[0056] In this boost converter mode, the inverter 1 can be connected to a phase L1, L2, L3 of the power grid 4. However, in contrast to the first embodiment, the power switches S1-, S2+, S3+ of all upper half-bridges HB1+, HB2+, HB3+ cycle synchronously with the grid voltage of the selected phase, i.e., here the third grid voltage U3 of the third phase L3, until the intermediate circuit voltage Uz reaches the specified bias voltage Uv. Fig. 9a and 9b, open circuit breakers are not shown, but the parallel freewheeling diodes D are shown. The circuit breakers shown are shown in Fig. 9a and Fig. b each clocked with a PWM.

[0057] During the upper half-wave, the power switches S1-, S2-, S3- of the lower half-bridges HB1-, HB2-, HB3- can be counter-clocked or opened against the power switches S1+, S2+, S3+ of all upper half-bridges HB1+, HB2+, HB3+ - the latter in Fig. 9a represented by the fact that only parallel freewheeling diodes D are shown. In the negative half-wave of the third phase voltage UL3, the semiconductor switches S1-, S2-, S3- of the lower half-bridges HB1-, HB2-, HB3- are clocked according to a PWM and the power switches S1+, S2+, S3+ of all upper half-bridges HB1+, HB2+, HB3+ are counter-clocked or opened against the power switches S1-, S2-, S3- of the lower half-bridges HB1-, HB2-, HB3- - the latter is represented in Fig. 9b by the fact that only parallel freewheeling diodes D are shown.

[0058] The switch position from Fig. 6 also retained for boost converter operation. If the first phase L1 were used in the second step, the first phase switch S41 would naturally have to be closed and the second phase switch S42, as well as the third phase switch S43, opened. If the second phase L2 were used in the second step, the second phase switch S42 would have to be closed and the first phase switch S41, as well as the third phase switch S43, opened.

[0059] For all embodiments, in boost converter mode, the DC / AC bridge 3 is clocked like a boost converter. Since the function of a boost converter is well known, this functionality will not be discussed in detail here. Thus, energy is taken in a controlled manner from the supply network 4, or from the mains voltage U3 of the selected phase, here the third phase L3, and charged into the intermediate circuit capacitors Cz, C+, C-, which results in a further increase in the intermediate circuit voltage Uz.

[0060] The applied intermediate circuit voltage Uz is compared with a predetermined bias voltage Uv. If the intermediate circuit voltage Uz reaches or exceeds the bias voltage Uv, the boost control cycle described above is terminated and the inverter 3 is connected to the power grid 4. This is done in the usual way by closing the phase filter switches SF1, SF2, SF3, the neutral filter switch SFN, the phase switches L41, L42, L43 and the neutral switch L4N, as shown in Fig. 2 or Fig. 6 Furthermore, at the start of normal operation, synchronization of the control unit 5 with the power supply network 4 can be carried out in the usual way, and then the conversion of the input DC voltage Ue provided by the DC voltage source 4 into the output AC voltage uL1, uL2, uL3 and the feeding into the power supply network 4 can begin.

[0061] Fig. 10shows the curve of the intermediate circuit voltage Uz, which is precharged in a first step up to the threshold voltage Us and then further charged in boost converter operation up to the bias voltage Uv.

[0062] The inverter 1 shown in the illustrated embodiment is designed for a power grid 4 with n=3 phases L1, L2, L3. Of course, power grids 4 with a different number n of phases can also be connected to an input DC voltage Ue via an inverter 1 according to the invention, and the method according to the invention can be applied.

Claims

1. Method for operating a three-phase inverter (1), comprising an intermediate circuit (Z), a DC / AC voltage bridge (3), and a control unit (5), wherein half bridges (HB1+, HB2+, HB3+, HB1-, HB2-, HB3-) of the DC / AC voltage bridge (3) are controlled by the control unit (5) to convert an input DC voltage (Ue) of a DC voltage input stage (20) via the intermediate circuit (Z) and the DC / AC voltage bridge (3) into an output AC voltage (uL1, uL2, uL3) applied at an output during normal operation mode, wherein the inverter (1) is switched to a precharge mode before the normal operation mode is activated, in which precharge mode an intermediate circuit voltage (Uz) of the intermediate circuit (Z) is precharged to a predefined bias voltage (Uv), characterized in that in the precharge mode one of the phase switches (S41, S42, S43) provided on the output side and a neutral conductor switch (S4N) provided on the output side are closed, wherein further phase switches (S41, S42, S43) on the output side are opened or remain open, in that at least two of the phase filter switches (SF1, SF2, SF3), which are provided in the phases (L1, L2, L3) between clock filters on the output side and mains filters, are closed and a neutral conductor filter switch (SFN) provided in the neutral conductor (N) between clock filter (TF) and mains filter (NF) remains open, and in that clock filters (TF) and mains filters (NF) form a current-limiting capacitive voltage divider, via which the intermediate circuit voltage (Uz) is precharged in the precharge mode via an energy supply network (4) connected to the output.

2. Method according to claim 1, characterized in that the intermediate circuit voltage (Uz) is precharged in a first step via the clock filters (TF) and mains filters (NF) on the output side via the energy supply network (4) to a threshold voltage (Us) of less than a predefined bias voltage (Uv), and in that subsequently, in a boost converter operation mode, half bridges (HB1+, HB2+, HB3+, HB1-, HB2-, HB3-) of the DC / AC voltage bridge (3) are clocked by the control unit (5) according to a boost converter, to further increase the intermediate circuit voltage (Uz) via the energy supply network (4), until the predefined bias voltage (Uv) is reached.

3. Method according to claim 2, characterized in that the intermediate circuit voltage (Uz) is precharged via the clock filters (TF) and mains filters (NF) on the output side via a phase (L1, L2, L3) of the energy supply network (4), and in that the intermediate circuit voltage (Uz) is further increased via the clock filters (TF) and mains filters (NF) on the output side via a phase (L1, L2, L3) of the energy supply network (4).

4. The method according to claim 3, characterized in that the intermediate circuit voltage (Uz) is precharged to the threshold voltage (Us) via the same phase (L1, L2, L3) and further increased to the bias voltage (Uv).

5. Method according to any of claims 2 to 4, characterized in that the threshold voltage (Us) corresponds to a value just below half a peak voltage of the mains voltage (U1, U2, U3) of the energy supply network (4).

6. Method according to claim 1, characterized in that in a boost converter operation mode, half bridges (HB1+, HB2+, HB3+, HB1-, HB2-, HB3-) of the DC / AC voltage bridge (3) are clocked by the control unit (5) according to a boost converter, to precharge the intermediate circuit voltage (Uz) via the energy supply network (4) up to the predefined bias voltage (Uv).

7. A circuit arrangement for a three-phase inverter (1), the circuit arrangement comprising an intermediate circuit (Z), a DC / AC voltage bridge (3), and a control unit (5), wherein the control unit (5) is configured to control half bridges (HB1+, HB2+, HB3+, HB1-, HB2-, HB3-) of the DC / AC voltage bridge (3) to convert an input DC voltage (Ue) of a DC voltage input stage (20) via the intermediate circuit (Z) and the DC / AC voltage bridge (3) into an output AC voltage (uL1, uL2, uL3) during normal operation, characterized in that the circuit arrangement comprises clock filters (TF) and mains filters (NF) on the output side, which are configurable as current-limiting capacitive voltage divider, via which the intermediate circuit (Z) is connectable to an energy supply network (4) in a precharge mode to precharge an intermediate circuit voltage (Uz) of the intermediate circuit (Z), wherein the power supply network (4) comprises n phases (L1, L2, L3) and a neutral conductor (N), wherein the circuit arrangement comprises phase switches (S41, S42, S43) and a neutral conductor switch (S4N) for disconnecting or connecting the main filter (NF) from or to the power supply network (4) between the main filters (NF) and the power supply network (4), wherein furthermore phase filter switches (SF1, SF2, SF3) are provided in the phases (L1, L2, L3) between the clock filters (TF) and main filters (NF) and a neutral conductor filter switch (SFN) is provided in the neutral conductor (N) between the clock filter (TF) and main filter (NF) for disconnecting or connecting the inverter (1) from or to the power supply network (4), and wherein the circuit arrangement is configured to close one of the phase switches (S41, S42, S43) and the neutral conductor switch (S4N) in precharge mode, and furthermore to close at least two of the phase filter switches (SF1, SF2, SF3) provided in the phases (L1, L2, L3) between the clock filters (TF) and line filters (NF) on the output side and to open or to keep open the neutral conductor filter switch (SFN) provided in the neutral conductor (N), in a way, that the clock filters (TF) and mains filters (NF) form the current-limiting capacitive voltage divider.