METHOD FOR CONTROLLING SHORT-CIRCUIT CURRENTS AND SEMICONDUCTOR CONTROL DEVICE FOR THIS PURPOSE

Description

[0001] The present invention relates to a device for controlling impulse short-circuit currents, i.e., adjusting them to a specific value or a complex situation by limiting and / or controlling the impulse short-circuit currents in power distribution networks ("semiconductor control device" or synonymously "semiconductor monitoring device") and its use.

[0002] The device according to the invention thus serves to ensure grid stability in power supply networks, preferably in those with feed-in points distributed over a small area, which is usually the case with medium voltage networks.

[0003] The present invention relates to a semiconductor shutdown device and its use. Furthermore, the present invention also relates to a device for generating and injecting defined short-circuit currents into the power grid, so that the grid can be started up, i.e., put into operation or kept in operation, even though it is in an unstable operating state ("semiconductor current limiting device"). Both aspects of the present invention (semiconductor current limiting device and semiconductor shutdown device) serve, individually or in combination, to ensure grid stability.

[0004] In contrast, WO 92 / 09943 A1 discloses a device for controlling surge short-circuit currents in power supply networks, which includes a control circuit for periodically generating an interruption signal in order to interrupt the current path for prescribed intervals and to control the current supplied to a load between a maximum current level and a minimum current level. This control thus takes place at prescribed periodic intervals, and not on an event-driven basis, i.e., upon the occurrence of a surge short-circuit current. Description

[0005] As more local (i.e., decentralized) power generators are connected to the electricity distribution networks, the need to suppress the contribution of these newly installed systems to peak short-circuit currents in the distribution network grows. In some cases, however, a more complex response than a simple shutdown is necessary. Therefore, it is advantageous for grid stability if a power grid that has entered an unstable operating state can be restarted (started, brought into operation) by injecting defined short-circuit currents from the feed-in points of the decentralized power generators (or from subordinate subnetworks, i.e., "from below") or, in the case of mere instability, stabilized again. The latter corresponds to the situation where the subordinate subnetwork or the (grid) feed-in point continues to operate during an instability (grid instability).

[0006] The definition of what constitutes (grid) instability, as well as its detection and elimination, is regulated in relevant standards and is familiar to experts. These standards also specify the current and voltage limits to be measured in order to identify a network fault, as well as the requirements for its elimination. Examples of such regulations are DIN EN 60909-0:2013-02 and VDE 0102:2013-02, which regulate the calculation and, implicitly, the measurement of short-circuit currents. Generally, the network operator specifies a permissible short-circuit current for the installation; if this current is exceeded, the installation must limit the current or disconnect it. VDE-AR-N 4105 specifies faults in the low-voltage range, and VDE-AR-N 4110 in the medium-voltage range, for which the installation must nevertheless remain connected to the grid for a certain period of time. State of the art

[0007] Particularly in densely populated medium-voltage networks, i.e., electricity distribution networks operating in the 1 kV to 50 kV range, the additional connection of asynchronous and especially synchronous generators for power generation is problematic because they exhibit a high peak short-circuit current. This also applies analogously at a higher level to electricity distribution networks connected to such medium-voltage networks, from which – due to the highly variable feed-in from decentralized renewable energy generators – peak currents can result in the higher-level power grid. A Leroy-Somer LSA 43.2 generator, typical for small combined heat and power plants (CHP units), has a maximum peak current of approximately 1 kA at a rated current of 115 A (see...). Fig. 1A , 1BAlthough the current drops to its rated value after 70 ms, network operators still require a shutdown within microseconds (i.e., already on the rising edge!) to protect against electrodynamic forces and prevent the 1 kA current from occurring in the first place. This applies particularly to highly meshed medium-voltage networks, such as those found in large cities. Detecting the current and shutting it down within a few milliseconds (ms), followed by reconnecting the running generator after the surge current has subsided, would solve the problem.

[0008] The following possibilities exist in the state of the art for solving such problems: Mechanical switches – these have high insulation capacity, low losses, and can be reset. However, they are too slow for this purpose, which is preventing surge currents in power distribution networks. Fuses – these cannot be reset and are also too slow. Is limiters (or Is circuits) – these devices trigger an explosive cap that quickly disconnects the generating unit from the grid. With complex control systems, these devices are selective enough to be used for this purpose, but they are very expensive (> €70,000) and cannot be reset. They must therefore be replaced after a single trip. "Selective" means that the complex control system of the Is limiter must detect in real time when a true surge short-circuit current is present and when, in the current case, it is merely a less critical grid instability (so-called...).This is a case of "flickering" due to otherwise non-critical mechanical switching processes. The Is limiter may only trip in the event of a genuine surge short-circuit current. Inverters – these have high losses and are also very expensive.

[0009] The semiconductor disconnect device disclosed here makes it possible to interrupt this surge short-circuit current more or less abruptly in the event of an exceedance. This is particularly advantageous for connections in the vicinity of underdeveloped medium-voltage networks that cannot accommodate any further short-circuit current.

[0010] With regard to future power grids, which will consist primarily of decentralized renewable energy generators (with limited capacity to provide short-circuit current), this approach will prove insufficient. Firstly, distance protection is based on defined overcurrents, and secondly, "low voltage ride-through" capability will become more important for a stable grid without large power plants. "Low voltage ride-through" refers to the – at least partial – tolerance of electrical generating units such as generators (or, more generally, feed-in units such as subordinate subnetworks relative to the respective higher-level grid) to short-term voltage dips: A generating / feed-in unit must not disconnect from the grid immediately during voltage dips, but must remain connected to the grid for a certain period and continue to feed in at least some power.Short-term voltage dips can occur, for example, as a result of grid faults such as short circuits, ground faults, or lightning strikes. The ability of distributed generation plants or subordinate subnetworks to perform a "low voltage ride-through" prevents a large-scale grid collapse caused by a domino effect of many smaller generation plants / subnetworks in the event of faults in the higher-level transmission grid. Methods and devices for ensuring distance protection are also known to those skilled in the art, for example, in the form of distance protection relays. The ability to feed overcurrent into the grid in a controlled manner is particularly beneficial during the transition phase of grid restructuring. This is especially true from the point at which large power plants can no longer supply enough electricity to largely ensure grid stability.In a completely new, decentralized network, the entire safety concept could be redesigned; however, in existing ("historically grown") networks, this possibility of a complete redesign of network safety does not exist. The present invention therefore also deals with the controlled provision of variably adjustable short-circuit currents into a low- or medium-voltage network.

[0011] Regarding the restart of power grids, there is currently no way to do this "from the bottom up," i.e., from individual grid connection points or converter stations in the subordinate grid (or the feed-in device). (A feed-in point is ultimately also a grid connection point, specifically one located at the edge of the grid, i.e., "peripheral.") In the current state of the art, a failed (partial) power grid can only be restarted from the higher-level authority (i.e., the main grid). This is disadvantageous for a rapid (potentially...(Automated) restart after network failure, as a higher-level authority is absolutely necessary to control the restart process, which must first receive and evaluate all "readiness messages" from the subordinate networks in order to then gradually reconnect these subordinate networks to the higher-level network. Task

[0012] The object of the present invention is to solve the problems existing in the prior art by providing a device for reliably detecting and limiting surge currents quickly and thereby protecting power distribution networks from surge currents. The device should also be cost-effective and reusable, i.e., restartable, so that no distinction needs to be made between genuine surge short-circuit currents and merely non-critical network instabilities resulting from harmless mechanical switching operations ("flicker").

[0013] The object of the present invention is not only to solve the problems existing in the prior art regarding the avoidance of surge short-circuit currents (as described above), but also to provide a means of restarting, i.e., starting / commissioning or stabilizing, higher-level power grids that are in a critical operating state or switched off from lower-level power grids by providing a device with which the higher-level grid can be commissioned or stabilized from the lower-level grid by injecting defined short-circuit currents from the lower-level grid into the higher-level grid and observing the behavior of the higher-level grid.Which network parameters (such as voltage, current flow, phase angle and the like) are required to monitor the behavior of the higher-level network, as well as the method of determining the required parameters, is known to the person skilled in the art from the prior art and from the relevant standards.

[0014] The overall task is therefore to control impulse short-circuit currents in power grids, i.e., to switch them off or limit them to a defined short-circuit current, and consists of the two sub-tasks "switching off impulse short-circuit currents" and "limiting / generating short-circuit currents in a defined manner", each of which already represents an inventive control of impulse short-circuit currents and thus brings about a technical improvement in grid stability. Solution to the task

[0015] This problem is solved according to the invention by the characterizing features of main claim 1. The dependent claims describe advantageous embodiments of the invention. In the course of describing the invention and the claims, range specifications always include all intermediate values ​​not explicitly mentioned and all conceivable sub-intervals.

[0016] The requirement of selectivity, which is mandatory for I s limiters, does not exist in the device according to the invention, because due to the reversibility of the switching process, the asynchronous or synchronous generator connected to the voltage network via the switching device according to the invention can, if advantageous, be switched on again in the next half-wave, either by the higher-level network control or, if necessary, by the internal self-control contained in the invention.

[0017] The solution according to the invention for achieving the required high switching speeds is preferably based on semiconductors; although it naturally also exhibits losses, similar to standard solutions known in the prior art, this is not disadvantageous overall, since the multiple reversibility of the switching process results in the device according to the invention, i.e., the switch, operating without wear. Here and in the following, the entire switching device according to the invention (synonym: "semiconductor switching device") is referred to as the "switch"; the actual switching semiconductor component, for example an IGBT or a MOSFET (metal-oxide-semiconductor field-effect transistor), is referred to as the "semiconductor switching element" to distinguish it, and the antiparallel arrangement of two such semiconductor switching elements is referred to as a "bidirectional semiconductor switch".The switching semiconductor components are those components of the device that have the ability to switch off currents.

[0018] The inventive design of the device with at least one inductive element (e.g., a coil) with defined inductance for generating and feeding defined short-circuit currents into the power grid is referred to within the scope of this disclosure as a "current limiter," since it increases grid stability by limiting and feeding the surge short-circuit current from the subordinate grid or from the injection point into the superior grid. This also corresponds to connecting an operating CHP unit or an operating sub-network to a superior grid that is not in a stable operating state. That is to say, the entire inventive device for controlling surge short-circuit currents comprises two basic embodiments: a) the entire shutdown device according to the invention (synonym: "semiconductor shutdown device", also called "switch" or "semiconductor shutdown device"), and b) the entire "current limiting device" according to the invention (synonym: "current limiter", or also called "semiconductor current limiting device"), which comprises the device according to paragraph a) and furthermore includes at least one inductive element (e.g. a coil) with defined inductance, at least one processor or an FPGA or a corresponding analog control circuit known to those skilled in the art, and optionally at least one further semiconductor switching element.

[0019] Both tasks, limiting a surge short-circuit current from a subnetwork or feed-in point for commissioning or stabilizing a higher-level network, and disconnecting a feed-in point or subnetwork, serve to increase network stability: the former preferably during the commissioning phase or in a critical operating phase of the higher-level network to establish network stability, the latter preferably to maintain the network stability of a higher-level network that is already operating stably.

[0020] These two aspects can be implemented independently, i.e., provided / used, as well as in combination. When implemented in combination, a control logic must be provided, which, according to the invention, can preferably be implemented locally or remotely. This logic adjusts the operating state of the device for controlling impulse short-circuit currents as follows, depending on the current operating state of the network: If the network is operating stably, the device switches to the mode for interrupting impulse short-circuit currents; if the network is out of service or in a critical operating state, the device switches to the mode for the defined generation and injection of short-circuit currents.

[0021] This task (the injection of defined short-circuit currents) is solved by an arrangement of bidirectional switches and inductors which—when connected downstream of a synchronous or asynchronous generator—can, through their control signal, set a short-circuit current or any other current to a desired value and maintain this current for a predetermined time. The maximum possible time is determined by the component selection and can, if necessary, be unlimited. The decisive factor here is primarily the design-related power dissipation of the components, or the design of the device's cooling system. If the cooling system is designed in such a way that the maximum component temperature is not exceeded, unlimited operation, i.e., the maintenance of the short-circuit current indefinitely, is possible. Those skilled in the art are aware of how to dimension / select the components, or...The cooling system must be designed to specify a certain period for maintaining the short-circuit current to be fed in, or to allow the defined short-circuit current to be fed in without time limit.

[0022] The device according to the invention for controlling impulse short-circuit currents in power supply networks thus comprises both (partial) devices individually or jointly.

[0023] In addition to the semiconductor switching elements preferably used according to the invention, the use of other non-mechanical switching elements, such as thyratrons, also falls within the scope of the invention. The term "non-mechanical switching elements" therefore includes, here and in the following, both semiconductor switching elements such as IGBTs and MOSFETs, as well as, for example, thyratrons or other non-semiconductor-based non-mechanical switching elements.

[0024] The "suppression" of intermittent short-circuit currents, as used here, means either preventing or reducing the intermittent short-circuit current. The device can be implemented in a power distribution network both with and without a neutral conductor.

[0025] The semiconductor switching elements connected in antiparallel to each other are so-called active semiconductor components such as transistors, IGBTs, MOSFETs, or diodes, whose switching states can be influenced by electronic control signals or the current flow itself, and they are located in the current paths of each phase of the AC power distribution network. When using IGBTs with an integrated freewheeling diode, the actual transistor and the diode are already arranged as required within the IGBT package. The use of IGBTs is therefore particularly preferred. However, the arrangement in question can also be realized by appropriately connecting at least two transistors without an integrated freewheeling diode and at least two separate diodes, whereby the diodes are, of course, also connected in antiparallel to each other, i.e.,are connected in opposite directions to each other, in parallel to the at least two transistors (see e.g. ). Fig. 2A , 2B The phrase "control of the antiparallel-connected semiconductor components" therefore always refers only to the control of the transistors, since only these can be controlled by a separate control signal. The limit value of the sum signal is freely chosen and predefined, depending on how quickly the switch-off should occur on the rising edge of the surge current. For example, a value of Umess-sum can be specified as the limit value, corresponding to x times the rated current (x > 1), such as two, three, four, five, six, seven, eight, nine, or ten times the rated current.

[0026] It should be noted that here and in the following, the term "shutdown" refers not only to the disconnection of the synchronous generator from the power grid, but also to the connection of at least one suitable load to absorb the current surge. In this sense, "shutdown" is also synonymous with "discharging the excess current." One or more suitable loads could, for example, be adequately dimensioned resistors, which then—in a manner known to those skilled in the art—dissipate the current surge. Fig. 9 The varistors shown as examples are connected in parallel.

[0027] The invention further comprises a disconnecting device having at least two semiconductor switching elements arranged antiparallel to each other in each phase of the power grid. The antiparallel or "interconnected" semiconductor switching elements are preferably IGBTs (" I insulated G ate B ipolar T transistors") to ensure that the current flows that occur can be safely blocked without excessively damaging the semiconductor switching elements in question. This ensures the desired restart capability of the invention, as the semiconductor switching elements can then perform two or more switching operations before they may need to be replaced due to safety / standard requirements. Fig. 2AFigure 1 shows a circuit diagram of such a component arrangement or connection according to the invention. As an alternative to selecting semiconductor switching elements that can reliably withstand the occurring current surges, at least largely without damage, it is also according to the invention to introduce several individually too weak, antiparallel-connected semiconductor switching elements in parallel into one or more current paths of the mains phase, so that each individual semiconductor switching element only has to withstand a portion of the total current surge. Fig. 2B Figure 1 shows an example of a corresponding circuit diagram with respect to one phase. The invention encompasses providing such a parallel arrangement of at least two semiconductor switching elements connected antiparallel to each other in the relevant current path in one or more phases of the power grid.

[0028] An antiparallel arrangement or connection of two semiconductor switching elements means, for example, that when using IGBTs, the two emitter terminals are connected to each other, and the collector terminal of one IGBT is connected to the relevant phase of the generator, and the collector terminal of the other IGBT is connected to the relevant phase of the load (power grid). The two IGBTs are controlled via their gate terminals.

[0029] Monitoring of the individual currents in the network phases, or, if applicable, in the individual current paths of the individual network phases, is carried out, for example, using current measuring transformers or by determining the voltage drop across the semiconductor switching elements. According to the invention, the current detection and the subsequent triggering (switching off, opening) of the switches, if necessary, is so rapid that the delay due to the time required for current detection and switching is significantly less than 1 µs. Preferably, the delay is a maximum of 600 ns, more preferably a maximum of 300 ns, and most preferably a maximum of 100 ns. This limits the short-circuit current delivered to the network to the rated current. No mechanical stresses occur. It is not necessary for the semiconductor switching elements (e.g., IGBTs or MOSFETs) to carry the short-circuit current, since they are already switched on the rising edge of the surge short-circuit current, i.e.,"opened" so that no more current flows.

[0030] False tripping, i.e., the suppression of current flow and / or the triggering of a complete shutdown without a critical current surge actually occurring, is unproblematic in contrast to I s limiters, since the switch operates without wear (no new detonator or replacement of the device is required), and can be switched back on (on) after checking the network status, or switches itself back on automatically.

[0031] The device thus comprises: At least one bidirectional semiconductor switch; at least one sub-device for current detection and evaluation, or one sub-device for current detection and another sub-device for current evaluation; at least one adjustable or fixed delay element, i.e., an adjustable or fixed time interval as a "reaction time" for the detection of a fault (impulse short-circuit current) on the one hand, and the response to it on the other. This delay element can be fixed, for example, by the design-related switching times of the electrical components used, so that the selection of the electrical components, in particular the semiconductor switching elements and the operational amplifiers with suitable response times, determines an unchanging reaction time. This is a hardware-based analog evaluation.An analog, inherently variable timing element can be made adjustable, for example, by using adjustable analog components such as adjustable capacitors, e.g., trimmer capacitors, variable capacitors in RC circuits, or adjustable inductors (coils) in RL circuits, and / or adjustable resistors, such as trimmer capacitors, in both RC and RL circuits. This delay element can also be made adjustable by incorporating a programmable microcontroller, for example, based on a [missing information]. F field P programmable G ate A array (FPGA) or a C complex P programmable L ogic DA device (CPLD) is used to extend the response time of the electronic components by sending appropriate control pulses. This extended response time can be either permanently programmed or adjusted depending on the current power grid conditions. The adjustability of this delay element, i.e., the response time of the semiconductor shutdown device, allows the device to be adapted to the specific power grid so that other grid disturbances, such as power line communications, are not misinterpreted. In contrast to hardware-based analog evaluation, this is a program-controlled digital evaluation. The adjustable time intervals are preferably in the microsecond range. At least one switching unit, i.e., a local control module ("self-control") for the shutdown device according to the invention, based, for example, on driver boards for the semiconductor switching elements and / or on freely programmable microprocessors and / or specially manufactured ASICs (application-specific integrated circuits). This enables the CHP unit connected via the device according to the invention to disconnect itself from the power distribution network if necessary. Optionally, at least one communication module for communication with at least one higher-level control system. If communication with a higher-level network control system is to be provided, a single-channel connection is required as a minimum requirement for this communication, with which at least one signal with two levels (high / low) can be specified by the higher-level control system to enable switching on and off by the higher-level control system.To expand functionality, it is advantageous if the communication module enables more detailed data exchange, including bidirectional (full-duplex) communication, for example in the form of a bus system such as I²C, CAN, or another bus system known to those skilled in the art.

[0032] The disconnecting device according to the invention (the "device") can be used in low-voltage, medium-voltage, and high-voltage networks operated with alternating current (multi-phase, preferably three-phase). It is preferably used in low- and medium-voltage networks in the voltage range of 230 V to 50 kV, and most preferably in low-voltage networks up to 690 V. The particularly preferred use in low-voltage networks results from the fact that network instabilities in low-voltage networks caused by the connection of combined heat and power plants (CHP units) have a particularly detrimental effect on densely meshed medium-voltage networks operated at approximately 10 kV, such as those found in large cities or densely populated rural areas. This also applies to the extension of the subject matter of the invention, namely its configuration as a current-limiting device.

[0033] In summary, the subject matter of the invention can be described as follows: The subject matter of the invention therefore comprises the following possibilities for obtaining (calculating) and evaluating the "sum signal" (hereinafter referred to as "evaluation variants"), which lead to the suppression of the surge short-circuit current when the "limit value" is exceeded: Evaluation variant 1: Determination and selection of the maximum value of the current (or the phase-specific individual measurement value Umess-L(x) corresponding to the current (with 1 ≤ x ≤ n)) in the n phases, for example by means of rectification in each phase, whereby the largest value is "passed through", i.e., forwarded and forms the sum signal, and comparison of this sum signal with the selected limit value; this variant corresponds to the embodiment according to Fig. 7Evaluation variant 2: Determination of the currents in the n phases (or the corresponding phase-specific individual measurements Umeasured-L(1) to Umeasured-L(n)) and comparison with the selected phase-specific limit values, which, as described above, are "summarized" under the term "limit value" or encompassed by it, whereby the sum signal in this evaluation variant results from the individual phase-specific comparisons with the phase-specific limit values. Evaluation variant 3: Determination of the currents in the n phases (or the corresponding phase-specific individual measurements Umeasured-L(1) to Umeasured-L(n)) and calculation of the sum signal by summing the phase-specific individual measurements and comparing this sum signal with the selected limit value. Evaluation variant 4: Calculation of the magnitudes of the currents in the n phases (orthe phase-specific individual measurements Umess-L(1) to Umess-L(n) corresponding to the currents and the use of these sign-independent values ​​instead of the signed actual current flows (or phase-specific individual measurements) according to the evaluation variants disclosed in the preceding bullet points.

[0034] All the evaluation methods mentioned have in common that they detect when the current flow becomes too high, i.e., when a surge short-circuit current occurs. The components required for implementing the various evaluation methods are essentially the same, but they are arranged differently in each case, which is familiar to those skilled in the art. For current measurement, these components include, for example, measuring resistors, measuring transformers, Hall effect sensors, internal component resistances, etc.; for evaluation, they include, for example, operational amplifiers, logic circuits, FPGAs, CPLDs, processors, etc.

[0035] The non-mechanical switching elements are so-called "active" or "controllable" semiconductor components such as thyratrons or semiconductor switching elements such as IGBTs and MOSFETs. According to the invention, the limit value of the sum signal Umess-sum mentioned in step c) is freely chosen depending on the requirements for grid stability; in particular, it is also within the scope of the invention and its equivalents to adjust, i.e., redefine, this limit value as required.

[0036] The subject matter of the invention further comprises a device characterized in that the device in each current path of each phase, comprising at least two non-mechanical switching elements, which are independently selected from the list comprising power transistors and thyratrons, and at least two diodes, wherein the non-mechanical switching elements and the diodes in each current path of each phase are connected antiparallel to each other; comprising a measuring device for measuring the current flow in each phase L1 to Ln of the supply line over time in order to obtain n phase-specific individual measured values ​​Umeas-L(1) to Umeas-L(n) proportional to the current flows, wherein this measuring device comprises current transformers and measuring resistors for measuring the current waveform; comprising a calculation device for calculating at least one sum signal Umeas-sum;an evaluation device which generates at least one control signal from the sum signal U mess-sum by comparison with the limit value for controlling the at least two non-mechanical switching elements per current path of each phase, wherein this evaluation device comprises at least one resistor, a reference voltage source and a comparator; a control which comprises at least one 1-bit error memory and at least one adjustable delay element.

[0037] The calculating device for calculating the sum signal U mess-sum can calculate this sum signal U mess-sum in different ways, namely by i) the determination and selection of the maximum value among the n phase-specific individual measurements Umeas-L(1) to Umeas-L(n) from the measuring device, wherein the computational device comprises components selected independently from the list including measuring resistors, measuring transformers, Hall probes, operational amplifiers, logic circuits, FPGAs, CPLDs, processors, and / or ii) the comparison of the n phase-specific individual measurements Umeas-L(1) to Umeas-L(n) from the measuring device with the respective corresponding phase-specific limit values, wherein the computational device comprises components selected independently from the list including measuring resistors, measuring transformers, Hall probes, operational amplifiers, logic circuits, FPGAs, CPLDs, processors, and / or iii) the rectification of the individual measurements Umeas-L(1) to Umeas-L(n) from the measuring device, wherein the computational device for the rectification of individual measurements includes resistors,The subordinate sub-device TB comprises diodes and operational amplifiers as well as a subordinate sub-device for combining the rectified individual measured values ​​U mess-L(1)-gleich to U mess-L(n)-gleich into a sum signal U mess-sum, which is proportional to the total current flow in the feed line, wherein this subordinate sub-device TB for combining the rectified individual measured values ​​comprises at least one diode in each input line of a rectified individual measured value U mess-L(1)-gleich to U mess-L(n)-gleich for decoupling the individual rectified individual measured values ​​from each other.and / or iv) the formation of the magnitudes |U mess-L(1) | to |U mess-L(n) | of the individual measured values ​​U mess-L(1) to U mess-L(n) from the measuring device and the use of these sign-independent values ​​|U mess-L(1) | to |U mess-L(n) | instead of the signed real individual measured values ​​U mess-L(1) to U mess-L(n) from the measuring device in all embodiments i) or ii) or iii) of this computational device, wherein this computational device comprises components selected independently from the list comprising measuring resistors, measuring transformers, Hall probes, operational amplifiers, logic circuits, FPGA, CPLD, processors, ,

[0038] An example of each of the aforementioned sub-devices can be found in the illustrations. Figs. 5 to 7 be extracted, namely: for the first sub-device, i.e. the measuring device, by way of example on Fig. 5Reference is made, for the second sub-device, i.e. the calculation device, by way of example to Fig. 6 Reference is made, for the third sub-device, i.e., the sub-device TB of the calculation device according to embodiment variant iii), by way of example to the left half of Fig. 7 referred to, and for the fourth sub-device, i.e. the evaluation device, by way of example to the right half of Fig. 7 referred.

[0039] The control system consists, for example, of so-called control boards for the respective non-mechanical control element or suitable, possibly programmable, microprocessors or computers or industrial controllers such as PLCs, SPSSs, or similar devices known to those skilled in the art. The adjustable delay element is determined—in a manner known to those skilled in the art—by selecting the components for the device according to the invention based on the operating parameters, in particular the switching times of the components, or—also in a manner known to those skilled in the art—by suitable programming of corresponding programmable components, such as those already mentioned above by way of example, although not exhaustively.

[0040] The subject matter of the invention further comprises a device for carrying out the method as described above, and which is characterized in that the device additionally has a safety device as a precautionary measure, wherein the person skilled in the art knows what type and strength of safety device is suitable and how it is to be installed in the circuit.

[0041] The subject matter of the invention further includes the use of a device as described above in a medium-voltage power network or in a low-voltage power network for suppressing impulse short-circuit currents during the start-up phase of at least one synchronous generator connected to the medium-voltage or low-voltage power network.

[0042] In addition to the embodiment of the subject matter of the invention as a semiconductor shutdown device described above, the subject matter of the invention in the embodiment as a semiconductor current limiting device has, among other things, the following features described below, whereby the previously described method and application variants of the semiconductor shutdown device also apply to the invention in the embodiment as a semiconductor current limiting device, i.e. both embodiments of the subject matter of the invention - semiconductor shutdown device and semiconductor current limiting device - can be combined with each other.

[0043] In its general, basic form, the subject matter of the invention comprises, as a device, at least one device for controlling impulse short-circuit currents in power supply networks, characterized in that the device in each current path of each phase, comprising at least two non-mechanical switching elements, which are independently selected from the list comprising power transistors and thyratrons, and at least two diodes, wherein the non-mechanical switching elements and the diodes in each current path of each phase are connected antiparallel to each other; comprising a measuring device for measuring the current flow in each phase L1 to Ln of the supply line over time in order to obtain n phase-specific individual measured values ​​Umeas-L(1) to Umeas-L(n) proportional to the current flows, wherein this measuring device comprises current transformers and measuring resistors for measuring the current waveform; comprising a calculation device for calculating at least one sum signal Umeas-sum;an evaluation device which generates at least one control signal from the sum signal U mess-sum by comparison with the limit value for controlling the at least two non-mechanical switching elements per current path of each phase, wherein this evaluation device comprises at least one resistor, a reference voltage source and a comparator; a control which comprises at least one 1-bit error memory and at least one adjustable delay element.

[0044] The invention further comprises a device for controlling impulse short-circuit currents in power supply networks as described in the preceding paragraph, characterized in that the device further includes at least one processor or FPGA or analog control circuit, and at least one coil (30)with defined inductance in each phase line, wherein this has at least one coil (30) in each phase line between the bidirectional semiconductor switch ( 10, 10' ) and is located on the external network.

[0045] The invention further comprises a device for controlling surge short-circuit currents in power supply networks as described in the preceding paragraph, characterized in that the device further comprises at least one additional bidirectional semiconductor switch. (40, 40' ) has a conductor that is located either between each pair of phases or between each pair of phases and the neutral conductor, and wherein the semiconductor switching elements forming this at least one additional bidirectional semiconductor switch are semiconductor switching elements selected from the list comprising IGBTs, MOSFETs, thyratrons.

[0046] The invention further comprises a device for controlling surge short-circuit currents in power supply networks as described above, characterized in that the device further comprises at least one additional bidirectional semiconductor switch. (40, 40') exhibits a free-running path to another phase or to the neutral conductor. Examples of implementation

[0047] The following section describes, by way of example, the calculations for the construction of a variant for a three-phase 20 kVA AC network. The contacting, housing, and connection of the device for carrying out the method are performed according to methods and selection criteria known in the prior art, without departing from the scope of the invention or its equivalents. Suitable contacting methods include, for example, welding, bonding, soldering, clamping, or screwing. This also applies analogously to the design of the device as a current-limiting device.

[0048] Furthermore, the results of experiments carried out in a high-voltage laboratory using various embodiments of the invention are presented. Short-circuit test for the exemplary experimental determination of a short-circuit current

[0049] A 3.8 kVA generator is loaded with its rated current using high-power resistive loads. In this operating condition, an all-phase short circuit is induced, and the resulting current waveforms are recorded using LEM converters and displayed graphically by a Tektronix TDS2002B digital storage oscilloscope (see figure). Fig. 3). Fig. 4 This shows an example of a recorded and analyzed oscillogram. The depicted curves represent the highest short-circuit current I determined in several runs. k The peak that occurred has the read and marked value of 8 • I name This ratio of I is never exceeded. k / I name used as the maximum value for all subsequent example calculations. Selection and dimensioning of power semiconductors (IGBTs, diodes)

[0050] For example, a three-phase 20 kVA three-phase network with a 120° phase shift (line-up factor √3) yields the following values ​​for power P (Eq. 1) and rated current I. name (Eq. 2): P = √ 3 * U * I I nenn = P √ 3 * U = 20000 VA √ 3 * 400 V ≈ 28 , 87 A

[0051] Taking into account the short-circuit current determined as described above, which is approximately eight times the rated current, the minimum required short-term current-carrying capacity of the semiconductor components to be used (e.g., IGBTs or MOSFETs) according to Eq. 3 in the present example is: I k max = 8 * I nenn = 8 * 28 , 87 A = 230 , 96 A

[0052] Taking these considerations into account, a person skilled in the art can select suitable semiconductor components from the datasheets available for all commercially available semiconductor components (e.g., IGBTs or MOSFETs) that can be used to construct the device according to the invention. This applies analogously to the semiconductor switching elements and, in a corresponding manner, to the other semiconductor components and other electronic components to be used for the device in its various embodiments.

[0053] According to the invention, the semiconductor switching elements are used in unswitched forward operation. The following characteristics, for example, are relevant, although this list is not intended to be restrictive: V CES [V] Maximum permissible collector-emitter voltage IC [A] Maximum permissible continuous collector current I CRM [A] Maximum permissible time-limited collector current T vjmax [°C] Maximum permissible semiconductor core temperature V CE(sat)max [V] Collector-emitter voltage drop at full conduction R th(jc) [°C / (kW)] Thermal resistance semiconductor core - IGBT package R th(ch) [°C / (kW)] Thermal resistance IGBT package - heat sink

[0054] Table 1 lists two commercially available semiconductor switching elements (IGBTs) with their corresponding characteristic data that can be used for the device according to the invention. The selection criteria mentioned for the power semiconductors also apply analogously and by way of example to the embodiment of the subject matter of the invention as a semiconductor current limiting device. Table 1: Semiconductor switching elements that can be used by example according to the invention Manufacturer Semikron ®< Fujielectric ®< IGBT model SKM300GA12E4 1MBI200HH-120L50 V CES 1200 V 1200 V IC / I CRM 300 A / 900 A 200 A / 400 A *)< V CE(at)max 2,45 V 4,15 V T vjmax 175 °C 150 °C R th(jc) 0.11 °C / W 0.067 °C / W *)< each at 80 °C

[0055] The power loss per semiconductor switching element (IGBT) at rated machine load is calculated using formula GI. 4: P Vnenn = I nenn * V CEsat max

[0056] For the present embodiment with a 20 kVA machine (28.87 A), the power loss is therefore 70.73 W for the aforementioned Semikron IGBT (hereinafter abbreviated / indexed as "Semi") and 119.81 W for the Fujielectric IGBT (hereinafter abbreviated / indexed as "Fuji"). It is readily apparent to those skilled in the art that a high value for VCEsat(max) results in a high power loss that must be dissipated as heat, so semiconductor switching elements with a low value for VCE(sat)max are particularly preferred. In this example, the power loss is 0.6% of the generator's rated power per IGBT. Since at least two antiparallel IGBTs are required per phase, the total power loss in this example of a three-phase grid connection is approximately 3.6% of the generator's rated power.

[0057] For the selection of a suitable IGBT, the consideration of operating temperatures under different operating conditions is also relevant, which is carried out as follows (the thermal resistance R th is abbreviated here and subsequently, if necessary, also as "Ww"): First, the expected ambient conditions, operating and tripping parameters are defined or determined: Ambient temperature: 55 °C Passive cooling via heat sink: 0.5 K / W Use of thermal paste: 0.007 K / W The triggering (shutdown) should reliably occur upon reaching the threshold value of (2.5 to 3) * In; this is in accordance with Fig. 4 This occurs after 1 ms. The relevant values ​​for R th(jc) in the respective "triggering case", i.e., the time / current flow at which the network disconnection is to take place, are taken from the characteristic curve of the transient thermal resistance in the datasheet of the semiconductor device: ∘ R th j − c IGBT 1 ms = 0 , 01 ° C / W Semi bzw . 0,0052 ° C / W Fuji ∘ R th j − c IGBT 9 ms = 0 , 035 ° C / W Semi bzw . 0,2 ° C / W Fuji

[0058] The actual calculation of the thermal resistance is carried out according to formula Eq. 5. Gesamt Ww = Ww IGBT + Ww Leitpaste + Ww Kühlkörper R thges = R th j − c + R thL + R thK = R th j − c + 0 , 007 K / W + 0 , 5 K / W mit R thges Semi = 0 , 617 K / W und R thges Fuji = 0 , 574 K / W .

[0059] The operating temperatures in the individual operating phases of the exemplary selected IGBTs are therefore as follows: T Chip Semi = 0 , 617 K / W * 70,73 W + 55 ° C = 98 , 64 ° C T Chip Semi = 0 , 01 K / W * 70 , 73 W * 3 + 98 , 64 ° C = 100 , 76 ° C T Chip Semi = 0 , 035 K / W * 70 , 73 W * 8 + 98 , 64 ° C = 118 , 44 ° C T Chip Fuji = 0 , 574 K / W * 119 , 81 W + 55 ° C = 123 , 77 ° C T Chip Fuji = 0 , 0052 K / W * 119 , 81 W * 3 + 123 , 77 ° C = 125 , 64 ° C T Chip Fuji = 0 , 02 K / W * 119 , 81 W * 8 + 123 , 77 ° C = 142 , 94 ° C

[0060] The relevant values ​​are compared again in Table 2. Table 2: Example operating temperatures Operating state Semikron Fujielectric 20 kVA nominal (normal operation) 98,64 °C 123,77 °C 20 kVA after shutdown (3x nominal I for 1 ms) 100,76 °C 125,64 °C 20 kVA "worst case" (8x nominal I for 9 ms) 118,44 °C 142,94 °C

[0061] A person skilled in the art can readily recognize from the calculated operating temperatures in Table 2 that while the use of the Fujielectric® IGBT is possible without departing from the scope of the invention or its equivalents, it is less advantageous than the use of the Semikron® IGBT due to the high operating temperatures. Furthermore, the low thermal resistance of the Fuji IGBT is insufficient to dissipate the heat generated in the component quickly enough. In the worst-case scenario, exceeding the maximum permissible junction temperature Tvjmax – which is 150 °C for this type – cannot be ruled out with sufficient certainty. If this temperature is exceeded, thermal destruction of the IGBT, or at least damage to it, is unavoidable.

[0062] In the embodiment of the invention as a semiconductor current-limiting device, at least one coil (i.e., an "inductor") is required, as well as a processor or an FPGA or a corresponding analog controller, which is used to trigger the current limiting, i.e., to inject the defined surge short-circuit current. Optionally, at least one conventional switch may also be provided. The calculation and selection methods required to select the necessary components according to the invention are known to those skilled in the art. The parameters required for this can be easily obtained by those skilled in the art from the respective component datasheets. Monitoring of operating currents, overcurrent detection / limit setting

[0063] The limit values ​​for operating currents, operating voltages, phase parameters and other characteristic values ​​required for the operation of a power distribution network, as well as the definitions of overcurrents, undervoltages and overvoltages, fault situations, operating states, etc., which must be observed in principle, are known to the expert and can be taken from the relevant standards in their respective valid form, for example DIN EN 60909-0:2013-02, VDE 0102:2013-02, VDE-AR-N 4105 and VDE-AR-N 4110.

[0064] Within the limits prescribed in the relevant standards, the person skilled in the art is permitted to select and use more suitable values, limit values, calculation methods, switching times and other parameters according to the invention in order to increase network security.

[0065] The methods for network monitoring, i.e., the detection of fault situations / operational disturbances, which can be used according to the invention in order to subsequently carry out switching / controlling / regulating processes according to the invention, are also known to the person skilled in the art, for example from the relevant standards.

[0066] The tripping threshold, or tripping range, must be flexibly defined based on two objectives. Firstly, short, non-critical load peaks, such as those occurring during connection or at the start of grid feed-in, must not trigger a shutdown. Secondly, the maximum current actually flowing in the event of a fault, i.e., during a short-circuit current surge, should be minimized. The compromise chosen here as an example involves tripping values ​​in the range of two and a half to three times the generator's rated current.

[0067] The in Fig. 5The illustrated measurement setup demonstrates a basic setup for real-time current measurement. Those skilled in the art are aware of other current monitoring devices that can be used without departing from the scope of the invention or its equivalents. In the exemplary measurement setup described, the line currents, i.e., the phase currents in phases L1, L2, and L3, are measured on the primary side by means of current transformers (e.g., current measuring transformers) T1, T2, and T3. It is also within the scope of the invention to use measuring resistors instead of current measuring transformers and to measure the voltage drop across them, or to use the internal resistance of one or more semiconductor switching elements as a measuring resistor and to measure the voltage drop across it. Those skilled in the art are aware of suitable electronic circuit arrangements for this purpose that can be used according to the invention.On the secondary side, the transducers are short-circuited via three identical resistors (Rmess), which are themselves connected in a star configuration. Those skilled in the art are familiar with the use of so-called "star connections" and their advantageous application. The primary current flowing through the transducers induces a secondary current in the transducers, which has a fixed turns ratio to the primary current and flows through the measuring resistors.

[0068] It is known to those skilled in the art that, in principle, only the phase in which the critical current surge was detected needs to be disconnected to protect the power grid from the surge short-circuit current. However, for the sake of a simpler device design, it is preferred to disconnect all phases, and possibly also the neutral conductor, when a surge short-circuit current is detected in one phase. Nevertheless, disconnecting only the phase in which the surge short-circuit current was detected is also within the scope of the invention. Consequently, monitoring the neutral conductor current and disconnecting the phases when a surge short-circuit current is detected in the neutral conductor is also within the scope of the invention.

[0069] The voltage drops (Umess) occurring across the resistors are recorded and fed to an evaluation circuit, which, for the sake of clarity, is arranged in Fig. 5Not shown. Numerous evaluation circuits and measuring devices are known to those skilled in the art that can be used without departing from the scope of the invention or its equivalents. The measuring resistors used should ideally have the same values ​​to avoid measurement distortions between the individual conductors. If the measuring resistors have different values, this can be taken into account mathematically by appropriate correction factors and, if necessary, calibration. The values ​​of the resulting measured voltages are directly proportional to the respective resistance values ​​and can be calculated using Ohm's law.

[0070] Since the three measured values ​​recorded in this way (one current measurement per phase) are alternating quantities, but IGBTs are digitally controlled in switching applications, it is preferable to rectify the measured values.

[0071] When a standard silicon diode is operated in forward bias, a voltage drop of approximately 0.6 to 0.7 V, known as the "threshold voltage," occurs across it. This threshold voltage must be significantly exceeded by the measured values ​​during nominal system operation to ensure proper circuit function. If relatively small resistance values ​​(Rmeasured) on the order of a few milliohms are used, the measured values ​​(Umeasured) exhibit relatively low voltage levels, complicating the evaluation. This inevitably leads to further problems, as complete rectification—especially in the 0 to 0.7 V range—is not guaranteed. Therefore, using standard silicon diodes would necessitate modifications to the entire circuit to ensure reliable current measurement.It is therefore readily apparent to a person skilled in the art that the use of commercially available standard diodes, while falling within the scope of the invention and its equivalents, does not represent a preferred embodiment.

[0072] This problem is preferably addressed through circuit design. The three measured values ​​Umeasured-L1, Umeasured-L2, and Umeasured-L3 are rectified using "active rectifiers." The core of these active rectifiers consists of op-amps (so-called "operational amplifiers") which have no threshold voltages. In this way, complete rectification is possible from 0 V. A further advantage of this design is the resulting flexibility: Firstly, the rectified measured values ​​can be raised or lowered to any voltage level within the op-amp's operating voltage range. Secondly, no power is drawn during measurement – ​​in direct comparison to implementations using silicon diodes – since op-amps are active components with a separate power supply. This minimizes measurement distortions.

[0073] In Fig. 6The preferred active rectification process, including the input and output variables of U mess-L1, is illustrated as an example (circuit diagram in the upper half, storage oscilloscope recording in the lower half). A 50 Hz sine wave with a peak amplitude of 1 V was chosen as the example input. The drawn guideline (horizontal line at 0.0 V) demonstrates that rectification occurs even at 0 V, completely without any threshold voltage. The increased voltage level of the output variable compared to the input variable is also evident. The voltage gain factor Gu used is calculated as follows: GU = R 18 / R 14 + R 17 = 56 kΩ / 10 kΩ + 10 kΩ = 2 , 8

[0074] This means that, in the present example, the rectified measured values ​​of up to 1 V are amplified to 2.8 V (2.8 * 1 V peak = 2.8 V peak). Preferably, circuits constructed and dimensioned exactly the same as in Fig. 6As shown by way of example for phase L1, rectifiers are also to be provided for the rectification of Umeas-L2 and Umeas-L3. The use of exactly identical rectifiers for the individual measuring voltages Umeas-L1, Umeas-L2, and Umeas-L3 is particularly preferred. However, other embodiments falling within the scope of the invention and its equivalents also have different rectifiers and thus make it possible to monitor the individual phases independently of one another with different sensitivities.

[0075] The rectified measured values ​​– preferably obtained identically as described above – are processed as described in Fig. 7 The described signals are combined and decoupled from each other using diodes. The resulting sum signal Umess-sum, which exhibits a voltage waveform analogous to the output voltage of a B6 bridge circuit as generally known to those skilled in the art, is fed to a comparator (e.g., component "LT1721"). Fig. 7) is supplied. A comparator compares two input quantities and makes a digital case distinction. If the input voltage is smaller than the comparison quantity ( Fig. 7 (1.5 V reference voltage source V7), the output level is approximately 0 V. If the input voltage exceeds the reference voltage, the output level assumes the operating or supply voltage level of the comparator. It is known to those skilled in the art that corresponding components exist which exhibit the opposite switching behavior and can, of course, be used in the same way without departing from the scope of the invention or its equivalents, or that in analog circuits it is technically simpler to implement a defined start state in the form of a so-called "active-low level" (see, e.g., Fig. 10 ).

[0076] There are therefore three ways to influence the trigger threshold, i.e., the generation of the shutdown pulse: The larger the selected resistance value of Rmess, the larger the Umess value will also be. The larger the ratio R18 / (R14+R17), the higher the rectified voltage (Umess-L1-equal, Umess-L2-equal, and Umess-L3-equal). The higher the comparator reference voltage, the later it switches to a high output level.

[0077] Fig. 8The operating principle is illustrated by an example simulation of an overload of L1. The voltage waveforms of Umess-L1, Umess-L2, and Umess-L3, the rectified sum signal Umess-sum at the comparator input, and the voltage waveform at the comparator output (V[out]) are shown. The reference voltage used at the comparator is 7.5 V. It is clearly visible that Umess-L1 exhibits the highest amplitude due to the overload. After rectification and signal aggregation, slight overshoots occur where the reference voltage is exceeded at specific points. With each overshoot, the comparator output (V(out)) waveform... Fig. 8) a high level, which means that the overload or short circuit is detected and a shutdown pulse is generated (V(out) at a high level). This pulse or pulse train is used to control or "reset" one or more so-called IGBT driver boards – which handle the actual IGBT control. By controlling or "resetting" the driver boards, all connected IGBTs are disabled, i.e., current flow on all collector-emitter paths in the IGBTs is interrupted, which ultimately means the electrical isolation of the line between the generator (e.g., generator) and the consumer (e.g., power distribution network). This achieves safe decoupling of the system (e.g., generator) from the grid. Known driver boards from the prior art are used for this purpose, without thereby departing from the scope of the invention and its equivalents. For example, the members of the "SKHI 10 / 12 (R)" model family..."of the manufacturer Semikron ®< called.

[0078] The shutdown device according to the invention must either store a detected network fault (i.e., a surge short-circuit current that led to the shutdown) and remain switched off in order to be subsequently switched back on by a higher-level network control system; in this case, the device must have at least a 1-bit fault memory, which is reset by the higher-level network control system when the device is switched back on. Alternatively, the device according to the invention comprises an internal control module (synonymous with controller) and has hardware- and / or software-implemented switching-on conditions, upon fulfillment of which the device itself can perform / initiate the switching back on of the synchronous generator, wherein in this embodiment a fault memory with a storage capacity of at least 2 bits is preferably used.

[0079] According to the invention, IGBTs are used as switches and "conducted" to achieve the "ON" switching state. Those skilled in the art know how IGBTs or other non-mechanical switching elements must be controlled to allow current flow. As a result of the conduction, the collector-emitter path becomes conductive, whereby the collector potential must be higher than that of the emitter. Since the currents to be switched are alternating currents, the use of two IGBTs per phase conductor is essential. Both emitter terminals are connected together (antiparallel arrangement / connection), and the current paths are determined automatically by the freewheeling diode typically integrated internally. Fig. 9 An example circuit diagram is shown. Is the one in Fig. 9When the left IGBT is switched on, the current flows through the freewheeling diode from the right IGBT and vice versa. Thus, both current paths for the positive and negative sine wave are clearly defined. Since both collectors are in Fig. 9 Since the components are located externally and the circuit design is symmetrical, the installation direction with respect to the generator and load sides is irrelevant. It is also within the scope of the invention and its equivalents to use semiconductor switching elements that do not have an integrated freewheeling diode and instead provide a separate external diode, which is configured accordingly. Fig. 9 is interconnected.

[0080] To further increase operational reliability with regard to any voltage spikes that may occur, varistors are provided in parallel to the collector-emitter path of each IGBT in some embodiments of the invention (see Figure 1). Fig. 9For example, if the maximum permissible collector-emitter voltage (VCES) is 1200 V, the varistor used should have a rating approximately equal to this value. A suitable type would be, for example, the Z80M112 from manufacturer CKE®. The rated breakdown voltage of this type is 1100 V ± 10%. Thus, the maximum voltage before breakdown is 1210 V.

[0081] Applying the selection criteria described above, the following specific experimental embodiments of the device according to the invention were implemented. The following experimental setups represent generator-grid connections in a low-voltage network using disconnect devices according to the invention. Example 1:

[0082] Test parameters: Low-voltage 3-phase network AEG laboratory generator (3 kW rated power, 4 A rated current, 32 A short-circuit current) Load: Short-circuit switch Triggering of the impulse short-circuit current via custom-built device Non-mechanical switching elements: Semikron IGBT, type SKM300GA12E4 Current measurement: Stangesness current measuring transformer Example 2:

[0083] Test parameters: Low-voltage 3-phase network AEG laboratory generator (30 kW rated power, 40 A rated current, 300 A short-circuit current) Load: Short-circuit switch Triggering of the impulse short-circuit current via custom-built device Non-mechanical switching elements: Semikron IGBT, type SKM300GA12E4 Current measurement: Stangesness current measuring transformer

[0084] The experimental data (e.g. currents, voltages, times, switching states) were recorded using a storage oscilloscope in all experiments / examples.

[0085] Fig. 10This shows the current and voltage waveforms recorded during the experiment, as well as the generated switching signals. The extremely short response time and the exceptionally fast shutdown are clearly evident. In the present case, in Fig. 10 In the example shown (Example 2), the results achieved were as follows: The time between exceeding the current limit, i.e., the occurrence of the surge short-circuit current, and tripping, i.e., disconnecting the generator from the grid, is approximately 700 ns. The current drops below 100 mA within 1 µs and is completely switched off after approximately 30 µs.

[0086] The embodiment of the subject matter of the invention as a device for ensuring grid stability in power supply networks by limiting a surge short-circuit current provides for the following embodiment possibilities, which are illustrated below by way of example with reference to the figures. Fig. 11A-C will be described in more detail.

[0087] It is known to those skilled in the art that when creating electronic circuit diagrams with appropriate software (e.g., "EAGLE" - "Easy Applicable Graphical Layout Editor"), the designation of the component pins is at least partially freely selectable, so that the numbering of pins generated by the software (e.g., emitter, collector, gate in the case of transistors) can have different numbers in different drawings. This does not apply to reference numerals according to relevant patent laws / regulations; in these cases, the same reference numerals in different drawings (each in conjunction with curved arrows) always denote the same technical feature.

[0088] Fig. 11AFigure 1 shows, using the example of a three-phase power grid, a first exemplary embodiment of the subject matter of the invention for feeding a defined short-circuit current into a power grid (phases L1 to L3, where the suffix "ext" denotes the external grid side, i.e., the higher-level power grid into which the current is fed). The reference numerals 10 and 10' The two semiconductor switching elements connected antiparallel to each other in one phase of the power grid are designated as such, in this example including an integrated freewheeling diode (not shown). This embodiment also features a varistor connected in parallel to the respective semiconductor switching elements in each phase. (20) on, as well as the additional inductance (coil) with the reference sign 30,which, even in this simplest version, makes it possible to limit and / or control the generation of surge short-circuit currents. For the sake of clarity, the processor or FPGA, or the corresponding analog controller required to trigger the current limiting, i.e., the injection of the defined surge short-circuit current, is not shown; the necessary control signal lines are connected to the terminals of the semiconductor switching elements marked "2" here. The basic operating principle is that the generation of the magnetic field in the inductor (coil) located in the phase line causes the current to be drawn. 30) A "buffer storage" is created for the fed-in electricity, from which power is drawn when disconnected from the grid, i.e., when the semiconductor switching elements are opened. 10, 10'and the energy "flowing out" from the collapsing magnetic field, initiated by the resulting collapse of the magnetic field, is fed into the power grid as a defined short-circuit current with decreasing intensity over time. This means that the disconnection from the grid in the event of a surge short-circuit current does not occur abruptly, but rather asymptotically, whereby the disconnected generator or the disconnected subnetwork can, if necessary, be reconnected to the higher-level grid even during the falling edge of the defined short-circuit current. Corresponding software algorithms or analogous control circuits with which this can be achieved according to the invention are known to those skilled in the art and are described in the following for the sake of clarity. Fig. 11A , 11B and 11C not shown.

[0089] Fig. 11BFigure 1 also shows, using the example of a three-phase power grid, a second exemplary embodiment of the subject matter of the invention for feeding a defined short-circuit current into a power grid (phases L1 to L3, where the suffix "ext" again denotes the external grid side, i.e., the higher-level power grid into which the current is fed). The reference numerals 10 and 10' Here too, the two semiconductor switching elements connected antiparallel to each other in one phase of the power grid are designated, in this example also with an integrated freewheeling diode (not shown). This embodiment also features the additional inductance (coil). 30 which makes it possible to limit and / or control impulse short-circuit currents, but does not require any in the phases to the respective semiconductor switching elements 10, 10'parallel-connected varistors, because in this embodiment the excess current is not absorbed by consumers (e.g. varistors), but by means of appropriate control of the additional pairwise antiparallel connected semiconductor switching elements. 40, 40' The current is diverted into one of the two other phases that still has capacity to absorb the current flow. This requires the control of the semiconductor switching elements connected between the phases. 40, 40'This is also carried out according to the invention in a manner known from the prior art by a processor or FPGA or a corresponding analog controller, wherein the signal lines are again connected to the terminals of the semiconductor switching elements marked "2". For the sake of clarity, the processor or FPGA or the corresponding analog controller, which is also required for triggering the current limiting and diverting the surge short-circuit current to another phase, i.e., injecting the defined surge short-circuit current, is not shown.

[0090] Fig. 11C Figure 1 also shows, using the example of a three-phase power grid, a third exemplary embodiment of the subject matter of the invention for feeding a defined short-circuit current into a power grid (phases L1 to L3, where the suffix "ext" again denotes the external grid side, i.e., the higher-level power grid into which the current is fed). The reference numerals 10and 10' Here too, the two semiconductor switching elements connected antiparallel to each other in one phase of the power grid are designated, in this example also with an integrated freewheeling diode (not shown). This embodiment also features the additional inductance (coil). 30 which makes it possible to limit and / or control impulse short-circuit currents, but does not require any in the phases to the respective semiconductor switching elements 10, 10' parallel-connected varistors, because in this embodiment the excess current is not absorbed by consumers (e.g. varistors), but by means of appropriate control of the additional pairwise antiparallel connected semiconductor switching elements. 40, 40'The current is diverted to the neutral conductor ("N"), which naturally still has capacity to absorb the current flow. This requires the control of the semiconductor switching elements connected between the phases and the neutral conductor. 40, 40' This is also carried out according to the invention in a manner known from the prior art by a processor or FPGA or a corresponding analog controller, wherein the signal lines are again connected to the terminals of the semiconductor switching elements marked "2". For the sake of clarity, the processor or FPGA or the corresponding analog controller required for triggering the current limiting and diverting the surge short-circuit current to the neutral conductor is not shown. Figure captions

[0091] Fig. 1A: Exemplary short-circuit current waveform of the Leroy-Somer synchronous machine (rated current approx. 115 A) during a short circuit near the generator (3-phase short-circuit curves, no-load at rated speed (star connection Y)). Fig. 1B: Exemplary time course of the current (50 Hz) during a short circuit near the generator ("worst case"). Fig. 2A: Circuit diagram (example) of an arrangement of two semiconductor switching elements, such as IGBTs (N / Nb = neutral conductor, ground conductor; the component symbols and terminal designations used are known to those skilled in the art).2B: Circuit diagram (example) of an arrangement of two semiconductor switching elements, such as IGBTs, connected antiparallel to each other in separate current paths (in the example: three) of a phase of a power grid, such that the components in each of the m current paths only have to withstand 1 / m of the total power (in the example one third, i.e. m = 3). Fig. 3: Exemplary schematic measurement setup for determining impulse short-circuit currents. The switch Q1, as the short-circuit initiating medium, has to carry all occurring currents in this test setup and must therefore be dimensioned accordingly. Fig. 4: Oscillogram of an evaluated short-circuit test (example). Fig. 5: Schematic measurement setup for current monitoring (example). Fig. 6: Exemplary circuit setup of an active rectifier and exemplary oscilloscope evaluation.Fig. 7: Exemplary circuit setup for overload evaluation / shutdown pulse generation from the sum signal of Umeasured-L1, Umeasured-L2, and Umeasured-L3. Fig. 8: Exemplary simulation of comparator signal ("V[out]") and further voltage waveforms in the event of tripping, i.e., when the selected limit value of Umeasured-sum is reached or exceeded (here, for example, 7.5 V). Fig. 9: Circuit layout (example) of two IGBTs per phase conductor. Fig. 10: Exemplary oscilloscope image of the implementation of the method according to the invention (Example 2). The in . Fig. 10The points in time marked by the vertical dashed lines 1)*, 2)*, and 3)* are: 1)* = Exceeding the threshold for detecting the surge short-circuit current (the sharp bend in the rectified voltage (su) just above this point results from the display exceeding its range at this time), 2)* = Start of the initiation of the network disconnection (switch-off; the period between point 1)* and point 2)* corresponds to the delay element, which in this (analog) test setup results from the operating parameters, i.e., switching times, etc., of the selected components), 3)* = Achieving complete network disconnection. The measured times, voltages, and currents can be Fig. 10 The following scaling factors can be extracted, with the lower left corner of Fig. 5A measuring bar with a length of approximately 5 scale divisions (Skt.) is shown, which applies to both the horizontal time scale and the vertical measuring scales: U Marker reference (synonym for the reference voltage of the reference voltage source for the comparator): 2V / Skt. Umess L1 (synonym for U measure-L1): 5 V / Skt. U across IGBT junction (voltage drop across the two IGBTs): 200 V / Skt. Rectified voltage (synonym for U measure-sum): 1 V / Skt. Imess L1 (measured phase current in phase L1): 20 A / Skt. Imess L2 (measured phase current in phase L2): 20 A / Skt. Imess L3 (measured phase current in phase L3): 20 A / Skt. Marker output / IGBT control (synonym for comparator output V(out): 10 V / Sct. Time scale: 100 µs / Sct. It is known to those skilled in the art that the scaling factors given above as examples, e.g.The rectified voltage must be selected appropriately to allow the individual signal waveforms to be displayed together on the display device used for the experimental setup. Fig. 11A: Device for monitoring impulse short-circuit currents in embodiment b), i.e., as a current limiting device according to the invention: Exemplary embodiment for a three-phase power network using an inductor (coil). (30) per phase in addition to the semiconductor switching elements connected antiparallel to each other (10, 10' ), which are already provided in embodiment a), . Fig. 11B: Device for controlling impulse short-circuit currents in embodiment b), i.e. as a current limiting device according to the invention: Exemplary embodiment for a three-phase power network using an inductor (coil) (30) per phase in addition to the semiconductor switching elements connected antiparallel to each other (10, 10'), which are already provided in version a), as well as further semiconductor elements connected in pairs in antiparallel to each other 40, 40', which are positioned between the phases. Fig. 11C: Device for controlling impulse short-circuit currents in embodiment b), i.e., as a current limiting device according to the invention: Exemplary embodiment for a three-phase power network using an inductor (coil) (30) per phase in addition to the semiconductor switching elements connected antiparallel to each other (10, 10' ), which are already provided in version a), as well as further semiconductor elements connected in pairs in antiparallel to each other 40, 40' , which are positioned between each phase and the neutral conductor ("N").

Claims

1. Device for controlling surge short-circuit currents in power supply networks, wherein the device - has at least two non-mechanical switching elements in each current path of each phase, which are independently selected from the list comprising power transistors and thyratrons, as well as at least two diodes, wherein the non-mechanical switching elements and the diodes in each current path of each phase are connected anti-parallel to each other; - has a measuring device for measuring the current flow over time in each phase L1 to Ln of the feed line in order to obtain n phase-specific individuallly measured values Umess-L(1) to Umess-L(n) that are proportional to the current flows, wherein this measuring device for measuring the current flow comprises current transformers and measuring resistors; - has a calculation device for calculating at least one sum signal Umess-sum ; - has an evaluation device which generates at least one control signal from the sum signal Umess-sum by comparison with the limit value for controlling the at least two non-mechanical switching elements per current path of each phase, wherein this evaluation device comprises at least one resistor, a reference voltage source and a comparator, and is arranged in such a way that the at least one control signal exists when the rectified sum signal Umess-sum has exceeded the reference voltage at a specific point; - has a control system comprising at least one 1-bit error memory and - has at least one adjustable delay element, characterized in that the device - has at least one processor or an FPGA or an analog control circuit ; - has at least one coil (30) with defined inductance in each phase line, wherein this at least one coil (30) in each phase line is located between the bidirectional semiconductor switch (10, 10') and the external network ; - has at least one further additional bidirectional semiconductor switch (40, 40'), which is located either between two phases or between one phase and the neutral conductor, and wherein the semiconductor switching elements forming this at least one additional bidirectional semiconductor switch are semiconductor switching elements selected from the list comprising IGBTs, MOSFETs, thyratrons.

2. Device according to claim 1, characterised in that the calculation device calculates the sum signal Umess-sum by i) determining and selecting the maximum value among the n phase-specific individual measured values Umess-L(1) to Umess-L(n) from the measuring device, wherein the calculation device components are selected independently of one another from the list comprising measuring resistors, measuring transformers, Hall probes, operational amplifiers, logic circuits, FPGA, CPLD, processors, and / or ii) comparing the n phase-specific individual measured values Umess-L(1) to Umess-L(n) from the measuring device with the respective corresponding phase-specific limit values, wherein the calculation device comprises components, independently selected from each other from the list comprising measuring resistors, measuring transformers, Hall probes, operational amplifiers, logic circuits, FPGA, CPLD, processors, and / or iii) rectifying the individual measured values Umess-L(1) to Umess-L(n) from the measuring device, wherein the calculation device for rectifying individual measured values comprises resistors, diodes and operational amplifiers as well as a subordinate sub-device TB for combining the rectified individual measured values Umess-L(1)-equal to Umess-L(n)-equal into a sum signal Umess-sum which is proportional to the total current flow in the feed line, wherein this subordinate sub-device TB for combining the rectified individual measured values comprises at least one diode in each input line of a rectified individual measured value Umess-L(1)-equal to Umess-L(n)-equal for decoupling the individual rectified individual measurement values from each other, and / or iv) forming the magnitudes |Umess-L(1)| to |Umess-L(n)| of the individuallly measured values Umess-L(1) to Umess-L(n) from the measuring device and the use of these sign-independent values |Umess-L(1)| to |Umess-L(n)| instead of the sign-bearing real individual measurement values Umess-L(1) to Umess-L(n) from the measuring device in all embodiments i) or ii) or iii) of this calculation device, wherein this calculation device comprises components independently selected from the list comprising measuring resistors, measuring transformers, Hall probes, operational amplifiers, logic circuits, FPGA, CPLD, processors.

3. Device according to claim 1 or claim 2, characterized in that the device additionally comprises a fuse.

4. Use of a device according to one of the preceding claims 1 to 3 in a medium-voltage power grid or in a low-voltage power grid for suppressing surge short-circuit currents during the start-up phase of at least one synchronous generator connected to the medium-voltage power grid or to the low-voltage power grid.

5. Device for controlling surge short-circuit currents in power supply networks according to claim 1, characterised in that the device further comprises at least one additional bidirectional semiconductor switch (40, 40') which enables a free-wheeling path to another phase or to the neutral conductor.