Circuit arrangement for balancing a divided DC voltage intermediate circuit

Description

[0001] The invention relates to a circuit arrangement for balancing a divided DC voltage intermediate circuit.

[0002] Multi-level inverters, also known as multi-point inverters, typically have a split DC link circuit comprising a series connection of a first DC link capacitor and a second DC link capacitor between a first DC link terminal and a second DC link terminal, and having a DC link midpoint between the two DC link capacitors.

[0003] When operating such a multi-level inverter to form an island grid, it must be suitable for connecting any load. This poses a problem with loads that consume different power levels depending on the voltage polarity, such as hair dryers whose heating coils are driven by a diode, or larger loads connected via a center-point rectifier. If such loads are connected to a multi-level inverter with a split DC link, without further measures, the electrical potential at the DC link center point would shift toward the potential at one of the DC voltage terminals, thereby causing overvoltages in one half of the DC link and the semiconductor switches connected to it.

[0004] Therefore, circuits for balancing divided DC intermediate circuits are known which, in the event of uneven voltage distribution across the two intermediate circuit halves, cause a charge equalization between the intermediate circuit capacitors, so that the potential of the intermediate circuit center is shifted towards a potential which lies in the middle between the potentials at the two DC voltage connections.

[0005] For example, the publication by K. Sano and H. Fujita, "Voltage-Balancing Circuit Based on a Resonant Switched-Capacitor Converter for Multilevel Inverters" in IEEE Transactions on Industry Applications, vol. 44, no. 6, pp. 1768-1776, Nov.-Dec. 2008, discloses, in its prior art review, the use of a bidirectional resonant switched capacitor converter (RSCC) for balancing a split DC link. A series circuit of a first and a second semiconductor switch, each having antiparallel diodes, is arranged in parallel with the first DC link capacitor, and a series circuit of a third and a fourth semiconductor switch, each having antiparallel diodes, is arranged in parallel with the second DC link capacitor.A first intermediate point between the first and second semiconductor switches is connected to a second intermediate point between the third and fourth semiconductor switches via a series circuit comprising a resonant capacitor and a resonant choke.

[0006] In addition to the previously described balancing circuit, the prior art discussion in WO 2016 / 011380 A1 discloses a circuit that differs from the previously described balancing circuit in that the resonant choke is not arranged between the resonant capacitor and the second intermediate point, but rather between a point between the second and third semiconductor switches and the intermediate circuit center. In this case, the first intermediate point is connected to the second intermediate point via the resonant capacitor.

[0007] Balancing of a split DC link can be carried out with this circuit in the same way as with the previously described balancing circuit, whereby the control of the semiconductor switches in both circuits is carried out in exactly the same way.

[0008] The publication M. Abbasi and J. Lam, "An improved voltage balancing technique for a softswitched high-gain converter with low voltage stress using duty ratio control for wind energy application," 2017 IEEE Energy Conversion Congress and Exposition (ECCE), 2017, pp. 4136-4143, discloses a modular DC-DC converter in which a series circuit of a first and a second semiconductor switch, each having anti-parallel diodes, is arranged in parallel with the first intermediate circuit capacitor and a series circuit of a third and a fourth semiconductor switch, each having anti-parallel diodes, is arranged in parallel with the second intermediate circuit capacitor, and in which a first intermediate point between the first and second semiconductor switches is connected to a second intermediate point between the third and fourth semiconductor switches via a series circuit of a resonant capacitor and a resonant choke.An additional circuit for balancing the intermediate circuit voltages comprises an auxiliary transformer whose primary winding is connected in parallel with the primary winding of the main transformer of a DC-DC converter module, and two diodes connected in parallel with the intermediate circuit capacitors.

[0009] Apart from the asymmetry of the voltages across the divided DC link caused by asymmetrical loads, symmetrical loads also result in a temporal fluctuation of the instantaneous load of the intermediate circuit halves. For example, in a three-phase, three-level inverter, the instantaneous power of the intermediate circuit halves fluctuates by approximately one-third of the average power. Since this power fluctuation occurs in antiphase for both intermediate circuit halves, the intermediate circuit halves are discharged unevenly, and the potential at the intermediate circuit center point fluctuates at three times the grid frequency. However, the resulting asymmetry of the voltages across the divided DC link balances out over time, so balancing is unnecessary in this case and would only cause unnecessary losses.

[0010] To avoid such unnecessary operation, it is conceivable to activate a balancing circuit only when a significant asymmetry occurs, i.e., only when the voltage difference between the intermediate circuit halves is above a specified threshold. However, in inverters designed for operation with a high voltage on the DC link, the potential fluctuations at the intermediate circuit center point can reach high values, for example, more than ± 10 V. Therefore, if a balancing circuit of the type described above is only activated above a correspondingly high threshold, the resonance current would oscillate very rapidly due to the high differential voltage, posing the risk of destroying the semiconductor switches.Furthermore, the voltage at the resonance capacitor Cres can oscillate to such high values ​​that in a circuit configuration according to WO 2016 / 011380 A1, in which this voltage is temporarily applied to a switch T2 or T3, this switch is destroyed.

[0011] It is therefore an object of the present invention to provide a circuit arrangement for balancing a split DC intermediate circuit, which is suitable for compensating asymmetries of the voltages at the intermediate circuit halves of the split DC intermediate circuit, without dangerously high currents or voltages occurring that could lead to the destruction of semiconductor switches.

[0012] This object is achieved according to the invention by a circuit arrangement according to independent claim 1. Advantageous embodiments of the invention are described in the dependent claims.

[0013] In a circuit arrangement according to the invention for balancing a split DC link, which comprises a series connection of a first DC link capacitor and a second DC link capacitor between a first DC voltage terminal and a second DC voltage terminal and has an DC link center point between the first DC link capacitor and the second DC link capacitor, the first DC voltage terminal is connected to a first intermediate point via a first semiconductor switch, the first intermediate point is connected to a bridge center point via a second semiconductor switch, the bridge center point is connected to a second intermediate point via a third semiconductor switch, and the second intermediate point is connected to the second DC voltage terminal via a fourth semiconductor switch. The semiconductor switches each have an antiparallel diode.Furthermore, a first terminal of a resonant capacitor is connected to the first intermediate point, and a second terminal of the resonant capacitor is connected to the intermediate circuit center via a connection path in which a resonant choke is arranged in series with the third semiconductor switch and which runs via the second intermediate point. The resonant capacitor and resonant choke thus form a resonant circuit or are at least connected to it by closing the second or third semiconductor switch.

[0014] In the circuit arrangement according to the invention, an additional winding is magnetically coupled to the resonant choke, wherein a first terminal of the additional winding is connected via a first diode to a first terminal of a counter-voltage source. A second terminal of the additional winding is connected to a second terminal of the counter-voltage source in such a way that energy coupled into the additional winding by the resonant choke is discharged into the counter-voltage source via the first diode. The polarity of the first diode with respect to the first terminal of the additional winding and the first terminal of the counter-voltage source inherently results from the feature that the energy coupled into the additional winding is discharged into the counter-voltage source via the first diode.A discharge only occurs as long as the voltage across the additional winding is greater than a counter voltage due to the counter voltage source plus the forward voltage of the first diode, ie not the complete energy of the resonant circuit formed by the resonant capacitor and the resonant choke is coupled into the additional winding and thus fed into the counter voltage source, but only a part of it.

[0015] In one embodiment of the circuit arrangement according to the invention, the second terminal of the auxiliary winding is connected directly to the second terminal of the counter-voltage source. In yet another embodiment, the first terminal of the auxiliary winding is connected to a third terminal of the counter-voltage source via a second diode. In this arrangement, the energy coupled into the auxiliary winding by the resonant choke is discharged via the first diode into the part of the counter-voltage source between the first terminal and the second terminal, or via the second diode into the part of the counter-voltage source between the second terminal and the third terminal, depending on the polarity of the voltage across the auxiliary winding.The polarity of the second diode with respect to the first terminal of the additional winding and the third terminal of the counter voltage source must be selected so that the energy coupled into the additional winding is discharged into the counter voltage source via the second diode.

[0016] In another embodiment of the circuit arrangement according to the invention, the second terminal of the auxiliary winding is not connected directly, but via a fourth diode to the second terminal of the counter-voltage source. Furthermore, the first terminal of the auxiliary winding is connected via a second diode to the second terminal of the counter-voltage source, and the second terminal of the auxiliary winding is connected via a third diode to the first terminal of the counter-voltage source. The polarity of the second diode, the third diode, and the fourth diode with respect to the first and second terminals of the auxiliary winding and the first and second terminals of the counter-voltage source, respectively, is to be selected such that the energy coupled into the auxiliary winding is discharged via the diodes into the counter-voltage source.

[0017] In this arrangement, depending on the polarity of the voltage across the additional winding, the electrical potential applied to the first terminal of the counter voltage source or the electrical potential applied to the second terminal of the counter voltage source is applied to the second terminal of the additional winding, in each case merely shifted by a forward voltage of the third or fourth diode, so that the energy coupled into the additional winding by the resonant choke is discharged into the counter voltage source via the first and fourth diodes or via the second and third diodes, depending on the polarity of the voltage across the additional winding.

[0018] An oscillation of the resonance current is prevented in the circuit arrangement according to the invention in that the voltage driving the current in the resonance circuit formed from the resonance capacitor and the resonance choke is limited in that it is transformed via the magnetic coupling to the additional winding, where it is clamped, depending on the embodiment, via the first or second diode or via the first and fourth diode or via the second and third diode to a voltage applied to the counter voltage source.

[0019] In the embodiment of the circuit arrangement according to the invention, in which the second terminal of the additional winding is connected via a third diode to the first terminal of the counter voltage source and via a fourth diode to the second terminal of the counter voltage source, a switchable connection can optionally be provided between the second terminal of the additional winding and a terminal of the counter voltage source which is at an intermediate potential between the electrical potentials applied to the first and second terminal of the counter voltage source.When the switchable connection is closed, the second terminal of the auxiliary winding is connected to the intermediate potential. When the switchable connection is open, the second terminal of the auxiliary winding is connected via the third diode to the electrical potential at the first terminal of the counter-voltage source and via the fourth diode to the electrical potential at the second terminal of the counter-voltage source. As a result, the switchable connection allows the counter-voltage to which the auxiliary winding is clamped to be switched between half and full voltage of the counter-voltage source, which then allows the balancing power to be varied.

[0020] Further embodiments are conceivable in which the voltage value of the counter voltage source can be adjusted and / or the effective counter voltage can be switched between the voltage of the complete counter voltage source and the voltage of only a part of the counter voltage source, so that the effective counter voltage, and thus the balancing power, can be adjusted.

[0021] In a circuit arrangement according to the invention, the counter voltage source is formed by the first intermediate circuit capacitor and / or the second intermediate circuit capacitor. The first DC voltage terminal then corresponds to the first terminal of the counter voltage source, and depending on the design, the intermediate circuit center point corresponds to the second terminal of the counter voltage source, and the second DC voltage terminal corresponds to the third terminal of the counter voltage source, or the second DC voltage terminal corresponds to the second terminal of the counter voltage source.

[0022] The advantage of forming the counter voltage source using the intermediate circuit capacitors of the DC link to be balanced is that no additional, separate counter voltage source is required. Furthermore, the energy extracted from the DC link via the auxiliary winding during the balancing process is simultaneously at least partially fed back into it. Depending on the design of the circuit arrangement according to the invention, the energy extracted from the first DC link capacitor is then even fed into the second DC link capacitor, or vice versa, thereby further supporting the balancing process.

[0023] In one embodiment of the circuit arrangement according to the invention, the resonance choke is arranged between the second terminal of the resonance capacitor and the second intermediate point, ie the first intermediate point is connected to the second intermediate point via a series circuit comprising the resonance capacitor and the resonance choke, and the bridge center point is directly connected to the intermediate circuit center point.

[0024] In another embodiment of the circuit arrangement according to the invention, the resonance choke is arranged between the intermediate circuit center point and the bridge center point, so that the first intermediate point is in this case directly connected to the second intermediate point via the resonance capacitor.

[0025] The four semiconductor switches in the circuit arrangement according to the invention are preferably arranged such that they each have the same forward direction and reverse direction for a current flow between the first DC voltage terminal and the second DC voltage terminal. Consequently, the antiparallel diodes of the four semiconductor switches between the first DC voltage terminal and the second DC voltage terminal also each have the same forward direction and reverse direction, which are opposite to the respective forward direction and reverse direction of the associated semiconductor switch.

[0026] In the circuit arrangement according to the invention, the voltage to be limited is applied to the resonant choke by a switching operation, i.e., suddenly. To avoid high pulse currents in the windings of the resonant choke and the auxiliary winding, the magnetic coupling between the two windings should therefore not be too good. The coupling factor between the resonant choke and the auxiliary winding can advantageously be in the range of 0.8 to 0.9, for example.

[0027] In one embodiment, the circuit arrangement according to the invention comprises a control circuit for controlling the semiconductor switches, wherein the control circuit is configured to control the first semiconductor switch and the third semiconductor switch with a first PWM (pulse width modulated) signal and to control the second semiconductor switch and the fourth semiconductor switch with a second PWM signal that is complementary to the first PWM signal, except for dead times to be taken into account during switching on and off processes. The pulse duration of the PWM signals is selected, for example, to be equal to half the period of a resonant oscillation of the resonant circuit formed by the resonant capacitor and the resonant choke. A dead time between switching off the first PWM signal and switching on the second PWM signal, or vice versa, is, for example, as small as the semiconductor switches used allow.This results in PWM signals whose frequency is below the resonance frequency of the oscillating circuit formed by the series connection of the resonance capacitor and the resonance choke and which usually have a duty cycle close to 50%.

[0028] When the semiconductor switches are controlled by the control circuit with such a first and second PWM signal, the circuit arrangement according to the invention symmetrizes the divided DC voltage intermediate circuit, in which the energy flow direction is automatically adjusted depending on the existing asymmetry of the voltages across the intermediate circuit halves.

[0029] In a further embodiment of the circuit arrangement according to the invention, the control circuit is configured to enable the PWM signals for the first semiconductor switch and the second semiconductor switch via a first enable signal and to enable the PWM signals for the third semiconductor switch and the fourth semiconductor switch via a second enable signal. The circuit arrangement according to the invention can be selectively activated via the first and second enable signals to transfer charges from the first intermediate circuit capacitor to the second intermediate circuit capacitor or vice versa.

[0030] In yet another embodiment, the circuit arrangement according to the invention comprises a control circuit for controlling the semiconductor switches, wherein the control circuit is configured to control the first semiconductor switch and the fourth semiconductor switch with a first PWM signal and to control the second semiconductor switch and the third semiconductor switch with a second PWM signal which, apart from dead times to be taken into account during switching on and off processes, is complementary to the first PWM signal, and wherein the control circuit is configured to enable the PWM signals for the first semiconductor switch and the second semiconductor switch via a first enable signal and the PWM signals for the third semiconductor switch and the fourth semiconductor switch via a second enable signal.

[0031] Furthermore, a circuit arrangement according to the invention can also comprise a control circuit for controlling the semiconductor switches, which is designed to control the first semiconductor switch with a first PWM signal and the second semiconductor switch with a second PWM signal which, apart from dead times to be taken into account during switching on and off processes, is complementary to the first PWM signal, and to control the third semiconductor switch with a third PWM signal and the fourth semiconductor switch with a fourth PWM signal which, apart from dead times to be taken into account during switching on and off processes, is complementary to the third PWM signal.In this embodiment, the control circuit is also configured to enable the PWM signals for the first semiconductor switch and the second semiconductor switch via a first enable signal and the PWM signals for the third semiconductor switch and the fourth semiconductor switch via a second enable signal.

[0032] A circuit arrangement according to the invention can thus comprise a control circuit for controlling the semiconductor switches, which is designed to control the first semiconductor switch together with the third semiconductor switch and, complementarily thereto, the second semiconductor switch together with the fourth semiconductor switch, or in each case either exclusively the first semiconductor switch and, complementarily thereto, the second semiconductor switch or exclusively the third semiconductor switch and, complementarily thereto, the fourth semiconductor switch with a PWM signal.In particular, a circuit arrangement according to the invention can therefore also comprise a control circuit for controlling the semiconductor switches, which is designed to exclude a simultaneous control of the first semiconductor switch and the fourth semiconductor switch with one and the same PWM signal and / or a simultaneous control of the second semiconductor switch and the third semiconductor switch with one and the same PWM signal.

[0033] The control circuit can, for example, be configured to set the first enable signal when the difference between the voltage at the first intermediate circuit capacitor and the voltage at the second intermediate circuit capacitor exceeds a first threshold value and to reset it again when the difference between the voltage at the first intermediate circuit capacitor and the voltage at the second intermediate circuit capacitor falls below a second threshold value. At the same time, the control circuit can be configured to set the second enable signal when the difference between the voltage at the second intermediate circuit capacitor and the voltage at the first intermediate circuit capacitor exceeds the first threshold value and to reset it again when the difference between the voltage at the second intermediate circuit capacitor and the voltage at the first intermediate circuit capacitor falls below the second threshold value.

[0034] The first threshold value and the second threshold value are preferably selected such that symmetrization is only activated when the difference between the voltages at the intermediate circuit halves is greater than the periodic fluctuations in the difference between the voltages at the intermediate circuit halves that potentially occur even with a symmetrical load.

[0035] Optionally, the first threshold can be selected to be smaller. After exceeding this smaller first threshold, the duty cycle of the PWM signals is initially limited to a smaller value, for example, 5%, to precharge the resonant capacitor. The full duty cycle of approximately 50% is then only set when a third threshold, which is in the aforementioned range, is exceeded.

[0036] For the embodiment in which the control circuit is configured to control the first and third semiconductor switches with a first PWM signal and the second and fourth semiconductor switches with a second PWM signal, a common enable signal can also be used instead of two enable signals, which is set when the amount of the difference between the voltage at the first intermediate circuit capacitor and the voltage at the second intermediate circuit capacitor exceeds a first threshold value and is reset again when the amount of the difference between the voltage at the first intermediate circuit capacitor and the voltage at the second intermediate circuit capacitor falls below a second threshold value.

[0037] According to a further embodiment of the circuit arrangement according to the invention, the control circuit is configured to synchronize the enabling of the PWM signals by the enable signals to edges of the PWM signals. This ensures that, with an appropriate selection of the pulse duration of the PWM signals, the semiconductor switches are always controlled for half the period of a resonant oscillation of the resonant circuit formed by the resonant capacitor and the resonant choke after the enabling, and not for a shorter duration.

[0038] The invention is explained in more detail below with reference to figures. The figures serve to illustrate embodiments of the invention, but do not limit the invention to the features shown. Fig. 1 shows a first embodiment of a circuit arrangement not falling within the scope of the claims, Fig. 2 shows a second embodiment of a circuit arrangement not falling within the scope of the claims, Fig. 3 shows a third embodiment of a circuit arrangement not falling within the scope of the claims, Fig. 4 shows a fourth embodiment of a circuit arrangement according to the invention, Fig. 5 shows a fifth embodiment of a circuit arrangement according to the invention, Fig. 6 shows a sixth embodiment of a circuit arrangement according to the invention, Fig. 7 shows a seventh embodiment of a circuit arrangement according to the invention, Fig. 8 shows an embodiment of a circuit arrangement according to the invention with a control circuit for controlling the semiconductor switches, and Fig. 9 shows yet another embodiment of a circuit arrangement according to the invention with a control circuit for controlling the semiconductor switches, and Fig. 10 shows a flowchart for generating signals for controlling the semiconductor switches of a circuit arrangement according to the invention by a state machine.

[0039] Fig. 1 shows a circuit arrangement 1 not falling within the scope of protection of the claims, in which a divided DC voltage intermediate circuit is arranged between a first DC voltage connection 2 and a second DC voltage connection 3, which is formed from the series connection of a first intermediate circuit capacitor C1 and a second intermediate circuit capacitor C2 with an intermediate circuit center point 4.

[0040] A series circuit of a first semiconductor switch T1 and a second semiconductor switch T2 is connected in parallel to the first intermediate circuit capacitor C1, and a series circuit of a third semiconductor switch T3 and a fourth semiconductor switch T4 is connected in parallel to the second intermediate circuit capacitor C2. The four semiconductor switches T1, T2, T3, and T4 form a half-bridge between the first DC voltage terminal 2 and the second DC voltage terminal 3, with a bridge center point 6 directly connected to the intermediate circuit center point 4.

[0041] The four semiconductor switches T1, T2, T3, T4 are in circuit arrangement 1 in Fig. 1 arranged so that they each have the same forward direction and reverse direction for a current flow between the first DC voltage terminal 2 and the second DC voltage terminal 3 and each have an anti-parallel diode 8, 9, 10, 11, the forward direction and reverse direction of which are each opposite to that of the associated semiconductor switch T1, T2, T3, T4.

[0042] An oscillating circuit formed by the series connection of a resonant capacitor Cres and a resonant choke Lres is connected between a first intermediate point 5 between the first semiconductor switch T1 and the second semiconductor switch T2 and a second intermediate point 7 between the third semiconductor switch T3 and the fourth semiconductor switch T4. Furthermore, an additional winding L1 is magnetically coupled to the resonant choke Lres, with a first terminal of the additional winding L1 being connected via a first diode D1 to a first terminal 22 of a counter-voltage source 23, and a second terminal of the additional winding L1 being connected directly to a second terminal 24 of the counter-voltage source 23.

[0043] In the embodiment of a circuit arrangement 1 according to Fig. 1 The energy coupled into the auxiliary winding L1 by the resonant choke Lres is discharged into the counter-voltage source 23 via the first diode D1, assuming the appropriate polarity of the voltage across the auxiliary winding L1. The winding direction of the resonant choke Lres and the auxiliary winding L1 on a common core can be chosen arbitrarily in this embodiment, ie, both in the same direction and in opposite directions.

[0044] At the Fig. 2 The embodiment of a circuit arrangement 1 not falling within the scope of protection of the claims shown in FIG. 1 is different from the embodiment in FIG. Fig. 1 The first terminal of the auxiliary winding L1 is additionally connected via a second diode D2 to a third terminal 25 of the counter voltage source 23. The counter voltage source 23 is designed as a split counter voltage source, wherein the electrical potential at the second terminal 24 of the counter voltage source 23 forms an intermediate potential between the electrical potential at the first terminal 22 and the electrical potential at the third terminal 25 of the counter voltage source 23.

[0045] In this embodiment, the energy coupled into the auxiliary winding L1 by the resonant choke Lres is discharged, depending on the polarity of the voltage across the auxiliary winding L1, via the first diode D1 into the part of the counter voltage source 23 between the first terminal 22 and the second terminal 24 or via the second diode D2 into the part of the counter voltage source 23 between the second terminal 24 and the third terminal 25. The winding direction of the resonant choke Lres and the auxiliary winding L1 on a common core can be selected arbitrarily in this embodiment, i.e., both in the same direction and in opposite directions.

[0046] In the embodiment of a circuit arrangement 1 not falling within the scope of protection of the claims in Fig. 3 the second terminal of the additional winding L1 is connected via a third diode D3 to the first terminal 22 of the counter voltage source 23 and via a fourth diode D4 to the second terminal 24 of the counter voltage source 23. In this embodiment of a circuit arrangement 1 according to the invention, the energy coupled into the additional winding L1 by the resonant choke Lres is discharged into the counter voltage source 23 either via the first diode D1 and the fourth diode D4 or via the second diode D2 and the third diode D3, depending on the polarity of the voltage across the additional winding L1. The winding direction of the resonant choke Lres and the additional winding L1 on a common core can also be selected as desired in this embodiment, ie both in the same direction and in opposite directions.

[0047] Fig. 4 shows a circuit arrangement 1 according to the invention, in which the counter voltage source 23 is formed by the divided DC voltage intermediate circuit arranged between the first DC voltage terminal 2 and the second DC voltage terminal 3. Accordingly, in this case, Fig. 2 In an analog arrangement, the first terminal of the additional winding L1 is connected via a first diode D1 to the first DC voltage terminal 2 and via a second diode D2 to the second DC voltage terminal 3, and the second terminal of the additional winding L1 is connected directly to the intermediate circuit center point 4.

[0048] In the embodiment of a circuit arrangement 1 according to the invention according to Fig. 4 The energy coupled into the additional winding L1 by the resonance choke Lres is discharged alternately via the first diode D1 into the first intermediate circuit capacitor C1 of the DC link and via the second diode D2 into the second intermediate circuit capacitor C2 of the DC link, ie alternately into one of the intermediate circuit halves. The winding sense of the resonance choke Lres and the additional winding L1 on a common core can be analogous to the embodiment in Fig. 2 arbitrarily, ie both in the same direction and in the opposite direction.

[0049] The Fig. 5 The embodiment of a circuit arrangement 1 according to the invention shown in FIG. 1 differs from that shown in FIG. Fig. 4 in that the second terminal of the additional winding L1 is not connected to the intermediate circuit center 4, but analogously to the embodiment in Fig. 3 via a third diode D3 to the first DC voltage terminal 2 and via a fourth diode D4 to the second DC voltage terminal 3. In this embodiment of a circuit arrangement 1 according to the invention, the energy coupled into the additional winding L1 by the resonant choke Lres is discharged either via the first diode D1 and the fourth diode D4 or via the second diode D2 and the third diode D3 into the DC voltage intermediate circuit formed by the series connection of the first intermediate circuit capacitor C1 and the second intermediate circuit capacitor C2, ie, regardless of the polarity of the voltage across the additional winding, always into both intermediate circuit halves. The winding sense of the resonant choke Lres and the coil L1 on a common core can be analogous to the embodiment in Fig. 3 arbitrarily, ie both in the same direction and in the opposite direction.

[0050] At the Fig. 6 The embodiment of a circuit arrangement 1 according to the invention shown in FIG. 1 is different from the embodiment in FIG. Fig. 5 A switchable connection 21 is arranged between the second terminal of the auxiliary winding L1 and the intermediate circuit center point 4. When the switchable connection 21 is closed, the second terminal of the auxiliary winding L1 is connected to the intermediate circuit center point 4, and when the switchable connection 21 is open, the second terminal of the auxiliary winding L1 is connected via the third diode D3 to the first DC voltage terminal 2 and via the fourth diode D4 to the second DC voltage terminal 3. As a result, the energy coupled into the auxiliary winding L1 by the resonance choke Lres is transferred to the auxiliary winding L1 when the switchable connection 21 is closed, as in the embodiment shown in Fig. 5 alternately discharged into one of the intermediate circuit halves and with the switchable connection 21 open as in the embodiment in Fig. 6 always in both intermediate circuit halves. Accordingly, the winding direction of the resonance choke Lres and the additional winding L1 on a common core can be chosen arbitrarily in this embodiment, ie, both in the same direction and in opposite directions.

[0051] The Fig. 7 shows an embodiment of a circuit arrangement 1 according to the invention, in which, compared to the embodiment in Fig. 4 The resonance choke Lres is connected between the intermediate circuit center point 4 and the bridge center point 6. In this case, only the resonance capacitor Cres is connected between the first intermediate point 5 and the second intermediate point 7.

[0052] The winding sense of the resonance choke Lres and the additional winding L1 on a common core is shown in Fig. 7 In conjunction with such a winding direction, the advantage of the embodiment in Fig. 7 compared to the embodiments in Fig. 4 and Fig. 5 that the energy coupled into the additional winding L1 by the resonance choke Lres is always discharged into that of the two intermediate circuit capacitors C1 or C2 into which the energy from the resonance circuit formed by the resonance choke Lres and the resonance capacitor Cres is also discharged, ie the discharge of the energy coupled into the additional winding L1 by the resonance choke Lres also contributes to the symmetrization of the DC intermediate circuit.

[0053] A further advantage of the embodiment according to Fig. 7 with a winding direction of the resonance choke Lres and the additional winding L1 as shown is that the arrangement of the additional winding L1 coupled to the resonance choke Lres can be designed as a component with only three connections.

[0054] In principle, of course, an embodiment as in Fig. 7 with a different winding direction of the resonance choke Lres and the additional winding L1 on a common core, which is chosen in opposite directions, but in this case the previously mentioned advantages are no longer present.

[0055] It is also possible to arrange the resonance choke Lres between the intermediate circuit center point 4 and the bridge center point 6 as shown in Fig. 7 the second connection of the additional winding L1 as shown in Fig. 5 via a third diode D3 to the first DC voltage terminal 2 and via a fourth diode D4 to the second DC voltage terminal 3. In this case, as in the embodiment according to Fig. 5 , the energy coupled into the additional winding L1 is always discharged into both intermediate circuit halves and thus no longer contributes to the symmetrization of the DC intermediate circuit.

[0056] In Fig. 8 an embodiment of a circuit arrangement 1 according to the invention with a control circuit 12 for controlling the semiconductor switches T1, T2, T3, T4 is shown.

[0057] A signal line for a first enable signal En_Pos is connected to a first input of a first AND gate 13 and to a first input of a second AND gate 14. A signal line for a second enable signal En_Neg is connected to a first input of a third AND gate 15 and to a first input of a fourth AND gate 16. Furthermore, a signal line for a first PWM signal PWM_1 is connected to a second input of each of the first AND gate 13 and the third AND gate 16, and a signal line for a second PWM signal PWM_2 is connected to a second input of each of the second AND gate 14 and the fourth AND gate 15. The outputs of the AND gates 13, 14, 15, and 16 are each connected via drivers 17, 18, 19, and 20 to control inputs of the semiconductor switches T1, T2, T3, and T4.

[0058] The control circuit 12 in Fig. 8 is thereby configured to enable or disable the first PWM signal PWM_1 via the first enable signal En_Pos for controlling the first transistor T1, to enable or disable the second PWM signal PWM_2 via the first enable signal En_Pos for controlling the second transistor T2, to enable or disable the first PWM signal PWM_1 via the second enable signal En_Neg for controlling the third transistor T3 and to enable or disable the second PWM signal PWM_2 via the second enable signal En_Neg for controlling the fourth transistor T4.

[0059] The control circuit 12 of the embodiment of a circuit arrangement 1 according to the invention in Fig. 9 differs from that in Fig. 8 in that a signal line for a first PWM signal PWM_1 is connected to a second input of the first AND gate 13 and the fourth AND gate 16, and a signal line for a second PWM signal PWM_2 is connected to a second input of the second AND gate 14 and the third AND gate 15.

[0060] The control circuit 12 in Fig. 9 is thereby configured to enable or disable the first PWM signal PWM_1 via the first enable signal En_Pos for controlling the first transistor T1, to enable or disable the second PWM signal PWM_2 via the first enable signal En_Pos for controlling the second transistor T2, to enable or disable the second PWM signal PWM_2 via the second enable signal En_Neg for controlling the third transistor T3 and to enable or disable the first PWM signal PWM_1 via the second enable signal En_Neg for controlling the fourth transistor T4.

[0061] Instead of connecting logic gates, as in the control circuit 12 in the Fig. 8 and 9 , suitable signals for controlling the semiconductor switches T1, T2, T3, T4 can also be generated by a state machine, for example using a microcontroller. A corresponding flowchart is shown in Fig. 10 shown.

[0062] First, in a first step S01, it is checked whether a difference Vpos - Vneg between the voltage Vpos at the first intermediate circuit capacitor C1 and the voltage Vneg at the second intermediate circuit capacitor C2 exceeds a first threshold value V1. If not, in a second step S02, it is checked whether a difference Vneg - Vpos between the voltage Vneg at the second intermediate circuit capacitor C2 and the voltage Vpos at the first intermediate circuit capacitor C1 exceeds the first threshold value V1. If this is also not the case, in a third step S03, all semiconductor switches T1, T2, T3, T4 are switched off, and steps S01 and S02 are repeated.

[0063] If, during the check in step S01, the difference Vpos - Vneg exceeds the first threshold value V1, the first semiconductor switch T1 is switched on in a fourth step S04, a time period ta is waited for in a fifth step S05, and then the first semiconductor switch T1 is switched off again in a sixth step S06. The time period ta corresponds, for example, to half the period of a resonant oscillation of the resonant circuit formed by the resonant capacitor Cres and the resonant choke Lres.

[0064] Subsequently, in a seventh step S07, a dead time tb is waited for before the second semiconductor switch T2 is switched on in an eighth step S08. The dead time tb takes into account the non-negligible switching times of the semiconductor switches T1, T2, T3, and T4 to ensure that the first semiconductor switch T1 and the second semiconductor switch T2 cannot be switched on simultaneously and then short-circuit the first intermediate circuit capacitor C1. The dead time tb should be selected to be as short as the semiconductor switches used allow.

[0065] In a ninth step S09, the time period ta is again waited for, then in a tenth step S10 the second semiconductor switch T2 is switched off again and in an eleventh step S11 the dead time tb is again waited for in order to ensure that the first semiconductor switch T1 and the second semiconductor switch T2 cannot be switched on at the same time.

[0066] In a twelfth step S12, a check is made to determine whether the difference between Vpos and Vneg falls below a second threshold value V2. If not, steps S04 to S12 are repeated. Otherwise, the program branches to step S03, where all semiconductor switches T1, T2, T3, and T4 are turned off. Steps S01 and S02 are then executed again as described above.

[0067] The second threshold value V2 is to be selected to be smaller than the first threshold value V1 in order to effect a hysteresis for the activation of the circuit arrangement 1 for symmetrization.

[0068] If during the check in step S02 the difference Vneg - Vpos exceeds the first threshold value V1, the fourth semiconductor switch T4 is switched on in a thirteenth step S13, the time period ta is waited for in a fourteenth step S14 and then the fourth semiconductor switch T4 is switched off again in a fifteenth step S15.

[0069] Subsequently, in a sixteenth step S16, the dead time tb is waited for before the third semiconductor switch T3 is switched on in a seventeenth step S17. In this case, the dead time tb takes into account the non-negligible switching times of the semiconductor switches T1, T2, T3, and T4 to ensure that the third semiconductor switch T3 and the fourth semiconductor switch T4 are not switched on simultaneously, as they would otherwise short-circuit the second intermediate circuit capacitor C2.

[0070] In an eighteenth step S18, the time period ta is again waited for, then in a nineteenth step S19 the third semiconductor switch T3 is switched off again and in a twentieth step S20 the dead time tb is again waited for in order to ensure that the third semiconductor switch T3 and the fourth semiconductor switch T4 are not switched on at the same time.

[0071] In a twenty-first step S21, a check is made to determine whether the difference between Vneg and Vpos falls below a second threshold value V2. If not, steps S13 to S21 are repeated. Otherwise, the program branches to step S03, in which all semiconductor switches T1, T2, T3, and T4 are turned off, and then steps S01 and S02 are executed again as previously described.

[0072] In an alternative, not shown embodiment of a state machine, in steps S01 and S12 in Fig. 10 the absolute value of the difference Vpos - Vneg is checked to see whether the first threshold value V1 is exceeded or the second threshold value V2 is not undershot. In such an embodiment of the state machine, steps S02, S21 and S13 to S20 are then omitted, and in steps S04 to S11, the semiconductor switch T3 is switched on or off simultaneously with the semiconductor switch T1, and the semiconductor switch T4 is switched on or off simultaneously with the semiconductor switch T2. The invention is not limited to the embodiments explicitly shown, but can be modified in many ways, in particular combined with other embodiments shown or known to the person skilled in the art. The scope of protection of the invention is limited by the claims. Bezugszeichenliste

[0073] 1Circuit arrangement 2DC voltage connection 3DC voltage connection 4DC link center point 5Intermediate point 6Bridge center point 7Intermediate point 8Antiparallel diode 9Antiparallel diode 10Antiparallel diode 11Antiparallel diode 12Control circuit 13AND gate 14AND gate 15AND gate 16AND gate 17Driver 18Driver 19Driver 20Driver 21Switchable connection 22Connection 23Countervoltage source 24Connection 25Connection T1 - T4 semiconductor switches D1 - D4 Diode C1Intermediate circuit capacitor C2Intermediate circuit capacitor CresResonance capacitor LresResonance choke L1Additional winding S01 - S21Step VposVoltage VnegVoltage V1 threshold V2 threshold PWM_1PWM signal PWM_2PWM signal En_PosEnable signal En_NegEnable signal

Claims

1. A circuit arrangement (1) for balancing a split DC link, which comprises a series circuit comprising a first DC-link capacitor (C1) and a second DC-link capacitor (C2) between a first DC-voltage terminal (2) and a second DC-voltage terminal (3) and has a DC-link center point (4) between the first DC-link capacitor (C1) and the second DC-link capacitor (C2), wherein, in the case of the circuit arrangement (1), the first DC-voltage terminal (2) is connected via a first semiconductor switch (T1, T4) to a first intermediate point (5), the first intermediate point (5) is connected via a second semiconductor switch (T2, T3) to a bridge center point (6), the bridge center point (6) is connected via a third semiconductor switch (T2, T3) to a second intermediate point (7), and the second intermediate point (7) is connected via a fourth semiconductor switch (T1, T4) to the second DC-voltage terminal (3), wherein the semiconductor switches (T1, T2, T3, T4) each have a antiparallel diode (8, 9, 10, 11), and furthermore a first terminal of a resonant capacitor (Cres) is connected to the first intermediate point (5), and a second terminal of the resonant capacitor (Cres) is connected to the DC-link center point (4) via a connecting path, in which a resonant inductor (Lres) is arranged in a series circuit with the third semiconductor switch (T2, T3), and which runs via the second intermediate point (7), characterized in that an additional winding (L1) is magnetically coupled to the resonant inductor (Lres), wherein a first terminal of the additional winding (L1) is connected via a first diode (D1, D2 ) to a first terminal (22, 25) of a countervoltage source (23), and a second terminal of the additional winding (L1) is connected to a second terminal (24) of the countervoltage source (23) in such a way that a discharge path is formed for discharging an energy coupled into the additional winding (L1) from the resonant inductor (Lres) into the countervoltage source (23) via the first diode (D1, D2), wherein the countervoltage source (23) is formed by the first DC-link capacitor (C1) and / or the second DC-link capacitor (C2).

2. The circuit arrangement (1) as claimed in claim 1, wherein the second terminal of the additional winding (L1) is connected directly to the second terminal (24) of the countervoltage source (23), wherein preferably the first terminal of the additional winding (L1) is connected via a second diode (D1, D2) to a third terminal (22, 25) of the countervoltage source (23).

3. The circuit arrangement (1) as claimed in claim 1, wherein the first terminal of the additional winding (L1) is connected via a second diode (D1, D2) to the second terminal (24) of the countervoltage source (23), and the second terminal of the additional winding (L1) is connected via a third diode (D3) to the first terminal (22) of the countervoltage source (23) and via a fourth diode (D4) to the second terminal (24) of the countervoltage source (23).

4. The circuit arrangement (1) as claimed in one of claims 1 to 3, wherein the resonant inductor (Lres) is arranged between the second terminal of the resonant capacitor (Cres) and the second intermediate point (7).

5. The circuit arrangement (1) as claimed in one of claims 1 to 3, wherein the resonant inductor (Lres) is arranged between the DC-link center point (4) and the bridge center point (6).

6. The circuit arrangement (1) as claimed in one of the preceding claims, wherein the semiconductor switches (T1, T2, T3, T4) are arranged in such a way that they each have an identical forward direction and reverse direction for a current flow between the first DC-voltage terminal (2) and the second DC-voltage terminal (3).

7. The circuit arrangement (1) as claimed in one of the preceding claims, comprising a drive circuit (12) for driving the semiconductor switches (T1, T2, T3, T4) using a PWM signal (PWM_1, PWM_2), wherein the drive circuit (12) is configured to rule out simultaneous driving of the first semiconductor switch (T1, T4) and the fourth semiconductor switch (T1, T4) using one and the same PWM signal (PWM_1, PWM_2) and / or simultaneous driving of the second semiconductor switch (T2, T3) and the third semiconductor switch (T2, T3) using one and the same PWM signal (PWM_1, PWM_2).

8. The circuit arrangement (1) as claimed in one of claims 1 to 7, comprising a drive circuit (12) for driving the semiconductor switches (T1, T2, T3, T4), wherein the drive circuit (12) is configured to drive the first semiconductor switch (T1, T4) together with the third semiconductor switch (T2, T3) and, in complementary fashion thereto, the second semiconductor switch (T2, T3) together with the fourth semiconductor switch (T1, T4) using a PWM signal (PWM_1, PWM_2) .

9. The circuit arrangement (1) as claimed in one of claims 1 to 7, comprising a drive circuit (12) for driving the semiconductor switches (T1, T2, T3, T4), wherein the drive circuit (12) is configured to drive in each case either exclusively the first semiconductor switch (T1, T4) and, in complementary fashion thereto, the second semiconductor switch (T2, T3) or exclusively the third semiconductor switch (T2, T3) and, in complementary fashion thereto, the fourth semiconductor switch (T1, T4) using a PWM signal (PWM_1, PWM_2) .

10. The circuit arrangement (1) as claimed in claim 8, wherein the drive circuit (12) is configured to drive the first semiconductor switch (T1, T4) and the third semiconductor switch (T2, T3) using a first PWM signal (PWM_1) and to drive the second semiconductor switch (T2, T3) and the fourth semiconductor switch (T1, T4) using a second PWM signal (PWM_2), which is complementary to the first PWM signal (PWM_1).

11. The circuit arrangement (1) as claimed in claim 10, wherein the drive circuit (12) is configured to enable the PWM signals (PWM_1, PWM_2) for the first semiconductor switch (T1, T4) and the second semiconductor switch (T2, T3) via a first enable signal (En_Pos) and the PWM signals (PWM_1, PWM_2) for the third semiconductor switch (T2, T3) and the fourth semiconductor switch (T1, T4) via a second enable signal (En_Neg).

12. The circuit arrangement (1) as claimed in claim 9, wherein the drive circuit (12) is configured to drive the first semiconductor switch (T1, T4) and the fourth semiconductor switch (T1, T4) using a first PWM signal (PWM_1) and to drive the second semiconductor switch (T2, T3) and the third semiconductor switch (T2, T3) using a second PWM signal (PWM_2), which is complementary to the first PWM signal (PWM_1), and wherein the drive circuit (12) is configured to enable the PWM signals (PWM_1, PWM_2) for the first semiconductor switch (T1, T4) and the second semiconductor switch (T2, T3) via a first enable signal (En_Pos) and the PWM signals (PWM_1, PWM_2) for the third semiconductor switch (T2, T3) and the fourth semiconductor switch (T1, T4) via a second enable signal (En_Neg).

13. The circuit arrangement (1) as claimed in claim 11 or 12, wherein the drive circuit (12) is configured to set the first enable signal (En_Pos) when the difference between the voltage across the first DC-link capacitor (C1) and the voltage across the second DC-link capacitor (C2) exceeds a first threshold value (V1) and to reset it again when the difference between the voltage across the first DC-link capacitor (C1) and the voltage across the second DC-link capacitor (C2) falls below a second threshold value (V2), and is additionally configured to set the second enable signal (En_Neg) when the difference between the voltage across the second DC-link capacitor (C2) and the voltage across the first DC-link capacitor (C1) exceeds the first threshold value (V1) and to reset it again when the difference between the voltage across the second DC-link capacitor (C2) and the voltage across the first DC-link capacitor (C1) falls below the second threshold value (V2).

14. The circuit arrangement (1) as claimed in one of claims 11 to 13, wherein the drive circuit (12) is configured to synchronize enabling of the PWM signals (PWM_1, PWM_2) by the enable signals (En_Pos, En_Neg) with edges of the PWM signals (PWM_1, PWM_2).

15. The circuit arrangement (1) as claimed in one of claims 7 to 14, wherein the frequency of the PWM signals (PWM_1, PWM_2) is below the resonant frequency of a resonant circuit formed from the series circuit comprising the resonant capacitor (Cres) and the resonant inductor (Lres)