Subscriber station for a serial bus system and method for communication in a serial bus system

Description

Technical area

[0001] The present invention relates to a subscriber station for a serial bus system and a method for communication in a serial bus system that operates with a high data rate as well as great flexibility and high error robustness. State of the art

[0002] Bus systems for communication between sensors and control units, for example in vehicles, are designed to enable the transmission of large amounts of data, depending on the number of functions of a technical system or vehicle. This often requires data to be transmitted faster from sender to receiver than before, and large data packets to be able to be transmitted if necessary.

[0003] A bus system is currently being introduced in vehicles in which data is transmitted as messages in the ISO11898-1:2015 CAN protocol specification using CAN FD. The messages are transmitted between the bus users of the bus system, such as sensors, control units, encoders, etc. For this purpose, the message is sent on the bus in a frame in which two communication phases are switched. In the first communication phase (arbitration), it is negotiated which of the bus system users is allowed to send its frame on the bus in the subsequent second communication phase (data phase or sending of the payload data). CAN FD is initially used by most manufacturers in the vehicle with a 500 kbit / s arbitration bit rate and 2 Mbps data bit rate. This means that during transmission on the bus, it is necessary to switch back and forth between a slow operating mode and a fast operating mode.

[0004] EP 2 712 123 A1 describes a bus system that operates according to the ISO 11898-1:2003 standard CAN bus system (now called Classical CAN) and tolerates CAN FD frames. At the end of the data phase, all receivers in the network tolerate an additional bit time before and after an edge that transitions from a recessive to a dominant state on the bus and starts an ACK acknowledgment time slot.

[0005] To enable even higher data rates in the second communication phase, a successor bus system to CAN FD, called CAN XL, is currently being developed and is currently being standardized by the CAN in Automation (CiA) organization. In addition to pure data transport via the CAN bus, CAN XL is intended to support other functions, such as functional safety, data security, and quality of service (QoS). These are fundamental properties required in an autonomous vehicle.

[0006] CAN XL is intended to support high bit rates in the data phase, for example, up to 15 Mbit / s or even 20 Mbit / s. To achieve this, corresponding transceivers, so-called CAN XL transceivers, are currently being standardized. The operating mode of these transceivers can be switched to achieve the required high bit rates in the data phase. In contrast, the bit rate in the arbitration phase remains at approximately 500 kbit / s to enable arbitration. This means that CAN XL must support a very high bit rate ratio. A bit rate ratio of 40 is conceivable, which corresponds to 20 Mbit / s in the data phase (high bit rate) to 500 kbit / s in the arbitration phase (low bit rate).

[0007] With CAN XL, a communication control device signals the transceiver that the transceiver must switch its operating mode. For signaling, the communication control device, in particular its protocol controller, uses pulse-width modulation (PWM) coding. The transceiver is, in particular, a CAN SIC XL transceiver.

[0008] The problem is that the PWM coding in the communication control device and the corresponding PWM decoding in the transceiver device lead to a time delay.

[0009] It should also be noted that with CAN the clock pulses can have a certain tolerance.

[0010] An additional problem is that the three effects described above—high bit rate ratio, PWM encoding / decoding, and clock tolerance—combinedly result in a large phase error at a subscriber station that is currently only the receiver of a message transmitted over the bus. Such subscriber stations can also be referred to as receiving nodes.

[0011] In the worst case, a "fast" receiving node attempts to sample the first bit of the data phase (DH1 bit) before the DH1 bit has reached the receiving node, and / or a "slow" receiving node samples the DH1 bit only after the DH1 bit has already passed on the bus. In both cases, this results in an invalid frame at the receiving node. This reduces the net data rate that can be transmitted on the bus system, because some frames must be retransmitted.

[0012] This means that a phase error at a subscriber station means that the bit rate switching from low to high within the CAN frame cannot be performed correctly under all circumstances. However, without reliable bit rate switching, reliable and robust communication is not possible. Disclosure of the invention

[0013] Therefore, it is an object of the present invention to provide a subscriber station for a serial bus system and a method for communication in a serial bus system that solve the aforementioned problems. In particular, a subscriber station for a serial bus system and a method for communication in a serial bus system are to be provided in which a high degree of error-robustness of the communication can be achieved even at high data rates and an increase in the amount of payload data per frame.

[0014] The object is achieved by a subscriber station for a serial bus system having the features of claim 1. The subscriber station has a communication control device for controlling communication between the subscriber station and at least one other subscriber station of the bus system, so that for a message exchanged between subscriber stations of the bus system, the bit time of a signal sent on the bus in the first communication phase can differ from a bit time of a signal sent in the second communication phase, and a transmitting / receiving device for transmitting the transmit signal to a bus of the bus system, wherein the communication control device is designed to generate the transmit signal according to a frame and to insert a field with a rising edge and a subsequent falling edge into the frame for the transition from the first communication phase to the second communication phase.and wherein the field between the rising edge and the subsequent falling edge has a predetermined length, so that a sampling time at which a communication control device of the at least one other subscriber station of the bus system will sample the first bit of the second communication phase is arranged between the rising edge and the subsequent falling edge, as described in claim 1.

[0015] The design of the subscriber station provides a modified ADS field, ensuring that the bit rate switching from the low to the high bit rate within the CAN frame can be performed correctly under all circumstances. In particular, the bit rate switching during the transition from the first communication phase (arbitration phase) to the second communication phase (data phase) functions reliably, even with a high phase error. In particular, the subscriber station can correctly sample the first bit of the second communication phase (data phase) and then the subsequent bits of the second communication phase (data phase) despite the phase error.

[0016] The subscriber station enables reliable and robust communication with CAN XL. This applies even with extreme system parameter settings, such as clock tolerance, PWM symbol length, bit timing settings, or other bus system parameters.

[0017] Another advantage is that the described design of the subscriber station for solving the aforementioned task can be implemented in a simple and therefore cost-effective manner.

[0018] Thus, with the subscriber station in the bus system it is possible to maintain an arbitration known from CAN in an initial communication phase and yet to significantly increase the transmission rate compared to CAN or CAN FD.

[0019] The procedure performed by the subscriber station can also be used if the bus system also includes at least one CAN subscriber station and / or at least one CAN FD subscriber station that sends messages according to the CAN protocol and / or CAN FD protocol.

[0020] Advantageous further embodiments of the subscriber station are specified in the dependent claims.

[0021] It is possible that the predetermined length of the field has at least three bits with the bit time of the second communication phase.

[0022] The falling edge can define the beginning of a predetermined bit of the second communication phase. The edge can be provided for synchronizing communication on the bus for a communication control device of the at least one other subscriber station of the bus system.

[0023] It is conceivable that the communication control device is designed to insert the field as a bit sequence with the logical value 1110.

[0024] In one embodiment, the communication control device can be designed to insert a bit with the bit time of the first communication phase in the field before the falling edge and subsequently a bit with the bit time of the second communication phase, wherein the communication control device is designed to additionally insert a number of M bits with the bit time of the second communication phase following the bit with the bit time of the second communication phase, each of which has the same logical value 1 as the first bit of the second communication phase, and wherein M is a natural number greater than or equal to 1.

[0025] The communication control device can act as a receiving node in the second communication phase, so that the communication control device only acts as a receiver but not as a transmitter of the frame on the bus, wherein the communication control device is designed to tolerate, in the field from and including the sampling time at which the communication control device samples the first bit of the second communication phase and before the falling edge of the field, a number of N bits with the bit time of the second communication phase, each having the logical value 1, where N is a natural number greater than or equal to 1, and wherein the communication control device is designed to use the falling edge of the field to synchronize to the communication on the bus.

[0026] It is conceivable that the subscriber station additionally has the transmitting / receiving device for transmitting the transmission signal to a bus of the bus system, wherein the communication control device is designed to signal to the transmitting / receiving device by means of pulse width modulation in the transmission signal that the transmitting / receiving device has to switch its operating mode, as described in claims 1 and 7. In this case, the communication control device can be designed to signal to the transmitting / receiving device directly after the rising edge of the field by means of pulse width modulation in the transmission signal that the transmitting / receiving device has to switch its operating mode from the operating mode of the first communication phase to a different operating mode of the second communication phase, as described in claim 8.

[0027] In one embodiment, the communication control device of the transmitting / receiving device signals with S directly consecutive PWM symbols in the transmission signal to which operating mode of the second communication phase the transmitting / receiving device has to switch its operating mode, where S is a natural number greater than or equal to 1.

[0028] According to one embodiment, the communication control device is configured to send at least the last part of a bit having the bit time of the first communication phase with the same logical value as the first bit in the field having the bit time of the second communication phase.

[0029] According to another embodiment, the transmitting / receiving device is configured to transmit the entire frame to the bus in the operating mode for transmitting and receiving the frame in the first communication phase.

[0030] It is possible that the frame created for the message is constructed in a way that is compatible with CAN FD, whereby in the first communication phase it is negotiated which of the participant stations of the bus system will receive at least temporarily exclusive, collision-free access to the bus in the subsequent second communication phase.

[0031] The previously described subscriber station can be part of a bus system that also comprises a bus and at least two subscriber stations connected to each other via the bus in such a way that they can communicate with each other serially. At least one of the at least two subscriber stations is a previously described subscriber station.

[0032] The aforementioned object is also achieved by a method for communication in a serial bus system according to claim 14. The method is carried out with a subscriber station of the bus system, which has a communication control device and a transmitting / receiving device, wherein the method comprises the steps of controlling, with the communication control device, communication of the subscriber station with at least one other subscriber station of the bus system, so that for a message exchanged between subscriber stations of the bus system, the bit time of a signal sent on the bus in the first communication phase can differ from a bit time of a signal sent in the second communication phase, and transmitting, with the transmitting / receiving device, the transmitted signal to a bus of the bus system,wherein the communication control device generates the transmission signal according to a frame and inserts into the frame a field with a rising edge and a subsequent falling edge for the transition from the first communication phase to the second communication phase, and wherein the field between the rising edge and the subsequent falling edge has a predetermined length, so that a sampling time at which a communication control device of the at least one other subscriber station of the bus system will sample the first bit of the second communication phase is arranged between the rising edge and the subsequent falling edge, as described in claim 14.

[0033] The method offers the same advantages as previously mentioned with regard to the subscriber station.

[0034] Further possible implementations of the invention also include combinations of features or embodiments described above or below with respect to the exemplary embodiments not explicitly mentioned. In this case, the person skilled in the art will also add individual aspects as improvements or additions to the respective basic form of the invention. Drawings

[0035] The invention is described in more detail below with reference to the accompanying drawings and exemplary embodiments. They show: Fig. 1 a simplified block diagram of a bus system according to a first embodiment; Fig. 2 a diagram illustrating the structure of a message that can be sent by a subscriber station of the bus system according to the first embodiment; Fig. 3 a simplified schematic block diagram of a subscriber station of the bus system according to the first embodiment; Fig. 4 a time course of bus signals CAN-XL_H and CAN-XL_L at the subscriber station according to the first embodiment; Fig. 5 a time profile of a differential voltage VDIFF of the bus signals CAN-XL_H and CAN-XL_L at the subscriber station according to the first embodiment; Fig. 6 bis Fig. 8 in each case a time profile of a signal which occurs during the transmission of a frame at terminals of the subscriber station according to the first exemplary embodiment, when the subscriber station is the sender of the message, during the transmission of which a switching of the operating mode of the transmitting / receiving device is carried out; Fig. 9 the temporal progression of signal states that a receiving node expects as a received signal at its receiving terminal when another subscriber station is the sender of the message and thus sends signals according to Fig. 6 bis Fig. 8 generated; Fig. 10 und Fig. 11 each a time profile of a signal that occurs during the transmission of a frame at terminals of a subscriber station according to a second embodiment, when the subscriber station is the sender of the message, during the transmission of which no switching of the operating mode of the transmitting / receiving device is carried out; and Fig. 12 the temporal progression of signal states that a receiving node expects as a received signal at its receiving terminal when another subscriber station is the sender of the message and thus sends signals according to Fig. 10 und Fig. 11 generated.

[0036] In the figures, identical or functionally equivalent elements are provided with the same reference numerals unless otherwise indicated. Description of the embodiments

[0037] Fig. 1 shows, as an example, a bus system 1, which is fundamentally designed, in particular, for a CAN bus system, a CAN FD bus system, a CAN XL bus system, and / or modifications thereof, as described below. The bus system 1 can be used in a vehicle, in particular a motor vehicle, an aircraft, etc., or in a hospital, etc.

[0038] In Fig. 1 The bus system 1 has a plurality of subscriber stations 10, 20, 30, each of which is connected to a bus 40 with a first bus wire 41 and a second bus wire 42. The bus wires 41, 42 can also be called CAN_H and CAN_L or CAN-XL_H and CAN-XL_L and are used for electrical signal transmission after coupling in the dominant levels or generating recessive levels or other levels for a signal in the transmit state. Messages 45, 46 in the form of signals can be serially transmitted between the individual subscriber stations 10, 20, 30 via the bus 40. If an error occurs during communication on the bus 40, as indicated by the jagged black block arrow in Fig. 1 As shown, an error frame 47 (error flag) can optionally be sent. Participant stations 10, 20, 30 are, for example, control units, sensors, display devices, etc. of a motor vehicle.

[0039] As in Fig. 1 As shown, the subscriber station 10 has a communication control device 11, a transmitting / receiving device 12 and a phase error compensation module 15. The subscriber station 20 has a communication control device 21, a transmitting / receiving device 22 and optionally a phase error compensation module 25. The subscriber station 30 has a communication control device 31, a transmitting / receiving device 32 and a phase error compensation module 35. The transmitting / receiving devices 12, 22, 32 of the subscriber stations 10, 20, 30 are each directly connected to the bus 40, even if this is not the case in Fig. 1 is not illustrated.

[0040] The communication control devices 11, 21, 31 each serve to control communication of the respective subscriber station 10, 20, 30 via the bus 40 with at least one other subscriber station of the subscriber stations 10, 20, 30 that are connected to the bus 40.

[0041] The communication control devices 11, 31 create and read first messages 45, which are, for example, modified CAN messages 45. The modified CAN messages 45 are constructed on the basis of a CAN XL format, which with respect to Fig. 2 is described in more detail, and in which the respective phase error compensation module 15, 35 is used. The communication control devices 11, 31 can also be designed to provide a CAN XL message 45 or a CAN FD message 46 for the transmitting / receiving device 32 or to receive one from it, as required. The respective phase error compensation modules 15, 35 are also used here. The communication control devices 11, 31 thus create and read a first message 45 or a second message 46, wherein the first and second messages 45, 46 differ in their data transmission standard, namely CAN XL or CAN FD in this case.

[0042] The communication control device 21 can be designed like a conventional CAN controller according to ISO 11898-1:2015, i.e., like a CAN FD-tolerant Classical CAN controller or a CAN FD controller. Additionally, the phase error compensation module 25, which has the same function as the phase error compensation modules 15, 35, is optionally present. The communication control device 21 creates and reads second messages 46, for example, CAN FD messages 46. The CAN FD messages 46 can include a number of 0 to 64 data bytes, which are also transmitted at a significantly faster data rate than a Classical CAN message. In particular, the communication control device 21 is designed like a conventional CAN FD controller.

[0043] The transceiver 22 can be designed as a conventional CAN transceiver according to ISO 11898-1:2015 or CAN FD transceiver. The transceivers 12, 32 can be designed to provide messages 45 according to the CAN XL format or messages 46 according to the current CAN FD format to or receive them from the associated communication control device 11, 31, as required.

[0044] With the two subscriber stations 10, 30, the formation and then transmission of messages 45 with the CAN XL format as well as the reception of such messages 45 is possible.

[0045] Fig. 2 shows a CAN XL frame 450 for the message 45, as provided by the communication control device 11 for the transmitting / receiving device 12 for transmission on the bus 40. In this case, the communication control device 11 creates the frame 450 in the present embodiment as compatible with CAN FD, as in Fig. 2 The same applies analogously to the communication control device 31 and the transmitting / receiving device 32 of the subscriber station 30.

[0046] According to Fig. 2 The CAN XL frame 450 for CAN communication on bus 40 is divided into different communication phases 451, 452, namely an arbitration phase 451 and a data phase 452. After a start bit (SOF), the frame 450 has an arbitration field 453, a control field 454 with an ADS field for switching between the communication phases 451, 452, a data field 455, a checksum field 456, and a frame termination field 457 containing a DAS field for switching between the communication phases 452, 451. This is followed by an end-of-frame field EOF.

[0047] In the arbitration phase 451, using an identifier (ID) with, for example, bits ID28 to ID18 in the arbitration field 453, the subscriber stations 10, 20, 30 negotiate bit by bit to determine which subscriber station 10, 20, 30 wishes to send the message 45, 46 with the highest priority and therefore receives exclusive access to the bus 40 of the bus system 1 for the next transmission time in the subsequent data phase 452. In the arbitration phase 451, a physical layer is used, similar to CAN and CAN-FD. The physical layer corresponds to the physical layer or layer 1 of the well-known OSI model (Open Systems Interconnection Model).

[0048] An important point during phase 451 is the use of the well-known CSMA / CR method, which allows simultaneous access of subscriber stations 10, 20, and 30 to bus 40 without destroying the higher-priority message 45, 46. This allows additional bus subscriber stations 10, 20, and 30 to be added to bus system 1 relatively easily, which is very advantageous.

[0049] The CSMA / CR method requires so-called recessive states on bus 40, which can be overwritten by other subscriber stations 10, 20, or 30 with dominant states on bus 40. In the recessive state, high-impedance conditions prevail at the individual subscriber stations 10, 20, or 30, which, in combination with the parasitics of the bus circuitry, results in longer time constants. This limits the maximum bit rate of today's CAN FD physical layer to approximately 2 megabits per second in real-world vehicle use.

[0050] In the data phase 452, in addition to a portion of the control field 454, the payload of the CAN-XL frame or message 45 from the data field 455 and the checksum field 456 are sent. This is followed by the DAS field, which serves to switch from the data phase 452 back to the data phase 451.

[0051] A sender of the message 45 begins sending bits of the data phase 452 to the bus 40 only when the subscriber station 10 as the sender has won the arbitration and the subscriber station 10 as the sender thus has exclusive access to the bus 40 of the bus system 1 for sending.

[0052] In general, the following different properties can be realized in the bus system with CAN XL compared to CAN or CAN FD: a) Adoption and, where necessary, adaptation of proven properties that are responsible for the robustness and user-friendliness of CAN and CAN FD, in particular frame structure with identifier and arbitration according to the CSMA / CR procedure, b) Increasing the net data transmission rate, in particular to approximately 10 megabits per second, c) Increasing the size of the payload data per frame, in particular to approximately 2 kbyte or any other value.

[0053] As in Fig. 2 As shown, in the arbitration phase 451 as the first communication phase, the subscriber station 10 partially uses, in particular up to and including the FDF bit, a format known from CAN / CAN-FD according to ISO11898-1:2015. In contrast, the subscriber station 10 uses a CAN XL format, which is described below, starting with the FDF bit in the first communication phase and in the second communication phase, the data phase 452.

[0054] In the present embodiment, CAN XL and CAN FD are compatible. The res bit known from CAN FD, referred to below as the XLF bit, is used to switch from the CAN FD format to the CAN XL format. Therefore, the frame formats of CAN FD and CAN XL are identical up to the res bit or XLF bit. A receiver only recognizes the format in which frame 450 is being transmitted at the res bit. A CAN XL subscriber station, i.e., subscriber stations 10 and 30 in this case, also supports CAN FD.

[0055] Alternatively to the Fig. 2 In addition to the frame 450 shown, which uses an 11-bit identifier ID28 to ID18, a CAN XL Extended Frame Format is optionally available, which uses a 29-bit identifier. This is identical to the familiar CAN FD Extended Frame Format from ISO11898-1:2015, up to the FDF bit.

[0056] According to Fig. 2 Frame 450 from the SOF bit up to and including the FDF bit is identical to the CAN FD Base Frame Format according to ISO11898-1:2015. Therefore, the known structure is not explained further here. Bits that are marked on their lower line in Fig. 2 represented by a thick line are sent as dominant or '0' in frame 450. Bits that are on their upper line in Fig. 2 represented by a thick line are transmitted in frame 450 as recessive or '1'. In the CAN XL data phase 452, symmetric '1' and '0' levels are used instead of recessive and dominant levels.

[0057] Generally, two different stuffing rules are applied when generating frame 450. Up to the FDF bit in the arbitration field 453, the dynamic bit stuffing rule of CAN FD applies, so that an inverse stuff bit is inserted after every five consecutive identical bits. In the data phase 452 up to the FCP field, a fixed stuffing rule applies, so that a fixed stuff bit is inserted after a fixed number of bits. Alternatively, two or more bits can be inserted as fixed stuff bits instead of just one.

[0058] In frame 450, the XLF bit follows directly after the FDF bit, which corresponds in position to the "res bit" in the CAN FD Base Frame Format, as mentioned above. If the XLF bit is sent as 1, i.e., recessive, it identifies frame 450 as a CAN XL frame. For a CAN FD frame, the communication controller 11 sets the XLF bit to 0, i.e., dominant.

[0059] After the XLF bit in frame 450, a resXL bit follows, which is a dominant bit for future use. The resXL must be sent as 0, i.e., dominant, for frame 450. However, if subscriber station 10 receives a resXL bit as 1, i.e., recessive, the receiving subscriber station 10 enters a protocol exception state, for example, as is the case with a CAN FD message 46 for res=1. Alternatively, the resXL bit could be defined the other way around, meaning it must be sent as 1, i.e., recessive. In this case, the receiving subscriber station enters the protocol exception state with a dominant resXL bit.

[0060] After the resXL bit, frame 450 is followed by an ADS (Arbitration Data Switch) sequence in which a predetermined bit sequence is encoded. This bit sequence allows for a simple and secure switchover from the bit rate of the arbitration phase 451 (arbitration bit rate) to the bit rate of the data phase 452 (data bit rate). Optionally, the physical layer in the transceiver device 12, 22, 32 is switched within the ADS field. In this case, the operating mode of the transceiver device 12, 32 is also switched during the ADS sequence. The bit sequence of the ADS field has an AL1 bit, which is transmitted as a logical 1, at least in its last part, for example, the last 50% of the bit. The AL1 bit is the last bit of the arbitration phase 451. The three following bits DH1, DH2, and DL1 are already transmitted at the data bit rate. Thus, bits DH1, DH2, and DL1 in CAN XL are short-term bits of data phase 452. Bits DH1 and DH2 each have the logical value 1.The last bit is bit DL1, which has the logical value 0. After the bit rate switchover, the receiving nodes synchronize to the falling edge of bit DL1. The ADS field is used to transition from the first communication phase 451 to the second communication phase 452.

[0061] Following the ADS sequence in frame 450 is an SDT field that identifies the content of data field 455. The content of the SDT field specifies what type of information is contained in data field 455. For example, the SDT field specifies whether data field 455 contains an Internet Protocol (IP) frame, a tunneled Ethernet frame, or something else.

[0062] The SDT field is followed by a SEC field, which indicates whether frame 450 is secured with the CAN security protocol or not. The SEC field is 1 bit wide and, like the SDT field, serves to indicate what type of information is contained in data field 455.

[0063] The SEC field is followed by a DLC field containing the data length code (DLC), which specifies the number of data bytes in data field 455 of frame 450. The data length code (DLC) can have any value from 1 up to the maximum number of bytes in the data field 455, or data field length. If the maximum data field length is 2048 bits, the data length code (DLC) requires 11 bits, assuming that DLC = 0 means a data field length of 1 byte and DLC = 2047 means a data field length of 2048 bytes. Alternatively, a data field 455 of length 0 could be permitted, as in CAN, for example. Here, DLC = 0 would encode the data field length with a number of 0 bytes. The maximum codable data field length of 11 bits, for example, is then (2 11< )-1 = 2047.

[0064] Following the DLC field in frame 450 is an SBC bit counter field (Stuff Bit Count). This field specifies the number of dynamic stuff bits transmitted in arbitration field 453. A receiving node uses the information in the SBC bit counter field to check whether the receiving node has received the correct number of dynamic stuff bits.

[0065] Following the SBC bit counter field is a preamble checksum (PCRC), also called a preface CRC. The preamble checksum (PCRC) is a checksum for securing the frame format of the 450 frame, i.e., all variable bits from the beginning of the 450 frame with the SOF bit to the beginning of the preamble checksum (PCRC), including all dynamic and optionally fixed stuff bits up to the beginning of the preamble checksum (PCRC). The length of the preamble checksum (PCRC) and thus of the checksum polynomial according to the cyclic redundancy check (CRC) must be selected according to the desired Hamming distance.

[0066] After the preamble checksum PCRC, a VCID (Virtual CAN Bus ID) field follows in frame 450. The VCID field is 1 byte long. The VCID field contains the number of a virtual CAN bus.

[0067] Following the VCID field in frame 450 is an AF (Acceptance Field). The AF field is 32 bits long. The AF field contains an address or other value for acceptance filtering.

[0068] Following the AF field in frame 450 is the data field 455. The data field 455 consists of P bytes B, where P is encoded in the DLC field as previously described. P is a natural number greater than or equal to 1.

[0069] After the data field 455, the checksum field 456 follows in the frame 450, containing a frame checksum FCRC and an FCP field. The frame checksum FCRC consists of the bits of the frame checksum FCRC. The length of the frame checksum FCRC and thus of the CRC polynomial must be selected according to the desired Hamming distance. The frame checksum FCRC secures the entire frame 450. Alternatively, only the data field 455 can be secured with the frame checksum FCRC.

[0070] After the frame checksum FCRC, the FCP field follows in frame 450. FCP stands for Frame Check Pattern. The FCP field consists of 4 bits, specifically the bit sequence 1100. A receiving node uses the FCP field to check whether the receiving node is bit-synchronized with the transmit data stream. Furthermore, a receiving node synchronizes itself to the falling edge in the FCP field.

[0071] The FCP field is followed by the frame termination field 457. The frame termination field 457 consists of two fields, namely the DAS field and the acknowledgment field or ACK field with at least one ACK bit and the ACK-Dlm bit.

[0072] The DAS field contains the DAS (Data Arbitration Switch) sequence, in which a predetermined bit sequence is encoded. The bit sequence DAH, AH1, AL2 allows a simple and secure switch from the data bit rate of the data phase 452 to the arbitration bit rate of the arbitration phase 451. Furthermore, during the DAS field, the operating mode of the transmitting / receiving device 12, 32 is switched, optionally from FAST to SLOW mode. The DAS field has Fig. 2 the bits DAH, AH1, AL2, AH2. The bit AH2 at the end of the DAS field is optional. The bit AH2 serves to maintain a distance from the acknowledgment field (ACK). The DAS field has at least three bits. For example, the bit sequence of the DAS sequence has an arbitration bit DAH and an arbitration bit AH1, each with the logical value 1. Within the DAH bit, the physical layer, i.e., the operating mode of the transceiver device 12, 32, is switched from FAST_TX or FAST_RX to SLOW. The AH1 bit is followed by the AL2 bit (logical 0) and the AH2 bit (logical 1). The two bits DAH and AH1 ensure that there is enough time for the operating mode switching of the transmitting / receiving device 11 and that all subscriber stations 10, 30 see a recessive level of significantly more than one arbitration bit time before the edge at the beginning of the AL2 bit (logical 0).This ensures secure synchronization of the subscriber stations of the bus system, which are currently reintegrating into communication on the bus.

[0073] In the frame termination field 457, the DAS field sequence is followed by the acknowledgment field (ACK). The acknowledgment field contains bits for confirming or denying the correct reception of frame 450. In the example of Fig. 2 An ACK bit and an ACK-dlm bit are provided. Optionally, a NACK bit and a NACK-dlm bit can also be present. The receiving subscriber stations 10, 30 send the ACK bit as dominant if they have received frame 450 correctly. The transmitting subscriber station sends the ACK bit as recessive. Therefore, the bit originally sent in frame 450 on bus 40 can be overwritten by the receiving subscriber stations 10, 30. The ACK-dlm bit is sent as a recessive bit, which serves to separate it from other fields. The NACK bit and the NACK-dlm bit allow a receiving subscriber station to signal incorrect reception of frame 450 on bus 40. The function of the bits is the same as that of the ACK bit and the ACK-dlm bit.

[0074] After the frame termination field 457, an end-of-frame (EOF) field follows in frame 450. The bit sequence of the end-of-frame (EOF) serves to mark the end of frame 450. The end-of-frame (EOF) field ensures that a number of 8 recessive bits are sent at the end of frame 450. This is a bit sequence that cannot occur within frame 450. This allows subscriber stations 10, 20, and 30 to reliably detect the end of frame 450.

[0075] The end of field (EOF) has a length that varies depending on whether a dominant or recessive bit was seen in the ACK bit. If the transmitting station received the ACK bit as dominant, the end of field (EOF) has 7 recessive bits. Otherwise, the end of field (EOF) is only 5 recessive bits long.

[0076] After the end field (EOF) in frame 450 there follows an inter-frame space (IFS - Inter Frame Space), which is Fig. 2 is not shown. This interframe spacing (IFS) is designed as in CAN FD according to ISO11898-1:2015.

[0077] Fig. 3 shows the basic structure of the subscriber station 10 with the communication control device 11, the transmitting / receiving device 12 and the phase error compensation module 15, which is part of the communication control device 11. The subscriber station 30 is constructed in a similar manner as in Fig. 3 shown, however, the phase error compensation module 35 is according to Fig. 1 arranged separately from the communication control device 31 and the transmitting / receiving device 32. Therefore, the subscriber station 30 will not be described separately.

[0078] According to Fig. 3 In addition to the communication control device 11 and the transceiver device 12, the subscriber station 10 has a microcontroller 13, to which the communication control device 11 is assigned, and a system ASIC 16 (ASIC = Application-Specific Integrated Circuit), which can alternatively be a system base chip (SBC) on which several functions necessary for an electronic module of the subscriber station 10 are combined. In addition to the transceiver device 12, the system ASIC 16 contains a power supply device 17, which supplies the transceiver device 12 with electrical power. The power supply device 17 typically supplies a CAN_Supply voltage of 5 V. However, depending on requirements, the power supply device 17 can supply a different voltage with a different value. Additionally or alternatively, the power supply device 17 can be designed as a current source.

[0079] The phase error compensation module 15 has an insertion block 151, which inserts a predetermined ADS field 1510 into the frame 450, and a signaling block 152. The blocks 151, 152 are described in more detail below.

[0080] The transmitting / receiving device 12 also has a transmitting module 121 and a receiving module 122. Although the following always refers to the transmitting / receiving device 12, it is alternatively possible to provide the receiving module 122 in a separate device external to the transmitting module 121. The transmitting module 121 and the receiving module 122 can be constructed as in a conventional transmitting / receiving device 22. The transmitting module 121 can, in particular, have at least one operational amplifier and / or one transistor. The receiving module 122 can, in particular, have at least one operational amplifier and / or one transistor.

[0081] The transceiver device 12 is connected to the bus 40, more precisely to its first bus wire 41 for CAN_H or CAN-XL_H and its second bus wire 42 for CAN_L or CAN-XL_L. The voltage supply for the power supply device 17, which supplies the first and second bus wires 41, 42 with electrical energy, in particular the CAN supply voltage, is provided via at least one terminal 43. The connection to ground or CAN_GND is realized via a terminal 44. The first and second bus wires 41, 42 are terminated with a terminating resistor 49.

[0082] The first and second bus wires 41, 42 are connected in the transmitting / receiving device 12 not only to the transmitting module 121, which is also referred to as transmitter, but also to the receiving module 122, which is also referred to as receiver, even if the connection in Fig. 3 not shown for simplicity.

[0083] During operation of the bus system 1, the transmitting module 121 converts a transmitting signal TXD or TxD of the communication control device 11 into corresponding signals CAN-XL_H and CAN-XL_L for the bus wires 41, 42 and transmits these signals CAN-XL_H and CAN-XL_L to the terminals for CAN_H and CAN_L on the bus 40.

[0084] The receiving module 122 forms from the bus 40 received signals CAN-XL_H and CAN-XL_L according to Fig. 4 a receive signal RXD or RxD and forwards it to the communication control device 11, as shown in Fig. 3 shown. With the exception of an idle or standby state, the transmitting / receiving device 12 with the receiving module 122 always listens for a transmission of data or messages 45, 46 on the bus 40 during normal operation, regardless of whether the transmitting / receiving device 12 is the sender of the message 45 or not.

[0085] According to the example of Fig. 4 The signals CAN-XL_H and CAN-XL_L have the dominant and recessive bus levels 401, 402, as known from CAN, at least in the arbitration phase 451. On the bus 40, a difference signal VDIFF = CAN-XL_H - CAN-XL_L is formed, which Fig. 5 for the arbitration phase 451. The individual bits of the signal VDIFF with the bit time t_bt1 can be detected in the arbitration phase 451 with a reception threshold T_a of, for example, 0.7 V. In the data phase 452, the bits of the signals CAN-XL_H and CAN-XL_L are sent faster, i.e. with a shorter bit time t_bt2, than in the arbitration phase 451. This can be seen from Fig. 6 bis Fig. 9 described in more detail. Thus, the CAN-XL_H and CAN-XL_L signals in data phase 452 differ from the conventional CAN_H and CAN_L signals at least in their faster bit rate.

[0086] The sequence of states 401, 402 for the signals CAN-XL_H, CAN-XL_L in Fig. 4 and the resulting voltage curve VDIFF of Fig. 5 serves only to illustrate the function of subscriber station 10. The sequence of data states for bus states 401, 402 can be selected as required.

[0087] In other words, the transmitting module 121, when switched to a first operating mode B_451 (SLOW), generates according to Fig. 4 a first data state as bus state 402 with different bus levels for two bus wires 41, 42 of the bus line and a second data state as bus state 401 with the same bus level for the two bus wires 41, 42 of the bus line of the bus 40.

[0088] In addition, the transmit module 121 transmits the bits at a higher bit rate to bus 40 for the timing of the CAN-XL_H and CAN-XL_L signals in a second operating mode, B_452_TX (FAST_TX), which includes the data phase 452. The CAN-XL_H and CAN-XL_L signals can also be generated in the data phase 452 using a different physical layer than in CAN FD. This allows the bit rate in the data phase 452 to be increased even further than in CAN FD. A subscriber station that is not a transmitter of frame 450 in the data phase 452 sets a third operating mode, B_452_RX (FAST_RX), in its transmit / receive device.

[0089] To signal the switchover from B_451 mode to B_452_TX (FAST_TX) or B_452_RX (FAST_RX) mode, the communication control device 11 performs pulse width modulation (PWM) of the transmit signal TxD. For this purpose, the communication control device 11 uses one or more PWM symbols per logical bit of the CAN XL frame 450. Generally, a PWM symbol consists of two phases: a 0 phase and a 1 phase. Furthermore, a PWM symbol is delimited by two identical edges, for example, two rising edges.

[0090] The phase error compensation module 15 from Fig. 3 , in particular its insertion block 151, serves to insert the ADS field 1510 into the frame 450 when the subscriber station 10 acts as the transmitter of the frame 450. Furthermore, the phase error compensation module 15, in particular its signaling block 152, can perform pulse width modulation (PWM), as described below for switching between the operating modes B_451 (SLOW) and B_452_TX (FAST_TX).

[0091] Fig. 6 shows the resulting digital transmission signal TxD over time t in the area of ​​switching from the arbitration phase 451 to the data phase 452 of a frame 450, in other words during the transition from phase 451 to phase 452. In frame 450, the ADS field 1510 is inserted after the bit resXL. The transmission signal TxD is sent serially by the communication control device 11 as the transmitter of the frame 450 to the transceiver device 12, as described in more detail below. Up to and including bit AL1, the bits of frame 450 have a bit duration t_bt1. From bit DH1, the first bit of the data phase 452, the bits of frame 450 have a bit duration t_bt2. The bit duration t_b2 in the example of Fig. 6 shorter than the bit duration t_bt1.

[0092] As in Fig. 1 As shown, the AL1 bit is sent with the logical value 1 in the present embodiment.

[0093] Fig. 7 shows the states resulting from the transmission signal TxD over time t, which occur serially at the connection TXD between the communication control device 11 and the transmitting / receiving device 12. For this purpose, the communication control device 11, for example the phase error compensation module 15, in particular the signaling block 152, carries out the pulse width modulation (PWM) of the transmission signal TxD in the data phase 452 from Fig. 6 More precisely, the pulse width modulation (PWM) of the transmit signal TxD starts from Fig. 6 with the AL1 bit. In the arbitration phase 451 before the AL1 bit, no pulse width modulation (PWM) of the transmit signal TxD occurs.

[0094] At the end of the arbitration phase 451, the transmitting / receiving device 12 recognizes, based on the high frequency of the signal edges at the TXD terminal, that the transmitting / receiving device 12 should switch from the arbitration phase operating mode B_451 to one of the fast operating modes B_452_TX (FAST_TX) or B_452_RX (FAST_RX), or should remain there. Based on the value of the first PWM symbol or the first S symbols, the transmitting / receiving device 12 recognizes whether it should switch to the B_452_TX (FAST_TX) or B_452_RX (FAST_RX) operating mode. S is a natural number greater than or equal to 1. Due to the PWM coding performed, the signal at the TXD terminal is delayed by a time period T_V1 compared to the TxD signal. The signaling block 152 generates the first S PWM symbols according to the operating mode to which the transceiver is to be switched and not depending on the value of the AL1 bit.

[0095] In the example in Fig. 7 For a PWM symbol SB_D0, the 0 phase is longer than the 1 phase, which corresponds to a bit in the data phase 452 with a logical value of 0 in the transmit signal TxD. In contrast, for a PWM symbol SB_D1, the 1 phase is longer than the 0 phase, which corresponds to a bit with a logical value of 1. Of course, the PWM symbols SB_D0 and SB_D1 can be defined differently, in particular, exactly the other way around as described above.

[0096] In addition, the first two PWM symbols in the signal at the TXD terminal in the example of Fig. 7 the logical value 0 (SB_D0). The transceiver 12, 32 evaluates the first two PWM symbols to decide which operating mode the transceiver 12, 32 should switch to. In the present example of Fig. 7 The transmitting / receiving device 12, 32 of the transmitting node should switch to the B_452_TX (FAST_TX) operating mode based on the two PWM symbols with the logical value 0. Switching to the B_452_RX (FAST_RX) operating mode is signaled by at least one different value of the first two PWM symbols in the AL1 bit.

[0097] As in Fig. 7 As shown, the communication control device 11, for example the phase error compensation module 15, in particular the signaling block 152, carries out the subsequent pulse width modulation (PWM) of the AL1 bit of the transmission signal TxD from Fig. 6 in such a way that all subsequent PWM symbols of the AL1 bit are transmitted with the logical value 1. Thus, in the second part of the AL1 bit, the part after the signaling of the type of operating mode B_452 of the transceiver device 12, 32 for the data phase 452, only symbols SB_D1 are present.

[0098] After the data phase 452, the pulse width modulation (PWM) of the transmit signal TxD ends, since no pulse width modulation (PWM) of the transmit signal TxD occurs during the arbitration phase 451, as previously described. The switchover from the B_452_TX (FAST_TX) or B_452_RX (FAST_RX) FAST_RX operating modes to the B_451 (SLOW) operating mode is signaled by deactivating the PWM coding and thus by the absence of multiple edges.

[0099] Fig. 8 shows the time course of a signal TxD_TC, which is generated by the transmitting / receiving device 12 from the states at the terminal TXD of Fig. 7 was decoded. In the example of Fig. 8 The transmitting / receiving device 12 switches its operating mode B_451, in which the frame has 450 bits with a bit duration of t_bt1, to the operating mode B_452_TX (FAST_TX) in the bit AL1, in which the frame has 450 bits with a bit duration of t_bt2. Furthermore, the bits of frame 450 can be transmitted to the bus 40 in the operating mode B_451 with a different physical layer than in the operating mode B_452_TX, as previously described.

[0100] The transmitting / receiving device 12 thus decodes the states at the terminal TXD of Fig. 7 into the signal TxD_TC according to Fig. 8 . For the AL1 bit, the first part AL1_0 of the AL1 bit results in a logical value of 0. For the second and last part AL1_1 of the AL1 bit in Fig. 8 results in a logical value of 1.

[0101] Each of the PWM symbols SB_D0, SB_D1 at the TXD terminal can only be decoded at the end of the respective PWM symbol SB_D0, SB_D1. Thus, the decoding in the transceiver 12 inserts an additional delay time T_V2 into the signal TxD_TC to be sent serially on the bus 40. The delay time T_V2 is equal to the duration of one symbol length of one of the PWM symbols SB_D0, SB_D1, as shown in Fig. 8 The phase error T_P, which is generated once in the transmitting station by the PWM encoding and decoding, is T_P = T_V1 + T_V2.

[0102] After the transmitting / receiving device 12 has detected the states at the terminal TXD from Fig. 7 into the signal TxD_TC according to Fig. 8 decoded, the transceiver 12 sends the signal TxD_TC to the bus 40 as the differential voltage VDIFF.

[0103] Fig. 9 shows the course of a signal RxD_E over time t, which the receiving subscriber station (receiving node), in particular its communication control device, expects at its RXD connection. Here, the receiving subscriber station (receiving node), in particular its communication control device, does not expect a predetermined value for the bit AL1, as indicated by the hatching in Fig. 9 In other words, the value for bit AL1 can be logic 1 or logic 0. Furthermore, the receiving subscriber station (receiving node), in particular its communication control device, samples bit DH1, the first bit of data phase 452, at a sampling time t1.

[0104] According to Fig. 9 is a large phase error T_P1 = T_V1 + T_V2 + "Phase error due to clock tolerance" between the expected receive signal RxD_E of Fig. 8 and the actual received signal, which is identical to the signal TxD_TC of Fig. 8 T_P1 is the distance from the beginning of the DH1 bit in Fig. 9 to the beginning of the DH1 bit in Fig. 8 However, the signal propagation time, especially via bus 40, is not taken into account and Fig. 6 bis Fig. 9 not shown because the signal propagation time has no influence on the phase error T_P1.

[0105] Despite the large phase error T_P1, the receiving node correctly samples the bit DH1, the first bit of the data phase 452, as logical 1. The reason for this is that the bit AL1 in its last part AL1_1 is already sent with the logical value 1, as can be seen in the comparison of Fig. 8 und Fig. 9 recognizable.

[0106] In addition, a receiving node tolerates, starting with the bit position of DH1, a number of 1 to N consecutively sampled bits with the logical value 1. N is a natural number greater than or equal to 1. In other words, after receiving the DH1 bit as a logical 1, the receiving node tolerates the receiving node sampling an additional zero to N - 1 bits of the second communication phase 452 with the logical value 1 before the receiving node detects the falling edge in the ADS field. For the bit rate ratios targeted for CAN XL, as previously described in relation to the task to be solved, and the expected phase errors, a value of N = 5 is advantageous or reasonable.

[0107] The next falling edge after the DH1 bit signals the beginning of the DL1 bit to the receiving node. All receiving nodes synchronize to this next falling edge after the DH1 bit.

[0108] As in Fig. 6 bis Fig. 9 shown, the phase error compensation module 15 of Fig. 3 Thus, in the present exemplary embodiment, the ADS field is configured such that it has an AL1 bit at its beginning, which is transmitted as a logical 1 at least in its last part AL1_1, which may, for example, correspond to more than 50% of the AL1 bit. Based on signaling in the first part AL1_1 of the AL1 bit, the transmitting / receiving device 12 switches its operating mode from the B_451 (SLOW) operating mode to the B_452_TX (FAST_TX) operating mode.

[0109] As a result, the ADS field is designed in such a way that it is ensured that not only the first bit DH1 of the data phase 452 can be sampled correctly, but also a synchronization between the transmitting node and the receiving node is carried out so that all bits of the data phase from the DL1 bit onwards can be sampled correctly.

[0110] Fig. 10 bis Fig. 12 show time profiles according to a second embodiment, which differ in the following aspects from the time profiles of Fig. 6 bis Fig. 10 differentiate.

[0111] In contrast to the first embodiment, in the second embodiment, no mode switching of the transceiver devices 12, 32 takes place. This applies in particular to the change between the communication phases 451, 452. As a result, no pulse width modulation (PWM) is used for coding the signaling in the transmission signal TxD of Fig. 10 which the associated communication control device 11, 31, in particular its protocol controller, has generated.

[0112] Thus, the signal TxD_TC is Fig. 11 , which the transceiver 12, 32 drives as differential voltage VDIFF on the bus 40 when the transceiver 12, 32 acts as a transmitting node, identical to the transmit signal TxD of Fig. 10 Since no PWM coding and therefore no decoding takes place, no one-time phase error T_P is generated between the transmit signal TxD_TC in the transceiver 12, 32 and the transmit signal TxD. Signal propagation times are in Fig. 10 bis Fig. 12 not shown because they have no influence on the phase error T_P0 and are therefore not relevant here.

[0113] In order to robustly carry out the switchover from the first communication phase 451 to the second communication phase 452 despite a possible large phase error T_P0 between a transmitting and receiving node, the communication control device 11, 31, in particular its protocol controller, proceeds as follows.

[0114] As in Fig. 10 As shown, the communication control device 11, 31, in particular its protocol controller, inserts at least one additional bit, or 1 to M additional bits, directly after the bit DH1, which have the same value as the first bit DH1 of the data phase 452. In the example of Fig. 10 The communication control device 11, 31, in particular its protocol controller, has inserted the bit DH2 directly after the bit DH1, thus M = 1 additional bit. M is a natural number greater than or equal to 1. The M bits each have the bit time t_bt2. Thus, the bit AL1 is sent completely with the logical value 1, as with the signal TxD_TC from Fig. 11 shown that the transceiver device 12, 32 can drive VDIFF as a differential voltage on the bus 40.

[0115] Fig. 12 shows the course of a signal RxD_E over time t, which the receiving subscriber station (receiving node), in particular its communication control device, expects at its RXD connection. Here, the receiving subscriber station (receiving node), in particular its communication control device, does not expect a predetermined value for the bit AL1, as indicated by the hatching in Fig. 12 In other words, the value for bit AL1 can be logical 1 or logical 0.

[0116] According to Fig. 12 There is a large phase error T_P0 = "Phase error due to clock tolerance" between the expected receive signal RxD_E of Fig. 12 and the actual received signal, which is identical to the signal TxD_TC of Fig. 11 T_P0 is the distance from the beginning of the DH1 bit in Fig. 11 to the beginning of the DH1 bit in Fig. 12 The phase error T_P0 is described as large because it is large compared to the bit time t_bt2 of the second communication phase. However, the signal propagation time, especially via bus 40, is not taken into account and is Fig. 10 bis Fig. 12 not shown because the signal propagation time has no influence on the phase error T_P0.

[0117] As a result of the phase error T_P0, the receiving subscriber station (receiving node), in particular its communication control device, samples the bit DH1, the first bit of the data phase 452, at the sampling time t1. Thus, the receiving node samples the DH1 bit while the DH2 bit is being transmitted, as in Fig. 12 shown.

[0118] However, starting with the bit position of DH1, the receiving node tolerates a number of 1 to N consecutively sampled bits with the logical value 1. The receiving node can skip these additional N-1 bits directly following the DH1 bit through synchronization. N is a natural number greater than or equal to 1. For the bit rate ratios targeted by CAN XL, as previously described in relation to the task to be solved, and the expected phase errors, a value of N = 1 is advantageous or reasonable.

[0119] Despite the phase error T_P0, the receiving node correctly samples bit DH1, the first bit of data phase 452, as a logical 1. The reason for this is that after bit DH1, another bit DH2 with the same logical value is sent.

[0120] As with the first embodiment, the next falling edge after the DH1 bit defines the beginning of the DL1 bit. All receiving nodes synchronize to this next falling edge after the DH1 bit.

[0121] The previously described configuration of the communication control device 11, 31 can compensate for a phase error T_P0, which arises, for example, when a transmitting node and a receiving node each use a clock source with a tolerance. This eliminates the problem if, due to the tolerance of the clock sources, a slow receiving node is significantly "behind" the transmitting node. Depending on the bit rate ratio of the data phase bit rate to the arbitration phase bit rate, this can amount to up to several data phase bits of phase error T_P0.

[0122] Therefore, it is not a problem that the receiving node tries to sample the DH1 bit only after the DH1 bit in the transmit signal (TxD_TC) has already passed.

[0123] Otherwise, the functionality of the bus system 1 of the two embodiments is the same.

[0124] Thus, the logic level of the first bit in the data phase 452 is extended in both directions compared to the current state of the art, so that both the sampling point t1 of a fast receiver and

[0125] Receiving node as well as the sampling point t1 of a slow receiver or receiving node correctly samples the value of the first bit DH1 in the data phase 452 as 1. To extend the frame backward, i.e., toward the end of frame 450, at least one new bit DH2 is introduced directly after the DH1 bit, which has the same value as the first bit DH1 of the data phase 452. The receiver or receiving node can skip this at least one bit DH2 through synchronization. Alternatively or additionally, to extend the frame forward, i.e., toward the beginning of frame 450, at least the rear or last part AL1_1 of the AL1 bit can be sent with the same value as the DH1 bit.

[0126] All previously described embodiments of the subscriber stations 10, 20, 30, the bus system 1, and the method implemented therein can be used individually or in all possible combinations. In particular, all features of the previously described embodiments and / or modifications thereof can be combined as desired. Additionally or alternatively, the following modifications are conceivable.

[0127] Although the invention has been described above using the CAN bus system as an example, the invention can be applied to any communication network and / or communication method that uses two different communication phases, in which the bus states generated for the different communication phases differ. In particular, the invention is applicable to the development of other serial communication networks, such as Ethernet and / or 100 Base-T1 Ethernet, fieldbus systems, etc.

[0128] In particular, bus system 1 according to the exemplary embodiments can be a communications network in which data can be transmitted serially at two different bit rates. It is advantageous, but not a mandatory requirement, that exclusive, collision-free access of a subscriber station 10, 20, 30 to a common channel is guaranteed in bus system 1, at least for certain periods of time.

[0129] Of course, the ADS field can have more bits than those described in the embodiments.

[0130] The number and arrangement of subscriber stations 10, 20, 30 in bus system 1 of the exemplary embodiments is arbitrary. In particular, subscriber station 20 can be omitted from bus system 1. It is possible for one or more of subscriber stations 10 or 30 to be present in bus system 1. It is conceivable for all subscriber stations in bus system 1 to be configured identically, i.e., only subscriber station 10 or only subscriber station 30 to be present.

Claims

1. Subscriber station (10; 30) for a serial bus system (1), having a communication control device (11; 31) for controlling a communication of the subscriber station (10; 20; 30) with at least one other subscriber station (10; 20; 30) of the bus system (1) and for generating a transmission signal (TxD) for a transmitting / receiving device (12; 32) of the subscriber station (10; 30) such that, for a message (45) exchanged between subscriber stations (10, 20, 30) of the bus system (1), the bit time (t_bt1) of a signal transmitted to the bus (40) in a first communication phase (451) may differ from a bit time (t_bt2) of a signal transmitted in the second communication phase (452), wherein the communication control device (11; 31) is configured to generate the transmission signal (TxD) according to a frame (450) and to insert a field (ADS) having a rising edge and a subsequent falling edge into the frame (450) to transition from the first communication phase (451) to the second communication phase (452), wherein the communication control device (11; 31) is configured to perform a pulse width modulation of the transmission signal (TxD) in the field (ADS) and the second communication phase (452) in order to use the pulse width modulation in the field (ADS) to signal to the transmitting / receiving device (12; 32) that the transmitting / receiving device (12; 32) is supposed to switch its operating mode from the operating mode (B_451) of the first communication phase (451) to a different operating mode (B_452_TX; 452_RX) of the second communication phase (452), wherein the communication control device (11; 31) is configured to perform the pulse width modulation of the transmission signal (TxD) to signal operating mode switching in the first bit (AL1) at the beginning of the field (ADS) in such a way that at least the last part of the first bit (AL1) of the field (ADS) has the value logic 1, and wherein the communication control device (11; 31) is configured to perform no pulse width modulation of the transmission signal (TxD) to signal operating mode switching if the transmitting / receiving device (12; 32) is not supposed to switch its operating mode from the operating mode (B_451) of the first communication phase (451) to an operating mode (B_452_TX; B_452_RX) of the second communication phase (452), and, directly after a second bit (DH1) of the field (ADS), which is the first bit (DH1) of the second communication phase (452), to insert at least one additional bit having the same value as the second bit (DH1) of the field (ADS), so that the field (ADS) has a predetermined length between the rising edge and the subsequent falling edge, and so that a sampling time (t1) at which a communication control device (21; 31; 11) of the at least one other subscriber station (10; 20; 30) of the bus system (1) will sample the first bit (DH1) of the second communication phase (452) is arranged between the rising edge and the subsequent falling edge.

2. Subscriber station (10; 30) according to Claim 1, wherein the predetermined length of the field (ADS) comprises at least three bits with the bit time (t_bt2) of the second communication phase (452).

3. Subscriber station (10; 30) according to Claim 1 or 2, wherein the falling edge defines the start of a predetermined bit (DL1) of the second communication phase (452).

4. Subscriber station (10; 30) according to one of the preceding claims, wherein the communication control device (11) is configured to insert the field (ADS) as a bit sequence containing the logic value 1110.

5. Subscriber station (10; 30) according to one of the preceding claims, wherein the communication control device (11) is configured to insert a bit with the bit time (t_bt1) of the first communication phase (451) and subsequently a bit (DH1) with the bit time (t_bt2) of the second communication phase (452) in the field (ADS) before the falling edge, wherein the communication control device (11) is configured to additionally insert a number of M bits with the bit time (t_bt2) of the second communication phase (452), each of which has the same logic value as the first bit (DH1) of the second communication phase (452), after the bit (DH1) with the bit time (t_bt2) of the second communication phase (452), and where M is a natural number greater than or equal to 1.

6. Subscriber station (10; 30) according to one of the preceding claims, wherein the communication control device (11) is configured to act as a receiving node in the second communication phase (452), so that the communication control device (11) acts only as a receiver but not as a transmitter of the frame (450) to the bus (40), wherein the communication control device (11) is configured to tolerate a number of N bits with the bit time (t_bt2) of the second communication phase (452), each of which has the logic value 1, in the field (ADS) from and including the sampling time (t1) at which the communication control device (21; 31; 11) samples the first bit (DH1) of the second communication phase (452), and before the falling edge of the field (ADS), N being a natural number greater than or equal to 1, and wherein the communication control device (11) is configured to use the falling edge of the field (ADS) to synchronize with the communication on the bus (40).

7. Subscriber station (10; 30) according to one of the preceding claims, moreover having the transmitting / receiving device (12; 32) for transmitting the transmission signal (TxD) to a bus (40) of the bus system (1).

8. Subscriber station (10; 30) according to Claim 7, wherein the communication control device (11) is configured to use pulse width modulation in the transmission signal (TxD) to signal to the transmitting / receiving device (12; 32) directly after the rising edge of the field (ADS) that the transmitting / receiving device (12; 32) needs to switch its operating mode from the operating mode (B_451) of the first communication phase (452) to one of two different operating modes (B_452_TX; 452_RX) of the second communication phase (452), and to which of the two operating modes (B_452_TX; B_452_RX) of the second communication phase (452).

9. Subscriber station (10; 30) according to Claim 7 or 8, wherein the communication control device (11; 31) is configured to use S directly consecutive PWM symbols (SB_D0; SB_1) in the transmission signal (TxD) to signal to the transmitting / receiving device (12; 32) to which operating mode of the second communication phase (452) the transmitting / receiving device (12; 32) needs to switch its operating mode, S being a natural number greater than or equal to 1.

10. Subscriber station (10; 30) according to one of Claims 7 to 9, wherein the communication control device (11; 31) is configured to transmit at least the last part (AL1_1) of a bit (AL1) that has the bit time (t_bt1) of the first communication phase (451) with the same logic value as the first bit (DH1) in the field (ADS) that has the bit time (t_bt2) of the second communication phase (452).

11. Subscriber station (10; 30) according to one of Claims 1 to 6, moreover having the transmitting / receiving device (22) for transmitting the transmission signal (TxD) to a bus (40) of the bus system (1), wherein the transmitting / receiving device (22) is configured to transmit the whole frame (450) to the bus (40) in the operating mode (B_451) for transmitting and receiving the frame (450) in the first communication phase (451).

12. Subscriber station (10; 30) according to one of the preceding claims, wherein the frame (450) formed for the message (45) is of a design compatible with CAN FD, and wherein negotiation takes place in the first communication phase (451) in order to determine which of the subscriber stations (10, 20, 30) of the bus system (1) receives at least temporarily exclusive, collision-free access to the bus (40) in the subsequent, second communication phase (452).

13. Bus system (1) having a bus (40), and at least two subscriber stations (10; 20; 30) which are connected to one another via the bus (40) in such a way that they can communicate serially with one another and at least one subscriber station (10; 30) of which is a subscriber station (10; 30) according to one of the preceding claims.

14. Method for communication in a serial bus system (1), the method being carried out using a subscriber station (10; 30) of the bus system (1), which subscriber station has a communication control device (11; 31) and a transmitting / receiving device (12; 22; 32), wherein the method comprises the steps of using the communication control device (11; 31) to control a communication of the subscriber station (10; 30) with at least one other subscriber station (10; 20; 30) of the bus system (1) such that, for a message (45) exchanged between subscriber stations (10, 20, 30) of the bus system (1), the bit time (t_bt1) of a signal transmitted to the bus (40) in a first communication phase (451) may differ from a bit time (t_bt2) of a signal transmitted in the second communication phase (452), and using the transmitting / receiving device (12; 32) to transmit the transmission signal (TxD) to a bus (40) of the bus system (1), wherein the communication control device (11; 31) generates the transmission signal (TxD) for a transmitting / receiving device (12; 32) of the subscriber station (10; 30) according to a frame (450) and inserts a field (ADS) having a rising edge and a subsequent falling edge into the frame (450) to transition from the first communication phase (451) to the second communication phase (452), wherein the communication control device (11; 31) performs a pulse width modulation of the transmission signal (TxD) in the field (ADS) and the second communication phase (452) in order to use the pulse width modulation in the field (ADS) to signal to the transmitting / receiving device (12; 32) that the transmitting / receiving device (12; 32) is supposed to switch its operating mode from the operating mode (B_451) of the first communication phase (451) to a different operating mode (B_452_TX; 452_RX) of the second communication phase (452), wherein the communication control device (11; 31) performs the pulse width modulation of the transmission signal (TxD) to signal operating mode switching in the first bit (AL1) at the beginning of the field (ADS) in such a way that at least the last part of the first bit (AL1) of the field (ADS) has the value logic 1, and wherein the communication control device (11; 31) performs no pulse width modulation of the transmission signal (TxD) to signal operating mode switching if the transmitting / receiving device (12; 32) is not supposed to switch its operating mode from the operating mode (B_451) of the first communication phase (451) to an operating mode (B_452_TX; B_452_RX) of the second communication phase (452), and, directly after a second bit (DH1) of the field (ADS), which is the first bit (DH1) of the second communication phase (452), inserts at least one additional bit having the same value as the second bit (DH1) of the field (ADS), so that the field (ADS) has a predetermined length between the rising edge and the subsequent falling edge, and so that a sampling time (t1) at which a communication control device (21; 31; 11) of the at least one other subscriber station (10; 20; 30) of the bus system (1) will sample the first bit (DH1) of the second communication phase (452) is arranged between the rising edge and the subsequent falling edge.