Semiconductor package arrangement
Patent Information
- Application Number
- DE602017086783
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2017-06-30
- Filing Date
- 2017-09-05
- Publication Date
- 2024-12-11
- Estimated Expiration
- 2037-09-05
AI Technical Summary
Semiconductor package assemblies face thermal electrical issues such as heat dissipation, cross talk, and signal propagation delay due to increased input/output connections, affecting reliability and quality, particularly due to mismatched thermal expansion coefficients between the core substrate and solder mask layers.
A semiconductor package assembly with a base that includes a core substrate and a single solder mask layer formed of the same material as the core substrate, reducing thermal cycling stress and improving reliability by eliminating the need for additional solder mask layers on the solder-bump-attach surface.
This configuration enhances the thermal cycling reliability of the semiconductor package assembly by minimizing stress and preventing cracks at the interface between solder-bump structures and solder mask layers, thereby improving the overall performance and durability of the package.