ELECTRONIC SYSTEM WITH AN ELECTRONIC CHIP FOR FORMING A PACKAGING AND METHOD FOR PRODUCING SAME

Description

GENERAL TECHNICAL FIELD AND PRIOR ART

[0001] The present invention relates to the field of manufacturing an electronic system suitable for being attached to a printed circuit, the printed circuit being then able to be mounted in an electronic device, for example, a smartphone. The present invention relates more particularly to an electronic system comprising an electronic chip forming a housing.

[0002] As is known, an electronic system may comprise several electronic chips which are mounted in a housing to form an interface between the electronic chips and the printed circuit, known to those skilled in the art by its English designation "Printed Circuit Board" (PCB). For this purpose, the housing comprises connection pins.

[0003] In order to improve the performance of such an electronic system, it is necessary to reduce or eliminate the parasitic elements generated by the connections that connect the different electronic chips to the package. To this end, it is desirable to reduce the electrical lengths of these connections by reducing the distances between the chips and miniaturizing the package. Also, it has been proposed to stack the electronic chips vertically in the same package in order to further reduce losses.

[0004] However, this miniaturization is difficult to achieve due to the limitations of current assembly techniques. Indeed, most assembly techniques require manufacturing a package, placing the electronic chips in the package, connecting said electronic chips to the package using micro-welded wires and encapsulating the assembly to protect it from its environment. The use of micro-welded wires generates high losses, which is a disadvantage.

[0005] Furthermore, it has been proposed to eliminate the housing and use an electronic chip as a housing so that it can be directly soldered onto a printed circuit using conductive balls positioned on the electronic chip. Such a flip-chip bonding method is known to those skilled in the art under its English term "flip-chip".

[0006] As is well known, we then speak of a chip-scale package called "CSP" (Chip Scale Package) since the package has exactly the same size as the electronic chip. Although this technique allows for the miniaturization of a package, it remains limited to a single electronic chip per package. In addition, this type of package does not allow for heterogeneous integration (system with several different electronic components) or three-dimensional integration (stack of electronic chips).

[0007] To eliminate this drawback, it has been proposed to use an interposer device, also called an "interposer", which comprises a front face and a rear face and which includes front face connectors, rear face connectors and through-silicon vias, known by their English designation "Through Silicon Via", connecting the rear face connectors to the front face connectors. The use of such an interposer device increases the time and cost of manufacturing electronic systems and can degrade their electrical performance.

[0008] To overcome this drawback, it has been proposed to significantly thin a daughter chip, by mounting it on a mother chip, depositing a passivation and planarization layer and connecting them together using planar metal interconnects. Thinning the daughter chip to a thickness below 30 µm is necessary to allow planarization of the system surface using the passivation layer and the application of conventional photolithography techniques for the realization of planar metal interconnects. Such planarization becomes difficult to achieve when the thickness of the daughter chip or the total thickness of a stack of daughter chips is greater than 30 µm, thus making the application of said photolithography techniques, and therefore the realization of metal interconnects, extremely difficult. Strong thinning is thus always necessary, which increases the complexity of handling and manufacturing the systems.

[0009] Also known in the prior art from patent application CN 103 632 991 B is a method for manufacturing an electronic system comprising connection bumps formed by metal growth on a metal growth layer which must be removed subsequently to avoid the formation of a short circuit. Such bumps make it possible to vertically offset connection ports of electronic components in the same connection plane. There is no interconnection of the electronic components between them in the electronic system. Also known in the prior art from patent application KR 2000 0043575 A is an electronic system on which metal members are deposited in several parts to form an interconnection. Also known is patent application JP2006013205 which presents an electronic component aiming at an electrical connection from the rear.

[0010] There is therefore a need to form an electronic system comprising an electronic chip forming a housing and on which several other electronic components are mounted in an optimal manner. GENERAL PRESENTATION OF THE INVENTION

[0011] For this purpose, the invention relates to an electronic system according to claim 1.

[0012] Advantageously, significant thinning of the electronic component and planarization of the surface of said system are not necessary for the integration and interconnection of the system, which advantageously makes it possible to overcome the problems linked to thinning and to interconnect a chip or a stack of chips of great thickness.

[0013] Advantageously, thanks to the invention, it is possible to form an electronic system allowing heterogeneous electronic components to be integrated in a simple and practical manner on a main electronic chip forming a package, without the need to significantly thin these components or to planarize the surface of the system, while maintaining a limited footprint. The main conductive ball advantageously allows the main chip to be connected despite the presence of the electronic component.

[0014] Such a high-tech electronic system can be mounted on a printed circuit board of a telephone or other compact device. The electronic system also has high performance given the very short lengths of the three-dimensional connections between the electronic components while having a low cost. The electronic system is also obtained with a limited number of technological steps, which reduces the manufacturing cost. The formation of three-dimensional interconnections by metal deposition allows for the creation of quality connections quickly and precisely. Such interconnections offer great flexibility in production. In addition, a large number of electronic systems can be produced simultaneously, further reducing the cost.

[0015] By means of the present invention, interconnections are made between the components in order to form an electronic system and benefit from synergies, which makes it possible to improve the electrical performance and reduce the number of inputs / outputs of the system and therefore the cost of the connection. This is advantageous in comparison to the patent application CN 103 632 991 B which teaches to move each connector away from the components and to make the electrical connections between the components via the motherboard (PCB).

[0016] Preferably, the connection pad is connected to the three-dimensional interconnection. Thus, the main conductive ball is connected to the electronic component and the main electronic chip, thereby forming a complex connection in a convenient manner.

[0017] Preferably, the connection pad is formed by metal deposition simultaneously with the three-dimensional interconnection. Thus, the connection pad is produced quickly at a reduced cost.

[0018] According to a preferred aspect, the electronic component comprising at least two connectors, the electronic system comprises two three-dimensional interconnections connected respectively to the first connector of the electronic component and to the second connector of the electronic component. Preferably, the interconnections are produced during the same technical step.

[0019] Preferably, the electronic system comprises an encapsulation layer so as to encapsulate the front surface of the main electronic chip and a portion of the main conductive ball. Such an encapsulation layer makes it possible to improve mechanical robustness as well as reliability, only the conductive balls which must be connected to the printed circuit are uncovered, the other electronic components being protected. It goes without saying that, for certain applications, components, such as sensors, may remain uncovered.

[0020] According to a preferred aspect, the electronic system comprises a metallurgical layer underlying the main conductive ball, known by its English name "under-bump metallurgy" (UBM). Such a metallurgical layer makes it possible to improve the mechanical robustness and reliability of the system.

[0021] Preferably, the electronic system comprises at least one vertical stack of electronic components, each electronic component comprising a front surface comprising at least one connector and a rear surface opposite the front surface, at least one three-dimensional interconnection connecting at least one connector of each electronic component to a connector of the main electronic chip and / or to a connector of another electronic component. Preferably, the three-dimensional interconnections are formed simultaneously. Thus, a large number of electronic components can be added to a main electronic chip in order to form, simply and at low cost, a high-tech electronic system.

[0022] Preferably, an electronic component positioned in front of the stack has smaller dimensions than an electronic component positioned behind the stack. Advantageously, the electronic components form a staircase stack, which facilitates the production of the interconnection(s). Preferably, the electronic components are the same size. More preferably, the electronic components are connected by three-dimensional staircase interconnections, which facilitates their production.

[0023] Preferably, the electronic system comprises at least one additional electronic component comprising a front surface comprising at least one connector and a rear surface opposite the front surface, the front or rear surface being positioned opposite the front surface of the main electronic chip, the connector of the additional electronic component being connected to said three-dimensional interconnection. Thus, several electronic components can be connected directly to a main electronic chip.

[0024] Preferably, the additional electronic component is an electronic chip, a surface-mounted device (SMD) or an inductive element. In the latter case, the inductive element is formed by metal deposition simultaneously with the three-dimensional interconnections.

[0025] According to a preferred aspect, the electronic system comprises at least one auxiliary electronic component comprising a front surface comprising at least one connector and a rear surface opposite the front surface, the front or rear surface being positioned opposite the front surface of the electronic component located furthest forward, the connector of said auxiliary electronic component being connected to said three-dimensional interconnection. Preferably, said three-dimensional interconnection forms a three-dimensional redistribution layer between the electronic component located furthest forward and the auxiliary electronic component. Thus, the additional electronic component can communicate with all the components of the electronic system. More preferably, the auxiliary electronic component is connected to the three-dimensional interconnections by a flip-chip technique, by soldering or by micro-welded wires.

[0026] Preferably, the electronic system comprises at least one auxiliary conductive ball, of smaller dimensions than the main conductive ball, which is connected to the three-dimensional interconnection, the set of conductive balls defining a single connection plane. Thus, the number of inputs / outputs of the electronic system can be increased by adding conductive balls to interconnections. Preferably, the auxiliary conductive balls are positioned in front of the electronic component located furthest forward. Thus, the connection surface of the electronic system is increased.

[0027] Preferably, the three-dimensional interconnect forms an upper three-dimensional redistribution layer between the auxiliary conductive ball and the foremost electronic component. Such an upper three-dimensional redistribution layer makes it possible to connect the auxiliary conductive ball to the other components of the electronic system in a practical manner by limiting the length of the connections.

[0028] In a preferred aspect, the electronic system includes a lower redistribution layer formed between the rearmost electronic component and the main electronic chip forming the package. Such a lower redistribution layer increases the integration density and facilitates the routing of connections and the positioning of conductive balls in order to meet the needs of high-density electronic systems.

[0029] Preferably, the three-dimensional interconnect has a width to height aspect ratio of less than 1:1.5, preferably less than 1:3. For example, for a three-dimensional interconnect that is 40µm wide and mounts on a component that is 300µm high, its aspect ratio is 1:7.5, while for another three-dimensional interconnect that is 15µm wide and mounts on a chip that is 150µm high, its aspect ratio is 1:10. Such a thin interconnect allows two components that are vertically spaced apart by a significant height to be conveniently connected while having a reduced width, which allows for high density of connections and system integration.

[0030] Preferably, the electronic system comprises at least one passive element formed simultaneously with the three-dimensional interconnection. Thus, the three-dimensional interconnection fulfills a connection function but also a passive function by forming passive elements (inductances, resistance, etc.).

[0031] Preferably, the electronic system comprises at least one spacer arranged between the main conductive ball and the main electronic chip forming a housing so as to increase the distance between the connection plane and the front surface of the main electronic chip. Thus, a large number of components and / or high-rise components can advantageously be stacked and / or mounted on the main electronic chip.

[0032] The invention also relates to a method for installing an electronic system according to one of the preceding embodiments on a printed circuit board, a method in which the main conductive ball of the electronic system is fixed on the printed circuit board by a so-called "flip-chip" turning technique.

[0033] Preferably, a filler layer is disposed between the electronic system and the printed circuit board so as to improve the robustness and reliability of the electronic system.

[0034] The invention further relates to an electronic card comprising a printed circuit and an electronic system as presented previously, the main conductive ball of which is secured to the printed circuit.

[0035] The invention also relates to a method of manufacturing an electronic system as presented previously, comprising: a step of providing a wafer comprising a plurality of main electronic chips, each main electronic chip comprising a front surface comprising at least one connector and a rear surface opposite the front surface, according to claim 5.

[0036] The invention makes it possible to produce an electronic system comprising heterogeneous electronic components in a practical and inexpensive manner by relying on three-dimensional interconnections. This advantageously takes advantage of the vertical dimension to increase the integration density.

[0037] Preferably, the step of producing a three-dimensional interconnection comprises: a step of depositing a metal bonding layer a step of depositing a thick resin layer and a step of making openings defining the shape of the three-dimensional interconnections a step of depositing a metal layer, and a step of dissolving the resin layer and a step of etching the metal bonding layer. PRESENTATION OF THE FIGURES

[0038] The invention will be better understood by reading the following description, given solely by way of example, and referring to the appended drawings in which: there Figure 1 is a schematic representation of a first embodiment of a system according to the invention; Figure 2 is a schematic representation of the system of the Figure 1 in position mounted on a printed circuit; the Figure 3 is a schematic representation of the system of the Figure 1in position mounted on a printed circuit board with a filling layer; the Figure 4 is a schematic representation of a second embodiment of a system according to the invention with an encapsulation layer; Figures 5a-5g are schematic representations of the fabrication of two systems; the Figure 6 is a schematic representation of a third embodiment of a system according to the invention; Figure 7 is a schematic representation of a fourth embodiment of a system according to the invention; figure 8 is a schematic representation of a fifth embodiment of a system according to the invention; Figures 9-13 are schematic representations of printed circuits comprising an electronic system according to the invention; the Figure 14 is a schematic representation of a sixth embodiment of a system according to the invention; Figure 15is a schematic representation of a seventh embodiment of a system according to the invention; figure 16 is a schematic representation of an eighth embodiment of a system according to the invention; Figure 17 is a schematic representation of a ninth embodiment of a system according to the invention; and the figure 18 is a schematic representation of the assembly of the system of the Figure 17 .

[0039] It should be noted that the figures set out the invention in detail to implement the invention, said figures can of course be used to better define the invention where appropriate. DESCRIPTION OF ONE OR MORE METHODS OF EMBODIMENT AND IMPLEMENTATION

[0040] An electronic system comprising a plurality of electronic components capable of being mounted on a printed circuit board to form an electronic card will be presented. Such an electronic card can be mounted in any type of electronic device, for example, a computer, a watch, a smartphone, a connected object, clothing, portable equipment, etc. Implementation form no. 1

[0041] In reference to the Figure 1 , an electronic system S is shown according to a first embodiment.

[0042] The electronic system S comprises a main electronic chip 1 forming a housing. In other words, the main electronic chip 1 forms a “package” as is known to those skilled in the art. The main electronic chip 1 is thus not protected in an attached housing but is capable of being directly secured to a printed circuit board CI as will be presented later.

[0043] As shown in the Figure 1 , the main electronic chip 1 is in the form of a flattened body, preferably a pad, comprising a front surface 1A comprising two connectors 11 and a rear surface 1B opposite the front surface 1A. In this example, the rear surface 1B forms the outer surface of the electronic system S after being secured to a printed circuit CI. It goes without saying that the number of connectors 11 could be different.

[0044] The electronic system S further comprises two connection pads 120 connected to the front surface 1A of said main electronic chip 1 and two main conductive balls 13 secured to said connection pads 120 and adapted to connect to a printed circuit CI. Such main conductive balls 13 are known to those skilled in the art under their English designation “micro-bump” and will not be presented in detail.

[0045] Still referring to the Figure 1 , the electronic system S comprises an electronic component 2 comprising a front surface 2A comprising two connectors 21 and a rear surface 2B opposite the front surface 2A. In this example, the electronic component 2 is an electronic chip. For the sake of clarity, in order to differentiate the electronic component 2 from the main electronic chip 1, the electronic component 2 will be referred to as a “daughter electronic chip”. It goes without saying that the electronic component could be in various forms, in particular, surface-mounted component, inductor, etc.

[0046] The rear surface 2B of the daughter electronic chip 2 is positioned facing the front surface 1A of the main electronic chip 1 so that the daughter electronic chip 2 protrudes from the front surface 1A of the main electronic chip 1. It goes without saying that the number of connectors 21 could be different.

[0047] The daughter electronic chip 2 has smaller dimensions than the main electronic chip 1 so that the connectors 11 of the main electronic chip 1 are clear, that is to say, not covered by the daughter electronic chip 2. In this example, the rear surface 2B of the daughter electronic chip 2 is directly secured to the front surface 1A of the main electronic chip 1 as illustrated in Figure 1 .

[0048] In this example, the electronic system S comprises a single daughter electronic chip 2 but it goes without saying that it could comprise several electronic components secured together on the front surface 1A of the main electronic chip 1. It is thus possible to form a highly technical electronic system S.

[0049] In this example, at least one three-dimensional interconnection 12 produced by metal deposition connects the connector of the daughter electronic chip 2 to a connection pad 120 and to the connector 11 of the main electronic chip 1, the connection pad 120 being formed by metal deposition simultaneously with the three-dimensional interconnection 12. The number of connectors 11, 21 connected to each other depends on the degree of interaction between the two electronic chips 1, 2 in the electronic system S.

[0050] In the example of the Figure 1 , the electronic system S comprises two three-dimensional interconnections 12 which are identical but it goes without saying that they could be different. Each three-dimensional interconnection 12 is simultaneously connected to a connector of the daughter electronic chip 2, to a connection pad 120 and to a connector 11 of the main electronic chip 1.

[0051] Instead of directly connecting the connection pads 120 of the main electronic chip 1 to a printed circuit IC, main conductive balls 13 of greater thickness are used so as to provide space in front of the front surface 1A of the main electronic chip 1 in order to secure (at least) a daughter electronic chip 2 or another electronic component. According to the invention, the main conductive balls 13 extend in front of the front surface of the electronic component located furthest forward.

[0052] Thus, a highly technical and compact electronic system S is obtained by cleverly using a main electronic chip 1 forming a housing. With reference to the Figure 1 , the main conductive balls 13 define a connection plane P extending parallel to the front surface 1A of the main electronic chip 1.

[0053] In reference to the Figure 2, we thus obtain an electronic system S which can be secured to a printed circuit CI by different techniques, in particular, a technique of securing by turning, known to those skilled in the art under its English name “flip-chip”. As illustrated in Figure 2 , the main conductive balls 13 of the electronic system S are secured to conductive tracks of the printed circuit CI.

[0054] Preferably, with reference to the Figure 3, after securing the electronic system S to the printed circuit CI, a filling material 15, known to those skilled in the art by its English designation “underfill”, is injected in order to improve the mechanical robustness of the electronic system S. Such a filling material 15 comprises, for example, a polymer such as epoxy or acrylate and which can be loaded with particles of silica, alumina, carbon, or others in order to adjust its mechanical properties such as its coefficient of thermal expansion, its Young's modulus or others. Manufacturing method

[0055] An example of manufacturing will be presented with reference to the Figure 5 illustrating several technical manufacturing stages.

[0056] In reference to the Figure 5a, a wafer is shown, known to those skilled in the art under the English designation "wafer" or "panel", comprising main electronic chips 1 capable of forming a package. The wafer may be made of a semiconductor material such as silicon, germanium, gallium arsenide, silicon carbide as well as glass, polymer or other rigid and / or flexible materials. The wafer may also comprise passive components.

[0057] In this example, two main electronic chips 1 are shown. Each main electronic chip 1 has a front surface 1A comprising two connectors 11 and a rear surface 1B opposite the front surface 1A.

[0058] In reference to the Figure 5B, daughter electronic chips 2 are transferred onto the main electronic chips 1 by a technique known to those skilled in the art, for example, the transfer technique known to those skilled in the art under the English term “pick and place”. In this example, a layer of glue 16 is deposited between the rear surface 2B of each daughter electronic chip 2 and the front surface 1A of the daughter electronic chip 2. Similarly, when several daughter electronic chips 2 are stacked vertically, they are preferably secured together by gluing.

[0059] Preferably, the total vertical thickness (daughter chip(s) 2 and glue layer(s) 16) is greater than 10 µm, more particularly, greater than 30 µm, 40 µm and 50 µm. The sides of the daughter electronic chips 2 may be straight, undercut and / or undercut. For the sake of clarity, only daughter electronic chips 2 having straight sides have been used in the figures.

[0060] In reference to the Figure 5c, a passivation layer 17 is then applied to the assembly so as to passivate, that is to say to make insulating, the exposed surfaces of the electronic chips 1, 2. Depending on the need of the system, such a passivation layer 17 is deposited in a conformal manner or in a manner to adapt the angle of the sides of the electronic chips 2 without it fulfilling a function of planarization of the surface of the system. The passivation layer 17 can be composed of an organic or inorganic material, such as a semiconductor oxide, a metal oxide, a polymer or any other electrically insulating materials. It can be deposited by spin coating, by spray, by lamination, by pressing, by growth, by printing (inkjet), by vacuum deposition or by any type of deposition known to those skilled in the art. Still with reference to the Figure 5c, openings 18 are subsequently made in the passivation layer 17, in order to uncover the connectors 11, 21 of the electronic chips 1, 2, using a photolithography process or using wet and / or dry chemical etching, by plasma or by laser. Preferably, photosensitive materials are favored given the advantages offered by the photolithography processes.

[0061] In the case where the surfaces and sides of the electronic chips 1, 2 are insulating except at the connectors 11, 21, the deposition of the passivation layer 17 may not be applied, thus reducing the manufacturing time and cost.

[0062] Then, with reference to the Figure 5d, three-dimensional interconnections 12 as well as connection pads 120 are formed to interconnect the connectors 11, 21 of the electronic chips 11, 21. The three-dimensional interconnections 12 are known per se, in particular, from patent application FR2965659. In this example, to produce the three-dimensional interconnections 12 and the connection pads 120, the method comprises: a step of depositing a metal layer by evaporation, by spraying or otherwise, which fulfills both a basic function of attachment and growth of the metal constituting the three-dimensional interconnections 12 and the connection pads 120. This metal layer can be composed of a single or several electrically conductive and / or semiconducting materials. a step of depositing a thick layer of photosensitive resin and a step of making openings by photolithography techniques, by laser ablation or others, in order to create a mold necessary for the deposition of the metal constituting the three-dimensional interconnections 12. These openings define the shape of the three-dimensional interconnections 12 as well as those of the metal tracks forming the three-dimensional redistribution layer (presented subsequently) and the connection pads 120.Depending on the integration requirement, the thickness of the photosensitive resin layer can vary from 40 to 700µm and the aspect ratio (resolution) from 0.5:1 to 50:1. a step of depositing a metal layer by electrolysis or any other metal growth technique. The deposited metal can be copper, gold, silver, nickel, a metal alloy or any other electrically conductive material. a step of dissolving the resin mold and a step of etching the bonding layer. These methods are known to those skilled in the art. However, in the case where the bonding notch contains gold, a solution based on Kl+I2 and additives could be used to etch this layer without damaging the three-dimensional interconnections 12. .

[0063] The three-dimensional interconnections 12 being created, with reference henceforth to the Figure 5e , the method comprises a step of depositing a second passivation layer 19. The Figure 5eillustrates a conformal passivation layer 19, that is, the difference between its thickness on the faces and on the sides of the electronic chips 1,2 varies by ±30%. However, the deposition of this passivation layer 19 could not be conformal or be omitted depending on the needs. Openings 190 are formed in the second passivation layer 19 so as to allow access to the connection pads 120 formed with the three-dimensional interconnections 12.

[0064] In reference to the Figure 5f , the method comprises a step of depositing the main conductive balls 13 in the openings 190 of the second passivation layer 19 so as to electrically connect to the connection pads 120. A plurality of electronic systems S are thus obtained on the same wafer.

[0065] Finally, with reference to the figure 5g, the wafer is cut in such a way as to separate the electronic systems S so that they can be used individually. Optionally, the wafer can be thinned in order to reduce the size of the electronic system S. Implementation form no. 2

[0066] Another embodiment of an electronic system S according to the invention is shown in Figure 4 . For the sake of clarity and brevity, elements which are identical or analogous between other embodiments are referenced with the same reference numeral, only the differences between the embodiments are presented in detail.

[0067] In reference to the Figure 4, the electronic system S comprises an encapsulation layer 14 so as to encapsulate the front surface of the electronic system S and a portion of the main conductive balls 13. Preferably, the encapsulation layer 14 is made of polymer, for example epoxy, and loaded or not with particles such as silica, alumina, etc. but it goes without saying that other similar materials could be suitable. Such an encapsulation layer 14 advantageously makes it possible to improve the mechanical robustness as well as the reliability of the electronic system S. Such an encapsulation layer 14 can advantageously be applied to all embodiments of the electronic system S.

[0068] Preferably, the encapsulation layer 14 is deposited following the deposition of the conductive balls 13. Such a step is advantageous because it is easily integrated into the manufacturing process of the electronic system S.

[0069] Alternatively, the main conductive balls 13 can be deposited after the deposition of the encapsulation layer 14, it is then necessary to make openings in the encapsulation layer 14 so as to access the connection pads 120. Implementation form no. 3

[0070] Another embodiment of an electronic system S according to the invention is shown in Figure 6 . For the sake of clarity and brevity, elements which are identical or analogous between other embodiments are referenced with the same reference numeral, only the differences between the embodiments are presented in detail.

[0071] In this example, the electronic system S comprises several daughter electronic chips 2 assembled vertically to form a stack. Each daughter electronic chip 2 comprises a front surface 2A comprising at least two connectors 21 and a rear surface 2B opposite the front surface 2A. The electronic chips 2 have the same orientation in the stack, the rear surface of a “front” chip being opposite the front surface of a “rear” chip. The daughter electronic chip 2 furthest to the rear of the stack is mounted on the front surface 1A of the main electronic chip 1.

[0072] In this embodiment, with reference to the Figure 6 , the electronic system S comprises a vertical stack of two daughter electronic chips in order to form a high-tech system. It goes without saying that the electronic system S could comprise a stack of a large number of electronic components of different natures.

[0073] In this example, the connection pads 120, the connectors 11 of the main electronic chip 1 and the connectors 21 of each daughter electronic chip 2 are respectively connected to each other using three-dimensional interconnections 12 produced by metal deposition. The connection pads 120 are formed simultaneously with said three-dimensional interconnections 12. Advantageously, even in the case of a plurality of daughter electronic chips 2, the three-dimensional interconnections 12 are produced during a single step.

[0074] Depending on the complexity, the steps of depositing the passivation layers 17 and depositing the three-dimensional interconnects 12 can be repeated to meet the need for high-density system integration.

[0075] Preferably, each daughter electronic chip 2 located in front of a stack has smaller dimensions than a daughter electronic chip 2 located behind said stack so as to form a stack facilitating the formation of three-dimensional interconnections 12 between the different daughter electronic chips 2. The compactness and the integration density are thus increased in a simple manner.

[0076] Preferably, the stacking is pyramidal ( Figure 6 ) or in a staircase manner. In the latter case, it is possible to stack 2 daughter electronic chips of the same size or 2 daughter electronic chips of a larger size on top of 2 daughter electronic chips of a smaller size. It goes without saying that the 2 daughter electronic chips can have different dimensions. Implementation form no. 4

[0077] Preferably, with reference to the Figure 7, the electronic system S may comprise auxiliary conductive balls 130 positioned in front of the front surface of the foremost daughter electronic chip 2. In this example, with reference to the Figure 7 representing an electronic system S comprising a stack of two daughter electronic chips 2, auxiliary conductive balls 130 are positioned on the front surface 2A of the foremost daughter electronic chip 2. Preferably, the main conductive balls 13 and the auxiliary conductive balls 130 belong to the same connection plane P so as to allow the electronic system S to be secured by a turning technique, that is to say, by a “flip-chip” method.

[0078] Preferably, the auxiliary conductive balls 130 are connected to the three-dimensional interconnections 12. Preferably, the three-dimensional interconnections 12 form an upper three-dimensional redistribution layer 12A between the front surface 2A of the foremost daughter electronic chip 2 and the auxiliary conductive balls 130. Such an upper three-dimensional redistribution layer 12A makes it possible to flexibly arrange the auxiliary conductive balls 130 to increase the number of inputs / outputs of the electronic system S.

[0079] When the electronic system S comprises a redistribution layer (upper, lower or lateral as will be presented later), a passivation layer is previously deposited on the upper surface of the stack. Preferably, this passivation layer comprises inclined sides so as to allow metal deposition. The sides are preferably made by forming openings in the passivation layer. Depending on the complexity, several deposits of passivation layers and several metal deposits can be made.

[0080] Thus, despite the stacking of the daughter electronic chips 2 on the main electronic chip 1, the auxiliary conductive balls 130 are conveniently offset on the front surface of the electronic system S, which guarantees easy connection to the connectors 11, 21 of the electronic chips 1, 2. Implementation Form No. 5

[0081] According to another embodiment, with reference to the figure 8 , the electronic system S may comprise an auxiliary electronic component 3, comprising a front surface comprising connectors and an opposite rear surface, which is mounted in front of the foremost daughter electronic chip 2.

[0082] In reference to the figure 8 , the upper three-dimensional redistribution layer 12A of the three-dimensional interconnections 12 makes it possible to conveniently connect the auxiliary electronic component 3 to the electronic chips 1, 2, in particular by “flip-chip” reversal ( Figure 8 ) or by micro-welded connections.

[0083] Such a manufacturing method is suitable for assembling, in a first step, a set of determined electronic chips while allowing the addition of an auxiliary electronic component 3, in a second step, depending on the needs. An electronic system S is thus produced in a flexible and practical manner. Such a manufacturing method also makes it possible to integrate an auxiliary electronic component 3 which could not be integrated into the stack of daughter electronic chips 2. In other words, the vertical thickness of the electronic system S is used to integrate a stack of chips 2 and an auxiliary electronic component 3. The auxiliary electronic component 3 is located behind the connection plane P so as to allow the electronic system S to be secured to a printed circuit CI. Variety of electronic systems

[0084] In reference to the figures 9 to 13, several examples of electronic systems S according to the invention are shown.

[0085] In reference to the figure 9 , the electronic system S comprises a main electronic chip forming a housing 1 on which are mounted: a stack of electronic chips 2 and an additional electronic component X1 positioned in front of the front surface 1A of the chip forming a housing so as to house the additional electronic component X1 next to the stack of daughter electronic chips 2.

[0086] To this end, with reference to the figure 9, the three-dimensional interconnections 12 define a lateral three-dimensional redistribution layer 12B, i.e. next to the stack of daughter electronic chips 2, in order to be able to connect the additional electronic component X1 to the other electronic chips 1, 2 without increasing the vertical thickness of the electronic system S. The auxiliary electronic component X1 can be connected by any means, for example, by a flipping technique ( Figure 9 ).

[0087] In reference to the Figure 10 , besides the additional electronic component X1 mounted next to the stack of daughter electronic chips 2 in a similar manner to the figure 9 , the electronic system S comprises an auxiliary electronic component 3 mounted on the stack of daughter electronic chips 2 by means of an upper redistribution layer 12A. Such an assembly has been presented with reference to the figure 8 and will not be presented again in detail.

[0088] In reference to the Figure 11 , instead of an additional electronic component 11 mounted by a flipping technique next to the stack of electronic chips 2, the electronic system S comprises an additional electronic component 11 mounted by micro-welded wires to the upper redistribution layer 12A.

[0089] In reference to the Figure 12 , instead of an additional electronic component X1 mounted next to the stack of daughter electronic chips 2, the electronic system S comprises one or more components X3, X4 of the “Surface Mounted Compound” type.

[0090] In reference to the figure 13, instead of an additional electronic component X1 mounted next to the stack of daughter electronic chips 2, the electronic system S comprises one or more inductive elements X5, X6 which are, preferably, produced simultaneously with the three-dimensional interconnections 12. In other words, the electronic system S comprises passive elements formed simultaneously with the three-dimensional interconnection. Embodiment No. 6

[0091] In the embodiment of the Figure 14 , the electronic system S comprises between the main electronic chip 1 forming a housing and a stack of daughter electronic chips 2, preliminary planar interconnections 7 defining a lower planar redistribution layer 7A so as to improve the routing between the main electronic chip 1 and the stack of daughter electronic chips 2, in particular, in the case of high density of connectors.

[0092] The preliminary planar interconnections 7 are formed prior to the three-dimensional interconnections 12 and before the deposition of daughter electronic chips 2 of the stack. In this example, the preliminary planar interconnections 7 are connected to the connectors 11 of the main electronic chip 1 and form the lower planar redistribution layer 7A. The three-dimensional interconnections 12 connect the preliminary interconnections 7 to the connectors 21 of the daughter electronic chips 2. In other words, the lower planar redistribution layer 7A is produced directly on the wafer comprising the main electronic chips 1. Embodiment No. 7

[0093] In the embodiment of the Figure 15, in order to adjust the thickness of the electronic system S, the electronic system S comprises spacers 6, insulating or insulated, arranged between at least one main conductive ball 13 and the main electronic chip 1 forming a housing. Such a spacer 6 makes it possible to separate the connection plane P of the electronic system S from the front surface of the main electronic chip 1 forming a housing. Such a design is suitable when a large height space is desired for adding the components. Thus, the electronic system S can always be mounted by turning over on a printed circuit board CI.

[0094] The shape of the spacers 6 depends on the requirements of the application. It can be rectangular, circular, spherical, parabolic, etc. without this having an impact on the technological process. Preferably, the spacers 6 are formed using a photolithography, injection or other technique. The spacers 6 can also be produced using the transfer of insulating and / or insulated structures, in the same way as a chip or a component is transferred to a substrate (chip / component transfer technique).

[0095] As a variant, with reference to the figure 16 , when forming the spacers 6 by depositing an insulating or insulated material, a layer of insulating or insulated material M can also be deposited on the daughter electronic chip 2. Such an embodiment advantageously makes it possible to omit the step of depositing a passivation layer before forming the three-dimensional interconnections 12.

[0096] Similarly, the daughter electronic chip(s) 2 can be passivated prior to their transfer to the main electronic chip 1 in order to benefit from the aforementioned advantages.

[0097] According to another aspect of the invention, with reference to figs 17 and 18, the main chip 1 comprises through vias 60 joining its front surface 1A to its rear surface 1B and allowing the mounting of an auxiliary box B. Also, the electronic system S can advantageously fulfill an interposer function. In this example, with reference to the figure 18 , the electronic system S comprises connection balls 130 connected to the rear surface 1B of the main chip 1 which are connected to the vias 60. Conclusion

[0098] The invention makes it possible to produce electronic systems on a chip scale, enabling heterogeneous and three-dimensional integration. This type of integration allows for significant miniaturization and improved system performance without using complex technologies such as through-hole vias.

[0099] Advantageously, the manufacturing method is carried out on a wafer scale and requires only a small number of technological steps allowing several electronic systems S to be produced simultaneously, which reduces manufacturing time and cost.

[0100] This process allows for great design flexibility. In addition, the topology of the main electronic chip 1 forming the package can be optimized to improve electrical and thermal performance and to meet the needs of applications with a large number of inputs / outputs and / or integrating sensors. Three-dimensional integration, by using the same metallization layer or by integrating several layers of metal, allows for optimal miniaturization without degrading functions.

[0101] The various embodiments have been described for electronic components in the form of electronic chips. However, it is recalled that other types of electronic components could be suitable.

Claims

1. An electronic system (S) comprising: - a main electronic chip (1) forming a package, said main electronic chip (1) comprising a front surface (1A) comprising a plurality of connectors (11) and a rear surface (1B) opposite the front surface (1A); - at least one electronic component (2) comprising a front surface (2A) comprising a plurality of connectors (21) and a rear surface (2B) opposite the front surface (2A); - the rear surface (2B) of the electronic component (2) being positioned in front of the front surface (1A) of the main electronic chip (1) so that the electronic component (2) projects vertically from the front surface (1A) of the main electronic chip (1); - a plurality of independent three-dimensional interconnections made by metal deposition connecting a connector (21) of the electronic component (2) to a connector (11) of the main electronic chip (1), at least three-dimensional interconnection having an aspect ratio, width to height, of less than 1:1.5 the system being characterized by - for each independent interconnection, at least one contact pad (120) connected to the front surface (1A) of said main electronic chip (1) and formed by metal deposition simultaneously with the three-dimensional interconnection; and - for each independent interconnection, at least one main conductive ball (13) rigidly secured to said contact pad and suitable for being connected to a printed circuit (CI), the main conductive ball (13) extending forward of the front surface (2A) of the electronic component (2).

2. The electronic system (S) according to the preceding claim, in which the electronic system (S) comprises an encapsulation layer (14) to encapsulate the front surface (1A) of the main electronic chip (1) and a portion of the main conductive ball (13).

3. The electronic system (S) according to one of claims 1 to 2, wherein the electronic system (S) comprises at least one auxiliary conductive ball (130), of smaller dimensions than the main conductive ball (13), which is connected to the three-dimensional interconnection (12), the set of conductive balls (13, 130) defining a single connection plane (P).

4. The electronic system (S) according to any of claims 1 to 3, in which at least one three-dimensional interconnection has an aspect ratio, width to height, of less than 1:3.

5. A method for manufacturing an electronic system (S) according to one of claims 1 to 4, comprising: - a step of providing a wafer comprising a plurality of main electronic chips (1), each main electronic chip (1) comprising a front surface (1A) comprising a plurality of connectors (11) and a rear surface (1B) opposite the front surface (1A), - a step of depositing at least one electronic component (2) on each front surface (1A) of each main electronic chip (1), each electronic component (2) comprising a front surface (2A) comprising a plurality of connectors (21) and a rear surface (2B) opposite the front surface (2A), the rear surface (2B) of the electronic component (2) being positioned in front of the front surface (1A) of the main electronic chip (1) so that the electronic component (2) projects vertically from the front surface (1A) of the main electronic chip (1), - a step for producing a plurality of independent three-dimensional interconnections (12) by metal deposition, so as, on the one hand, to connect a connector (21) of the electronic component (2) to a connector (11) of the main electronic chip (1) and, on the other hand, to form, for each independent interconnection, a contact pad (120) connected to the front surface (1A) of said main electronic chip (1), - a step of securing, for each independent interconnection, at least one main conductive ball (13) directly to said contact pad (120), said main conductive ball (13) being adapted to connect to a printed circuit (CI), the main conductive ball (13) extending forward of the front surface (2A) of the electronic component (2), and - a step of cutting the wafer to form independent electronic systems (S) comprising a package formed by the main electronic chip (1).