Stress relief structure for high-power semiconductor components

Description

[0001] Demand for power semiconductor devices with lower on-state resistance (RdsON) values, smaller die (chip) area, and smaller packaging is increasing. In addition to technical advances in semiconductor processing and concept cell design, improvements in die metallization and package-to-die interaction are needed to meet this increased demand. Recent advancements in die metallization and package-to-die interaction include the use of copper metallization on the die and the use of copper clips in the packaging.

[0002] The introduction of copper metallization brings new challenges in the die-to-package interaction as compared to standard aluminum metallization. Increased die bow / warpage and higher residual stress within the die after the soldering process are two examples of challenges exasperated by incorporating copper into die and packaging technologies. Die bow / warpage and residual stress may dramatically influence the die and clip attach processes, leading to formation of voids in the solder and a tilted die with respect to the lead frame or other substrate to which the die is attached.

[0003] The formation of voids within the conductive connection, for example between the die and die attach substrate or between the die and clip, can hinder electrical and thermal properties of the packaged device to such an extent that early failure may occur. Moreover, package devices with such voids cannot always be screened.

[0004] If a die is titled with respect to the substrate to which it is attached, an unusually small amount of solder may be present under one corner or edge of the die as compared to the other corners / edges. The unusually small amount of solder may degrade during temperature cycling, leading to early failure of the device.

[0005] US 2012 / 0261817 A1 discloses a semiconductor device that includes a semiconductor body, a plurality of contact pads formed on a surface of the semiconductor body, a passivation layer formed on the surface between the contact pads, and a stress buffer layer formed on the passivation layer, wherein the stress buffer is patterned to expose the contact pads. Further, the semiconductor device includes a layer stack that is formed on the stress buffer layer and the contact pads. The layer stack includes an adhesion layer, a barrier layer, a seed layer and a metal layer.

[0006] US 2011 0 230 046 A1 discloses a semiconductor die with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of a device integrated in the die. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling.

[0007] US 2011 0 298 048 A1 discloses a semiconductor device capable of relaxing stress transferred to a contact region during wire bonding and improving reliability of wire bonding. The semiconductor device comprises contact regions, an interlayer insulating film, an emitter electrode, and a stress relaxation portion. The contact regions are provided at a certain interval in areas exposing at a surface of a semiconductor substrate. The interlayer insulating film is provided on the surface of the semiconductor substrate between adjacent contact regions. The emitter electrode is provided on an upper side of the semiconductor substrate and electrically connected to each of the contact regions. The stress relaxation portion is provided on an upper surface of the emitter electrode in an area only above the contact regions. The stress relaxation portion is formed of a conductive material. A Young's modulus of the material of the stress relaxation portion is lower than a Young's modulus of the material of the emitter electrode.

[0008] US 2014 0 264 766 A1 discloses a method of forming a stress relieved film stack. The method comprises forming a film stack on a first side of a substrate, the film stack comprising a plurality of film layers and creating a plurality of film stack openings according to a cutting pattern and along at least a portion of a buffer region. The plurality of film stack openings extend from a top surface of the film stack to the substrate. A deflection of the substrate may be determined, and the cutting pattern selected prior to creating the film stack openings based on the deflection of the substrate. The substrate may have a deflection of less than about 2 µm after the creating the plurality of film stack openings. And at least one of the plurality of film layers may comprise one of titanium nitride, silicon carbide and silicon dioxide.

[0009] US 2004 / 0070042 A1 discloses a method to enable wire bond connections over active and / or passive devices and / or low-k dielectrics, formed on an integrated circuit die. A semiconductor substrate having active and / or passive devices is provided, with interconnect metallization formed over the active and / or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and / or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

[0010] More robust techniques which reduce die bow / warpage and higher residual stress within a die of a power semiconductor device in a semiconductor package are needed.

[0011] One embodiment of the present invention relates to a semiconductor package according to claim 1

[0012] In an embodiment, the stress relieving layer or layer stack may comprise a material selected from the group consisting of a polymer, an imide, an alloy of aluminum and copper, an oxide, a nitride, silicon nitride, oxynitride, a nitride-based ceramic, and SiCOH.

[0013] Separately or in combination, the metal layer or layer stack may be an uppermost metal layer of the semiconductor device. Part of the stress relieving layer or layer stack may be free of openings or have a large opening to provide a generally planar surface topography over which the metal layer or layer stack may comprise one or more contact pads.

[0014] Separately or in combination, the plurality of openings in the stress relieving layer or layer stack may be arranged in a regular pattern so that the patterned surface topography of the stress relieving layer or layer stack may have a regular pattern.

[0015] Separately or in combination, the plurality of openings in the stress relieving layer or layer stack may be arranged in a checkerboard pattern, a honeycomb pattern or in stripes so that the patterned surface topography of the stress relieving layer or layer stack may have a checkerboard pattern, a honeycomb pattern or a striped pattern, respectively.

[0016] Separately or in combination, the stress relieving layer or layer stack may have a corrugated profile with alternating ridges and grooves in a cross-section through any row of the plurality of openings.

[0017] Separately or in combination, the plurality of openings in the stress relieving layer or layer stack may comprise an arrangement of regularly-spaced openings of the same or substantially same shape. For example, the shape of the regularly-spaced openings may be selected from the group consisting of square, rectangular, hexagonal, ellipsoidal, and polygonal.

[0018] Separately or in combination, the plurality of openings in the stress relieving layer or layer stack may comprise rows of regularly spaced openings of the same shape.

[0019] Separately or in combination, the stress relieving layer or layer stack may cover between 10% and 100% of an entire main surface of the semiconductor body over which the stress relieving layer or layer stack is disposed. For example, the stress relieving layer or layer stack may cover the entire main surface of the semiconductor body over which the stress relieving layer or layer stack is disposed.

[0020] Separately or in combination, the plurality of openings may be formed in the stress relieving layer or layer stack over a first part of the semiconductor body, and the stress relieving layer or layer stack may be free of openings or have a large opening over a second part of the semiconductor body adjacent the first part to provide a generally planar surface topography. For example, the first part of the semiconductor body may be a central part of the semiconductor body and the second part of the semiconductor body may be a periphery region of the semiconductor body which laterally surrounds the central part.

[0021] Separately or in combination, the metal layer or layer stack may comprise: a barrier metal layer covering a top main surface of the stress relieving layer or layer stack and sidewalls of the openings in the stress relieving layer or layer stack; and a copper layer covering the barrier metal layer.

[0022] Separately or in combination, in a same row of the openings in the stress relieving layer or layer stack, a spacing between adjacent ones of the openings may be approximately equal to a width of the openings.

[0023] Separately or in combination, the stress relieving layer or layer stack may be formed on an AlCu layer, and the metal layer or layer stack may be in electrical contact with the AlCu layer through the plurality of openings or through a large opening in the stress relieving layer or layer stack.

[0024] Separately or in combination, the stress relieving layer or layer stack may comprise a doped region and / or polysilicon at a rear main surface of the semiconductor body which is structured with recesses and the metal layer or layer stack may comprise a barrier layer covering the structured rear main surface of the semiconductor body and a copper layer formed on the barrier layer and filling the recesses in the structured rear main surface of the semiconductor body.

[0025] Another embodiment of the present invention relates to a method according to claim 5

[0026] In an embodiment, part of the stress relieving layer or layer stack may be free of openings or have a larger opening to provide a generally planar surface topography over which the metal layer or layer stack may comprise a contact pad, and the metal connector may be attached to the contact pad.

[0027] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

[0028] The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows. The embodiments of the figures show partial aspects, but not all of the features of an embodiment of the present invention, which is defined by the appended claims. Figure 1 illustrates a cross-sectional view of part of a semiconductor device having a stress relieving layer or layer stack. Figure 2 illustrates a perspective view of the stress relieving layer or layer stack and a metal layer or layer stack formed on the stress relieving layer or layer stack. Figure 3 illustrates a perspective view of the stress relieving layer or layer stack without the metal layer or layer stack. Figure 4A illustrates a plan view of the metal layer or layer stack formed on the stress relieving layer or layer stack. Figure 4B illustrates a cross-sectional view of the structure taken through the line labeled A-A' in Figure 4A. Figure 4C illustrates a cross-sectional view of the structure taken through the line labeled B-B' in Figure 4A. Figure 5 illustrates a plan view of another embodiment of the metal layer or layer stack formed on the stress relieving layer or layer stack. Figure 6 illustrates a plan view of another embodiment of the metal layer or layer stack formed on the stress relieving layer or layer stack. Figure 7 illustrates a plan view of another embodiment of the metal layer or layer stack formed on the stress relieving layer or layer stack. Figure 8 illustrates a plan view of another embodiment of the metal layer or layer stack formed on the stress relieving layer or layer stack. Figure 9 illustrates a plan view of another embodiment of the metal layer or layer stack formed on the stress relieving layer or layer stack. Figure 10 illustrates a plan view of another embodiment of the metal layer or layer stack formed on the stress relieving layer or layer stack. Figure 11 illustrates a partial cross-sectional view of another embodiment of the metal layer or layer stack formed on the stress relieving layer or layer stack with a smaller elastic modulus than the metal layer or layer stack Figure 12 illustrates a partial cross-sectional view of another embodiment of the metal layer or layer stack formed on the stress relieving layer or layer stack. Figure 13 illustrates a partial cross-sectional view of another embodiment of the metal layer or layer stack formed on the stress relieving layer or layer stack. Figure 14 illustrates a cross-sectional view of a semiconductor package that includes the semiconductor device shown in Figure 1. Figures 15A and 15B illustrate respective cross-sectional views of part of a semiconductor device having a stress relieving layer or layer stack. Figures 16 illustrates a partial cross-sectional view of another embodiment of the metal layer or layer stack formed on the stress relieving layer or layer stack with a higher elastic modulus than the metal layer or layer stack.

[0029] Embodiments described herein provide a stress relieving layer or layer stack disposed over at least part of a semiconductor body, for counteracting stress imparted by a metal layer or layer stack disposed above the stress relieving layer or layer stack. The stress relieving layer or layer stack has a plurality of openings which yield a patterned surface topography. The patterned surface topography for the stress relieving layer or layer stack is transferred to the surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack absorbs at least some of the stress imparted by the metal layer or layer stack during temperature cycling and / or residual stress stored within the metal layer or layer stack, reducing the likelihood of die bow / warpage and high mechanical stress.

[0030] Figure 1 illustrates a cross-sectional view of part of a semiconductor device 100. The semiconductor device 100 includes a semiconductor body 102. The semiconductor body 102 may be part of a semiconductor wafer prior to die singulation, or may be part of a semiconductor die (chip) post die singulation. In either case, one or more passive and / or active devices may be formed in the semiconductor body 102. A power device such as an insulated gate bipolar transistor (IGBT), power metal-oxide-semiconductor field effect transistor (MOSFET), high-electron mobility transistor (HEMT), power diode, half-bridge, full-bridge, etc. is formed in the semiconductor body 102. In addition, a logic device such as a processor, ASIC (application-specific integrated-circuit), memory, controller, etc. may be formed in the semiconductor body 102. In addition, a sensor such as a Hall sensor, microelectromechanical systems (MEMS), etc. may be formed in the semiconductor body 102. Still other types of passive and / or active devices may be formed in the semiconductor body 102. The device(s) formed in the semiconductor body 102 are not shown in Figure 1 for ease of illustration, but may include doped regions of different conductivity types, gate structures, trenches, field plates, ohmic contacts, etc.

[0031] A stress relieving layer (i.e. a single stress relieving layer) or layer stack (i.e. more than one stress relieving layer stacked one above the other) 104 is disposed over at least part of the semiconductor body 102. That is, the stress relieving layer or layer stack 104 covers all or only a portion of the semiconductor body 102. For example, the stress relieving layer or layer stack 104 may cover between 10% and 100% of the entire main surface 106 of the semiconductor body 102 over which the stress relieving layer or layer stack 104 is disposed. In one embodiment, the stress relieving layer or layer stack 104 may cover the entire main surface 106 of the semiconductor body 102 over which the stress relieving layer or layer stack 104 is disposed.

[0032] The stress relieving layer or layer stack 104 has a plurality of openings 108 which yield a patterned surface topography for the stress relieving layer or layer stack 104. That is, the surface 110 of the stress relieving layer or layer stack 104 facing away from the semiconductor body 102 has a patterned shape which is defined by the number, spacing, shape and dimensions of the openings 108 formed in the stress relieving layer or layer stack 104. The openings 108 in the stress relieving layer or layer stack 104 may be arranged in a regular or irregular pattern so that the patterned surface topography of the stress relieving layer or layer stack 104 has a corresponding regular or irregular pattern, respectively. The openings 108 may be formed by a standard etch process such as masking and wet or dry etching of the stress relieving layer or layer stack 104, by laser drilling of the stress relieving layer or layer stack 104, by patterned deposition of the stress relieving layer or layer stack 104, etc.

[0033] A metal layer (i.e. a single metal layer) or layer stack (i.e. more than one metal layer stacked one above the other) 112 is formed on the stress relieving layer or layer stack 104 and occupies the openings 108 in the stress relieving layer or layer stack 104. The metal layer or layer stack 112 may partly or completely fill the openings 108 in the stress relieving layer or layer stack 104. Any commonly used metal(s) or metal stack in the semiconductor industry may be used.

[0034] The patterned surface topography of the stress relieving layer or layer stack 104 is transferred to the surface 114 of the metal layer or layer stack 112 facing away from the semiconductor body 102. Accordingly, the surface 114 of the metal layer or layer stack 112 facing away from the semiconductor body 102 has the same or substantially same patterned shape as the surface 110 of the stress relieving layer or layer stack 104 facing away from the semiconductor body 102. While the metal layer or layer stack 112 and the stress relieving layer or layer stack 104 have the same or substantially same general shape / structure / contour, the relative dimensions may differ. For example, the vertical sidewalls 116 of the openings 108 in the stress relieving layer or layer stack 104 may be covered with slightly more or slightly less material than the horizontal parts 118, and the thickness of the metal layer or layer stack 112 along the sidewalls 116 of the openings 108 may be different than the thickness of the metal layer or layer stack 112 at the bottom 120 of the openings 108 and on the horizontal parts 118 of the stress relieving layer or layer stack 104. Also, the surface 114 of the metal layer or layer stack 112 with the patterned topography is not planarized. Hence, the metal layer or layer stack 112 retains the patterned surface topography transferred from the stress relieving layer or layer stack 104. The metal layer or layer stack 112 may be a thick layer such that the patterned surface topography transferred from the stress relieving layer or layer stack 104 may be barely visible.

[0035] The stress relieving layer or layer stack 104 also has a different elastic modulus (e.g. Young's modulus) than the metal layer or layer stack 112 over a temperature range, which may or may not be the full (entire) operating range of the semiconductor device 100. In one embodiment, the stress relieving layer or layer stack 104 has a smaller elastic modulus than the metal layer or layer stack 112 over the temperature range of interest. For example, the stress relieving layer or layer stack 104 may comprise one or more of a stable or dissolvable polymer, an imide, an alloy of aluminum and copper, and an oxide. The stress relieving layer or layer stack 104 absorbs at least some of the stress imparted by the metal layer or layer stack 112 during temperature cycling and / or residual stress stored within the metal layer or layer stack 112, reducing the likelihood of die bow / warpage and high mechanical stress.

[0036] In another embodiment, the stress relieving layer or layer stack 104 has a higher elastic modulus than the metal layer or layer stack 112 over the temperature range of interest. For example, the stress relieving layer or layer stack 104 may comprise one or more of a tungsten-based alloy, e.g., with titanium or nitride, nickel or a nickel-based alloy, e.g., with vanadium or phosphorus, doped silicon and / or polysilicon. In the case of doped silicon, the rear main surface 122 of the semiconductor body 102 may be doped with phosphorus, then structured, e.g., by etching, and then filled, e.g., with copper. The stress relieving layer or layer stack 104 may compensate some of the stress imparted by the metal layer or layer stack 112 during temperature cycling and / or residual stress in a way to reduce the likelihood of die bow / warpage and high mechanical stress.

[0037] The metal layer or layer stack 112 and the corresponding stress relieving layer or layer stack 104 may be applied over either side of the semiconductor body 102. That is, the metal layer or layer stack 112 and the corresponding stress relieving layer or layer stack 104 may be applied over the front main surface 106 of the semiconductor body 102, over the rear main surface 122 of the semiconductor body 102, or over both main surfaces 106, 122.

[0038] The metal layer or layer stack 112 with the same or substantially same patterned surface topography as the stress relieving layer or layer stack 104 may be the uppermost (final) metallization of the semiconductor device 100. In this case, the metal layer or layer stack 112 provides one or more points of external electrical contact for the device(s) formed in the semiconductor body 102. For example, the metal layer or layer stack 112 may include a gate pad, a source pad and / or drain pad in the case of a power transistor device such as an IGBT, bipolar transistor, HEMT, MEMS, etc. The metal layer or layer stack 112 may include an anode pad and / or a cathode pad in the case of a power diode device. The metal layer or layer stack 112 may include a substantial number of pads in the case of a logic device.

[0039] The metal layer or layer stack 112 with the same or substantially same patterned surface topography as the stress relieving layer or layer stack 104 instead may be the lowermost (first) metallization closest to the semiconductor body 102. In this case, an additional layer or layer stack 124 such as an oxide or one or more additional metal layers or layer stacks may be provided above the metal layer or layer stack 112. The number and composition of layers disposed above the metal layer or layer stack 112 may vary for different areas of the semiconductor device 100 independent of the metal layer or layer stack 112 and stress relieving layer or layer stack 104. The metal layer or layer stack 112 with the same or substantially same patterned surface topography as the stress relieving layer or layer stack 104 instead may be an intermediary metallization. In this case, one or more additional metal layers or layer stacks are formed above the intermediary metal layer or layer stack and one or more additional metal layers or layer stacks are formed below the intermediary metal layer or layer stack, with an interlayer dielectric separating the different metallization layers.

[0040] Figure 1 shows the metal layer or layer stack 112 as either the uppermost (final) metallization or as an intermediary metallization. In this case, one or more additional metallization layers may be provided between the metal layer or layer stack 112 and the semiconductor body 102, and additional layer(s) may be disposed between the intermediary metallization and the semiconductor substrate as indicated by the vertical dotted line.

[0041] For example, one of the additional layer or layer stack 124 may be an additional metallization such as a wiring layer on which the stress relieving layer or layer stack 104 is formed. The metal layer or layer stack 112 with the same or substantially same patterned surface topography as the stress relieving layer or layer stack 104 may be in electrical contact with the additional metallization layer through the openings 108 in the stress relieving layer or layer stack 104. In one embodiment, the openings 108 in the stress relieving layer or layer stack 104 are arranged independent of the layout of the additional metallization layer 124. That is, while the openings 108 in the stress relieving layer or layer stack 104 enable electrical contact between the two metallization layers 112, 124 separated by the stress relieving layer or layer stack 104, the layout of the openings 108 is designed so that the stress relieving layer or layer stack 104 absorbs at least some of the stress imparted by the overlying metal layer or layer stack 112 during temperature cycling and / or residual stress stored within the metal layer or layer stack 112.

[0042] Figure 2 illustrates a perspective view of the stress relieving layer or layer stack 104 and the metal layer or layer stack 112 with the same or substantially same patterned surface topography, according to an embodiment. Figure 3 illustrates a perspective view of the stress relieving layer or layer stack 104 without the metal layer or layer stack 112. According to this embodiment, the stress relieving layer or layer stack 104 has rows 126 of regularly-spaced openings 108 of the same or substantially same shape. The shape of the regularly-spaced openings 108 may be square, rectangular, hexagonal, ellipsoidal, polygonal, etc. While the openings 108 in the stress relieving layer or layer stack 104 are shown as being arranged in a regular pattern in Figures 2 and 3, the pattern instead may be irregular. In either case, the patterned surface topography of the stress relieving layer or layer stack 104 is transferred to the metal layer or layer stack 112 formed on the stress relieving layer or layer stack 104 so that the metal layer or layer stack 112 has the same or substantially same patterned surface topography as the stress relieving layer or layer stack 104.

[0043] Figure 4A illustrates a plan view of the metal layer or layer stack 112 formed on the stress relieving layer or layer stack 104. Figure 4B illustrates a cross-sectional view of the structure taken through the line labeled A-A' in Figure 4A. Figure 4C illustrates a cross-sectional view of the structure taken through the line labeled B-B' in Figure 4A. As described above, the metal layer or layer stack 112 may be the uppermost (final) metallization, lowermost (first) metallization or an intermediary metallization.

[0044] The cross-sectional in Figure 4B transects through a row of the openings 108 in the stress relieving layer or layer stack 104, whereas the cross-sectional in Figure 4C transects through the structure between adjacent rows 108. According to this embodiment, the stress relieving layer or layer stack 104 covers the entire main surface 106 of the semiconductor body 102 over which the stress relieving layer or layer stack 104 is disposed. As shown in Figures 4B and 4C, the surface topography of the metal layer or layer stack 112 follows the surface topography of the stress relieving layer or layer stack 104. That is, the surface 114 of the metal layer or layer stack 112 facing away from the semiconductor body 102 has the same or substantially same patterned shape as the surface 110 of the stress relieving layer or layer stack 104 facing away from the semiconductor body 102.

[0045] Figure 5 illustrates a plan view of another embodiment of the metal layer or layer stack 112 formed on the stress relieving layer or layer stack 104. According to this embodiment, the metal layer or layer stack 112 is the uppermost (final) metal layer of the semiconductor device 100. The stress relieving layer or layer stack 104 is out of view in Figure 5. However, part of the stress relieving layer or layer stack 104 is free of openings and has a generally planar surface topography. The generally planar surface topography is transferred to the metal layer or layer stack 112. The metal layer or layer stack 112 may include one or more contact pads 200 disposed over the part of the stress relieving layer or layer stack 104 which is free of openings, e.g. in the case of a current or temperature sensor routed in the planar part of the metal layer or layer stack 112. That is, the one or more contact pads 200 are formed in a part 202 of the metal layer or layer stack 112 that has a generally planar surface topography. In another embodiment, part of the stress relieving layer or layer stack 104 has a large opening to provide a generally planar surface topography over which the one or more contact pads 200 are formed, e.g. to contact a metal layer disposed below the stress relieving layer or layer stack 104. In either case, each contact pad 200 has a relatively top planar surface. External electric connections can be made to the one or more contact pads 200, e.g., by way of bond wires, metal ribbons, metal clips, solder, etc. The remainder of the metal layer or layer stack 112 has a nonplanar surface topography which mimics the nonplanar surface topography of the underlying stress relieving layer or layer stack 104. The exploded view in Figure 5 enlarges the border between the planar and nonplanar surface topographies of the metal layer or layer stack 112.

[0046] The metal layer or layer stack 112 may include one or more bridge areas 201 for electrically connecting neighboring regions of the metal layer or layer stack 112 without connecting the metal layer or layer stack 112 to an underlying conductive structure such as a metal or polysilicon line. The underlying conductive structure may be a source finger, gate finger, etc. routed under the metal layer or layer stack 112. The stress relieving layer or layer stack 104 is present under each bridge area 201, as descried herein, and acts as a bridge mechanism for connecting neighboring regions of the metal layer or layer stack 112 while also isolating the metal layer or layer stack 112 from an underlying conductive structure e.g. in the case of a gate finger, a source finger, a metal connection of a sensor such as a current or temperature, etc.

[0047] Figure 6 illustrates a plan view of another embodiment of the metal layer or layer stack 112 formed on the stress relieving layer or layer stack 104. According to this embodiment, the openings 108 in the stress relieving layer or layer stack 104 are arranged in a checkerboard pattern so that the patterned surface topography of the stress relieving layer or layer stack 104 has a checkerboard pattern which is transferred to the metal layer or layer stack 112. The spacing (Sp) between adjacent ones of the openings 108 in the same row 126 of openings 108 in the stress relieving layer or layer stack 104 may be approximately equal to the width (W) of the openings 108. Other spacings and widths are contemplated. The spacing (Sp) and the width (W) may be different, and may differ between rows of openings 108 in the stress relieving layer or layer stack 104. The openings 108 in the stress relieving layer or layer stack 104 are not visible in Figure 6.

[0048] Figure 7 illustrates a plan view of another embodiment of the metal layer or layer stack 112 formed on the stress relieving layer or layer stack 104. According to this embodiment, the openings 108 in the stress relieving layer or layer stack 104 are arranged in a honeycomb pattern so that the patterned surface topography of the stress relieving layer or layer stack 104 has a honeycomb pattern which is transferred to the metal layer or layer stack 112. The spacing (Sp) between adjacent ones of the openings 108 in the same row 126 of openings 108 in the stress relieving layer or layer stack 104 may be approximately equal to the width (W) of the openings 108. Other spacings and widths are contemplated. The spacing (Sp) and the width (W) may be different, and may differ between rows of openings 108 in the stress relieving layer or layer stack 104. The openings 108 in the stress relieving layer or layer stack 104 are not visible in Figure 7.

[0049] Figure 8 illustrates a plan view of another embodiment of the metal layer or layer stack 112 formed on the stress relieving layer or layer stack 104. According to this embodiment, the metal layer or layer stack 112 covers at least 90% of the semiconductor body 102 and is segmented into separate sections 300, 302, 304. Some of the sections 300, 302, 304 may include contact pads 306, and / or some or all the sections 300, 302, 304 may form contact pads by themselves. In each case, each section 300, 302, 304 of the metal layer or layer stack 112 has the same or substantially same patterned shape as the portion of the surface of the stress relieving layer or layer stack 104 underlying that section 300, 302, 304. The separate sections 300, 302, 304 may be electrically connected by to each other by bridge areas, e.g., as previously described herein in connection with Figure 5.

[0050] Figure 9 illustrates a plan view of another embodiment of the metal layer or layer stack 112 formed on the stress relieving layer or layer stack 104. The embodiment shown in Figure 9 is similar to the one shown in Figure 8. Different, however, the metal layer or layer stack 112 covers less than 90%, e.g. between about 75% to 25%, of the semiconductor body 102.

[0051] Figure 10 illustrates a plan view of another embodiment of the metal layer or layer stack 112 formed on the stress relieving layer or layer stack 104. According to this embodiment, the stress relieving layer or layer stack 104 has a corrugated profile with alternating ridges 400 and grooves 402 in a transverse cross-section through any row of the plurality of openings 108. The metal layer or layer stack 112 has the same or substantially same corrugated profile as the stress relieving layer or layer stack 104.

[0052] Figure 11 illustrates a partial cross-sectional view of another embodiment of the metal layer or layer stack 112 formed on the stress relieving layer or layer stack 104. According to this embodiment, the metal layer or layer stack 112 includes a barrier metal layer 500 such as WTi, Ta, TaN, TiN, Ti, W, TiW, etc. covering the top main surface 110 of the stress relieving layer or layer stack 104 and sidewalls 116 of the openings 108 in the stress relieving layer or layer stack 104. The metal layer or layer stack 112 includes a copper layer 502 covering the barrier metal layer 500. The barrier metal layer 500 and copper layer 502 may be formed using any common copper metallurgy process such as physical or chemical deposition, electroplating, etc. In some cases, the barrier metal layer 500 may be omitted if the base metal composition of the metal layer or layer stack 112 is less likely to diffuse, e.g., in the case of Cu-Ge alloys such as epitaxial CusGe. The material on which the stress relieving layer or layer stack 104 is formed may be the semiconductor body 102, another layer or layer stack 124, e.g., such as another Cu layer, an AICu layer, etc., or an insulating layer, e.g., such as oxide, nitride, silicon nitride, oxynitride, nitride-based ceramics, SiCOH, etc.

[0053] Figure 12 illustrates a partial cross-sectional view of another embodiment of the metal layer or layer stack 112 formed on the stress relieving layer or layer stack 104. The exploded view in Figure 12 enlarges part of the illustrated semiconductor device. According to this embodiment, the stress relieving layer or layer stack 104 comprises imide and covers the entire main surface 106 of the semiconductor body 102 over which the stress relieving layer or layer stack 104 is disposed. The overlying metal layer or layer stack 112 includes a barrier metal layer 600 such as WTi, Ta, TaN, TiN, etc. covering the top main surface 110 of the stress relieving layer or layer stack 104 and sidewalls 116 of the openings 108 in the stress relieving layer or layer stack 104. The overlying metal layer or layer stack 112 includes a copper layer 602 covering the barrier metal layer 600. The barrier metal layer 600 and copper layer 602 may be formed using any common copper metallurgy process such as physical or chemical deposition, electroplating, etc. The overlying metal layer or layer stack 112 is in electrical contact with an underlying metal layer or layer stack 124 through the openings 108 in the stress relieving layer or layer 104. In one embodiment, the underlying metal layer or layer stack 124 includes an AICu layer 604 on which the stress relieving layer or layer 104 is formed and a barrier layer 606 such as W, TiW, etc. under the AICu layer. The barrier layer 606 is separated from the semiconductor body 102 by a dielectric layer 608, e.g., such as borophosphosilicate glass (BPSG). The dielectric layer 608 may have grooves which allow for electrical contact to the semiconductor body 102.

[0054] The plurality of openings 108 in the stress relieving layer or layer stack 104 may be arranged in a regular or irregular pattern so that the patterned surface topography of the stress relieving layer or layer stack 104 has a corresponding regular or irregular pattern, respectively. Figure 12 illustrates an embodiment in which the spacing (Sp) between adjacent ones of the openings 108 in the same row of openings 108 in the stress relieving layer or layer stack 104 is approximately equal to the width (W) of the openings 108. For example, the spacing (Sp) and the width (W) may be approximately 10 µm (microns). Other spacings and widths are contemplated, and the 10 µm example given above is purely illustrative and should not be considered limiting. The spacing (Sp) and the width (W) parameters may be different, and may differ across rows of openings 108 in the stress relieving layer or layer stack 104.

[0055] The height or thickness (H) of the stress relieving layer or layer stack 104 may be in a range of about 6 to 11 µm, for example. The inventors have discovered that increasing the height / thickness (H) of an imide-based stress relieving layer or layer stack having a patterned surface topography as described herein from about 6 µm to 11 µm increases bow / warpage at lower temperatures below about 250 C, whereas the bow / warpage remains mostly unchanged for higher temperatures above about 250 C. The height / thickness (H) of the stress relieving layer or layer stack 104 instead may be less than 6 µm or greater than 11 µm. The inventors have also discovered that the bow / warpage change (slope) around 300°C is flatter for dies with an imide-based stress relieving layer or layer stack having a patterned surface topography as described herein, compared with dies having zero coverage by such a patterned imide-based stress relieving layer or layer stack. This is particularly important as the solidification of solder happens around this temperature, leading to a more stable die attach process with respect to process variation of the die processing.

[0056] Figure 13 illustrates a partial cross-sectional view of another embodiment of the metal layer or layer stack 112 formed on the stress relieving layer or layer stack 104. The embodiment shown in Figure 13 is similar to the one shown in Figure 12. Different, however, the plurality of openings 108 in the stress relieving layer or layer stack 104 are formed over a first part 700 of the semiconductor body 102 and a large opening is formed in the stress relieving layer or layer stack 104 over a second part 702 of the semiconductor body 102 adjacent the first part 700 to provide a generally planar surface topography. The metal layer or layer stack 112 contacts the underlying additional layer or layer stack 124 through the large opening. The inventors have discovered that partial coverage of a die with a stress relieving layer or layer stack having a patterned surface topography as described herein (e.g. about 50% coverage or the inner part of the die) is still beneficial in terms of bow / warpage reduction, but not to the same extent as full coverage. The same also applies for placement of the patterned surface topography on the outer half (periphery) of the die.

[0057] In one embodiment, the first part 700 of the semiconductor body 102 is a central part of the semiconductor body 102 and the second part 702 is a periphery region of the semiconductor body 102 which is located along at least one side of the central part or which laterally surrounds the central part in its entirety. The semiconductor device formed in the semiconductor body 102 is disposed in the central part of the semiconductor body 102, which may be considered the active region of the semiconductor body 102. The active region of the semiconductor body 102 is the region of the semiconductor body 102 that includes the constituent parts of the device. For example, the active region may include doped regions of different conductivity types, gate structures, trenches, field plates, ohmic contacts, etc.

[0058] Figure 14 illustrates a cross-sectional view of a semiconductor package 800 that includes the semiconductor device 100 shown in Figure 1. The semiconductor body 102 of the device 100 is attached to a standard substrate 802 such as a printed circuit board (PCB), lead frame, etc. The semiconductor package 800 also includes a metal connector 804 such as a clip attached at one end to the metal layer or layer stack 112 of the semiconductor device 100. The opposite end of the metal connector 804 is attached to the substrate 802, e.g., to a metal trace of a PCB, to a lead of a lead frame, etc. The metal connector 804 may be joined to the metal layer or layer stack 112 by solder 806. The inventors have discovered that using a metal layer or layer stack having a patterned surface topography as described herein localizes and distributes solder voids in the 'dimpled' or 'depressed' regions 808 of the metal layer or layer stack 112.

[0059] In one embodiment, part of the stress relieving layer or layer stack 104 may be free of openings or have a large opening to provide a generally planar surface topography. The metal layer or layer stack 112 may have a contact pad disposed over the generally planar surface topography, e.g., as described previously herein in connection with Figures 5, 8 and 9. The metal connector 804 may be attached to the contact pad in this case. Still other metal connector attachment configurations are contemplated and within the scope of the embodiments described herein.

[0060] While the embodiments previously described herein describe the surface 114 of the metal layer or layer stack 112 with the patterned topography as being non-planarized, the surface 114 instead may be subjected to a planarization process such as chemical-mechanical polishing (CMP). Figure 15A illustrates a corresponding a semiconductor device 900. As shown in Figure 15A, the top surface 114 of the metal layer or layer stack 112 is generally planar. Adequate stress relief is provided by the stress relieving layer or layer stack 104 since the openings 108 in the stress relieving layer or layer stack 104 are filled with metal. In some cases, the top surface 110 of the stress relieving layer or layer stack 104 may be partly visible after planarization of the metal layer or layer stack 112, e.g. as shown in Figure 15B. The metal layer or layer stack 112 may be recessed below the top surface 110 of the stress relieving layer or layer stack 104 depending on the type of planarization process employed or by design.

[0061] Figures 16 illustrates a partial cross-sectional view of an embodiment in which a copper layer 1000 and a barrier metal layer 1002 are formed on the rear main surface 122 of the semiconductor body 102 to form a back-side metallization stack. According to this embodiment, the stress relieving layer or layer stack 104 has a higher elastic modulus than the back-side metallization stack 1000 / 1002 over the temperature range of interest. For example, the stress relieving layer or layer stack 104 may comprise doped silicon and / or polysilicon. In the case of doped silicon, the rear main surface 122 of the semiconductor body 102 may be doped with phosphorus, then structured, e.g., by etching, so that the rear main surface 122 of the semiconductor body 102 has recesses. The rear main surface 122 of the semiconductor body 102 is then covered by the barrier metal layer 1002 and the recesses are then filled with the copper layer 1000. The stress relieving layer or layer stack 104 may compensate some of the stress imparted by the back-side metallization stack 1000 / 1002 during temperature cycling and / or residual stress in a way to reduce the likelihood of die bow / warpage and high mechanical stress, as previously described herein.

[0062] Spatially relative terms such as "under", "below", "lower", "over", "upper" and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as "first", "second", and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

[0063] As used herein, the terms "having", "containing", "including", "comprising" and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

Claims

1. A semiconductor package comprising a power semiconductor device attached to a substrate (802) and a metal clip (804) attached at one end to a metal layer stack (112) of the power semiconductor device and at an opposite end to the substrate (802), the power semiconductor device, comprising: a semiconductor body (102); a stress relieving layer or layer stack (104) disposed over at least part of the semiconductor body (102), the stress relieving layer or layer stack (104) comprising a plurality of openings (108) which yield a patterned surface topography for the stress relieving layer or layer stack (104); the metal layer stack (112) formed on the stress relieving layer or layer stack (104) and occupying the plurality of openings (108) in the stress relieving layer or layer stack (104); and a wiring layer (124) on which the stress relieving layer or layer stack (104) is formed, wherein the metal layer stack (112) is in electrical contact with the wiring layer (124) through the plurality of openings (108) in the stress relieving layer or layer stack (104), wherein the patterned surface topography of the stress relieving layer or layer stack (104) is transferred to a surface of the metal layer or layer stack (112) facing away from the semiconductor body (102) and the metal clip (804) is joined to the metal layer stack (112) by solder, wherein the stress relieving layer or layer stack (104) has a different elastic modulus than the metal layer or layer stack (112) over a temperature range, wherein the wiring layer (124) is arranged on a dielectric layer (608) that is directly formed on the semiconductor body (102) and comprises grooves which allow for electrical contact to the semiconductor body (102), and wherein the metal layer stack (112) comprises a copper layer (602) and a barrier layer (606) separated from the semiconductor body (102) by the dielectric layer (608).

2. The semiconductor package of claim 1, wherein part of the stress relieving layer or layer stack (104) is free of openings (108) or has a large opening to provide a generally planar surface topography over which the metal layer or layer stack (112) comprises one or more contact pads.

3. The semiconductor package of any one of claims 1 to 2, wherein the plurality of openings (108) in the stress relieving layer or layer stack (104) is arranged in a regular pattern so that the patterned surface topography of the stress relieving layer or layer stack (104) has a regular pattern.

4. The semiconductor package of any one of the preceding claims, wherein the wiring layer (124) comprises an AlCu layer (604).

5. A method of manufacturing a semiconductor package with a power semiconductor device and a metal clip (804) attached to a metal layer stack (112) of the power semiconductor device, the method comprising: forming one or more devices in a semiconductor body (102); forming a stress relieving layer or layer stack (104) over at least part of the semiconductor body (102); forming a plurality of openings (108) in the stress relieving layer or layer stack (104) and which yield a patterned surface topography for the stress relieving layer or layer stack (104); and forming the metal layer stack (112) on the stress relieving layer or layer stack (104) so that the metal layer stack (112) occupies the plurality of openings (108) in the stress relieving layer or layer stack (104) and the patterned surface topography of the stress relieving layer or layer stack (104) transfers to a surface of the metal layer or layer stack (112) facing away from the semiconductor body (102), the metal stack (104) having a different elastic modulus than the stress relieving layer or layer stack (112) over a temperature range; and attaching the power semiconductor device to the substrate (802) and joining one end of the metal clip (804) to the metal layer stack (112) by solder and attaching an opposite end of the metal clip to the substrate (802), wherein the method further comprises: forming a wiring layer (124) on which the stress relieving layer or layer stack (104) is formed, wherein the metal layer or layer stack (112) is in electrical contact with the wiring layer (124) through the plurality of openings (108) in the stress relieving layer or layer stack (104), wherein the wiring layer (124) is formed on a dielectric layer (608) that is directly formed on the semiconductor body (102) and comprises grooves which allow for electrical contact to the semiconductor body (102), and wherein the metal layer stack (112) comprises a copper layer (602) and a barrier layer (606) separated from the semiconductor body (102) by the dielectric layer (608).