OPERATIONAL AMPLIFIER AND CHIP

Description

TECHNICAL FIELD

[0001] This application relates to the field of electronic technologies, and in particular, to an operational amplifier and a chip.BACKGROUND

[0002] An operational amplifier (OPA) is the most fundamental module in an analog circuit. For example, the operational amplifier is an indispensable module in an integrator, a filter, an adder, and an analog-to-digital converter. In some extreme conditions, performance of a transistor is affected, and a speed of the operational amplifier is reduced or performance of the operational amplifier deteriorates. For example, as an operating temperature increases or decreases, a threshold voltage of the transistor varies inversely. This may cause an insufficient voltage margin of the transistor, and the transistor cannot maintain operating in a saturation region. Alternatively, a process variation or an unstable operating voltage may also cause an insufficient voltage margin of the transistor, and affects performance of the operational amplifier. With technology development and process evolution, a design requirement for the operational amplifier becomes increasingly high. It is expected in the industry that the operational amplifier can maintain good operating performance in some extreme conditions.

[0003] US2012049960 relates to a pre-driver and a digital transmitter using the same.

[0004] STEFANO D'AMICO ET AL, "Active-Gm-RC Continuous-Time Biquadratic Cells", ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, KLUWER ACADEMIC PUBLISHERS, BO, (20051201), vol. 45, no. 3, doi:10.1007 / 510470-005-4956-9, ISSN 1573-1979, pages 281 - 294, relates to active-Gm-RC continuous-time biquadratic cells.

[0005] FRANCESCO CENTURELLI ET AL, "An improved common-mode feedback loop for the differential-difference amplifier", ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, KLUWER ACADEMIC PUBLISHERS, BO, (20120925), vol. 74, no. 1, doi:10.1007 / S10470-012-9961-1, ISSN 1573-1979, pages 33 - 48 relates to common-mode feedback loop for the differential-difference amplifier.SUMMARY

[0006] This application provides an operational amplifier and a chip, to improve performance of the operational amplifier.

[0007] The invention has been defined in the independent claims. Further specific technical features have been defined in the dependent claims.

[0008] In accordance with certain implementations, the reference voltage that varies with the temperature and / or the operating voltage is provided to the common-mode feedback circuit, so that the common-mode voltage of the output voltage of the operational amplifier can be adjusted based on the temperature and / or the operating voltage. Therefore, a voltage margin of a transistor in the operational amplifier can be flexibly adjusted in real time based on the temperature and / or the operating voltage, and operating performance of the operational amplifier is improved.

[0009] In accordance with certain implementations, the first level switching circuit and the second level switching circuit are disposed in the common-mode feedback circuit, to perform level switching on the input voltage of the common-mode feedback circuit, to ensure operating performance of the amplification circuit in the common-mode feedback circuit, and improve operating performance of the operational amplifier.

[0010] In accordance with certain implementations, to compensate for a phase margin of the common-mode feedback circuit, the common-mode voltage is directly coupled to the last stage of amplification circuit in the amplification circuit via a filter circuit, to form a one-stage amplification effect on the common-mode voltage. Because there is only one pole, the common-mode voltage attenuates relatively slowly at a high frequency, so that a phase margin compensation effect is formed, and performance of the operational amplifier when operating at a high frequency is improved.BRIEF DESCRIPTION OF DRAWINGS

[0011] FIG. 1 is a schematic diagram of a framework of an operational amplifier according to an implementation of this application; FIG. 2 is a schematic diagram of a differential amplification circuit according to an implementation of this application; FIG. 3 is a schematic diagram of a differential amplification circuit according to another implementation of this application; FIG. 4 is a schematic diagram of a reference voltage generation circuit according to an implementation of this application; FIG. 5 is a schematic diagram of a reference voltage generation circuit according to another implementation of this application; FIG. 6 is a schematic diagram of a reference voltage generation circuit according to still another implementation of this application; FIG. 7 is a schematic diagram of a buffer according to an implementation of this application; FIG. 8 is a schematic diagram of an operational amplifier according to another implementation of this application; FIG. 9 is a schematic diagram of a common-mode feedback circuit according to an implementation of this application; and FIG. 10 is a schematic diagram of a chip according to an implementation of this application. DESCRIPTION OF IMPLEMENTATIONS

[0012] To make the objectives, technical solutions, and advantages of this invention clearer, the following further describes various implementations in detail with reference to the accompanying drawings. The implementations described below are not all claimed, they are included to help understanding the context of the invention. While the description refers to various implementations, the embodiments of the invention are those which comprise at least all the features of an independent claim. Any implementation which does not fall within the scope of the claims does not form part of the invention, but rather included as an illustrative example that is useful for understanding the invention.

[0013] Implementations of this application provide an operational amplifier, to improve operating performance of the operational amplifier in a low-voltage operating state.

[0014] In the related art, the operational amplifier usually includes a common-mode feedback circuit, and the common-mode feedback circuit is configured to adjust a common-mode voltage of an output voltage of the operational amplifier. An input terminal of the common-mode feedback circuit is configured to receive the output voltage and a reference voltage of the operational amplifier, and output a feedback signal based on the output voltage and the reference voltage. The feedback signal is used to adjust the common-mode voltage of the output voltage. In the implementations of this application, the common-mode voltage is a signal relative to a common ground, and a differential-mode voltage is a difference between two signals. In this application, the common-mode voltage of the input voltage may also be referred to as an input common-mode voltage. The common-mode voltage of the output voltage may also be referred to as an output common-mode voltage. In a conventional design, an input common-mode voltage and an output common-mode voltage of an operational amplifier are usually constant, and do not vary with a process, an operating voltage, and a temperature ("PVT" for short). The process refers to a difference that is between performance parameters of devices in different production batches, different wafers, or different positions in a same wafer and that is caused in a process of manufacturing a circuit due to an error in a manufacturing process, for example, an error of doping density. For example, a difference between threshold voltages of transistors is caused by a process error.

[0015] The implementations of this application provide an operational amplifier. A common-mode voltage of an output voltage of the operational amplifier may vary in real time with a process, an operating voltage, and / or a temperature, so that a voltage margin of a transistor in a circuit can be flexibly adjusted and allocated in real time. Therefore, a problem of circuit performance deterioration caused by an insufficient voltage margin of the transistor in extreme conditions is resolved. The voltage margin may refer to a voltage constraint condition in which the transistor operates in a saturation region.

[0016] It should be noted that the operational amplifier in the implementations of this application may be implemented by a metal-oxide-semiconductor field-effect transistor (MOSFET). In this application, the MOSFET may also be referred to as a MOS transistor or a transistor. The MOS transistor includes two types, namely, an N-type MOS transistor and a P-type MOS transistor. The N-type MOS transistor and the P-type MOS transistor may be referred to as an NMOS transistor and a PMOS transistor, or an NMOS and a PMOS, respectively.

[0017] FIG. 1 is a schematic structural diagram of an operational amplifier 100. As shown in FIG. 1, the operational amplifier 100 includes a differential amplification circuit 110, a reference voltage generation circuit 120, and a common-mode feedback circuit 130. A structure of each circuit in the operational amplifier 100 is described in detail below.

[0018] The differential amplification circuit 110 is configured to receive and amplify an input voltage VIN to generate an output voltage VOUT. The differential amplification circuit is further configured to receive a feedback signal V FB , and the feedback signal V FB is used to adjust a common-mode voltage V CM of the output voltage.

[0019] The differential amplification circuit 110 may be of a fully differential structure. In other words, both the input voltage VIN and the output voltage VOUT may be differential signals. The differential amplification circuit 110 includes multiple stages of amplification circuits and an output voltage of a previous stage of amplification circuit is configured as an input voltage of a current stage of amplification circuit.

[0020] In an example, FIG. 2 is a schematic circuit diagram of a differential amplification circuit 110 according to an implementation of this application. The differential amplification circuit 110 includes three stages of amplification circuits, namely, a first-stage amplification circuit 1101, a second-stage amplification circuit 1102, and a third-stage amplification circuit 1103. V in and V ip represent input voltages of the first-stage amplification circuit 1101. V on1 and V op1 represent output voltages of the first-stage amplification circuit 1101, and V on1 and V op1 are also input voltages of the second-stage amplification circuit 1102. V on2 and V op2 represent output voltages of the second-stage amplification circuit 1102, and V on2 and V op2 are also input voltages of the third-level amplification circuit 1103. V on and V op represent output voltages of the third-stage amplification circuit 1103. The input voltages V in and V ip of the first-stage amplification circuit 1101 are the input voltage VIN of the operational amplifier, and the output voltages V on and V op of the third-stage amplification circuit 1103 are the output voltage VOUT of the operational amplifier. V B1 and V B2 represent bias voltages of a bias circuit, and the bias circuit is configured to provide a bias current for input pair transistors. Generally, each stage of amplification circuit includes input pair transistors and a bias circuit. For example, input pair transistors of the first-stage amplification circuit 1101 are a transistor M 1 and a transistor M 2 , and a bias circuit includes a transistor M 20 . Input pair transistors of the second-stage amplification circuit 1102 are a transistor M 7 and a transistor M 8 , and a bias circuit includes a transistor M 24 and a transistor M 25 . Input pair transistors of the third-stage amplification circuit 1103 are a transistor M 11 and a transistor M 12 , and a bias circuit includes a transistor M 26 and a transistor M 27 .

[0021] In another example, FIG. 3 is a schematic circuit diagram of a differential amplification circuit 110 according to another implementation of this application. The differential amplification circuit 110 in FIG. 3 is a three-stage feedforward amplification circuit. "Feedforward" means that each stage of amplification circuit directly receives the input voltage of the operational amplifier and receives an output voltage of a previous-stage amplification circuit. By adding the feedforward circuit, there are three paths from the input voltage to the output voltage. A first path is a three-stage amplification path, and an input signal sequentially passes through three amplification circuits to form a three-stage amplification effect. A feature of the three-stage amplification effect is that a low-frequency gain is high, and gain attenuation is relatively fast at a high frequency because there are three poles. A second path is a two-stage amplification path. The input voltage is directly coupled to a second-stage amplifier through a first feedforward and output, and then forms a two-stage amplification effect together with a third-stage amplifier. A feature of the two-stage amplification effect is that a gain is relatively high at a medium frequency, and attenuation is relatively fast at a high frequency because there are two poles. A third path is a one-stage amplification path. The input voltage is directly coupled to the output voltage through a second feedforward amplification circuit to form a one-stage amplification effect. Gain attenuation is relatively slow at a high frequency because there is only one pole. Through the feedforward amplification circuit, a new zero can be generated to offset the poles inside the three-stage amplification circuit, thereby improving a phase margin of the differential amplification circuit. As shown in FIG. 3, the differential amplification circuit 110 includes a first-stage amplification circuit 1111, a second-stage amplification circuit 1112, and a third-stage amplification circuit 1113. A circuit structure of the first-stage amplification circuit 1111 is the same as or similar to the circuit structure of the first-stage amplification circuit 1101 in FIG. 2. The second-stage amplification circuit 1112 may include two pairs of input pair transistors and a bias circuit. A first pair of input pair transistors are a transistor M 7 and a transistor M 8 , and are configured to receive output voltages V on1 and V op1 of the first-stage amplification circuit 1111. A second pair of input pair transistors are a transistor M 5 and a transistor M 6 , and are configured to receive input voltages V in and V ip of the operational amplifier. The bias circuit includes a transistor M 21 . The third-stage amplification circuit may also include two pairs of input pair transistors. A first pair of input pair transistors are a transistor M 11 and a transistor M 12 , and are configured to receive output voltages V on2 and V op2 of the second-stage amplification circuit 1112. A second pair of input pair transistors are a transistor M 9 and a transistor M 10 , and are configured to receive input voltages V in and V ip of the operational amplifier. The bias circuit includes a transistor M 22 . The differential amplification circuit 110 in each of FIG. 2 and FIG. 3 is merely an example. The differential amplification circuit may further include other types of variations, optimizations, or configurations, which are not listed one by one in this application.

[0022] The reference voltage generation circuit 120 is configured to: detect status information of the operational amplifier 100, and generate a reference voltage V Ref based on the status information, and the status information includes a temperature and / or an operating voltage V DD of the operational amplifier 100.

[0023] The foregoing reference voltage V Ref is generated based on status information. In other words, the reference voltage V Ref may vary in real time depending on the temperature and / or the operating voltage V DD of the operational amplifier. The operating voltage V DD is also a source voltage.

[0024] The foregoing reference voltage generation circuit 120 has a plurality of implementations. In an example, FIG. 4 is a schematic circuit diagram of a reference voltage generation circuit 120 according to an implementation of this application. A reference voltage V Ref in FIG. 4 may reflect a temperature variation. As shown in FIG. 4, the reference voltage generation circuit 120 includes a first bias circuit 1201 and a first MOS transistor M 23 . The first bias circuit 1201 is configured to provide a drain current to the first MOS transistor M 23 , a gate of the first MOS transistor M 23 is short-circuited to a drain, and the reference voltage V Ref is a drain voltage V PT of the first MOS transistor M 23 . The foregoing first bias circuit 1201 may be, for example, a current source. The current source is configured to provide a constant current I 1 . The foregoing first MOS transistor M 23 may be configured to detect a temperature of the circuit, and the temperature variation can be reflected in the drain voltage V PT of M 23 . In addition, it should be noted that, because the first MOS transistor M 23 and other MOS transistors in an operational amplifier are usually located in a same chip, a process of the first MOS transistor M 23 and a process of the other MOS transistors in the operational amplifier may be considered to be the same. Therefore, a process variation can also be reflected in the drain voltage V PT of the first MOS transistor M 23 . In other words, V PT in FIG. 4 can reflect both the temperature variation and the process variation.

[0025] Specifically, the drain voltage V PT of the first MOS transistor M 23 may be expressed by using the following formula: V PT = 2 I 1 μC ox W L 23 + V th

[0026] Parameters in formula (1) are shown as follows. It can be learned from the following descriptions of the parameters that V PT can reflect the temperature variation and the process variation.

[0027] µ represents electron mobility or hole mobility of the transistor, and is in 1 / T 2< relationship with the temperature. That is, the higher the temperature, the lower µ , and the higher V PT ; or the lower the temperature, the higher µ , and the lower V PT .

[0028] C ox represents a unit gate oxide parasitic capacitance of a transistor, and is equal to a dielectric constant of an oxidized layer divided by a thickness of the oxidized layer. Both the dielectric constant of the oxidized layer and the thickness of the oxidized layer are affected by the process. For example, generally, the faster the process (FF), the larger C ox , and the lower V PT ; or the slower the process (FF), the smaller C ox , and the higher V PT . Fast (fast) or slow (slow) process means that a conduction speed of the MOS transistor increases or decreases due to a difference in the process. For example, FF represents that conduction speeds of an NMOS and a PMOS are both high; SS represents that the conduction speeds of the NMOS and the PMOS are both low; FS represents that the conduction speed of the NMOS is high and the conduction speed of the PMOS is low; and SF represents that the conduction speed of the NMOS is low and the conduction speed of the PMOS is high. W L 23 represents a width-to-length ratio of the transistor M 23 .

[0029] I 1 represents the drain current of the transistor M 23 .

[0030] V th represents a threshold voltage of the transistor M 23 , and is affected by both the temperature and the process. Generally, the higher the temperature, the lower V th ; or the lower the temperature, the higher V th . The faster the process, the lower V th ; or the slower the process, the higher V th .

[0031] In another example, FIG. 5 is a schematic circuit diagram of a reference voltage generation circuit 120 according to another implementation of this application. A reference voltage V Ref in FIG. 5 may reflect a variation in an operating voltage V DD . As shown in FIG. 5, the reference voltage generation circuit 120 may include a voltage divider circuit 1211. The voltage divider circuit 1211 is located between the operating voltage V DD and a ground, and the reference voltage V Ref is a voltage V v of a voltage divider node of the voltage divider circuit. The voltage divider circuit 1211 may be a series circuit including a resistor R 1 and a resistor R 2 .

[0032] In still another example, FIG. 6 is a schematic circuit diagram of a reference voltage generation circuit 120 according to still another implementation of this application. A reference voltage V Ref in FIG. 6 may reflect a temperature variation and an operating voltage variation. Further, the reference voltage V Ref may also reflect a process variation. As shown in FIG. 6, the reference voltage generating circuit 120 includes: a first bias circuit 1221 and a first MOS transistor M 28 , where the first bias circuit is configured to provide a drain current to the first MOS transistor M 28 , and a gate of the first MOS transistor M 28 is short-circuited to a drain; and a first summation circuit 1222, where an input terminal of the first summation circuit 1222 is configured to receive a drain voltage V PT and the operating voltage V DD of the first MOS transistor M 28 , and the reference voltage V Ref is a voltage V PVT of an output terminal of the first summation circuit 1222. The first summation circuit 1222 may be a proportional summation circuit. To be specific, the reference voltage V Ref may be expressed as V Ref = a × V PT + b × V DD , where a and b represent constants. V PT represents the drain voltage of the first MOS transistor M 28 . For a calculation manner of V PT , refer to formula (1). V DD represents the operating voltage. In an example, the first summation circuit 1222 in FIG. 6 may include a resistor R 1 , a resistor R 2 , and a resistor R 3 . One terminal of each of R 1 , R 2 , and R 3 is connected to an output terminal of the first summation circuit 1222, and the other terminal of R 1 , the other terminal of R 2 , and the other terminal of R 3 are configured to connect to the operating voltage V DD , the drain voltage V PT of the first MOS transistor M 28 , and the ground, respectively. It can be deduced that the output voltage V PVT of the first summation circuit 1222 may be expressed as:

[0033] To prevent the resistor R 3 from shunting the drain current provided by the first bias circuit to the first MOS transistor M 28 , a resistance value of R 3 may be set to be far greater than an equivalent resistance 1 / g m28 of the first MOS transistor M 28 , and g m28 represents a transconductance of the first MOS transistor M 28 . Alternatively, a buffer may be disposed between the drain of the first MOS transistor M 28 and the resistor R 3 , to avoid shunting of R 3 . The buffer may include an amplifier.

[0034] Optionally, to enhance a driving capability of the reference voltage V Ref , a buffer may be added to the output terminal of the circuit in each of FIG. 4 to FIG. 6. The buffer may include an amplifier. For example, FIG. 7 is a schematic circuit diagram of a buffer according to an implementation of this application. The buffer includes an amplifier A 1 .

[0035] Optionally, a first summation circuit 1222 may be implemented in another manner, provided that a function of the first summation circuit 1222 is to implement proportional summation of V PT and V DD . Details are not described herein one by one.

[0036] The common-mode feedback circuit 130 is configured to: receive the output voltage VOUT and the reference voltage V Ref , and provide the feedback signal V FB to the differential amplification circuit 110 based on the output voltage VOUT and the reference voltage V Ref .

[0037] FIG. 8 is a schematic circuit diagram of an operational amplifier 100 according to another implementation of this application. As shown in FIG. 8, the foregoing common-mode feedback circuit 130 includes a second summation circuit 131, a first level switching circuit 132, a second level switching circuit 133, and an amplification circuit 134.

[0038] The second summation circuit 131 is configured to: receive the output voltage VOUT, and generate the common-mode voltage V CM based on the output voltage VOUT. The input voltage VIN may include differential input voltages V in and V ip , the output voltage VOUT may include differential output voltages V on and V op , and the second summation circuit 131 may also be a proportional summation circuit. The second summation circuit 131 may be configured to generate a common-mode voltage V CM of the output voltages V on and V op . V CM meets the following condition: V CM = (V on + V op ) / 2.

[0039] The first level switching circuit 132 is configured to receive the common-mode voltage V CM , and convert the common-mode voltage V CM to obtain a first voltage V 1 . The second level switching circuit 133 is configured to receive the reference voltage V Ref , and convert the reference voltage V Ref to obtain a second voltage V 2 . The first level switching circuit 132 and the second level switching circuit 133 may be composed by passive resistors. A passive device can reduce power consumption of the level switching circuit, improve linearity, and speed up an operation.

[0040] In extreme conditions, for example, when a temperature is extremely high or extremely low, or a process deviates greatly from normal, performance of a MOS transistor is affected, and the MOS transistor may not operate in a saturation region. Therefore, performance deterioration of the circuit is caused. That the MOS transistor operates in the saturation region means that when the MOS transistor is operating, a gate-source voltage and a drain-source voltage of the MOS transistor meet the following condition: V DS ≥ V GS − V th

[0041] V DS represents a voltage between a drain and a source of the MOS transistor, V GS represents a voltage between a gate and the drain of the MOS transistor, and V th represents a threshold voltage of the MOS transistor. Functions of the foregoing first level switching circuit 132 and the foregoing second level switching circuit 133 are to perform level switching on an input voltage of the amplification circuit 134, that is, adjust gate-source voltages V GS of input pair transistors to ensure that the input pair transistors of the amplification circuit 134 operate in the saturation region. Therefore, the operational amplifier can operate properly in extreme conditions.

[0042] The amplification circuit 134 includes input pair transistors and an output terminal, where a gate of a second MOS transistor in the input pair transistors is configured to receive the first voltage V 1 , a gate of a third MOS transistor in the input pair transistors is configured to receive the second voltage V 2 , and the output terminal of the amplification circuit is configured to generate the feedback signal V FB . The first voltage V 1 output by the first level switching circuit 132 enables the second MOS transistor to operate in the saturation region, and the second voltage V 2 output by the second level switching circuit 133 enables the third MOS transistor to operate in the saturation region.

[0043] In some examples, alternatively, the common-mode feedback circuit 130 may not include the first level switching circuit 132 and the second level switching circuit 133. In this case, an input terminal of the amplification circuit 134 may be configured to receive the common-mode voltage V CM and the reference voltage V Ref .

[0044] FIG. 9 is a schematic circuit diagram of a common-mode feedback circuit 130 according to another implementation of this application. As shown in FIG. 9, the common-mode feedback circuit 130 includes a second summation circuit 131, a first level switching circuit 132, a second level switching circuit 133, and an amplification circuit 134. The second summation circuit 131 includes resistors R 5 and R 7 . The first level switching circuit 132 includes a pull-down resistor R 6 . The second level switching circuit 133 includes a pull-down resistor R 10 . During level switching, if V CM or V REF needs to be decreased, a pull-down resistor may be used in the level switching circuit, that is, one terminal of the resistor is grounded. If V CM or V REF needs to be increased, a pull-up resistor may be used in the level switching circuit, that is, one terminal of the resistor is connected to the operating voltage. The amplification circuit 134 may be a single-stage or multi-stage amplification circuit. An input terminal of the amplification circuit 134 is configured to receive V 1 and V 2 , and an output terminal of the amplification circuit 134 is configured to output a feedback signal V FB . A second MOS transistor in input pair transistors in the foregoing amplification circuit 134 is equivalent to a transistor M 13 in the amplification circuit 134, and a third MOS transistor in the input pair transistors in the foregoing amplification circuit 134 is equivalent to a transistor M 14 in the amplification circuit 134. V B3 is a bias voltage.

[0045] Still referring to FIG. 8, the feedback signal V FB generated by the common-mode feedback circuit 130 is fed back to the differential amplification circuit 110, to adjust the common-mode voltage V CM of an output voltage of the differential amplification circuit 110. For example, the feedback signal V FB may be sent to a gate of a transistor of a bias circuit of a stage of amplification circuit in the differential amplification circuit 110. In some examples, design factors such as a unit gain bandwidth and a phase margin of an operational amplifier are comprehensively considered. It is assumed that the differential amplification circuit includes K stages of amplification circuits. A (K-1) th< stage of amplification circuit includes a second bias circuit, and a gate of a fourth MOS transistor in the second bias circuit is configured to receive the feedback signal V FB , where K ≥ 2. For example, referring to FIG. 2, for the three stages of amplification circuits, the feedback signal V FB is sent to gates of the transistors M 24 and M 25 in the bias circuit of the second-stage amplification circuit 1102. In other words, the foregoing fourth MOS transistor is equivalent to the transistors M 24 and M 25 . Alternatively, referring to FIG. 3, the feedback signal V FB is sent to a gate of the transistor M 21 in the bias circuit of the second-stage amplification circuit 1112. In other words, the foregoing fourth MOS transistor in the second bias circuit is equivalent to the transistor M 21 .

[0046] The common-mode feedback circuit 130 includes a filter circuit 135. The filter circuit 135 is configured to: receive the common-mode voltage V CM , and filter out a direct current component of the common-mode voltage V CM , to obtain a fast path feedback signal V FBF . The fast path feedback signal V FBF is an alternating current component of the common-mode voltage. It is assumed that the differential amplification circuit 110 includes the K stages of amplification circuits, where K ≥ 2, and a K th< stage of amplification circuit includes a third bias circuit. A gate of a fifth MOS transistor in the third bias circuit is configured to receive the fast path feedback signal V FBF , where K ≥ 2. For example, referring to FIG. 2, for the three stages of amplification circuits, the fast path feedback signal V FBF is sent to gates of the transistors M 26 and M 27 in the bias circuit of the third-stage amplification circuit 1103. In other words, the foregoing fifth MOS transistor is equivalent to the transistors M 26 and M 27 . Alternatively, referring to FIG. 3, the fast path feedback signal V FBF is sent to a gate of the transistor M 22 in the bias circuit of the third-stage amplification circuit 1113. In other words, the foregoing fifth MOS transistor in the third bias circuit is equivalent to the transistor M 23 .

[0047] The filter circuit 135 may include any circuit module that can implement the foregoing functions. For example, FIG. 9 further shows the filter circuit 135. The filter circuit 135 may include a capacitor C 6 . One terminal of C 6 is configured to receive the common-mode voltage V CM , and the other terminal of C 6 is configured to output the fast path feedback signal V FBF .

[0048] Similar to the principle of the three-stage feedforward circuit described above, the filter circuit 135 herein also introduces a feedforward circuit, to compensate for the phase margin of the common-mode feedback circuit. The operating principle is as follows: The common-mode voltage is directly coupled to the last stage of amplification circuit through the feedforward circuit, to form a one-stage amplification effect on the common-mode voltage. Because there is only one pole, the common-mode voltage attenuates slowly at a high frequency, thereby forming a phase margin compensation effect. Optionally, still referring to FIG. 2 and FIG. 3, a resistor R 11 may be disposed in the third bias circuit. One terminal of the resistor R 11 is configured to connect to the bias voltage V B2 , and the other terminal is configured to connect to the gate of the fifth MOS transistor. In a case of a low frequency, because the capacitor has a characteristic of blocking a direct current and allowing an alternating current to pass, the filter circuit 135 does not operate, and the bias voltage V B2 is transmitted to the gate of the fifth MOS transistor via the resistor R 11 . As the frequency increases, the filter circuit 135 starts to operate, and impedance of R 11 increases relative to the filter circuit 135, so that the gate of the fifth MOS transistor starts to be affected by both V B2 and the filter circuit 135. When the frequency is sufficiently high, the impedance of R 11 is far less than that of the filter circuit 135. In this case, the gate voltage of the fifth MOS transistor is mainly affected by the filter circuit 135. In other words, the gate voltage of the fifth MOS transistor is mainly affected by the fast path feedback signal V FBF .

[0049] Optionally, the common-mode feedback circuit 130 described above is merely an example. Various variations or optimizations may be further performed based on the foregoing circuit. For example, as shown in FIG. 9, after the second summation circuit 131 is configured, because the gate of the input transistor M 13 has a parasitic capacitor, there is a pole at the gate of the M 13 when the input transistor M13 operates at a high frequency. Capacitors C 5 and C 6 may be disposed between the gate of the input transistor M 13 and the output voltages V op and V on in the amplification circuit 134 to offset the pole, thereby optimizing the performance of the circuit.

[0050] Optionally, to achieve circuit matching, the circuit of the input terminal of the amplification circuit 134 can be symmetrically distributed. For example, to ensure symmetry, in the common-mode feedback amplification circuit in FIG. 9, the input pair transistors M 13 and M 14 use a symmetric structure design, and the resistors and capacitors may use the following configuration: R 5 = R 7 = Rs= R 9 , C 5 = C 7 = C 8 = C 9 , R 6 = R 10 , and C 6 = C 10 .

[0051] In this implementation of this application, the reference voltage that varies with the temperature and / or the operating voltage is provided to the common-mode feedback circuit, so that the common-mode voltage of the output voltage can be adjusted based on the temperature and / or the operating voltage. Therefore, a voltage margin of a transistor in the operational amplifier can be flexibly adjusted in real time based on the temperature and / or the operating voltage, and operating performance of the operational amplifier is improved.

[0052] Further, in this implementation of this application, because the process of the first MOS transistor is the same as that of the other MOS transistors in the operational amplifier, a process variation may also be reflected in the reference voltage. Therefore, the operational amplifier can also adjust the voltage margin of the transistor in the operational amplifier based on the process, to improve operating performance of the operational amplifier.

[0053] It should be noted that the operational amplifier is usually applied to a scenario in which a plurality of operational amplifiers are connected in series, to implement a multi-stage filtering effect. An output of a previous operational amplifier is usually used as an input of a current operational amplifier. Therefore, an output common-mode voltage of the previous operational amplifier is usually an input common-mode voltage of the current operational amplifier. This scenario is common in a filter or Delta-Sigma analog-to-digital converter (ADC) design.

[0054] It can be learned from the foregoing descriptions of formula (1) that the slower the process, the lower the temperature, and the higher the threshold voltage. For example, Table 1 shows an example of a correspondence between an operating state of the operational amplifier and the threshold voltage of the transistor. With reference to FIG. 3 and Table 1, the following describes a principle of adjusting the output common-mode voltage V CM based on the status information. Table 1 Operating statusThreshold voltage V th TT (normal process) 25°C0.38 VSS (slow process) -40°C0.45 V

[0055] Referring to FIG. 3, it is assumed that two operational amplifiers in FIG. 3 are connected in series. In this case, a common-mode voltage V CM of output voltages V op and V on of a previous operational amplifier is a common-mode voltage of input voltages V in and V ip of a current operational amplifier. For example, assuming that V Ref is set to 0.55 V, due to a common-mode feedback effect, the output common-mode voltage of the previous operational amplifier is also 0.55 V, and the input common-mode voltage of the current operational amplifier is also 0.55 V Herein, it is assumed that overdrive voltages of transistors M 1 and M 2 , M 5 and M 6 , and M 9 and M 10 in the operational amplifier are equal to 70 mV. The overdrive voltage is a residual voltage by which a gate-source voltage exceeds a threshold voltage of the transistor, that is, V GS - V th .

[0056] When an operating process of the operational amplifier is the normal process (TT) and the operational amplifier operates at 25°C, the threshold voltages V th of the input pair transistors M 1 and M 2 , M 5 and M 6 , and M 9 and M 10 are equal to 0.38 V according to Table 1. The input common-mode voltage of the current operational amplifier is 0.55 V After the threshold voltages V th and the overdrive voltage are subtracted (that is, V GS - V th ), drain-source voltages V DS reserved for M 20 , M 21 , and M 22 are 100 mV. M 20 , M 21 , and M 22 can operate in a saturation region, and in this case, the current operational amplifier can operate properly.

[0057] When the operational amplifier operates in the slow process (SS) and the operating temperature is -40°C, the threshold voltages V th of the input pair transistors M 1 and M 2 , M 5 and M 6 , and M 9 and M 10 are up to 0.45 V according to Table 1. If the reference voltage V Ref remains 0.55 V, the input common-mode voltage of the current operational amplifier also remains 0.55 V. After the threshold voltages V th 0.45 V and the overdrive voltages 70 mV of M 1 and M 2 , M 5 and M 6 , and M 9 and M 10 are subtracted from the input common-mode voltage, the overdrive voltages reserved for M 20 , M 21 , and M 22 are only 30 mV. M 20 , M 21 , and M 22 enter a linear region, and the current operational amplifier cannot operate properly. If the reference voltage generation circuit in FIG. 4 is used, the reference voltage V Ref varies with a temperature and a process. According to formula (1), when the operational amplifier is in the slow process (SS) and operates at -40°C, V Ref also increases by 70 mV. In this way, the output common-mode voltage of the previous operational amplifier increases from 0.55 V to 0.62 V, the input common-mode voltage of the current operational amplifier also increases to 0.62 V, and after the threshold voltages V th and the overdrive voltages of M 1 and M 2 , M 5 and M 6 , and M 9 and M 10 are subtracted from the input common-mode voltage, the overdrive voltages reserved for M 20 , M 21 , M 22 are still 100 mV. M 20 , M 21 , and M 22 operate in the saturation region, and the operational amplifier can still operate properly.

[0058] Similarly, if the operational amplifier operates in extreme conditions in which a process is fast, a temperature is high, or an operating voltage fluctuates, the operational amplifier may also perform corresponding adjustment based on the temperature, the process, or the operating voltage, so that the transistor can maintain operating in the saturation region, thereby improving operating performance of the operational amplifier and the circuit in the extreme conditions.

[0059] The operational amplifier 100 provided in this implementation of this application may be applied to various operating environments. For example, the operational amplifier 100 may be applied to a low-voltage operating scenario. With process evolution and a requirement for low power consumption, an operating voltage provided for a circuit is increasingly low. However, for an analog circuit, if the operating voltage is decreased, the voltage margin for maintaining the transistor to operate in the saturation region is increasingly small. The output common-mode voltage of the operational amplifier in this application may be adjusted based on the temperature and / or the operating voltage. Therefore, the voltage margin of the transistor in the operational amplifier may be flexibly adjusted in real time based on the temperature and / or the operating voltage, and operating performance of the operational amplifier is improved when the operational amplifier operates at a low voltage.

[0060] The operational amplifier provided in this implementation of this application may be applied to a plurality of types of circuits. For example, in a Delta-Sigma ADC, or in a circuit such as an integrator or a filter.

[0061] In addition, an implementation of this application further provides a chip 1000. FIG. 10 is a schematic diagram of the chip 1000 according to an implementation of this application. As shown in FIG. 10, the foregoing operational amplifier 100 is disposed on the chip.

[0062] The foregoing descriptions are merely specific implementations of this application, but are not intended to limit the protection scope of this application. Variations or replacements readily figured out by a person skilled in the art within the technical scope disclosed in this application shall fall within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

[0063] In the several implementations provided in this application, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the described apparatus implementations are merely examples. For example, the unit division is merely logical function division and may be other division in actual implementation. For example, a plurality of units or components may be combined or integrated into another system, or some features may be ignored or not performed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections may be implemented through some interfaces, indirect couplings or communication connections between the apparatuses or units, or electrical connections, mechanical connections, or connections in other forms.

[0064] The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual requirements to achieve the objectives of the solutions of the implementations in this application.

[0065] In addition, functional units in the implementations of this application may be integrated into one processing unit, or each of the units may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in a form of hardware, or may be implemented in a form of a software functional unit.

[0066] The scope of protection shall be defined by the appended claims.

Claims

1. An operational amplifier (100), comprising: a differential amplification circuit (110), configured to receive and amplify an input voltage to generate an output voltage, wherein the differential amplification circuit is further configured to receive a feedback signal, and adjust a common-mode voltage of the output voltage based on the feedback signal; a reference voltage generation circuit (120), configured to: detect status information of the operational amplifier, and generate a reference voltage based on the status information, wherein the status information comprises a temperature and / or an operating voltage of the operational amplifier; and a common-mode feedback circuit (130), configured to: receive the output voltage and the reference voltage, and provide the feedback signal to the differential amplification circuit based on the output voltage and the reference voltage; wherein the reference voltage generation circuit either comprises: a first bias circuit (1201) and a first metal-oxide-semiconductor, MOS, transistor (M23), the first bias circuit is configured to provide a drain current to the first MOS transistor, and a gate of the first MOS transistor is short-circuited to a drain, and the reference voltage is a drain voltage of the first MOS transistor; or the reference voltage generation circuit comprises: a voltage divider circuit (1211), the voltage divider circuit is located between the operating voltage and a ground, and the reference voltage is a voltage of a voltage divider node of the voltage divider circuit; or the reference voltage generation circuit comprises: a first bias circuit (1221) and a first MOS transistor (M28), wherein the first bias circuit is configured to provide a drain current to the first MOS transistor, and a gate of the first MOS transistor is short-circuited to a drain; and a first summation circuit (1222), wherein an input terminal of the first summation circuit is configured to receive a drain voltage of the first MOS transistor and the operating voltage, and the reference voltage is a voltage at an output terminal of the first summation circuit; wherein a process of the first MOS transistor is the same as that of other MOS transistors in the operational amplifier; wherein the common-mode feedback circuit comprises: an amplification circuit (134), comprising input pair transistors (M13, M14) and an output terminal, wherein a gate of a second MOS transistor (M13) in the input pair transistors is configured to receive a first voltage based on the output voltage, a gate of a third MOS transistor (M14) in the input pair transistors is configured to receive a second voltage based on the reference voltage, and the output terminal of the amplification circuit is configured to generate the feedback signal; and a filter circuit (135), the filter circuit is configured to receive the common-mode voltage and filter out a direct current component of the common-mode voltage, to obtain a fast path feedback signal, and the fast path feedback signal is an alternating current component of the common-mode voltage; and wherein the differential amplification circuit comprises K stages of amplification circuits, wherein an output voltage of a (K-1)th stage of the K stages of amplification circuits is configured as an input voltage of a Kth stage of the K stages of amplification circuits, the (K-1)th stage comprises a second bias circuit, and a gate of a fourth MOS transistor in the second bias circuit is configured to receive the feedback signal, and the Kth stage comprises a third bias circuit, and a gate of a fifth MOS transistor in the third bias circuit is configured to receive the fast path feedback signal wherein K ≥ 2.

2. The operational amplifier according to claim 1, wherein the common-mode feedback circuit comprises: a second summation circuit, configured to: receive the output voltage, and generate the common-mode voltage based on the output voltage; a first level switching circuit, configured to: receive the common-mode voltage, and convert the common-mode voltage to obtain the first voltage; a second level switching circuit, configured to: receive the reference voltage, and convert the reference voltage to obtain the second voltage; and wherein: the first voltage output by the first level switching circuit enables the second MOS transistor to operate in a saturation region, and the second voltage output by the second level switching circuit enables the third MOS transistor to operate in the saturation region; wherein the second summation circuit includes resistors R5 and R7, the first level switching circuit includes a pull-down resistor R6, the second level switching circuit includes a pull-down resistor R10, wherein during level switching, if the common-mode voltage or the reference voltage is to be decreased, a pull-down resistor is used in the level switching circuit, and if the common-mode voltage or the reference voltage is to be increased, a pull-up resistor is used in the level switching circuit.

3. A chip, wherein the operational amplifier according to claim 1 or 2 is disposed on the chip.