MANUFACTURING METHOD OF A FUSE FOR AN INTEGRATED CIRCUIT DURING ITS MANUFACTURING

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of securing integrated circuits, in particular by non-clonable physical functions. PREVIOUS STATE OF THE ART

[0002] Currently, the counterfeiting of integrated circuits poses a major problem for manufacturers and users. To combat this counterfeiting, efforts are underway to find ways to distinguish between a legitimate circuit and a counterfeit one.

[0003] One initial solution would be to assign a unique identifier to each integrated circuit and build a database of legitimate identifiers. This solution is not very viable because it is quite easy to emulate (or replay) a valid identifier using a hardware or software exploit.

[0004] A more effective solution is to use a challenge-response mechanism that enables authentication while protecting against replay attacks. This technique relies on using a function to calculate the response to the challenge. The function must be unique for each integrated circuit and unclonable. In fact, an attacker must not be able to physically recreate or clone such a function. This type of function is called a "physical unclonable function" (PUF).

[0005] Prior art has shown integrated circuits comprising different kinds of PUFs exploiting the functional dispersions inherent in the circuits.

[0006] One technique for PUFs (Personal Uncertainty Loops) exploits the variability induced in signal propagation times at the limits of the circuit's electronic constraints. A prime example is an integrated circuit incorporating an arbiter-based PUF. This involves inserting electrical signals into the input of a long path of combinational circuits and detecting the fastest signal. A race is established within the circuit between the different signals propagating along various combinational paths, and the signal that arrives first is detected by the arbiter. The input electrical signals define the challenge, and the first detected signal defines the response.

[0007] Another example is the ring-oscillator PUF described in the paper by Gassend et al. entitled "Silicon Random Functions"; proceedings of the Computer and Communications Security Conference, Nov. 2002 .This PUF (Programmable Function) consists of several delay loops oscillating at specific frequencies that control counters. The loops are arranged identically, but inherent technological variations result in loops with slightly different frequencies. The counters controlled by the loops are then used to generate the response bits to a challenge.

[0008] A second PUF technique exploits instabilities at startup. For example, SRAM memories, already present in a large majority of circuits, can be used as PUFs. The basic principle is to recover the memory state at startup, which is normally unique. Based on the same principle, PUFs can be implemented using butterfly circuits made from matrices of two cross-locks where the state of the memory point at startup is undetermined. This technique is described in the paper by Kumar et al. entitled "The Butterfly PUF: Protecting IP on every FPGA"; Workshop on Cryptographic Hardware and Embedded Systems (CHES), Sep 2007, Vienna . In the same vein, we also find bistable ring circuits composed of an odd number of inverters and also having an indeterminate state at startup.

[0009] A third PUF technique exploits technological variations in resistance within a circuit. Such a technique is described in the paper by R. Helinski et al. entitled "A Physical Unclonable Function Defined Using Power Distribution System Equivalent Resistance Variations"; DAC 2009 . More specifically, the authors propose measuring the voltage drop in an integrated circuit between power supply and ground planes due to technological variations in resistances defined by the circuit's conductive traces and interconnections. The voltage drop is proportional to the current measured in short-circuited inverters arranged across the entire circuit surface.

[0010] However, all the PUFs described above are based on operating at the limits of the electronic constraints of the circuits and are therefore highly sensitive to environmental variations. In particular, changes in temperature, supply voltage, or electromagnetic interference can affect their performance by decreasing their robustness and increasing their volatility (i.e., their intra-circuit variability). Thus, for a constant challenge, the PUF may return different results depending on environmental conditions, meaning that a legitimate circuit could potentially be declared counterfeit.

[0011] Another problem concerns the aging of the integrated circuit. Indeed, due to operation at the limits of electronic constraints, the slightest defect that can occur during the aging of the circuit causes the PUF to no longer respond in the same way, and consequently, the integrated circuit can no longer be identified.

[0012] To overcome these shortcomings, it is often necessary to add to the PUF a post-processing circuit for the received response, which is costly in terms of footprint and consumption.

[0013] Another technique, described in US2014 / 0042627, involves randomly blocking a portion of the interconnect holes during the etching process of an integrated circuit, thus creating a random set of interconnect holes. More specifically, the technique described in this document uses a two-phase copolymer that polymerizes directly on the integrated circuit to form particles that create electrical contacts with varying resistance values.

[0014] However, this type of polymerization depends on the geometry and nature of the layer on which the copolymer is deposited and does not ensure a very random distribution of resistive values.

[0015] Prior art also includes patent application US2014 / 203448.

[0016] The object of the present invention is to propose a method for personalizing or securing an integrated circuit that remedies the aforementioned drawbacks, in particular by creating a PUF with a highly random character that does not depend on the geometry and nature of the layers of the integrated circuit while being virtually insensitive to variations in environmental conditions without the addition of a costly post-processing circuit, and without the introduction of significant modifications in the manufacturing process of the circuit. DESCRIPTION OF THE INVENTION

[0017] This objective is achieved with a method for securing an integrated circuit during its fabrication. The scope of the invention is defined by the claims in the appendix. According to one embodiment, said method comprises the following steps: delimitation of said integrated circuit into a first zone called the standard zone and a second zone called the safety zone, said standard zone comprising at least two levels of conductive traces connected to each other and to electronic components via metallic interconnections, introduction of a layer of resin loaded with contaminating particles configured to randomly obstruct, during an etching step of the safety zone, a portion of the interconnection holes provided in said safety zone, thus forming a set of random interconnection holes, and metallization of said set of random interconnection holes of the safety zone to form a random interconnection structure suitable for its electrical continuity to be tested, thus defining a non-clonable physical function,said random interconnection structure being formed between at least two levels of conductive patterns at the same levels as the conductive tracks in the standard area.

[0018] This allows for the robust identification and securing of the integrated circuit, insensitive to variations in environmental conditions. Unlike prior art, this method does not exploit uncontrolled means in the electrical operation of the circuit, but rather in the physical implementation of the interconnect structure itself. It is independent of the geometry and nature of the integrated circuit layers and introduces only a minimal number of additional steps compared to a standard manufacturing process. Furthermore, because the implementation of the random interconnect structure is uncontrolled, the cost of cloning becomes prohibitively high, and reverse engineering, whether by imaging or machine learning, is extremely difficult.

[0019] Advantageously, the contaminating particles are nanoparticles made of a dielectric or metallic type material selected from the following materials: silicon, silicon dioxide SiO2, metal TiN.

[0020] This allows for particles that are compatible with the layer loaded with contaminating particles while also being suitable for use in a cleanroom.

[0021] Advantageously, the contaminating particles have a diameter that is substantially equal to or greater than that of the interconnecting holes.

[0022] This minimizes the number of partially blocked holes. It should be noted that the particle size can also be invariably larger or smaller than the interconnecting holes.

[0023] Advantageously, the contaminating particles have a concentration of between approximately 0.1% and 20% by selected mass depending on the particle size.

[0024] This allows for a concentration low enough not to clog all the interconnection holes while clogging an optimal number of these holes.

[0025] Advantageously, securing the integrated circuit is integrated at the stage of implementing the initial electrical interconnections and involves the following steps: creation of a first level of conductive patterns on the surface of said standard and safety zones, deposition on the surface of the first level of conductive patterns of a first multilayer comprising a barrier to a metallic diffusion as well as an etching mask, deposition on the surface of the first multilayer of a second multilayer of photosensitive resin comprising said resin layer loaded with contaminating particles, optical lithography in the safety zone to isolate the interconnection holes provided in this safety zone, the standard zone remaining protected by the second multilayer, transfer of the interconnection holes of the safety zone unobstructed or obstructed by contaminating particles into the etching mask, cleaning of the surface of the standard and safety zones to remove the second multilayer.

[0026] The various steps described above demonstrate that the element of randomness lies in the manufacturing process itself, and not in different masks or etchings. Furthermore, all successive steps are regulated and controlled to ensure extremely low variability in the key functional parameters of the integrated circuits.

[0027] Advantageously, the second multilayer comprises a first layer of etching mask of the type carbon organic layer "SOC", a second layer of etching mask of the type silicon-enriched organic layer "SiARC" and a third layer of photosensitive resin, the contaminating particles being included in said first layer of etching mask SOC.

[0028] This allows the number of steps to be reduced even further while ensuring a highly random nature.

[0029] The process also includes the following steps: deposition on the surface of the standard and safety zones of at least a third multilayer of photosensitive resin, optical lithography in the standard zone to isolate the interconnect holes provided in the standard zone, transfer of the interconnect holes from the standard zone into the etching mask, re-cleaning of the surface of the standard and safety zones to remove the third multilayer of photosensitive resin, transfer into the metallic diffusion barrier layer and filling with a metal of the interconnect holes in the standard and safety zones, and realization of a second level of conductive patterns on the surface of the standard and safety zones.

[0030] Advantageously, the process involves applying a voltage higher than a reading voltage to break fragile partial interconnections.

[0031] This eliminates fragile contacts and thus virtually eliminates any variation due to aging.

[0032] Advantageously, the random interconnection structure models a random electrical continuity queryable by a challenge-response authentication protocol, said random interconnection structure being formed between at least two corresponding levels of conductive patterns, a portion of the conductive patterns being configured to receive a challenge, while another portion of the conductive patterns is configured to provide the response to said challenge.

[0033] This allows for highly secure authentication that is protected against replay attacks.

[0034] Advantageously, the process involves the realization of a plurality of random interconnection structures between at least two levels of conductive patterns.

[0035] This allows for further securing of the integrated circuit through the challenge-response technique.

[0036] According to another embodiment of the present invention, the securing of the integrated circuit is carried out at the level of the manufacturing of logic circuits (front-end).

[0037] The invention also relates to a secure integrated circuit that can be obtained using a method according to the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present invention will be better understood upon reading the description of exemplary embodiments given by way of illustration only and in no way limiting, with reference to the accompanying drawings in which: THE Figs. 1A And 1B illustrate in a very schematic way a method for securing an integrated circuit, according to one embodiment of the invention; The Fig. 2illustrates in a very schematic way a cross-sectional view of a secure integrated circuit produced by the securing process according to an embodiment of the invention; and The Figs. 3A-3J illustrate in a very schematic way the steps of a process for securing an integrated circuit, according to a preferred embodiment of the invention. DETAILED DESCRIPTION OF SPECIFIC METHODS OF IMPLEMENTATION

[0039] The concept behind the invention is the random and deliberate obstruction of connection holes during the realization of a metallic interconnection level by the controlled introduction of a layer loaded with a particulate contaminant.

[0040] THE Figs. 1A And 1B illustrate in a very schematic way a method of securing an integrated circuit, according to an embodiment of the invention.

[0041] The securing method according to the invention is perfectly integrated into the manufacturing process itself of the integrated circuit 1 on a silicon wafer 3. In the manufacturing process, the patterns on the silicon wafer 3 are created using a photorepetition method, making each integrated circuit identical to the others. All successive steps are regulated and controlled to ensure extremely low variability in the functional parameters of the integrated circuits. However, the manufacturing method includes inherently random physical implementation steps that introduce discernible characteristics, ensuring the uniqueness or customization of each integrated circuit 1 without altering its initial functional parameters.

[0042] Indeed, during the standard fabrication of integrated circuit 1 (or electronic chip), the safety process involves delimiting integrated circuit 1 into a first surface area called the standard area 5a and a second surface area called the safety area 5b. The standard area 5a corresponds to the functional part of the basic integrated circuit 1. This area 5a is occupied by the basic electronic components coupled by metallic interconnects 7a adapted to perform the specific functions of the circuit. Conversely, the safety area 5b is occupied by a non-clonable physical function (PUF) designed to secure the basic circuit.

[0043] The fact that the standard surface area is separate from the safety surface area and that both areas are at the same level facilitates the execution of steps in both areas and reduces the number of process steps. The example of the Fig. 1AThe diagram shows the safety circuit next to the functional circuit, but of course, the two circuits can be arranged differently. For example, the safety circuit can be in a central area surrounded by the functional circuit. In yet another example, the safety circuit can be placed in a corner of the functional circuit, and so on.

[0044] There Fig. 1B shows that after the delimitation of zones 5a and 5b, a first level of conductive patterns 9a, 9b is made on the surface of the standard zone 5a and the safety zone 5b.

[0045] A first multilayer 13 is then deposited on the surface of the first level 8 of conductive patterns 9a, 9b. The first multilayer 13 includes a barrier to metallic diffusion as well as an etching mask. Next, a second multilayer 15 is deposited on the surface of the first multilayer 13. The second multilayer 15 includes a resin layer loaded with contaminating particles 19 configured to randomly obstruct, during an etching step of the safety zone 5b, a portion of the interconnection holes provided in said safety zone 5b, thus forming a set of random interconnection holes 17b.

[0046] The process further includes metallizing the set of random interconnect holes 17b of the safety zone 5b to form a random interconnect structure 7b defining a non-clonable physical function.

[0047] This random interconnection structure creates a non-clonable physical function modeled by random electrical continuity that can be queried by a challenge-response authentication protocol.

[0048] There Fig. 2 illustrates in a very schematic way a cross-sectional view of a secure integrated circuit produced by the securing process according to an embodiment of the invention.

[0049] The secure integrated circuit (or secure electronic chip) thus comprises a standard area 5a and a security area 5b. The standard area 5a typically comprises at least two levels of conductive traces 9a and 11a connected via metallic interconnects 7a to the various electronic components (not shown) of the integrated circuit 1.

[0050] The safety zone 5b includes a random interconnection structure 7b formed between at least two levels 8 and 10 of corresponding conductive patterns 9b and 11b suitable for testing the electrical continuity of this random interconnection structure 7b. It should be noted that the conductive patterns 9b and 11b can be of any shape or configuration depending on the desired complexity. For example, the conductive patterns 9b and 11b can be formed by an array (e.g., several dozen) of intersecting conductive grids or tracks, or of any other shape. Advantageously, the safety zone 5b can include a plurality of random interconnection structures 7b (only one is shown) and a plurality of corresponding levels of conductive patterns (only two levels are shown), thus increasing the complexity of the PUF.

[0051] The random interconnect structure(s) 7b model(s) electrical continuity between the different conductive patterns that can be used to implement a challenge-response authentication protocol. More specifically, part of the conductive patterns 9b and 11b is configured to receive a stimulus defining a challenge, while another part of the conductive patterns 9b and 11b is configured to provide an output signal corresponding to the response to the challenge. The response is thus dependent on the electrical continuity of the random interconnect structure specific to the electronic chip, as well as on the challenge used. The conductive patterns receiving the stimulus form an input to the integrated circuit, while those providing the response form the output of the integrated circuit. The conductive patterns selected to form the input or output are predetermined according to the specifications of the authentication protocol.

[0052] Each integrated circuit 1 resulting from the safety process thus has in its safety zone 5b a unique physical interconnection structure 7b whose manufacturing process is random and uncontrolled and therefore, extremely difficult to clone.

[0053] After the secure integrated circuits are manufactured, an "enrollment" phase is carried out. This phase consists of building a database containing legitimate "challenge-response" pairs for each integrated circuit 1. Specifically, for each integrated circuit 1, a tester randomly generates a number N of challenges C and sends them to the integrated circuit 1. Each challenge C consists of a stimulus applied to the input of the integrated circuit 1, and the response R to each challenge C is retrieved from the output of the integrated circuit 1. Indeed, the PUF, which defines a secret function F, calculates the response R to each challenge C (i.e., R = F(C)). The tester retrieves the N responses R associated with the N challenges C and stores the corresponding N challenge-response pairs (C, R) in a database (not shown).

[0054] Thus, the authentication of a secure integrated circuit 1 can be tested throughout its lifecycle. More specifically, a user of an integrated circuit 1 can request a challenge (or a challenge-response pair) from the manufacturer (or the entity that owns the database of challenge-response pairs). The challenge C is applied to the integrated circuit 1, and the latter calculates the response R to the challenge C. Then, the user (or the manufacturer) compares the response R generated by the integrated circuit 1 with the one stored in the database to verify the legitimacy of the integrated circuit 1. Note that, for added security, the challenge-response pair already used is then deleted from the database to prevent any replay.

[0055] THE Figs. 3A-3J illustrate in a very schematic way the steps of a process for securing an integrated circuit, according to a preferred embodiment of the invention.

[0056] As is known to those skilled in the art, the fabrication of the integrated circuit 1 on the standard area 5a is considered to have been carried out beforehand according to the usual steps of preparing an oxide layer on a substrate, transferring the design of the circuit to be reproduced using a mask, etching, doping, making subsequent layers, etc.

[0057] Thus, we start with a plate 3 delimited into a safety zone 5b and a standard zone 5a whose entire manufacturing process, known as "front-end", has been carried out, meaning that almost the entire circuit that we are trying to secure has been manufactured.

[0058] According to this embodiment, the securing of the integrated circuit 1 then begins at the end of the front-end and is integrated into the sequence of semiconductor compound manufacturing steps at the "back-end", that is to say, during the realization of the first electrical interconnections to properly interconnect the components with each other as well as with input-output electrodes.

[0059] There Fig. 3A illustrates in a very schematic way a first step in the securing process.

[0060] The first step E1 ( Fig. 3AThis step consists of creating a first level 8 of conductive patterns 9a and 9b on the surface of the standard 5a and safety 5b areas of the board 3. The conductive patterns 9a and 9b can be made of copper, aluminum, or another electrically conductive material. It should be noted that this step can be considered a final step already performed at the "front-end" of the integrated circuit manufacturing process.

[0061] The second stage E2 ( Fig. 3B The process involves depositing a first multilayer 13 onto the surface of the first level 8, comprising the conductive motifs 9a and 9b. The first multilayer 13 includes a metal diffusion barrier 13a and a hard etching mask 13b. This first multilayer 13 is, for example, a bilayer composed of a SiN layer acting as a barrier 13a and a SiO2 layer acting as an etching mask 13b.

[0062] The third stage E3 ( Fig. 3C) consists of depositing a second multilayer 15 of photosensitive resin comprising contaminating particles 19 on the standard 5a and safety 5b areas.

[0063] Advantageously, the second multilayer 15 consists of a stack of sublayers which may be composed, for example, of a first layer of etching mask of the type of SOC (Spin On Carbon) organic layer 151, a second layer of etching mask of the type of silicon-enriched organic layer SiARC (Silicon Anti Reflective Coating) 152 and a third layer of photosensitive resin 153. The thicknesses of these three layers may vary according to the nature of the products used as well as the dimensions of the interconnection holes called "vias" targeted. They are typically around 150nm for the first SOC layer 151, around 30nm for the second SiARC layer 152 and around 100nm for the third photosensitive resin layer 153. All these layers 151, 152, 153 can be deposited by the known spin coating method.

[0064] Advantageously, the contaminating particles 19 are added to the first layer of the SOC 151 etching mask (referred to as the polymer film or SOC film) before the spin coating. The size, shape, and material of the particles 19 are advantageously chosen to optimize their distribution over the interconnect holes in the most random manner possible. More specifically, the contaminating particles 19 are nanoparticles made of a dielectric, metallic, or polymer material. For example, this material can be silicon (Si), silicon dioxide (SiO2), Al2O3, silicon nitride, or any other material compatible with front-end processes. The size of the nanoparticles is chosen according to the dimensions of the targeted interconnect holes, which are generally cylindrical in shape.More specifically, the nanoparticles 19 have a diameter that is approximately equal to or greater than that of the interconnect holes. It should be noted that the particle size can also be invariably larger or smaller than the interconnect holes, but in this case, it is the average value of the size distribution that is approximately equal to or greater than that of the vias.

[0065] Furthermore, the nanoparticles 19 are present at a sufficiently low concentration, ranging from approximately 0.1% to 20% by mass, selected according to particle size. Within these limits, the concentration has virtually no effect on the coating properties of the SOC 151 film and, moreover, allows for a very homogeneous distribution within this film. This makes it possible to deactivate an optimal number of interconnect holes without blocking all of them. More specifically, the concentration of the nanoparticles 19 is adjusted according to the density of the circuit motifs and the proportion of electrical interconnects that one seeks to eliminate.

[0066] Advantageously, the surface of the nanoparticles 19 is treated so that its physicochemical surface properties are compatible with the chemical nature of the SOC film 151. This makes it possible to increase the efficiency of the process by optimizing the dispersion of the nanoparticles 19 in the polymer film 151 and avoiding the formation of particle aggregates in this film 151.

[0067] It should be noted that the SOC 151 film does not exhibit any particular characteristics for the lithography steps, and therefore, adding the nanoparticles to this first layer 151 advantageously allows the same lithography steps to be used as in a standard process. Furthermore, the SOC 151 film is quite thick and easily accommodates the nanoparticles 19. However, it is also possible to insert them into the third resin layer 153 or even into the thin second SiArc layer 152.

[0068] The fourth stage E4 ( Fig. 3D) consists of performing optical lithography in the safety zone 5b to expose the interconnection holes 17b provided in this zone 5b. The resin is developed and the patterns are transferred into the SiArc.

[0069] Alternatively, lithography can be of the electronic type, EUV, nano printing or any other type.

[0070] The standard zone 5a remains protected by the second multilayer 15 of photosensitive resin. Thus, optical lithography is performed only on the safety circuit. The particles 19 then partially or completely obstruct, in a random manner, some of the interconnect holes 17b in the safety zone 5b. This random distribution of nanoparticles in the SOC layer will partially or completely block the opening of the SOC during the etching step. This step clearly demonstrates that the randomness is inherent in the manufacturing process itself, and not in different masks or etching techniques.

[0071] The fifth stage E5 ( Fig. 3EThis involves transferring blocked or unblocked interconnect holes 17b into the etching mask. The SOC film 151 loaded with nanoparticles 19 is opened by a dry etching process (e.g., oxygen-based) to reproduce the patterns created by lithography. The chemical nature of the nanoparticles is chosen so that the plasma used to open the SOC will not etch them. For example, if the plasma used to open the SOC is primarily oxygen-based, silicon (Si), silicon dioxide (SiO2), Al2O3, or silicon nitride nanoparticles are used. The nanoparticles can also be made of metals compatible with the metal contamination requirements of the developed component.

[0072] Following the structuring of security zone 5b, the sixth stage E6 ( Fig. 3F) consists of cleaning the surface of the standard 5a and safety 5b areas in order to remove the second multilayer 15 of photosensitive resin and contaminating particles 19. A surface condition is again obtained that is suitable for carrying out lithography and engraving in the standard area.

[0073] Advantageously, for the removal of the second multilayer 15, a dry etching process can be used, offering good etch selectivity between the nanoparticles and the barrier layers. However, if the etch selectivity is insufficient, a buffer barrier layer can be added on top of those used for the metallic track fabrication process. This new buffer layer is made of a dielectric or metallic material that allows for the selective removal of the nanoparticles. For example, if the nanoparticles are SiO2-based, a SiN or TiN buffer layer can be used.

[0074] The seventh stage E7 ( Fig. 3G ) resumes the usual circuit manufacturing process as originally planned in standard zone 5a. Thus, at least a third multilayer (or layer) 21 of photosensitive resin is first deposited on the surface of standard zone 5a and safety zone 5b. Then, optical lithography is performed in standard zone 5a to isolate the interconnect holes 17a provided in this zone 5a.

[0075] The eighth stage E8 ( Fig. 3H ) consists of transferring the interconnection holes 17a from the standard area 5a into the etching mask. Then, the surface of the standard area 5a and the safety area 5b is re-cleaned to remove the third multilayer 21 of photosensitive resin.

[0076] The ninth and tenth stages E9-E10 ( Figs. 3I and 3J ) consist of transferring the interconnection holes 17a and 17b from the standard zone 5a and the safety zone 5b into the metallic diffusion barrier layer.

[0077] The eleventh stage E11 ( Fig. 3K ) consists of filling the interconnection holes 17a and 17b with a metal 23, for example, copper or aluminum. The filling can be carried out selectively so as not to fill the smallest openings.

[0078] The twelfth stage E12 ( Fig. 3L ) consists of creating a second level of conductive patterns 11a, 11b on the surface of the standard 5a and safety 5b zones respectively.

[0079] This embodiment demonstrates that all successive steps are regulated and controlled to ensure extremely low variability of the key circuit functionality parameters in the standard zone 5a, while by design allowing for an uncontrolled implementation of the random interconnection structure 7b in the safety zone 5b. This reinforces the uniqueness of each electronic chip 1, enabling its very precise identification while making cloning extremely difficult.

[0080] Advantageously, to prevent any variation due to aging, an electrical treatment is performed to eliminate fragile partial interconnections in the safety zone 5b. More specifically, a voltage higher than the readout voltage is applied to break very thin partial interconnections with excessive resistance. Furthermore, to test the authenticity of an integrated circuit 1, a challenge signal with a very low current intensity can be applied, preserving the circuit's identity throughout its lifetime.

[0081] It should be noted that the method of implementation of the security process according to the Figs. 3A-3J is transposable to the "Front End", that is, during the manufacturing of logic circuits.

Claims

1. Method for securing an integrated circuit during the realisation thereof, said method comprising the following steps: - delimiting of said integrated circuit (1) into a first zone referred to as standard zone (5a) and into a second zone referred to as security zone (5b), said standard zone comprising at least two levels of conductive tracks (9a, 11a) connected to one another and to electronic components via metallic interconnections, - introducing of a layer of resin loaded with contaminant particles (19) configured to randomly obstruct during a step of etching of the security zone (5b) a portion of the vias provided in said security zone (5b) thus forming a random set of vias (17b), and - metalizing of said random set of vias (17b) of the security zone (5b) in order to form a random interconnection structure (7b) adapted so that its electrical continuity can be tested, thereby defining a physical unclonable function, said random interconnection structure (7b) being formed between at least two levels (8, 10) of conductive patterns (9b, 11b) at the same levels as the conductive tracks of the standard zone.

2. Method according to claim 1, characterised in that the contaminant particles (19) are nanoparticles formed from a material of the dielectric or metallic type selected from the following materials: silicon, silicon dioxide SiO2, silicon, metal TiN.

3. Method according to claim 1 or 2, characterised in that the contaminant particles (19) have a diameter that is substantially greater than or equal to that of the vias.

4. Method according to any preceding claim, characterised in that the contaminant particles (19) have a concentration between about 0.1% to 20% by mass selected according to the size of the particles.

5. Method according to any preceding claim, characterised in that the securing of the integrated circuit is integrated on the realisation of the first vias and further comprises the following steps: - realising a first level (8) of conductive patterns (9a, 9b) on the surface of said standard (5a) and security (5b) zones, - depositing on the surface of the first level (8) of conductive patterns (9a, 9b) of a first multilayer (13) comprising a metal diffusion barrier as well as an etching mask, - depositing on the surface of the first multilayer (13) of a second multilayer (15) of photosensitive resin comprising said resin layer loaded with contaminant particles (19), - optical lithography in the security zone (5b) for insulating the vias (17b) provided in this security zone, with the standard zone remaining protected by the second multilayer (15), - transferring of the vias of the security zone (5b) non-obstructed or obstructed by contaminant particles in the etching mask, - cleaning of the surface of the standard (5a) and security (5b) zones in order to remove the second multilayer (15).

6. Method according to claim 5, characterised in that the second multilayer (15) comprises a first layer of etching mask of the carbon-enriched organic layer type SOC (151), a second layer of etching mask of the silicon-enriched organic layer type SiARC (152) and a third layer of photosensitive resin (153), the contaminant particles (19) being comprised in said first layer of etching mask SOC (151).

7. Method according to claim 6, characterised in that it further comprises the following steps: - depositing on the surface of the standard (5a) and security (5b) zones of at least one third multilayer (21) of photosensitive resin, - optical lithography in the standard zone (5a) for insulating the vias (17a) provided in the standard zone (5a), - transferring of the vias (17a) of the standard zone (5a) in the etching mask, - re-cleaning of the surface of the standard (5a) and security (5b) zones in order to remove the third multilayer (21) of photosensitive resin, - transferring in the metal diffusion barrier layer and filling by a metal (23) of the vias (17a, 17b) in the standard (5a) and security (5b) zones, and - realising of a second level (10) of conductive patterns (11a, 11b) on the surface of the standard (5a) and security (5b) zones.

8. Method according to any preceding claim, characterised in that it comprises an application of a voltage greater than a reading voltage in order to break down fragile partial vias.

9. Method according to any preceding claim, characterised in that the random interconnection structure (7b) models a random electrical continuity that can be queried by a challenge-response authentication protocol, said random interconnection structure (7b) being formed between at least two corresponding levels (8, 10) of conductive patterns (9b, 11b), with a portion of the conductive patterns being configured to receive a challenge, while another portion of the conductive patterns is configured to supply the response to said challenge.

10. Method according to any preceding claim, characterised in that it comprises the realisation of a plurality of random interconnection structures between at least two levels of conductive patterns.

11. Method according to any preceding claim, characterised in that the securing of the integrated circuit is realised at the manufacturing of logic circuits.