BEAT CONFIGURATION SYSTEM AND PROCEDURES

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of communication, and in particular, to a clock configuration system and method.BACKGROUND

[0002] In increasingly complex communication systems, with a rapid increase in the amount of data transmission, various communication protocols support higher and higher rates, and the number of data transmission channels integrated into each communication module is increasing. In a single channel, line rates in transmitting and receiving directions are completely independent. The line rates in respective channels are independent, and sampling frequencies in the transmitting and receiving directions are completely independent. The above features bring the advantages of powerful data processing capability and flexible use. At the same time, due to increasing combinations of AD / DA sampling frequencies and transmission channel line rates, a design scale becomes larger and larger. In the case where a conventional clock design and configuration manner continues to be used, the complexity of the system will be increased, and clock configuration is also increasingly difficult.

[0003] Internet publication "Virtex-5 FPGA RocketIO GTP Transceiver" shows how to use the RocketIO ™< GTP transceivers in Virtex ®< -5 FPGAs.

[0004] Internet publication "Virtex-5 FPGA Interface to a JESD204A Compliant ADC" describes how to interface the Virtex ®< -5 LXT, SXT, TXT, and FXT devices featuring GTP / GTX transceivers to an analog-to-digital (ADC) converter compliant to JEDEC Standard No. 204A (JESD204A) Serial Interface for Data Converters.

[0005] Patent literature CN109521834A discloses a DP signal generating device and a method. The device includes a control unit, a clock adjusting unit and a signal adjusting unit. The control unit is used for calculating the frequency division coefficient and the frequency multiplication coefficient according to the output bandwidth required by the module to be tested and the frequency of the first reference clock. The clock adjusting unit is configured to perform frequency doubling processing on the first reference clock according to the frequency doubling coefficient to obtain a high-frequency clock signal. The signal adjusting unit is used for dividing the high-frequency clock signal according to the frequency dividing coefficient, and converting the received DP parallel data into serial data output according to the frequency dividing clock.

[0006] Patent literature (CN107315448A) discloses a design method for a clock management framework of a low-power multi-core SoC. A PLL (phase-locked loop) circuit is integrated in an SoC chip; an input clock is subjected to frequency doubling to obtain a high-frequency clock required in the SoC chip; the clock subjected to the frequency doubling is subjected to frequency division of different multiples through a frequency divider according to application configuration information to obtain working clocks required by all modules in the SoC chip; the selection of a clock source is controlled through an external port CLKMODE, and an external clock source mode or a PLL mode is selected.

[0007] Patent literature CN205563555U relates to a signal processing technique field provides an implementation system of self -defined variable bit wide SPI bus agreement based on FPGA, and this system includes clock frequency module, address count module, mode -selection module, control state machine, parallel serial conversion module, chip selection distribution module, data count module.

[0008] While the above publications may achieve their intended purposes, there is still a need for a new and improved clock configuration system and method.SUMMARY

[0009] In view of the above, according to an embodiment of the present application, a clock configuration system is provided, which includes: a clock generation circuit, and a communication module includes a configuration unit, a clock management unit, and a communication circuit; the clock generation circuit is connected to the clock management unit in the communication module; the clock management unit is connected to the communication circuit; and the communication circuit is connected to the configuration unit; the clock generation circuit is configured to provide a reference clock to the communication module; the configuration unit is configured to configure a line rate and a data bit width for data transmission in the communication circuit, determine a clock frequency division coefficient according to the line rate and the data bit width, and set the clock frequency division coefficient into the clock management unit; and the clock management unit is configured to determine an operating clock frequency according to the reference clock and the clock frequency division coefficient, and provide the operating clock frequency to the communication circuit; where the clock management unit includes a Phase Locked Loop, PLL, circuit, a transmit divider, and a data channel divider; the communication circuit includes a transmit data processing unit, a transmit transport layer unit, a plurality of transmit channels, and a plurality of parallel-serial conversion units; wherein each transmit channel corresponds to a respective one of the parallel-serial conversion units; the PLL circuit is connected to the clock generation circuit, the transmit divider, and the data channel divider; the transmit divider is connected to the transmit data processing unit and the transmit transport layer unit; the data channel divider is connected to each of the plurality of transmit channels, and each transmit channel is connected to a respective one of the parallel-serial conversion units; the configuration unit is configured to configure a line rate and a data bit width for each transmit channel, determine a first frequency division coefficient according to a total line rate and a total data bit width of the transmit channels, and set the first frequency division coefficient into the transmit divider; the configuration unit is further configured to determine a second frequency division coefficient, and set the second frequency division coefficient into the data channel divider; the PLL circuit is configured to transmit the reference clock to the transmit divider and the data channel divider; the transmit divider is configured to determine a first operating clock frequency according to the reference clock and the first frequency division coefficient, and provide the first operating clock frequency to the transmit data processing unit and the transmit transport layer unit; the data channel divider is configured to determine a second operating clock frequency according to the reference clock and the second frequency division coefficient, and provide the second operating clock frequency to each of the plurality of transmit channels; and each of the plurality of parallel-serial conversion units is connected to the clock generation circuit and is configured to receive the reference clock, and generate, according to the reference clock, a third operating clock frequency for each parallel-serial conversion unit; and where determination of the second frequency division coefficient includes: acquiring a maximum value of the ratio of the line rate to the data bit width among the transmit channels; and determining the second frequency division coefficient according to the maximum value and the reference clock.

[0010] According to an embodiment of the present application, a clock configuration method is provided, which is performed by the clock configuration system according to an embodiment of the present application. The method includes: receiving a reference clock, and acquiring a configured line rate and a configured data bit width for data transmission; determining a clock frequency division coefficient according to the line rate and the data bit width; determining an operating clock frequency according to the clock frequency division coefficient and the reference clock; and providing the operating clock frequency to the communication module.BRIEF DESCRIPTION OF DRAWINGS

[0011] FIG. 1 depicts a schematic diagram of a clock configuration system according to an embodiment of the present application; FIG. 2 depicts a schematic diagram of a clock configuration system according to an embodiment of the present application; and FIG. 3 depicts a flowchart of a clock configuration method according to an embodiment of the present application. DETAILED DESCRIPTION

[0012] Objects, technical schemes and advantages of the present application will be clearer from a detailed description of embodiments of the present application in conjunction with the drawings. It is to be noted that if not in collision, the embodiments in the present application and features in the embodiments may be combined with each other.

[0013] It is to be understood that specific embodiments described herein are intended only to explain and not to limit the present application.

[0014] In subsequent descriptions, a suffix such as "module", "component", or "unit" used for representing an element is used only for describing the present application, and does not have any particular meanings. Therefore, "module", "component" and "unit" are exchangeable.

[0015] FIG. 1 depicts a schematic diagram of a clock configuration system according to an embodiment of the present application. As shown in FIG. 1, the system includes: a clock generation circuit 10, a communication module 20, and an AD / DA circuit 30. The communication module 20 includes a configuration unit 21, a clock management unit 22, and a communication circuit 23.

[0016] The clock generation circuit 10 is connected to the clock management unit 22 in the communication module 20. The clock management unit 22 is connected to the communication circuit 23. The communication circuit 23 is connected to the configuration unit 21.

[0017] The clock generation circuit 10 is configured to provide a reference clock to the communication module 20 and the AD / DA circuit 30. The configuration unit 21 is configured to configure a line rate and a data bit width of data transmission in the communication circuit 23, determine a clock frequency division coefficient according to the line rate and the data bit width, and configure the clock frequency division coefficient in the clock management unit 22. The clock management unit 22 is configured to determine an operating clock frequency according to the reference clock and the clock frequency division coefficient, and provide the operating clock frequency to the communication circuit 23.

[0018] The configuration unit can be understood as a general command center of the system, and configure, according to different application scenarios, various units in a certain order to schedule the operation of the system. A look-up table may be pre-generated for configurations of various scenarios, and corresponding configuration information in the table is selected for configuration according to different scenarios. For example, it is assumed that, during scenario switching, first configuration information in the table is selected for Scenario 1, and second configuration information in the table is selected when Scenario 2 is switched to.

[0019] The clock configuration system in the embodiment may be applied to JESD204B / C protocol different-rate clock configuration.

[0020] In an embodiment, the clock management unit includes a Phase Locked Loop (PLL) circuit, a transmit divider, and a data channel divider. The communication circuit includes a transmit data processing unit, a transmit transport layer unit, a plurality of transmit channels, and a plurality of parallel-serial conversion units, where the transmit channels are in one-to-one correspondence to the parallel-serial conversion units. The PLL circuit is connected to the clock generation circuit, the transmit divider, and the data channel divider, respectively. The transmit divider is connected to the transmit data processing unit and the transmit transport layer unit, respectively. The data channel divider is connected to the plurality of transmit channels. Each transmit channel is connected to a corresponding parallel-serial conversion unit. The configuration unit is configured to configure line rates and data bit widths for the transmit channels, determine a first frequency division coefficient according to a total line rate and a total data bit width of the transmit channels, and configure the first frequency division coefficient in the transmit divider. The configuration unit is further configured to determine a second frequency division coefficient, and set the second frequency division coefficient into the data channel divider. The PLL circuit is configured to transmit the reference clock to the transmit divider and the data channel divider. The transmit divider is configured to determine a first operating clock frequency according to the reference clock and the first frequency division coefficient, and provide the first operating clock frequency to the transmit data processing unit and the transmit transport layer unit. The data channel divider is configured to determine a second operating clock frequency according to the reference clock and the second frequency division coefficient, and provide the second operating clock frequency to the plurality of transmit channels. The plurality of parallel-serial conversion units are each connected to the clock generation circuit and configured to receive the reference clock, and generate, according to the reference clock, a third operating clock frequency required by the parallel-serial conversion units.

[0021] The PLL circuit is configured to adjust the reference clock and transmit the adjusted reference clock to the transmit divider, the data channel divider, and the receive divider. The process of adjustment may be a process of frequency spreading of the reference clock. The frequency spreading may be understood as increasing the reference clock by an integral multiple. For example, in case that the reference clock is at 150 Hz, the reference clock is at 450 Hz after increasing by 3 times.

[0022] The parallel-serial conversion unit is further configured to convert parallel transmit data to serial transmit data. If N parallel-serial conversion units are present, the clock generation circuit provides N reference clocks.

[0023] In an embodiment, the first frequency division coefficient may be determined according to the total line rate and the total data bit width of the transmit channels by: acquiring a first ratio of the total line rate to the total data bit width of the transmit channels; and determining the first frequency division coefficient according to the first ratio and the reference clock.

[0024] In particular, the first ratio is a first operating clock frequency. Provided that the line rate configured for each transmit channel is R1(i) and the configured data bit width is W1(i), then the determined first operating clock frequency is f 1 = ∑ i R 1 i ∑ i W 1 i . The first frequency division coefficient is determined according to the calculated first clock frequency and the adjusted reference clock, and is configured in the transmit divider, so that the transmit divider generates the first operating clock frequency according to the first frequency division coefficient and the adjusted reference clock. The first frequency division coefficient may be a ratio of the first clock frequency to the adjusted reference clock.

[0025] In an embodiment, the system further includes: a plurality of first transmit data conversion units and a plurality of second transmit data conversion units. The first transmit data conversion units and the second transmit data conversion units are in one-to-one correspondence to the transmit channels. Each first transmit data conversion unit is connected between the transmit transport layer unit and a respective one of the transmit channels. Each second transmit data conversion unit is connected between a respective one of the transmit channels and a respective one of the parallel-serial conversion units.

[0026] Each first transmit data conversion unit has a write end connected to the transmit divider and configured to receive the first operating clock frequency transmitted by the transmit divider. Each first transmit data conversion units has a read end connected to the data channel divider and configured to receive the second operating clock frequency transmitted by the data channel divider. Each first transmit data conversion unit is configured to convert an operating clock frequency of transmit data from the first operating clock frequency into the second operating clock frequency.

[0027] Each second transmit data conversion unit has a write end connected to the data channel divider and configured to receive the second operating clock frequency transmitted by the data channel divider. Each second transmit data conversion unit has a read end connected to a parallel-serial conversion unit and configured to receive the third operating clock frequency transmitted by the parallel-serial conversion unit. Each second transmit data conversion unit is configured to convert a bit width of the transmit data, and / or convert the operating clock frequency of the transmit data from the second operating clock frequency into the third operating clock frequency.

[0028] In an embodiment, the transmit channel includes: a transmit link layer unit and a transmit data logic processing unit. The transmit link layer unit is connected between the first transmit data conversion unit and the transmit data logic processing unit. The transmit data logic processing unit is connected between the transmit link layer unit and the second transmit data conversion unit. The data channel divider is configured to provide the second operating clock frequency to the transmit link layer unit and the transmit data logic processing unit.

[0029] The transmit link layer unit is configured to encode the transmit data. The transmit data logic processing unit is configured to frame and scramble the encoded transmit data.

[0030] The encoding of transmit data may include 8B / 10B encoding, 64b / 66b encoding or the like. The scrambling process may involve: performing a logical operation (such as XOR operation) on a pseudo-random sequence generated by a pseudo-random code generator, and the transmit data, to change features of the transmit data, so as to change the transmit data into an unpredictable data flow. The framing may be performed in a manner such that a head and a tail are added to the front and the back of a piece of data to form a frame.

[0031] In an embodiment, the clock management unit further includes a receive divider. The communication circuit includes a receive data processing unit, a receive transport layer unit, a plurality of receive channels, and a plurality of serial-parallel conversion units. The receive channels are in one-to-one correspondence to the serial-parallel conversion units. The receive divider is connected to the PLL circuit, the receive data processing unit, and the receive transport layer unit. The data channel divider is connected to the plurality of receive channels. A receive channel is connected to a respective one of the serial-parallel conversion units.

[0032] The configuration unit is configured to configure line rates and data bit widths of the receive channels, determine a third frequency division coefficient according to a total line rate and a total data bit width of the receive channels, and set the third frequency division coefficient into the receive divider. The PLL circuit is configured to transmit the reference clock to the receive divider.

[0033] The receive divider is configured to determine a fourth operating clock frequency according to the reference clock and the third frequency division coefficient, and provide the fourth operating clock frequency to the receive data processing unit and the receive transport layer unit.

[0034] The data channel divider is further configured to provide the second operating clock frequency to the plurality of transmit channels. The plurality of serial-parallel conversion units are connected to the clock generation circuit and configured to receive the reference clock, and generate, according to the reference clock, a fifth operating clock frequency required by the serial-parallel conversion units.

[0035] The third frequency division coefficient may be determined according to the total line rate and the total data bit width of the receive channels by: acquiring a second ratio of the total line rate to the total data bit width of the receive channels; and determining the third frequency division coefficient according to the second ratio and the reference clock.

[0036] The second ratio may be understood as the fourth operating clock frequency. Assuming that the line rate configured for each receive channel is R2(i) and the configured data bit width is W2(i), the determined fourth operating clock frequency is f 4 = ∑ i R 2 i ∑ i W 2 i . The third frequency division coefficient is determined according to the calculated fourth clock frequency and the adjusted reference clock, and is set into the receive divider, so that the receive divider generates the fourth operating clock frequency according to the third frequency division coefficient and the adjusted reference clock. The third frequency division coefficient may be a ratio of the fourth operating clock frequency to the adjusted reference clock.

[0037] In an embodiment, the second frequency division coefficient may be determined by: acquiring a maximum value of the ratios of the line rates to the data bit widths of each of the transmit channels and / or each of the receive channels; and determining the second frequency division coefficient according to the maximum value and the reference clock.

[0038] The determined second operating clock frequency is f 2 = max R i W i . The second frequency division coefficient is determined according to the calculated second clock frequency and the adjusted reference clock, and is configured in the data channel divider, so that the data channel divider generates the second operating clock frequency according to the second frequency division coefficient and the adjusted reference clock. The above processing has the advantage of ensuring that the line rates of data in the transmit link layer unit, the transmit data logic processing unit, the receive link layer unit, and receive data logic processing unit are greater than the line rates of all channels. The second frequency division coefficient may be a ratio of the second clock frequency to the adjusted reference clock.

[0039] In an embodiment, the system further includes: a plurality of first receive data conversion units and a plurality of second receive data conversion units. The first receive data conversion units and the second receive data conversion units are respectively in one-to-one correspondence to the receive channels. Each first receive data conversion unit is connected between the receive transport layer unit and a respective one of the receive channels. Each second receive data conversion unit is connected between a respective one of the receive channels and a respective one of the parallel-serial conversion units.

[0040] Each first receive data conversion unit has a read end connected to the receive divider and configured to receive the fourth operating clock frequency transmitted by the receive divider. Each first receive data conversion unit has a write end connected to the data channel divider and configured to receive the second operating clock frequency transmitted by the data channel divider. Each first receive data conversion unit is configured to convert an operating clock frequency of receive data from the second operating clock frequency into the fourth operating clock frequency.

[0041] Each second receive data conversion unit has a read end connected to the data channel divider and configured to receive the second operating clock frequency transmitted by the data channel divider. Each second receive data conversion unit has a write end connected to a respective one of the serial-parallel conversion units and configured to receive the fifth operating clock frequency transmitted by the serial-parallel conversion unit. Each second receive data conversion unit is configured to convert a bit width of the receive data, and / or convert the operating clock frequency of the receive data from the fifth operating clock frequency into the second operating clock frequency.

[0042] In an embodiment, the receive channel includes: a receive link layer unit and a receive data logic processing unit. The receive link layer unit is connected between a first receive data conversion unit and a receive data logic processing unit. The receive data logic processing unit is connected between a receive link layer unit and a second receive data conversion unit. The data channel divider is configured to provide the second operating clock frequency to the receive link layer unit and the receive data logic processing unit.

[0043] The receive link layer unit is configured to decode the receive data. The receive data logic processing unit is configured to deframe and descramble the encoded receive data.

[0044] Descrambling is a reverse process of scrambling, and involves performing the same logical operation on the scrambled receive data by the same pseudo-random code as that of a transmitting end, and restoring data before scrambling. The deframing is a reverse process of framing, and involves identifying the start and end of a frame according to head and end tags of the receive data after a data flow is received.

[0045] FIG. 2 depicts a schematic diagram of a clock configuration system according to an embodiment of the present application. As a further illustration of the above embodiment, as shown in FIG. 2, the clock management unit 22 includes a PLL, a transmit divider, a data channel divider, and a receive divider. The communication circuit includes a communication circuit responsible for transmit data and a communication circuit responsible for receive data. The communication circuit responsible for transmit data includes: a transmit data processing unit, a transmit transport layer unit, a plurality of transmit channels, and a plurality of parallel-serial conversion units. Each transmit channel includes a transmit link layer unit and a transmit data logic processing unit. The communication circuit responsible for receive data includes: a receive data processing unit, a receive transport layer unit, a plurality of receive channels, and a plurality of serial-parallel conversion units. Each receive channel includes a receive link layer unit and a receive data logic processing unit.

[0046] The transmit channels are in one-to-one correspondence to the parallel-serial conversion units. The receive channels are in one-to-one correspondence to the serial-parallel conversion units.

[0047] In an embodiment, the transmit divider is configured to provide the first operating clock frequency to the transmit data processing unit and the transmit transport layer unit. The data channel divider is configured to provide the second operating clock frequency to the transmit link layer unit, the transmit data logic processing unit, the receive link layer unit, and the receive data logic processing unit. The receive divider is configured to provide the fourth operating clock frequency to the receive data processing unit and the receive transport layer unit.

[0048] In an embodiment, as shown in FIG. 2, the PLL circuit is connected to the clock generation circuit, the transmit divider, and the data channel divider, respectively. The transmit divider is connected to the transmit data processing unit and the transmit transport layer unit. The data channel divider is connected to the plurality of transmit channels. Each transmit channel is connected to a respective one of the parallel-serial conversion units.

[0049] In an embodiment, the configuration unit 21 is configured to configure line rates and data bit widths for each of the transmit channels, determine a first frequency division coefficient according to a total line rate and a total data bit width of the transmit channels, and set the first frequency division coefficient into the transmit divider; and the configuration unit is further configured to determine a second frequency division coefficient according to the line rate and data bit width of each of the transmit channels and / or the receive channels, and set the second frequency division coefficient into the data channel divider.

[0050] In an embodiment, the transmit divider provides the first operating clock frequency to the transmit data processing unit and the transmit transport layer unit. The data channel divider provides the second operating clock frequency to a plurality of transmit channels, that is, to the transmit link layer units and the transmit data logic processing units.

[0051] In an embodiment, each of the plurality of parallel-serial conversion units is connected to the clock generation circuit and configured to receive the reference clock, and generate, according to the reference clock, a third operating clock frequency required by the parallel-serial conversion units.

[0052] In an embodiment, as shown in FIG. 2, the system further includes: a plurality of first transmit data conversion units and a plurality of second transmit data conversion units. The first transmit data conversion units and the second transmit data conversion units are both in one-to-one correspondence to the transmit channels. Each first transmit data conversion unit is connected between the transmit transport layer unit and a respective one of the transmit channels. Each second transmit data conversion unit is connected between a respective one of the transmit channels and a respective one of the parallel-serial conversion units.

[0053] Each first transmit data conversion unit is configured to convert a clock domain of the transmit data. Each second transmit data conversion unit is configured to convert a bit width and / or a clock domain of the transmit data. Converting the clock domain may be understood as converting an operating clock frequency of the transmit data.

[0054] Each first transmit data conversion unit has a write end connected to the transmit divider and configured to receive the first operating clock frequency transmitted by the transmit divider. Each first transmit data conversion unit has a read end connected to the data channel divider and configured to receive the second operating clock frequency transmitted by the data channel divider. Each first transmit data conversion unit is configured to convert an operating clock frequency of transmit data from the first operating clock frequency into the second operating clock frequency.

[0055] The write end of each first transmit data conversion unit can be understood as the end of the first transmit data conversion unit to which data is inputted, and the read end can be understood as the end of the first transmit data conversion unit from which data is outputted.

[0056] Each second transmit data conversion unit has a write end connected to the data channel divider and configured to receive the second operating clock frequency transmitted by the data channel divider. Each second transmit data conversion unit has a read end connected to a parallel-serial conversion unit and configured to receive the third operating clock frequency transmitted by the parallel-serial conversion unit. Each second transmit data conversion unis is configured to convert a bit width of the transmit data, and / or convert the operating clock frequency of the transmit data from the second operating clock frequency into the third operating clock frequency.

[0057] The write end of each second transmit data conversion unit can be understood as the end of the second transmit data conversion unit to which data is inputted, and the read end can be understood as the end of the second transmit data conversion unit from which data is outputted.

[0058] Each of the first transmit data conversion units and the second transmit data conversion units is implemented as a pingpong-RAM. The pingRAM and the pongRAM may each store one frame of data. In each first transmit data conversion unit, data is written at a line rate of R1(i) at the write end, and data is read at a line rate of f2*W1(i) at the read end. In each second transmit data conversion unit, data is written at a line rate of f2*W1(i) at the write end, and data is read at a line rate of R1(i) at the read end.

[0059] In an embodiment, as shown in FIG. 2, the transmit channel includes: a transmit link layer unit and a transmit data logic processing unit. Each transmit link layer unit is connected between a first transmit data conversion unit and a transmit data logic processing unit. Each transmit data logic processing unit is connected between a transmit link layer unit and a second transmit data conversion unit. The data channel divider is configured to provide the second operating clock frequency to the transmit link layer units and the transmit data logic processing units.

[0060] Each transmit link layer unit is configured to encode the transmit data. Each transmit data logic processing unit is configured to frame and scramble the encoded transmit data. In this embodiment, the encoding of the transmit link layer unit and the framing and scrambling of the transmit data logic processing unit are all configured by the configuration unit.

[0061] In an embodiment, as shown in FIG. 2, the clock management unit further includes a receive divider. The communication circuit includes a receive data processing unit, a receive transport layer unit, a plurality of receive channels, and a plurality of serial-parallel conversion units. The receive channels are in one-to-one correspondence to the serial-parallel conversion units.

[0062] In an embodiment, as shown in FIG. 2, the receive divider is connected to the PLL circuit, the receive data processing unit, and the receive transport layer unit. The data channel divider is connected to the plurality of receive channels. Each receive channel is connected to a respective one of the serial-parallel conversion units.

[0063] The configuration unit 21 is configured to configure line rates and data bit widths of the receive channels, determine a third frequency division coefficient according to a total line rate and a total data bit width of the receive channels, and set the third frequency division coefficient into the receive divider.

[0064] The PLL circuit is configured to transmit the adjusted reference clock to the receive divider. The receive divider is configured to provide the fourth operating clock frequency to the receive data processing units and the receive transport layer units.

[0065] In this embodiment, the data channel divider is further configured to provide the second operating clock frequency to the plurality of transmit channels.

[0066] In an embodiment, each of the plurality of serial-parallel conversion unit is connected to the clock generation circuit and configured to receive the reference clock, and generate, according to the reference clock, a fifth operating clock frequency required by the serial-parallel conversion units.

[0067] Each serial-parallel conversion unit is further configured to convert serial receive data into parallel receive data. If N serial-parallel conversion units present, it is necessary for the clock generation circuit provide N reference clocks.

[0068] In an embodiment, the system further includes: a plurality of first receive data conversion units and a plurality of second receive data conversion units. The first receive data conversion units and the second receive data conversion units are both in one-to-one correspondence to the receive channels.

[0069] Each first receive data conversion unit is connected between the receive transport layer unit and a respective one of the receive channels. Each second receive data conversion unit is connected between a respective one of the receive channels and a respective one of the parallel-serial conversion units.

[0070] In this embodiment, each first receive data conversion unit is configured to convert a clock domain of the receive data. Each second receive data conversion unit is configured to convert a bit width and / or a clock domain of the received data. Converting the clock domain may be understood as converting an operating clock frequency of the received data.

[0071] In an embodiment, each first receive data conversion unit has a read end connected to the receive divider and configured to receive the fourth operating clock frequency transmitted by the receive divider. Each first receive data conversion unit has a write end connected to the data channel divider and configured to receive the second operating clock frequency transmitted by the data channel divider. Each first receive data conversion unit is configured to convert an operating clock frequency of the received data from the second operating clock frequency into the fourth operating clock frequency.

[0072] The write end of each first receive data conversion unit can be understood as the end of the first receive data conversion unit to which data is inputted, and the read end can be understood as the end of the first receive data conversion unit from which data is outputted.

[0073] In an embodiment, each second receive data conversion unit has a read end connected to the data channel divider and configured to receive the second operating clock frequency transmitted by the data channel divider. Each second receive data conversion unit has a write end connected to a serial-parallel conversion unit and configured to receive the fifth operating clock frequency transmitted by the serial-parallel conversion unit. Each second receive data conversion unit is configured to convert a bit width of the received data, and / or convert the operating clock frequency of the received data from the fifth operating clock frequency into the second operating clock frequency.

[0074] The write end of each second receive data conversion unit can be understood as the end of the second receive data conversion unit to which data is inputted, and the read end can be understood as the end of the second receive data conversion unit from which data is outputted.

[0075] Each of the first receive data conversion units and the second receive data conversion units is implemented as a pingpong-RAM. The pingRAM and the pongRAM may each store one frame of data. In each first transmit data conversion unit, data is written at a line rate of f2*W2(i) at the write end, and data is read at a line rate of R2(i) at the read end. In each second transmit data conversion unit, data is written at a line rate of R2(i) at the write end, and data is read at a line rate of f2*W2(i) at the read end.

[0076] In an embodiment, each receive channel includes: a receive link layer unit and a receive data logic processing unit. Each receive link layer unit is connected between a first receive data conversion unit and a receive data logic processing unit. Each receive data logic processing unit is connected between a receive link layer unit and a second receive data conversion unit. The data channel divider is configured to provide the second operating clock frequency to the receive link layer units and the receive data logic processing units.

[0077] Each receive link layer unit is configured to decode the received data. Each receive data logic processing unit is configured to deframe and descramble the encoded received data. In this embodiment, the decoding of the receive link layer unit and the deframing and descrambling of the receive data logic processing unit are all configured by the configuration unit.

[0078] In this embodiment, the transmit link layer units and the transmit data logic processing units in the plurality of transmit channels and the receive link layer units and the receive data logic processing units in the plurality of receive channels share a single second operating clock frequency, so that the number of clocks will not be increased due to an increase in the number of the transmit channels and the receive channels, simplifying the process of clock configuration.

[0079] In the technical scheme of this embodiment, a clock generation circuit and a communication module are included. The communication module includes a configuration unit, a clock management unit, and a communication circuit. The clock generation circuit is configured to provide a reference clock to the communication module. The configuration unit is configured to configure a line rate and a data bit width of data transmission in the communication circuit, determine a clock frequency division coefficient according to the line rate and the data bit width, and set the clock frequency division coefficient into the clock management unit. The clock management unit is configured to determine an operating clock frequency according to the reference clock and the clock frequency division coefficient, and provide the operating clock frequency to the communication circuit. The operating clock frequency is determined according to the configured line rate and data bit width, so that the complexity of clock configuration in the communication module can be reduced.

[0080] FIG. 3 depicts a flowchart of a clock configuration method according to an embodiment of the present application. As shown in FIG. 3, the method includes S310 to S340.

[0081] At S310, a reference clock is received, and a configured line rate and a configured data bit width for data transmission are acquired.

[0082] At S320, a clock frequency division coefficient is determined according to the line rate and the data bit width.

[0083] At S330, an operating clock frequency is determined according to the clock frequency division coefficient and the reference clock.

[0084] At S340, the operating clock frequency is provided to the communication module.

[0085] Please refer to the description in the above embodiments for the procedure of clock configuration, which is not repeated here.

[0086] In this embodiment, a reference clock is received, and a configured line rate and a configured data bit width for data transmission are acquired; a clock frequency division coefficient is determined according to the line rate and the data bit width; an operating clock frequency is determined according to the clock frequency division coefficient and the reference clock; and the operating clock frequency is provided to the communication module. The operating clock frequency is determined according to the configured line rate and the configured data bit width, so that the complexity of clock configuration in the communication module can be reduced.

[0087] Clock configuration system and method are provided in the embodiments of the present application, the system includes a clock generation circuit and a communication module. The communication module includes a configuration unit, a clock management unit, and a communication circuit. The clock generation circuit is configured to provide a reference clock to the communication module. The configuration unit is configured to configure a line rate and a data bit width of data transmission in the communication circuit, determine a clock frequency division coefficient according to the line rate and the data bit width, and set the clock frequency division coefficient into the clock management unit. The clock management unit is configured to determine an operating clock frequency according to the reference clock and the clock frequency division coefficient, and provide the operating clock frequency to the communication circuit. The operating clock frequency is determined according to the configured line rate and data bit width. The plurality of transmit channels and the plurality of receive channels in the communication circuit share one operating clock frequency, so that the number of clocks will not be increased due to an increase in the number of the transmit channels and the receive channels, thus simplifying the process of clock configuration is simplified, and reducing the complexity of clock configuration in the communication module.

[0088] Some embodiments of the present application are described above and which are not intended to limit the protection scope of the present application.

[0089] Embodiments of the present application may be implemented as computer program instructions executed by a data processor of a mobile apparatus, for example, in a processor entity, may be implemented as hardware, or may be implemented as a combination of software and hardware. The computer program instructions may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcodes, firmware instructions, status setting data, or source or object codes written in any combination of one or more programming languages.

[0090] A detailed description of example embodiments of the present application has been provided above through demonstrative and non-restrictive examples. However, in consideration of the drawings and claims, various modifications and alternations to the above embodiments are obvious to those skilled in the art, without departing from the scope of the present application. Accordingly, the proper scope of the present application will be defined by the claims.

Claims

1. A clock configuration system, comprising: a clock generation circuit (10), and a communication module (20) comprising a configuration unit (21), a clock management unit (23), and a communication circuit (22); wherein, the clock generation circuit (10) is connected to the clock management unit (23) in the communication module (20); the clock management unit (23) is connected to the communication circuit (22), and the communication circuit (22) is connected to the configuration unit (21); the clock generation circuit (10) is configured to provide a reference clock to the communication module (20); the configuration unit (21) is configured to configure a line rate and a data bit width for data transmission in the communication circuit (22), determine a clock frequency division coefficient according to the line rate and the data bit width, and set the clock frequency division coefficient into the clock management unit (23); and the clock management unit (23) is configured to determine an operating clock frequency according to the reference clock and the clock frequency division coefficient, and provide the operating clock frequency to the communication circuit (22); wherein, the clock management unit (23) comprises a Phase Locked Loop, PLL, circuit, a transmit divider, and a data channel divider; the communication circuit (22) comprises a transmit data processing unit, a transmit transport layer unit, a plurality of transmit channels, and a plurality of parallel-serial conversion units; wherein each transmit channel corresponds to a respective one of the parallel-serial conversion units; the PLL circuit is connected to the clock generation circuit (10), the transmit divider, and the data channel divider; the transmit divider is connected to the transmit data processing unit and the transmit transport layer unit; the data channel divider is connected to each of the plurality of transmit channels, and each transmit channel is connected to a respective one of the parallel-serial conversion units; the configuration unit (21) is configured to configure a line rate and a data bit width for each transmit channel, determine a first frequency division coefficient according to a total line rate and a total data bit width of the transmit channels, and set the first frequency division coefficient into the transmit divider; the configuration unit (21) is further configured to determine a second frequency division coefficient, and set the second frequency division coefficient into the data channel divider; the PLL circuit is configured to transmit the reference clock to the transmit divider and the data channel divider; the transmit divider is configured to determine a first operating clock frequency according to the reference clock and the first frequency division coefficient, and provide the first operating clock frequency to the transmit data processing unit and the transmit transport layer unit; the data channel divider is configured to determine a second operating clock frequency according to the reference clock and the second frequency division coefficient, and provide the second operating clock frequency to each of the plurality of transmit channels; and each of the plurality of parallel-serial conversion units is connected to the clock generation circuit (10) and is configured to receive the reference clock, and generate, according to the reference clock, a third operating clock frequency for each parallel-serial conversion unit; and wherein determination of the second frequency division coefficient comprises: acquiring a maximum value of the ratio of the line rate to the data bit width among the transmit channels; and determining the second frequency division coefficient according to the maximum value and the reference clock.

2. The system of claim 1, wherein determination of the first frequency division coefficient according to the total line rate and the total data bit width of the transmit channels comprises: acquiring a first ratio of the total line rate to the total data bit width of the transmit channels; and determining the first frequency division coefficient according to the first ratio and the reference clock.

3. The system of claim 1, further comprising: a plurality of first transmit data conversion units and a plurality of second transmit data conversion units, and each first transmit data conversion unit and each second transmit data conversion unit corresponding to a respective one of the transmit channels; wherein, each first transmit data conversion unit is connected between the transmit transport layer unit and a respective one of the transmit channels, and each second transmit data conversion unit is connected between a respective one of the transmit channels and a respective one of the parallel-serial conversion units; each first transmit data conversion unit has, a write end connected to the transmit divider and configured to receive the first operating clock frequency transmitted by the transmit divider, and a read end connected to the data channel divider and configured to receive the second operating clock frequency transmitted by the data channel divider; and each first transmit data conversion unit is configured to convert an operating clock frequency of transmit data from the first operating clock frequency into the second operating clock frequency; and each second transmit data conversion unit has a write end connected to the data channel divider and configured to receive the second operating clock frequency transmitted by the data channel divider, and a read end connected to a respective one of the parallel-serial conversion units and configured to receive the third operating clock frequency transmitted by the respective one of the parallel-serial conversion units, and each second transmit data conversion unit is configured to convert a bit width of the transmit data, and / or convert an operating clock frequency of the transmit data from the second operating clock frequency into the third operating clock frequency.

4. The system of claim 3, wherein each transmit channel comprises a transmit link layer unit and a transmit data logic processing unit; the transmit link layer unit is connected between a respective one of the first transmit data conversion units and a respective one of the transmit data logic processing units; and the transmit data logic processing unit is connected between the transmit link layer unit and a respective one of the second transmit data conversion units; and the data channel divider is configured to provide the second operating clock frequency to the transmit link layer unit and the transmit data logic processing unit of each transmit channel.

5. The system of claim 4, wherein the transmit link layer unit is configured to encode the transmit data, and the transmit data logic processing unit is configured to frame and scramble the encoded transmit data.

6. The system of claim 1, wherein the clock management unit (23) further comprises a receive divider; the communication circuit (22) comprises a receive data processing unit, a receive transport layer unit, a plurality of receive channels, and a plurality of serial-parallel conversion units; wherein each receive channel corresponds to a respective one of the serial-parallel conversion units; the receive divider is connected to the PLL circuit, the receive data processing unit, and the receive transport layer unit; the data channel divider is connected to each of the plurality of receive channels; and each receive channel is connected to a respective one of the serial-parallel conversion units; the configuration unit (21) is configured to configure a line rate and a data bit width for each receive channel, determine a third frequency division coefficient according to a total line rate and a total data bit width of the receive channels, and set the third frequency division coefficient into the receive divider; the PLL circuit is configured to transmit the reference clock to the receive divider; the receive divider is configured to determine a fourth operating clock frequency according to the reference clock and the third frequency division coefficient, and provide the fourth operating clock frequency to the receive data processing unit and the receive transport layer unit; the data channel divider is further configured to provide the second operating clock frequency to each of the plurality of transmit channels; and each of the plurality of serial-parallel conversion units is connected to the clock generation circuit (10) and is configured to receive the reference clock, and generate, according to the reference clock, a fifth operating clock frequency for each serial-parallel conversion unit.

7. The system of claim 6, wherein determination of the third frequency division coefficient according to the total line rate and the total data bit width of the receive channels comprises: acquiring a second ratio of the total line rate to the total data bit width of the receive channels; and determining the third frequency division coefficient according to the second ratio and the reference clock.

8. The system of claim 6, wherein determination of the second frequency division coefficient comprises: acquiring a maximum value of the ratio of the line rate to the data bit width among the transmit channels and / or among the receive channels; and determining the second frequency division coefficient according to the maximum value and the reference clock.

9. The system of claim 6, further comprising: a plurality of first receive data conversion units and a plurality of second receive data conversion units; and each first receive data conversion unit and each second receive data conversion unit corresponding to a respective one of the receive channels; wherein, each first receive data conversion unit is connected between the receive transport layer unit and a respective one of the receive channels, and each second receive data conversion unit is connected between a respective one of the receive channels and a respective one of the parallel-serial conversion units; each first receive data conversion unit has, a read end connected to the receive divider and configured to receive the fourth operating clock frequency transmitted by the receive divider, and a write end connected to the data channel divider and configured to receive the second operating clock frequency transmitted by the data channel divider; and each first receive data conversion unit is configured to convert an operating clock frequency of receive data from the second operating clock frequency into the fourth operating clock frequency; and each second receive data conversion unit has, a read end connected to the data channel divider and configured to receive the second operating clock frequency transmitted by the data channel divider, and a write end connected to a respective one of the serial-parallel conversion units and configured to receive the fifth operating clock frequency transmitted by the respective one of the serial-parallel conversion units; and each second receive data conversion unit is configured to convert a bit width of the receive data, and / or convert an operating clock frequency of the receive data from the fifth operating clock frequency into the second operating clock frequency.

10. The system of claim 9, wherein each receive channel comprises a receive link layer unit and a receive data logic processing unit; the receive link layer unit is connected between a respective one of the first receive data conversion units and the receive data logic processing unit, and the receive data logic processing unit is connected between the receive link layer unit and a respective one of the second receive data conversion units; and the data channel divider is configured to provide the second operating clock frequency to the receive link layer unit and the receive data logic processing unit of each receive channel.

11. The system of claim 10, wherein the receive link layer unit is configured to decode the receive data; and the receive data logic processing unit is configured to deframe and descramble the encoded receive data.

12. A clock generation method, performed by the system of any one of claims 1 to 11, comprising: receiving (S310) a reference clock, and acquiring a configured line rate and a configured data bit width for data transmission; determining (S320) a clock frequency division coefficient according to the line rate and the data bit width; determining (S330) an operating clock frequency according to the clock frequency division coefficient and the reference clock; and providing (S340) the operating clock frequency to the communication module (20).