A processing method of SOC chip IP clock in DFT

Abstract

The application relates to the field of power terminal chips, in particular to a processing method of an SOC chip IP clock in DFT, which comprises comprehensive setting, logical processing methods, comprehensive testing and IP clock embedding DFT; first, the entire SOC chip interior is set, then the time in the IP clock interior is corresponded to the SOC chip interior to record and scan the SOC chip interior state and is sent to the exterior to record; second, the entire SOC interior operation condition is recorded, the operation condition is modified to the existing condition through an external controller, the operation result is output in combination with the external operation condition, scanning is carried out, and the next step comprehensive testing is transmitted; third, the SOC chip is combined with the IP clock to carry out inverse operation, the clock source supply of each sub-module in the chip interior and the working frequency of the system are dynamically managed according to different applications of the chip, so that the overall power consumption of the chip is reduced, and the WATCHDOG is serviced through software intervals.

Description

A method for processing SOC chip IP clock in DFT Technical Field

[0001] This invention relates to the field of power terminal chips, specifically to a method for processing the IP clock of a SOC chip in DFT. Background Technology

[0002] With the development of science and technology and the improvement of economic level, users are placing increasingly higher demands on the quality, reliability, stability, and economy of electricity. Especially since my country has joined the WTO, the power industry will face international competition. Those who fail to improve the quality of their power systems will be eliminated by the market; therefore, the intelligentization of power systems is essential.

[0003] SoC chips offer advantages such as high integration, powerful system functions, small size, low power consumption, strong electromagnetic interference resistance, high reliability, and low cost, making them widely used in the field of power terminal chips, especially in the formation of power measurement or control systems. However, in DFT design with high test coverage, clocks of the same frequency are often connected together, which may lead to IP clock synchronization issues and cause inconvenience for later maintenance. Summary of the Invention

[0004] The purpose of this invention is to provide a method for processing the IP clock of a SOC chip in DFT, so as to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A method for processing the IP clock of a SOC chip in DFT, including comprehensive settings, logic processing methods, comprehensive testing, and embedding the IP clock into DFT;

[0007] The first step is to configure the entire SOC chip internally, and then record the time inside the SOC chip by mapping the time inside the IP clock, and scan the internal state of the SOC chip and send it to the outside for recording.

[0008] The second step is to record the internal operation conditions of the entire SOC, modify the operation conditions to the existing conditions through the external controller, combine them with the external operation conditions, output the operation results, scan them, and transmit them to the next step of comprehensive testing.

[0009] The third step is to combine the SOC chip with the IP clock to perform inverse operations. By dynamically managing the clock source supply of each sub-module inside the chip and the operating frequency of the system according to different applications of the chip, the overall power consumption of the chip is reduced and a guarantee measure to prevent system failure is taken. The WATCHDOG is serviced by software at intervals to ensure that the system works normally.

[0010] The fourth step is to embed the IP clock into the DFT. Through the functions of RAM and ROM, the IP clock is combined with the DFT. The information of the IP clock is sent to the inside of the DFT through the external IP, so that the DFT and the IP clock are synchronized.

[0011] Preferably, the internal DDR of the IP clock transmits data using both the rising and falling edges of the clock, and the frequency of the DDR chip clock pin is half of the transmission frequency.

[0012] Preferably, the peripheral device requests a signal from the DMA controller via a transfer request within the SOC chip, and then requests a bus from the CPU, using the system bus to complete the data transfer between the peripheral device and the memory.

[0013] Preferably, the data generated inside the SOC chip is sent to the external RAM for storage, and then transmitted via DMAC.

[0014] Preferably, the SOC chip is connected to other circuits. Using the layout and routing tools in EDA, the internal circuit diagram of the SOC chip is generated and sent to the ROM for storage.

[0015] Preferably, the maximum SOC output power is +5dBm.

[0016] Preferably, AD acquisition is achieved by interrupting DMA after AD acquisition is completed, and then the signal time is synchronized with the internal time of the SOC through the IP clock.

[0017] Compared with the prior art, the beneficial effects of the present invention are:

[0018] This invention discloses a method for processing the IP clock of a SOC chip in the DFT. The IP clock is embedded in the DFT. Through the functions of RAM and ROM, the IP clock is combined with the DFT. The IP clock information is sent to the inside of the DFT through the external IP, so that the DFT and the IP clock are synchronized, which facilitates maintenance. Detailed Implementation

[0019] The technical solutions in the embodiments of the present invention have been clearly and completely described. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] The present invention provides a technical solution:

[0021] A method for processing the IP clock of a SOC chip in DFT, including comprehensive settings, logic processing methods, comprehensive testing, and embedding the IP clock into DFT;

[0022] The first step is to configure the entire SOC chip internally, and then record the time inside the SOC chip by mapping the time inside the IP clock, and scan the internal state of the SOC chip and send it to the outside for recording.

[0023] The second step is to record the internal operation conditions of the entire SOC, modify the operation conditions to the existing conditions through the external controller, combine them with the external operation conditions, output the operation results, scan them, and transmit them to the next step of comprehensive testing.

[0024] The third step is to combine the SOC chip with the IP clock to perform inverse operations. By dynamically managing the clock source supply of each sub-module inside the chip and the operating frequency of the system according to different applications of the chip, the overall power consumption of the chip is reduced and a guarantee measure to prevent system failure is taken. The WATCHDOG is serviced by software at intervals to ensure that the system works normally.

[0025] The fourth step is to embed the IP clock into the DFT. Through the functions of RAM and ROM, the IP clock is combined with the DFT. The information of the IP clock is sent to the inside of the DFT through the external IP, so that the DFT and the IP clock are synchronized.

[0026] Preferably, the internal DDR of the IP clock transmits data using both the rising and falling edges of the clock, and the frequency of the DDR chip clock pin is half of the transmission frequency.

[0027] Preferably, the peripheral device requests a signal from the DMA controller via a transfer request within the SOC chip, and then requests a bus from the CPU, using the system bus to complete the data transfer between the peripheral device and the memory.

[0028] Preferably, the data generated inside the SOC chip is sent to the external RAM for storage, and then transmitted via DMAC.

[0029] Preferably, the SOC chip is connected to other circuits. Using the layout and routing tools in EDA, the internal circuit diagram of the SOC chip is generated and sent to the ROM for storage.

[0030] Preferably, the maximum SOC output power is +5dBm.

[0031] Preferably, AD acquisition is achieved by interrupting DMA after AD acquisition is completed, and then the signal time is synchronized with the internal time of the SOC through the IP clock.

[0032] In this embodiment, a method for processing the IP clock of a SOC chip in DFT is used. The internal DDR of the IP clock transmits data using both the rising and falling edges of the clock. The frequency of the DDR chip clock pin is half the transmission frequency. Through a transmission request within the SOC chip, the peripheral device requests a signal from the DMA controller, then requests a bus from the CPU. The system bus is used to complete the data transfer between the peripheral device and the memory. Data generated within the SOC chip is sent to the external RAM for storage, and then transmitted via DMAC. The SOC chip connects to other circuits. Using placement and routing tools in EDA, the internal circuit diagram of the SOC chip is generated and sent to the ROM for storage. The maximum SOC output power is +5dBm. After AD acquisition is completed, an interrupt triggers DMA to achieve AD acquisition. The signal time is then synchronized with the internal SOC time using the IP clock.

[0033] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for processing the IP clock of a SOC chip in DFT, comprising comprehensive setup, logical processing, comprehensive testing, and embedding the IP clock into DFT; the first step, comprehensive setup, involves setting up the entire SOC chip internally, then recording the internal state of the SOC chip by mapping the time within the IP clock, and scanning the internal state of the SOC chip to the external system for recording; the second step, logical processing, involves recording the internal operation conditions of the entire SOC chip, modifying the operation conditions through an external controller to combine existing conditions with external operation conditions, outputting the operation result, and scanning; the third step, comprehensive testing, involves combining the SOC chip with the IP clock to perform inverse operations, dynamically managing the clock source supply of each sub-module within the chip and the system operating frequency according to different applications, thereby reducing the overall power consumption of the chip and preventing system failure as a safeguard measure, and providing intermittent WATCHDOG service through software to ensure normal system operation; the fourth step... The IP clock is embedded in the DFT. Through the functions of RAM and ROM, the IP clock and DFT are combined. The IP clock information is sent to the internal DFT through the external IP, so that the DFT and IP clock are synchronized. The DDR chip inside the IP clock transmits data on both the rising and falling edges of the clock. Through the transfer request inside the SOC chip, the peripheral requests a signal to the DMA controller, and then requests the bus from the CPU. The system bus is used to complete the data transfer between the peripheral and the memory. The data generated inside the SOC chip is sent to the internal RAM for storage, and then transferred through the DMA controller. The SOC chip is connected to other circuits. With the help of the placement and routing tools in EDA, the internal circuit diagram of the SOC chip is generated and sent to the internal ROM for storage. After the AD acquisition is completed, the DMA controller is triggered by the interrupt to complete the AD sampling. Then, the signal time is synchronized with the internal time of the SOC chip through the IP clock.

2. The method for processing the SOC chip IP clock in DFT according to claim 1, characterized in that: The clock pin frequency of a DDR chip is half the transmission frequency.

3. The method for processing the SOC chip IP clock in DFT according to claim 1, characterized in that: The maximum output power of the SOC chip is +5dBm.