DETECTION AND MEASURING UNIT FOR THE DETECTION OF ELECTROMAGNETIC INTERFERENCES, DETECTION SYSTEM WITH SUCH AN ANALYSIS UNIT AND ANALYSIS METHOD

Description

technical field

[0001] The invention relates to the field of electromagnetic disturbance detection in order to prevent the harmful consequences of such electromagnetic disturbance.

[0002] The invention relates more specifically to a detection and measurement unit for the detection of electromagnetic disturbances, a system for detecting such electromagnetic disturbances, and a method for detection and measurement. Prior state of the art

[0003] Electromagnetic disturbance detection systems, or electromagnetic pulse detection systems, are designed to monitor civilian or military installations against various intentional electromagnetic stresses over a wide frequency band, such as ultra-wideband (ULB) electromagnetic waves. Such systems include, as illustrated in the figure 1 : an ultra-wideband signal detection device comprising one or more antennas 10, the detection device being able to be equipped with a limiter to protect downstream electronic components, a processing and digitization unit 20 of the electromagnetic signal received by the detection device adapted to provide from the electromagnetic signal at least one digital signal representative of the envelope of the received electromagnetic signal in at least one given frequency band, a detection and measurement unit 30 configured to receive the at least one representative digital signal provided by the processing unit and to identify and measure the electromagnetic pulses, an analysis unit 40 for analyzing the measurements provided by the detection and measurement unit.

[0004] In a typical configuration of electromagnetic interference detection systems, the detection and measurement unit 30 is generally provided by means of a digital processing architecture based on the acquisition of representative digital signal(s) and, after a storage step, data processing to detect and measure electromagnetic pulses within the stored data. This type of configuration corresponds in particular to that implemented using digital oscilloscopes and other data acquisition cards.

[0005] However, such acquisitions require a relatively large amount of storage memory. Indeed, if we start with a sampling frequency of 100 MHz and a signal with a relatively low repetition rate, thus requiring an acquisition time of 3 seconds, we need to store 300 million samples, which, for values ​​coded in 8 bits, means a memory of 300 MB.

[0006] Therefore, for such a typical configuration, the detection and analysis units are relatively complex and require a relatively large storage capacity.

[0007] To simplify these detection and analysis units, some documents, such as US document 2017 / 0212161, propose using a simplified electromagnetic pulse detection method based on comparing the representative digital signal provided by the ultra-wideband signal detection device with a simple threshold. While such a simplified detection method opens the possibility of simpler real-time detection and analysis units, it is nonetheless unsatisfactory. Indeed, such a solution for discriminating electromagnetic pulses is unreliable and can lead to false positives or result in poorer detection accuracy.

[0008] Thus, there is currently no detection and measurement unit that allows simple, fast and reliable detection and measurement of electromagnetic pulses, particularly to allow real-time analysis of the representative digital signal.

[0009] We also know, from US document 2014 / 080417 A1, of an EHF communication device based on EHF signal detection on the basis of hysteresis and, from US document 5 514 987 A, of a regenerative comparator in the form of a digital circuit. Description of the invention

[0010] The invention aims to overcome the drawbacks listed above and thus provides a detection and measurement unit that enables simpler and faster detection and measurement of electromagnetic pulses than that implemented by prior art detection and measurement units, while also being relatively inexpensive to implement. To this end, the invention is defined by the claims.

[0011] The invention relates to a detection and measurement unit for detecting electromagnetic disturbances, the detection and measurement unit being configured to receive a digital signal representative of the envelope of an electromagnetic signal received in a given frequency band in which an electromagnetic disturbance is likely to occur, the detection and measurement unit comprising: a detection subunit configured to compare the amplitude of the representative digital signal with a first trigger threshold and a second stop threshold, the second stop threshold corresponding to an amplitude lower than that corresponding to the first trigger threshold, the detection subunit being further configured to detect an electromagnetic pulse at each detection of the passage of the amplitude of the representative digital signal through the second stop threshold on the falling edge after the amplitude of the representative digital signal has passed through the first trigger threshold on the rising edge.

[0012] The detection and measurement unit includes a programmable logic circuit which has been pre-programmed to act as a detection subunit, the programmable logic circuit being preferably a complex programmable logic circuit, better known by the English acronym CPLD.

[0013] Such a unit provides simple electromagnetic pulse detection, since it is based on a simple amplitude comparison with threshold values, while remaining reliable due to the use of a dual threshold instead of a single threshold, which can be the source of problems, as will be discussed in relation to the... Figures 3A and 3B This involves either detecting false positives (tripled pulses in the example provided) in the case of a threshold that is too low, or detecting pulses that are too weak (only the pulses with the highest amplitudes are then detected). Thus, such simplification and reliability of detection allows the development of detection units capable of operating in real time without requiring significant storage for post-processing of the representative digital signal.

[0014] Moreover, with such simplicity the invention is implemented from a simple circuit of the type programmable logic circuit and allows reliable detection and measurement of electromagnetic pulses at low cost.

[0015] The detection and measurement unit may further include a pulse / s time duration measurement subunit in communication with the detection subunit, the pulse / s time duration measurement subunit being configured to measure the pulse / s duration between the passages through the amplitude of the digital signal representing the first rising edge trigger threshold and the passage through the second falling edge stop threshold.

[0016] In this way, the detection and measurement unit is able to determine the duration of electromagnetic pulses from the pulse / s time measurement subunit by simply monitoring the output of the detection subunit.

[0017] The detection subunit may include: a first comparator adapted to compare the amplitude of the representative digital signal with the first trigger threshold, the first comparator having a first state when the amplitude of the representative digital signal is less than, or even less than or equal to, the first trigger threshold and a second state otherwise; a second comparator adapted to compare the amplitude of the representative digital signal with the second stop threshold, the second comparator having a third state when the amplitude of the representative digital signal is greater than, or even greater than or equal to, the second stop threshold and a fourth state otherwise. a first flip-flop having a first flip-flop input connected to the first comparator and a second flip-flop input connected to the second comparator, the first flip-flop being configured to switch from a fifth state to a sixth state when the first comparator presents the second state, and to switch from the sixth state to the fifth state when the second comparator presents the fourth state, a pulse counter connected to an output of the first flip-flop and configured to count one pulse each time the first flip-flop switches from a state chosen from the sixth state and the fifth state to the other state from the sixth state and the fifth state.

[0018] This functional configuration of the detection subunit makes it possible to provide such a detection subunit using a simple logic circuit, thus allowing, for example, its programming via a programmable logic circuit. Furthermore, given the simplicity of the logic circuit, this functional configuration permits the use of programmable logic circuits.

[0019] It should also be noted that by "counting one pulse each time the first flip-flop passes from a state chosen from the sixth state and the fifth state to the other state from the sixth state and the fifth state", it must be understood that there is the counting of one pulse: either only when transitioning from the fifth state to the sixth state, with the fifth state then being the chosen state, or only when transitioning from the sixth state to the fifth state, with the sixth state then being the chosen state.

[0020] It should be noted that, by analogy, in the rest of this document, each time a state is chosen from among two states for a passage from said chosen state to the other state (therefore not chosen), the condition is fulfilled only during the passage from the chosen state to the other state, the chosen state being a predefined data.

[0021] The subunit of measurement for pulse duration (in pulses / seconds) may include: a first clock configured to alternately present a seventh state and an eighth state with a predefined alternation frequency, a first logic gate presenting a first gate input connected to an output of the first flip-flop and a second gate input connected to the first clock, the first logic gate being configured to present a ninth state when the first flip-flop presents the sixth state and when the clock presents the seventh state, the first logic gate presenting a tenth state the rest of the time, a pulse duration / s counter connected to an output of the first logic gate and configured to count one first clock pulse each time the first logic gate presents the ninth state, the number of alternations counted corresponding to the pulse duration / s.

[0022] In the same way as the detection subunit, such a functional configuration of the pulse time duration measurement subunit / s offers the possibility of providing such a pulse time duration measurement subunit / s from a simple logic circuit and thus allows, for example, to be able to program it from a programmable logic circuit.

[0023] The detection and measurement unit may further include a maximum pulse amplitude measurement subunit capable of measuring a maximum amplitude level reached by the representative digital signal.

[0024] In this way, it is possible to obtain information on the amplitude of the electromagnetic pulses detected during the measurement period considered.

[0025] The maximum pulse amplitude measurement subunit may comprise a plurality of comparison sets, each comprising a third comparator and its respective flip-flop.

[0026] the third comparator of each comparator set being adapted to compare the amplitude of the representative digital signal with a respective third trigger threshold which is distinct from the third thresholds of the other third comparators, said third comparator having an eleventh state when the amplitude of the representative digital signal is less than, or even less than or equal to, the corresponding third trigger threshold and a twelfth state otherwise,

[0027] the third flip-flop of each comparison set having a third flip-flop input connected to the third comparator of said comparison set, said third flip-flop being configured to switch from a thirteenth state to a fourteenth state when the third comparator of said comparison set is in the twelfth state,

[0028] the comparison sets being configured so that the third trigger thresholds of the third comparators are spread over a range of amplitudes expected for the representative digital signal.

[0029] Such a functional configuration of the maximum pulse amplitude measurement subunit offers the possibility of providing such a subunit from a simple logic circuit and thus allows, for example, to be programmed from a programmable logic circuit.

[0030] The detection and measurement unit may include a subunit of measurement of a repetition period of electromagnetic pulses.

[0031] Such a subunit of period measurement makes it possible to estimate a repetition frequency of these electromagnetic pulses and thus better identify the risks associated with these electromagnetic pulses.

[0032] The subunit of measurement for the repetition frequency of electromagnetic pulses may include: a frequency divider configured to switch between a fifteenth and sixteenth state each time the first flip-flop transitions to a given state among the fifth and sixth states, a double-period counter connected to an output of the frequency divider and configured to count one double period each time the frequency divider transitions from a state chosen among the fifteenth and sixteenth states to the other state among the fifteenth and sixteenth states, a second clock configured to alternately display a seventeenth and eighteenth state with a second predefined alternation frequency, a second logic gate having a third gate input connected to an output of the frequency divider and a fourth gate input connected to the second clock,the second logic gate being configured to present a nineteenth state when the frequency divider is in the fifteenth state and when the second clock is in the seventeenth state, the logic gate being in a twentieth state the rest of the time, a period timer connected to an output of the second logic gate and configured to count one pulse of the second clock each time the frequency divider transitions from one state chosen from the fifteenth state and the sixteenth state to the other state chosen from the fifteenth state and the sixteenth state.

[0033] Such a functional configuration of the electromagnetic pulse repetition frequency measurement subunit offers, in the same way as other subunits, the possibility of providing such a subunit from a simple logic circuit and thus allows, for example, to be able to program it from a programmable logic circuit.

[0034] The detection and measurement unit may include a buffer configured to retrieve the period duration counter at each transition of the frequency divider from the sixteenth state to the fifteenth state.

[0035] The detection subunit can be configured to receive a zeroing signal and, upon receiving this zeroing signal, to provide a number of electromagnetic pulses detected since a previous zeroing and to reset a count of the number of electromagnetic pulses to zero.

[0036] The detection subunit, the pulse duration / s measurement subunit, the maximum pulse amplitude measurement subunit, and the electromagnetic pulse repetition period measurement subunit can be configured to receive a zeroing signal and to perform the following actions upon receiving this zeroing signal: a supply of respectively a number of electromagnetic pulses detected, a pulse time duration / s, a maximum measured pulse amplitude, and a repetition period of electromagnetic pulses measured since a previous zeroing and resetting of a count of the number of electromagnetic pulses.

[0037] The invention further relates to an electromagnetic disturbance detection system comprising: an electromagnetic signal receiving unit configured to receive at least a portion of the electromagnetic radiation to which the detection system is subjected in the form of an electromagnetic signal received in a given frequency band and to provide a digital signal representative of the envelope of said electromagnetic signal, a detection and measurement unit as defined above.

[0038] Such a detection system has the advantages associated with the detection and measurement unit according to the invention that it comprises.

[0039] The invention further relates to an analysis method for detecting electromagnetic disturbances implemented using a detection and measurement unit as defined above, the method comprising the steps of: reception of a digital signal representative of the envelope of an electromagnetic signal received in a given frequency band in which an electromagnetic disturbance is likely to appear, comparison of the amplitude of the representative digital signal with a first trigger threshold and a second stop threshold, the second stop threshold corresponding to an amplitude lower than that corresponding to the first trigger threshold, detection of an electromagnetic pulse at each detection of the passage of the amplitude of the representative digital signal through the second threshold on the falling edge after the amplitude of the representative digital signal has passed through the first threshold on the rising edge.

[0040] Such a process can be implemented with a detection and measurement unit according to the invention and thus benefit from the advantages associated with it.

[0041] The analysis process for detecting electromagnetic disturbances may further include the following steps: provision of a first clock signal having a first predefined alternation frequency, modulation of the first clock signal with an electromagnetic pulse detection signal provided during the electromagnetic pulse detection step, counting the number of clock signals remaining after modulation with the electromagnetic pulse detection signal.

[0042] Such a method allows for a simple measurement of the duration of electromagnetic pulses. Brief description of the drawings

[0043] The present invention will be better understood upon reading the description of exemplary embodiments, given purely for illustrative purposes and in no way limiting, with reference to the attached drawings in which: There figure 1illustrates the main elements of an electromagnetic disturbance detection system, whether prior art or according to the invention. figure 2 illustrates a functional diagram of an electromagnetic disturbance detection and measurement unit according to the invention, The figure 3A illustrates the principle of electromagnetic pulse detection implemented in prior art processes, The figure 3B illustrates the principle of electromagnetic pulse detection based on the use of two threshold values ​​according to the invention, The figure 4 illustrates the principle of determining the duration of electromagnetic pulses implemented within the framework of the invention, The figure 5 illustrates a functional diagram of a subunit for measuring the repetition period of electromagnetic pulses according to a second embodiment of the invention, The figure 6graphically illustrates the principle of measuring the repetition frequency of electromagnetic pulses as implemented in the second embodiment of the invention.

[0044] Identical, similar or equivalent parts of the different figures carry the same numerical references in order to facilitate the transition from one figure to another.

[0045] The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more legible.

[0046] The different possibilities (variants and modes of implementation) should be understood as not being mutually exclusive and can be combined with each other. Description of the implementation methods

[0047] There figure 1illustrates the main elements of an electromagnetic disturbance detection system, whether prior art or according to the invention, used for the detection of electromagnetic disturbances.

[0048] Thus, such a detection system 1 comprises: an ultra-wideband signal detection device comprising one or more antennas 10, the detection device being able to be equipped with a limiter to protect the downstream electronic components, a processing and digitization unit 20 of the electromagnetic signal received by the detection device adapted to provide from the electromagnetic signal at least one digital signal representative of the envelope of the received electromagnetic signal in at least one given frequency band, a detection and measurement unit 30 configured to receive the at least one representative digital signal provided by the processing unit and to identify and measure the electromagnetic pulses, an analysis unit 40 for analyzing the measurements provided by the detection and measurement unit.

[0049] The ultra-wideband signal detection device 10 and the processing and digitization unit 20 according to the first embodiment of the invention may conform to those implemented in the prior art. In particular, the ultra-wideband signal detection device 10 and the processing and digitization unit 20 may conform to the teaching of document EP 3157181 B1.

[0050] It should be noted that, according to a standard configuration used in the prior art, and in particular in document EP 3157181 B1, the processing and digitization unit 20 is adapted to provide several digital signals representative of the envelope of the received electromagnetic signal in distinct frequency bands, and the detection system 1 comprises, for each frequency band, a separate detection and measurement unit 30 adapted to process the representative digital signal corresponding to said frequency band. Thus, although, for the sake of simplicity, only a single detection and measurement unit is described below, it is perfectly conceivable, without departing from the scope of the invention, that the detection system 1 comprises a plurality of detection and measurement units 30.

[0051] In accordance with the figure 2 According to the invention, the detection and measurement unit 30 comprises: a detection subunit 310 configured to compare the amplitude of the representative digital signal 501, such as that illustrated on the Figures 3A and 3Bwith a first trigger threshold S1 and a second stop threshold S2, the second stop threshold S2 corresponding to an amplitude lower than that corresponding to the first trigger threshold S1, the detection subunit 310 being further configured to detect an electromagnetic pulse at each detection of the passage of the amplitude of the representative digital signal through the second stop threshold S2 on the falling edge after the amplitude of the representative digital signal has passed through the first trigger threshold S1 on the rising edge, a pulse / s time measurement subunit 320 in communication with the detection subunit 310, the pulse / s time measurement subunit 320 being configured to measure the pulse / s duration between the passages of the amplitude of the representative digital signal 501 through the first trigger threshold S1 on the rising edge and the passage of the second stop threshold S2 on the falling edge,a maximum pulse amplitude measurement subunit 330 capable of measuring the maximum amplitude level reached by the representative digital signal 501, an interface subunit 340 to interface between the other subunits 310, 320, 330 of the detection and measurement unit 30 and the analysis unit 40.

[0052] According to a particularly advantageous embodiment of the invention, such a detection and measurement unit 30 may comprise a programmable logic circuit (not shown) that has been pre-programmed to function as at least some, or even all, of the subunits 310, 320, 330, 340 of the detection and measurement unit 30. The programmable logic circuit is preferably a complex programmable logic circuit (CPLD). According to this embodiment, the programmable logic circuit has sub-parts, each programmed to function as a respective subunit 310, 320, 330, 340 of the detection and measurement unit 30.Of course, in the case where the system includes a plurality of detection and measurement units 30, these can share a single programmable logic circuit to provide all or part of the subunits 310, 320, 330, 340 of these detection and measurement units 30 or each include their respective programmable logic circuit or even a partial sharing of the programmable logic circuits between the detection and measurement units 30.

[0053] Such a possibility is made possible by decomposing each of the subunits into a programmable logic function in such a programmable logic circuit.

[0054] Thus, according to such a functional decomposition and as shown by the figure 2 The 310 detection subunit may include: a first comparator 311 adapted to compare the amplitude of the representative digital signal 501 with the first trigger threshold S1, the first comparator 311 having state 0, as a first state E1, when the amplitude of the representative digital signal is less than, or even less than or equal to, the first trigger threshold S1 and a state 1, as a second state E2, otherwise, a second comparator 312 adapted to compare the amplitude of the representative digital signal 501 with the second stop threshold S2, the second comparator 312 having a state 0, as a third state E3, when the amplitude of the representative digital signal is greater than, or even greater than or equal to, the second stop threshold S2 and a state 1, as a fourth state E4, otherwise,a first flip-flop 314 having a first flip-flop input connected to the first comparator 311 and a second flip-flop input connected to the second comparator 312, the first flip-flop 314 being configured to transition from state 0, as fifth state E5, to state 1, as sixth state E6, when the first comparator is in state 1 (i.e., second state E2), and to transition from state 1 to state 0 when the second comparator 312 is in state 1 (i.e., fourth state E4), a pulse counter 316 connected to an output of the first flip-flop 314 and configured to count one pulse each time the first flip-flop 314 transitions from a state chosen from state 1, i.e., sixth state E6, and state 0, i.e., fifth state E5, to the other state 1 (E6) and state 0 (E5). ,

[0055] Note that the pulse counter 316 presents, as illustrated on the figure 2, a reset input connected to the analysis unit such that when the analysis unit transmits a reset signal, the pulse counter 316 transmits the number of electromagnetic pulses counted since the last reset to the interface subunit 340 and the number of electromagnetic pulses is reset to zero.

[0056] Interface subunit 340 is then configured to provide the number of pulses detected to analysis unit 40.

[0057] Thus, with simple logic functions accessible via a programmable logic circuit, reliable detection can be achieved, unlike the methods used in the prior art. Such reliability is demonstrated on the Figures 3A and 3B , there figure 3A illustrating the risks of "false positive" detection inherent in the use of a single threshold S'1, the figure 3B illustrating the benefits of using two thresholds S1, S2.

[0058] Indeed, we can see, on the figure 3A An electromagnetic pulse can exhibit erratic amplitude variations, potentially leading to the detection of multiple pulses (here, three pulses shown in curve 510') when only one should actually be detected, as illustrated in curve 510. In the case of this invention, the use of a first detection threshold S1 and a second stopping threshold S2, with the second stopping threshold S2 corresponding to an amplitude lower than that of the first detection threshold S1, avoids this problem. Indeed, the relatively high first detection threshold allows the system to wait until the pulse reaches a sufficiently large amplitude, while the second stopping threshold ensures that the pulse has fully terminated before detection.

[0059] In the context of counting the number of pulses, in order to allow good autonomy to the detection system 1, the pulse counter 316 is a 24-bit counter, that is to say adapted to count a number of electromagnetic pulses that can go up to a little more than 16.7 million electromagnetic pulses.

[0060] Similarly, it is possible to provide the subunit of measurement for pulse duration / s 320 according to such a functional decomposition. According to this possibility, the subunit of measurement for pulse duration / s 320 comprises: a first clock 321 configured to alternately display a state 1, as the seventh state, and a state 0, as the eighth state E8, with a predefined alternation frequency; a first logic gate 323, having a first gate input connected to an output of the first flip-flop 314 and a second gate input connected to the first clock 321; the first logic gate being an AND gate and thus configured to display a state 1, as the ninth state E9, when the first flip-flop is in state 1 and when the first clock 321 is in state 1; the first logic gate 323 displaying a state 0, as the tenth state E10, the rest of the time; a pulse duration / s counter 325 connected to an output of the first logic gate 323 and configured to count one first clock pulse each time the logic gate 323 is in state 1, i.e., the ninth state E9,the number of counted alternations corresponding to the pulse duration / s.

[0061] The counting principle implemented by the pulse / s time duration measurement subunit 320 is illustrated by the figure 4The first graph illustrates, with curve 510, the output signal of the first flip-flop. A transition to 1 corresponds to the detection of an electromagnetic pulse, and a state 0 corresponds to the absence of an electromagnetic pulse. The second graph illustrates the output 512 of the first clock 321, which alternates between states 1 and 0 at a given frequency. Each alternation corresponds to one beat of the first clock 21. The first logic gate 323 combines these signals to provide the clock beats corresponding to the detection of electromagnetic pulses, as shown in the third graph with curve 514. In this way, the pulse duration counter 325 can count the number of clock beats corresponding to the detection of electromagnetic pulses.This number of beats multiplied by the period of the first clock t clk allows us to directly determine the duration of the electromagnetic pulses between two interrogations.

[0062] Indeed, the pulse duration counter / s 325 is, like the pulse counter 316, equipped with a reset input connected to the analysis unit 40 in such a way that when the analysis unit transmits a reset signal, the pulse duration counter / s 316 transmits the number of beats of the first clock 321 counted since the last reset to the interface subunit 340 and resets the number of beats of the first clock 321 counted.

[0063] The interface subunit 340 is then configured to provide the number of beats of the first clock 321 counted to the analysis unit 40, which can itself determine, from this value and the number of pulses provided by the detection subunit 310, an average pulse duration. Such a determination can be made using the following equation: τ pulse = N clk . t clk N imp

[0064] With N imp the number of electromagnetic pulses provided by the pulse counter 316, t clk the clock period; N clk the number of clock beats provided by the pulse duration / s counter 325 and τ pulse the calculated average pulse duration.

[0065] It should be noted that the frequency of the first clock is chosen based on the expected average duration of the electromagnetic pulses and the desired time resolution. In this case, the inventors have chosen a frequency of 100 MHz, corresponding to a resolution of 10 ns. Of course, this value is provided only as an example, and other frequencies are perfectly conceivable, such as a frequency between 1 MHz and 500 MHz, without departing from the scope of the invention.

[0066] To ensure a certain autonomy for the detection and measurement unit, the pulse duration counter / s 325 can be a 32-bit counter, i.e., capable of measuring more than 4.29 billion clock pulses.

[0067] Similarly to the detection subunits and pulse duration / s measurement subunit 320, the maximum pulse amplitude measurement subunit 330 can also be provided according to such a functional decomposition. According to this possibility, the maximum pulse amplitude measurement subunit 330 can comprise a plurality of comparator sets, not shown, each comprising a third comparator and its respective flip-flop.

[0068] The third comparator of each comparator set is adapted to compare the amplitude of the representative digital signal with a respective third trigger threshold which is distinct from the third trigger thresholds of the other third comparators, said third comparator having a state 0, as the eleventh state, when the amplitude of the representative digital signal is less than, or even less than or equal to, the corresponding third trigger threshold and one being 1, as the twelfth state, otherwise.

[0069] The third flip-flop of each comparison set having a third flip-flop input connected to the third comparator of said comparison set, said third flip-flop being configured to go from state 0, as the thirteenth state, to state 1, as the fourteenth state, when the third comparator of said comparison set is in state 1, i.e. the twelfth state.

[0070] The third thresholds are preferentially chosen to be distributed over a range of amplitudes expected for the representative digital signal.

[0071] Thus, between two queries, as soon as the amplitude of the representative digital signal exceeds one of the third thresholds, the corresponding third flip-flop will transition from state 0 (the thirteenth state) to state 1 (the fourteenth state), and the fact that the digital signal had an amplitude exceeding this third trigger threshold will be recorded by the state of said third flip-flop. During the reset, the state of each of the third flip-flops is transmitted to interface subunit 340 before all the third flip-flops have transitioned to state 0 (the thirteenth state).In this way, from the correspondence between the third flip-flops and the corresponding third thresholds, the analysis unit is able to determine the upper third trigger threshold that has been exceeded by the electromagnetic pulses and estimate the maximum amplitude of the electromagnetic pulses that were received between two zeroings.

[0072] With such a detection and measurement unit 30, it is therefore possible with simple logic functions to obtain good detection of electromagnetic pulses in real time and information on them including the average duration and maximum amplitude.

[0073] Such a detection and measurement unit 30 is suitable for enabling the implementation of a pulse detection and measurement process comprising the following steps: reception of a digital signal representative of the envelope of an electromagnetic signal received in a given frequency band in which an electromagnetic disturbance is likely to appear, such as that provided by the processing and digitization unit 20, comparison of the amplitude of the representative digital signal with the first trigger threshold S1 and the second stop threshold S2, the second stop threshold S2 corresponding to an amplitude lower than that corresponding to the first trigger threshold S2, detection of an electromagnetic pulse at each detection of the passage of the amplitude of the representative digital signal through the second threshold S2 on the falling edge after the amplitude of the representative digital signal has passed through the first threshold S1 on the rising edge.

[0074] Similarly, in order to determine the duration of electromagnetic pulses, the detection and measurement unit 30 is thus adapted for the implementation of a process for determining the duration of electromagnetic pulses comprising the following steps: provision of a first clock signal having a first predefined alternation frequency, modulation of the first clock signal with an electromagnetic pulse detection signal provided during the electromagnetic pulse detection step, counting the number of clock signals remaining after modulation with the electromagnetic pulse detection signal.

[0075] It can also be noted that the detection and measurement unit 30 is also adapted to allow the measurement of the maximum amplitude of electromagnetic pulses through the implementation of a process comprising the following steps: comparison of the amplitude of the representative digital signal with a plurality of third trigger thresholds distinct from each other in order to detect whether the amplitude of the digital signal reaches and / or exceeds said third trigger thresholds, the third trigger thresholds being distributed over a range of expected amplitudes for the representative digital signal, the third trigger threshold corresponding to the highest amplitude of the digital signal which has been reached / exceeded by the representative signal, said third trigger threshold corresponding to the maximum amplitude measurement.

[0076] In a second embodiment of the detection and measurement unit 30, as shown on the figure 5 , in addition include a subunit of measurement of a repetition frequency of electromagnetic pulses 350.

[0077] Thus, a detection and measurement unit 30 according to the second embodiment differs from a detection and measurement unit 30 according to the first embodiment only in that it further comprises the subunit of measurement of a repetition period of electromagnetic pulses 350.

[0078] According to the advantageous embodiment of the invention in which the detection and measurement unit 30 may include a programmable logic circuit, it is also possible within this second embodiment to provide a functional decomposition of the measurement subunit of a repetition period of electromagnetic pulses 350. According to this embodiment, the measurement subunit of a repetition period of electromagnetic pulses 350 may include, as illustrated in the figure 5 : a frequency divider 351 configured to switch between state 0, as the fifteenth state E15, and state 1, as the sixteenth state E16, at each transition of the first flip-flop 314 to a given state chosen from state 0, i.e., the fifth state E5, and state 1, i.e., the sixth state E6 (here, as will be shown in connection with the figure 6, the transition to state 1 (E6)), a double-period counter 357 connected to an output of the frequency divider 351 and configured to count one period each time the frequency divider 351 transitions from a state chosen from state 0, i.e., the fifteenth state E15, and state 1, i.e., the sixteenth state E16, to the other state from state 1 (E16) and state 0 (E15), here at each rising edge transition from state 0 (E15) to state 1 (E16), a second clock 353 configured to alternately present a state 1, as the seventeenth state E17, and a state 0 as the eighteenth state E18, this with a second predefined alternation frequency, a second logic gate 355 presenting a third gate input connected to an output of the frequency divider 351 and a fourth gate input connected to the second clock 353, the second logic gate 355 being configured to present a state 1, as the nineteenth state E19,When the frequency divider 351 is in state 1, i.e., the fifteenth state E15, and when the second clock 353 is in state 1, i.e., the seventeenth state E17, the logic gate is in state 0, as the twentieth state E20, the rest of the time, a period timer 359 connected to an output of the second logic gate 355 and configured to count one pulse of the second clock each time the frequency divider 351 transitions from a state chosen from state 0, i.e., the fifteenth state E15, and state 1, i.e., the sixteenth state E16, to the other state from state 0 (E15) and state 1 (E16).

[0079] It should be noted that, in accordance with this second embodiment and as illustrated on the figure 5The subunit for measuring a repetition period of electromagnetic pulses 350 further includes a buffer memory 358, connected to an output of the frequency divider 351 and the period duration counter 359, and which is configured to interface between the latter and the interface subunit 340. The buffer memory 358 is more precisely configured to retrieve the value of the period duration counter 359 at each transition of the output of the frequency divider 351 to the state 0, that is to say to the fifteenth state E15, ensuring, in effect, that only the complete periods of the frequency divider 351 are taken into account.

[0080] In accordance with this use of a buffer memory 358, the double period counter 357 is configured to count one period each time the frequency divider 351 goes from one state among state 1, i.e. the sixteenth state E16, to state 0, i.e. the seventeenth state E17, thus ensuring that only complete alternations are counted.

[0081] The principle of measuring the repetition period of electromagnetic pulses is illustrated by the figure 6The first graph illustrates an example of the 510 signal provided by the first flip-flop 314 for regular electromagnetic pulses. The second graph shows the output of the frequency divider 351 when it receives the 510 signal. Note that the 518 signal at the output of the frequency divider 351 corresponds, as expected, to two periods of the electromagnetic pulses. Thus, the 518 signal is in state 1 for every other period of the signal at the output of the first flip-flop 314. The third graph illustrates the 520 output of the second clock 353, which alternates between state 1 and state 0 at a second given frequency. The second logic gate 355 combines these signals to provide the clock beats corresponding to every other period of the 510 signal, which corresponds to the electromagnetic pulses, as shown in the fourth graph with curve 522.In this way, the period duration counter 359 will be able to count the number of beats of the second clock corresponding to one period out of two d. This number of beats multiplied by the period of the second clock t clk2 allows us to go directly back to the duration of the electromagnetic pulses between two interrogations.

[0082] Indeed, the period duration counter 359 and the buffer memory 358 are, like the pulse counter 316, equipped with a reset input connected to the analysis unit 40, here through the period duration counter 359 for the buffer memory, such that when the analysis unit 40 transmits a reset signal, the buffer memory 358 transmits to the interface subunit 340 the number of beats of the second clock 321 counted since the last reset for the complete alternations of the frequency divider 351 and the number of beats of the second clock 355 of the buffer memory 358 and the period duration counter 359 is reset to zero.

[0083] Similarly, the double period counter 357 is also provided with a reset input connected to the analysis unit 40 through, here, the period duration counter 359 and the buffer memory, such that when the analysis unit 40 transmits a reset signal, the double period counter 357 transmits the number of double periods counted since the last reset, these double periods preferentially consisting only of complete double periods, and the counted number of double periods in the double period counter 357 is reset to zero.

[0084] The interface subunit 340 is then configured to provide the second clock beat count N clk2 321 to the analysis unit 40, which can itself determine, from this value and the number of double periods N div provided by the double period counter 357, an average frequency of the electromagnetic pulses. Such a determination can be made using the following equation: f imp = N div N clk 2 . t clk 2

[0085] With N div the number of double periods provided by the double period counter 357, t clk2 the period of the second clock; N clk2 the number of beats of the second clock 321 counted by the period duration counter 359 and f imp the average frequency of the determined electromagnetic pulses.

[0086] It should be noted that the frequency of the second clock is chosen based on the expected frequency of the electromagnetic pulses and the desired resolution. In this case, the inventors chose a frequency of 10 MHz, which corresponds to an expected frequency of less than 10 MHz. Of course, this value is provided only as an example, and other frequencies are perfectly conceivable, such as a frequency between 10 kHz and 50 MHz, without departing from the scope of the invention.

[0087] In order to ensure a certain autonomy of the detection and measurement unit 30, the double period counter 357 can be a 32-bit counter, i.e. capable of counting more than 4.29 billion double periods and the period duration counter 359 can be a 32-bit counter, i.e. capable of measuring more than 4.29 billion second clock pulses.

[0088] It should be noted that, in both the first and second embodiments, the various functional stages of the different subunits have states arbitrarily chosen to be either 1 or 0 to facilitate reading this document. Of course, some or all of these states can be inverted without departing from the scope of the invention. Similarly, with such state inversions, for example, if the output of the first flip-flop is inverted, the first logic gate can then be of the exclusive OR type, that is, capable of transitioning to state 1 when both the first flip-flop and the first clock are in state 0.

Claims

1. Detection and measurement unit (30) for detecting electromagnetic interference, the detection and measurement unit (30) being configured to receive a digital signal representative (501) of the envelope of an electromagnetic wave received in a given frequency band, in which an electromagnetic interference is susceptible to appear, the measurement and detection unit (30) comprising: - a programmable logic circuit which was previously programmed to act as a detection subunit (310) configured to compare the amplitude of the representative digital signal (310) with a first triggering threshold (S1) and a second stopping threshold (S2), the second stopping threshold (S2) corresponding to an amplitude less than that corresponding to the first triggering threshold (S1), the detection subunit (310) being furthermore configured to detect an electromagnetic pulse on each detection of the passage of the amplitude of the digital signal through the second stopping threshold (S2) in a falling edge after the amplitude of the digital signal has passed through the first triggering threshold (S 1) in a rising edge.

2. Detection and measurement unit (30) according to claim 1, wherein the detection and measurement unit (30) further comprises a temporal pulse(s) duration measurement subunit (320) communicating with the detection subunit (310), the temporal pulse(s) duration measurement subunit (320) being configured to measure the pulse duration(s) between the passages by the amplitude of the digital signal (501) of the first triggering threshold (S 1) in a rising edge and the passage of the second stopping threshold (S2) in a falling edge.

3. Detection and measurement unit (30) according to claim 1 or 2, wherein the detection subunit (310) comprises: - a first comparator (311) adapted to compare the amplitude of the representative digital signal (501) with the first triggering threshold (S1), the first comparator (311) having a first state (E1) when the amplitude of the digital signal is less than, or is less than or equal to, the first triggering threshold (S1) and a second state (E2) otherwise, - a second comparator (312) adapted to compare the amplitude of the representative digital signal (501) with the second stopping threshold (S2), the second comparator (312) having a third state (E3) when the amplitude of the representative digital signal is greater than, or is greater than or equal to, the second stopping threshold (S2) and a fourth state (E4) otherwise, - a first latch (314) having a first latch input connected to the first comparator (311) and a second latch input connected to the second comparator (312), the first latch (314) being configured to switch from a fifth state (E5) to a sixth state (E6) when the first comparator has the second state (E2) , and to switch from the sixth state (E6) to the fifth state (E5) when the second comparator (312) has the fourth state (E4), - a pulse counter (316) connected to an output of the first latch (314) and configured to count a pulse each time the first latch (314) switches from a state chosen from the sixth state (E6) and the fifth state (E5) to the other state from the sixth state (E6) and the fifth state (E5).

4. Detection and measurement unit (30) according to claims 2 and 3, wherein the temporal pulse(s) duration measurement subunit (320) comprises: - a first clock (321) configured for have in alternation a seventh state (E7) and an eighth state (E8) with a first predefined alternating frequency, - a first logic gate (323) having a first gate input connected to an output of the first latch (314) and a second gate input connected to the first clock (321), the first logic gate being configured to have a ninth state (E9) when the first latch (314) has the sixth state (E6) and when the clock (321) has the seventh state (E7), the first logic gate (323) having a tenth state (E10) the rest of the time, - a pulse(s) duration counter connected to an output of the first logic gate (323) and configured to count a first clock pulsation each time the first logic gate has the ninth state (E9), the number of alternations counted corresponding to the pulse(s) duration.

5. Detection and measurement unit (30) according to any of the claims 1 to 4, further comprising a maximum pulse amplitude measurement subunit (330) capable of measuring a maximum amplitude level reached by the representative digital signal (501).

6. Detection and measurement unit (30) according to claim 5, wherein the maximum pulse amplitude measurement subunit (330) comprises a plurality of comparison units each comprising a third comparator and respective latch, the third comparator of each comparison unit being adapted to compare the amplitude of the digital signal with a respective third triggering threshold which is distinct from the third triggering thresholds of the other third comparators, said third comparator having an eleventh state, when the amplitude of the representative digital signal is less than, or is less than or equal to, the corresponding third triggering threshold and a twelfth state otherwise, the third latch of each comparison unit having a third latch input connected to the third comparator of said comparison unit, said third latch being configured to switch from a thirteenth state to a fourteenth state when the third comparator of said comparison unit has the twelfth state, the comparison units being configured so that the third triggering thresholds of the third comparators are distributed across a range of expected amplitudes for the digital signal.

7. Detection and measurement unit (30) according to any of the claims 1 o 6, further comprising an electromagnetic pulse repeat period measurement subunit (350).

8. Detection and measurement unit (30) according to claims 3 and 7, taken alone or in combination with any of claims 4 to 5, wherein the electromagnetic pulse repeat period measurement subunit (350) comprises: - a frequency divider (351) configured to switch between a fifteenth state (E15) and sixteenth state (E16) on each switch of the first latch (314) to a given state chosen from the fifth state (E5) and the sixth state (E6), - a double-period number counter (357) connected to an output of the frequency divider (357) and configured to count a double-period each time the frequency divider (351) switches from a state (0,1) chosen from the fifteenth state (E15) and the sixteenth state (E16) to the other state from the fifteenth state (E15) and the sixteenth state (E16), - a second clock (353) configured for have in alternation a seventeenth state (E17) and an eighteenth state (E15) with a second predefined alternating frequency, - a second logic gate (355) having a third gate input connected to an output of the frequency divider (351) and a fourth gate input connected to the second clock (353), the second logic gate (355) being configured to have a nineteenth state (E19) when the frequency divider (351) has the fifteenth state (E15) and when the second clock (353) has the seventeenth state (E1), the logic gate having a twentieth state (E20) the rest of the time, - a period duration counter connected to an output of the second logic gate (355) and configured to count a second clock pulsation each time the frequency divider (351) switches from a state (0,1) chosen from the fifteenth state (E15) and the sixteenth state (E16) to the other state (0,1) from the fifteenth state (E15) and the sixteenth state (E16).

9. Detection and measurement unit according to claim 8, further comprising a buffer memory (358) configured to retrieve the value of the period duration counter on each switch of the frequency divider (351) from the sixteenth state (E16) to the fifteenth state (E15).

10. Detection and measurement unit (30) according to any of claims 1 to 9, wherein the detection subunit (310) is configured to receive a reset signal and to carry out, on receiving this reset signal, a supply of a number of electromagnetic pulses detected since a previous reset and a reset to zero of a counting of the number of electromagnetic pulses.

11. Detection and measurement unit (30) according to claims 2, 5 and 7 taken in combination, wherein the detection subunit (310), the temporal pulse(s) duration measurement subunit (320), the maximum pulse amplitude measurement subunit (330) and the electromagnetic pulse repeat period measurement subunit (350), are configured to receive a reset signal and to carry out, on receiving this reset signal: - a supply respectively of a number of electromagnetic pulses detected, a temporal pulse(s) duration, a measured maximum pulse amplitude, and a number of electromagnetic pulses measured since a previous reset and - a reset to zero of a counting of the number of electromagnetic pulses.

12. Electromagnetic interference detection system (1) comprising: - a unit for receiving electromagnetic signals configured to receive at least a portion of an electromagnetic radiation to which the detection system is subjected in the form of an electromagnetic wave received in a given frequency band and to supply a digital signal representative of the envelope of said electromagnetic wave, - a detection and measurement unit according to any of claims 1 to 11.

13. Analysis method for detecting electromagnetic interference carried out using a programmable logic circuit which was previously programmed to act as a detection subunit, the method comprising the steps of: - receiving a digital signal representative of the envelope of an electromagnetic wave received in a given frequency band, in which an electromagnetic interference is susceptible to appear, - comparing the amplitude of the representative digital signal with a first triggering threshold and a second stopping threshold, the second stopping threshold corresponding to an amplitude less than that corresponding to the first triggering threshold, - detecting an electromagnetic pulse on each detection of the passage of the amplitude of the representative digital signal through the second threshold in a falling edge after the amplitude of the representative digital signal has passed through the first stopping threshold in a rising edge.

14. Analysis method for detecting electromagnetic interference according to claim 13, further comprising the steps of: - supplying a first clock signal having a first predefined alternating frequency, - modulating the first clock signal with an electromagnetic pulse detection signal supplied during the step of detecting an electromagnetic pulse, counting the remaining clock signal number after modulation with the electromagnetic pulse detection signal.