Clock gating circuit conversion method and device and related equipment

Abstract

The embodiment of the invention provides a clock gating circuit conversion method and device and related equipment, and the method comprises the steps: obtaining target circuit design data of a clock gating circuit before conversion, the target circuit design data being part of data in the circuit design data of the clock gating circuit before conversion; predicting the power consumption income of the clock gating circuit before conversion based on the target circuit design data by using a pre-established power consumption income prediction model to obtain a power consumption income prediction result; wherein the power consumption income prediction model is used for predicting a power consumption change trend between the clock gating circuit before conversion and the clock gating circuit after conversion so as to form a power consumption income prediction result; if it is determined that the power consumption income prediction result is the forward power consumption income, the clock gating circuit before conversion is converted into the clock gating circuit after conversion. According to the technical scheme provided by the embodiment of the invention, the efficiency of determining the switching effectiveness of the clock gating circuit can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of integrated circuit design, and specifically to a clock gating circuit conversion method, device and related equipment. Background Art

[0002] Clock gating technology aims to reduce the clock flip rate of timing devices such as triggers (D Flip Flop, DFF) in digital circuits to optimize the power consumption of digital circuits. As a method for optimizing the power consumption of digital circuits, it is widely used in large-scale integrated circuit design.

[0003] Therefore, effective clock gating circuit conversion is very important for reducing circuit power consumption. In this context, how to provide a technical solution to improve the efficiency of determining the effectiveness of clock gating circuit conversion has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a clock gating circuit conversion method, apparatus and related devices to improve the efficiency of determining the effectiveness of clock gating circuit conversion.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present invention provides a clock gating circuit conversion method, comprising:

[0007] Acquire target circuit design data of the clock gating circuit before conversion, wherein the target circuit design data is part of the circuit design data of the clock gating circuit before conversion;

[0008] Using a pre-established power consumption benefit prediction model, based on the target circuit design data, the power consumption benefit of the clock gating circuit before conversion is predicted to obtain a power consumption benefit prediction result; wherein the power consumption benefit prediction model is used to predict the power consumption change trend between the clock gating circuit before conversion and the clock gating circuit after conversion to form a power consumption benefit prediction result;

[0009] If it is determined that the power consumption benefit prediction result is a positive power consumption benefit, the clock gating circuit before conversion is converted to obtain a clock gating circuit after conversion.

[0010] In a second aspect, an embodiment of the present invention provides a clock gating circuit conversion device, comprising:

[0011] A data acquisition module, used to acquire target circuit design data of the clock gating circuit before conversion, wherein the target circuit design data is part of the circuit design data of the clock gating circuit before conversion;

[0012] A power consumption benefit prediction module, used to use a pre-established power consumption benefit prediction model to predict the power consumption benefit of the clock gating circuit before conversion based on the target circuit design data to obtain a power consumption benefit prediction result; wherein the power consumption benefit prediction model is used to predict the power consumption change trend between the clock gating circuit before conversion and the clock gating circuit after conversion to form a power consumption benefit prediction result;

[0013] The circuit conversion module is used for converting the clock gating circuit before conversion to obtain the clock gating circuit after conversion if it is determined that the power consumption benefit prediction result is a positive power consumption benefit.

[0014] In a third aspect, an embodiment of the present invention provides a simulation device, including:

[0015] A data analysis module, used for analyzing the clock gating circuit before conversion, and obtaining target circuit design data of the clock gating circuit before conversion, wherein the target circuit design data is part of the circuit design data of the clock gating circuit before conversion;

[0016] A power consumption benefit prediction model selection module is used to select a power consumption benefit prediction model, and use the power consumption benefit prediction model to predict the power consumption benefit of the clock gating circuit before the conversion based on the target circuit design data to obtain a power consumption benefit prediction result; the power consumption benefit prediction model is used to predict the power consumption change trend between the clock gating circuit before the conversion and the clock gating circuit after the conversion to form a power consumption benefit prediction result;

[0017] If it is determined that the power consumption benefit prediction result is a positive power consumption benefit, the clock gating circuit before conversion is converted to obtain a clock gating circuit after conversion.

[0018] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the clock gating circuit conversion method as described in the first aspect.

[0019] In a fifth aspect, an embodiment of the present invention provides a storage medium, wherein the storage medium stores a program, and when the program is executed, the clock gating circuit conversion method as described in the first aspect is implemented.

[0020] In a sixth aspect, an embodiment of the present invention provides a computer program product, including a computer program, which, when executed by a processor, implements the clock gating circuit conversion method as described in the first aspect.

[0021] A clock gating circuit conversion method provided by an embodiment of the present invention includes: obtaining target circuit design data of the clock gating circuit before conversion, wherein the target circuit design data is part of the circuit design data of the clock gating circuit before conversion; using a pre-established power consumption benefit prediction model to predict the power consumption benefit of the clock gating circuit before conversion based on the target circuit design data to obtain a power consumption benefit prediction result; wherein the power consumption benefit prediction model is used to predict the power consumption change trend between the clock gating circuit before conversion and the clock gating circuit after conversion to form a power consumption benefit prediction result; if it is determined that the power consumption benefit prediction result is a positive power consumption benefit, the clock gating circuit before conversion is converted to obtain a clock gating circuit after conversion.

[0022] It can be seen that the technical solution provided by the embodiment of the present invention, before converting the clock gating circuit before conversion to the clock gating circuit after conversion, uses the power consumption benefit prediction model in advance to predict the power consumption benefit of the clock gating circuit before conversion, and obtains the power consumption benefit prediction result. Since the power consumption benefit prediction model is used to predict the power consumption change trend between the clock gating circuit before conversion and the clock gating circuit after conversion. Therefore, it can be judged whether the clock gating circuit before conversion needs to be converted according to the power consumption benefit prediction result formed by the power consumption benefit prediction model; if it is determined that the power consumption benefit prediction result corresponding to the clock gating circuit before conversion is a positive power consumption benefit, that is, it indicates that the power consumption of the gated circuit after conversion can produce a positive effect (the power consumption of the clock gating circuit after conversion is reduced), then the clock gating circuit before conversion is converted. Since the input data of the power consumption benefit prediction model is part of the design data (i.e., the target circuit design data) in the circuit design data of the clock gating circuit before conversion, the amount of calculation for obtaining the power consumption benefit prediction result can be reduced, and the complex calculation process of calculating the power consumption of the clock gating circuit after conversion and the power consumption of the clock gating circuit before conversion can be avoided, and the calculation difficulty of obtaining the power consumption benefit prediction result can be reduced. Thus, it is possible to quickly determine whether a clock gating circuit before conversion can generate positive power consumption benefits when converted to a clock gating circuit after conversion, thereby improving the efficiency of determining the effectiveness of the conversion of the clock gating circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0024] Figure 1It is a flow chart of a clock gating circuit conversion method provided by an embodiment of the present invention;

[0025] Figure 2 is a schematic diagram of the design structure of a clock gating circuit before conversion provided by an embodiment of the present invention;

[0026] Figure 3 is a schematic diagram of the design structure of a converted clock gating circuit provided by an embodiment of the present invention;

[0027] Figure 4 It is a schematic diagram of the relationship between the turn-on level probability and the power consumption change trend provided by an embodiment of the present invention;

[0028] Figure 5 It is a schematic diagram of the relationship between the number of drivers and the power consumption change trend provided by an embodiment of the present invention;

[0029] Figure 6 is another schematic flow chart of the clock gating circuit conversion method provided by an embodiment of the present invention;

[0030] Figure 7 It is a structural schematic diagram of a clock gating circuit conversion device provided by an embodiment of the present invention;

[0031] Figure 8 It is a structural schematic diagram of a simulation device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] As the integration of large-scale integrated circuits increases, the clock frequency increases, and the power consumption becomes more and more serious. In order to reduce the power consumption of circuits, various power consumption optimization methods are increasingly used in various stages from front-end design to back-end. The power consumption of integrated circuits includes dynamic power consumption and static power consumption, with dynamic power consumption being the main part (the power consumption described in this article is mainly dynamic power consumption).

[0034] When the device operating voltage and load are fixed, the power consumption of the digital circuit is proportional to the flip rate of the device input signal. As the signal with the highest flip rate in the digital circuit, the clock often accounts for the largest proportion of the power consumption caused by its flip.

[0035] Clock gating technology aims to reduce the clock flip-flop rate of sequential devices such as triggers in digital circuits to achieve the purpose of optimizing power consumption. As a method of optimizing digital circuit power consumption, it is widely used in large-scale integrated circuit design. The specific method is to analyze the circuit logic of the trigger in the digital circuit, extract the clock gating enable signal, and perform clock gating circuit conversion so that the clock of the sequential device is stopped when it is in the hold state (that is, the value of the next state is equal to the current state), thereby effectively reducing the flip-flop rate of the clock input of the sequential device.

[0036] The purpose of parsing the circuit logic of the trigger in the digital circuit is to understand when the trigger updates its state by analyzing the circuit logic of the trigger.

[0037] The conversion of the clock gating circuit will add a clock gating unit in the circuit. If the power consumption of the converted clock gating circuit is greater than that of the clock gating circuit before the conversion, then the conversion of the clock gating circuit before the conversion is meaningless. In addition, the introduction of the clock gating unit in the converted clock gating circuit will increase the power consumption. This will affect the effect of the converted clock gating circuit on reducing power consumption. In other words, the circuit design data of the clock gating circuit before the conversion includes the design information of the clock gating enable signal (which is subsequently converted into the clock gating unit). Whether the clock gating circuit before the conversion should be converted depends on whether the converted clock gating circuit can achieve the purpose of reducing power consumption.

[0038] However, as the scale of integrated circuit design continues to increase, the amount of circuit design data also continues to increase, thereby increasing the complexity and difficulty of determining the power consumption of the clock gating circuit before conversion, the power consumption of the clock gating circuit after conversion, and the power consumption comparison, and increasing the time spent in determining the effectiveness of the clock gating circuit conversion.

[0039] To solve the above problems, an embodiment of the present invention provides a clock gating circuit conversion method to improve the efficiency of determining the effectiveness of clock gating circuit conversion.

[0040] Please refer to Figure 1 , Figure 1 The present invention is a flowchart of a clock gating circuit conversion method provided by an embodiment of the present invention.

[0041] like Figure 1 As shown, the method comprises the following steps:

[0042] Step S101, obtaining target circuit design data of a clock gating circuit before conversion.

[0043] The target circuit design data is part of the circuit design data of the clock gating circuit before conversion. The clock gating circuit before conversion is called the clock gating circuit before conversion.

[0044] The clock gating circuit before conversion may be a digital circuit designed with a clock gating signal during the digital circuit design process of a large-scale integrated circuit. The number of the clock gating circuits before conversion in one large-scale integrated circuit may be multiple.

[0045] The target circuit design data is used to input into a power consumption benefit prediction model to calculate a power consumption benefit prediction result of the clock gating circuit before conversion.

[0046] In digital circuit design, the clock gating circuit before conversion is usually optimized using EDA (Electronic Design Automation) tools based on the description information of the logic circuit connection relationship (such as the description information formed by the register transfer level code), that is, the clock gating circuit before conversion is converted to obtain a converted clock gating circuit with a clock gating unit.

[0047] To understand the application of clock gating technology, please refer to Figure 2 and Figure 3 , Figure 2 is a schematic diagram of the design structure of a clock gating circuit before conversion provided by an embodiment of the present invention, Figure 3 It is a schematic diagram of the design structure of the converted clock gating circuit provided by an embodiment of the present invention.

[0048] The clock gating technology provided by various EDA tools includes the analysis of the clock gating enable signal E and the conversion of the clock gating circuit. The basic method is to analyze the clock gating circuit (driving circuit of the trigger) before conversion as follows:

[0049] D_nxt = E*X + !E*Q;

[0050] Wherein, E is the clock gating enable signal, D_nxt is the actual data signal received by the input port of the trigger, X is the input data signal, and Q is the data signal output by the output port of the trigger.

[0051] Then, the clock gating circuit before the conversion is converted.

[0052] like Figure 2 As shown, in the clock gating circuit before conversion with a clock gating enable signal E, a logic AND gate is provided at the data input port D of each flip-flop (DFF), and the input of the logic AND gate is the transmitted data signal xi (i is the number of flip-flops driven by the clock gating enable signal) and the clock gating enable signal E.

[0053] exist Figure 2 In the design structure shown, the activation state of the clock signal CLK received by the clock signal CK port in each trigger is controlled by the turn-on level of the clock gating enable signal E (which means that the clock gating enable signal can control the clock to be in the on state), thereby reducing the power consumption caused by the clock signal flipping when no data flipping occurs (the trigger is in the hold state).

[0054] Figure 3 Shown is based on Figure 2 The clock gating circuit before conversion is converted to obtain the clock gating circuit after conversion.

[0055] like Figure 3 As shown, in the converted clock gating circuit, the clock gating enable signal E is converted into a clock gating unit (Latch-based Clock Gating, LAT), which is set at the source of the clock path of the circuit to control the activation state of the clock signal CLK.

[0056] Step S102 , using a pre-established power consumption benefit prediction model, based on the target circuit design data, the power consumption benefit of the clock gating circuit before conversion is predicted to obtain a power consumption benefit prediction result.

[0057] The power consumption benefit prediction model is used to predict the power consumption variation trend between the clock gating circuit before conversion and the clock gating circuit after conversion to form a power consumption benefit prediction result.

[0058] The power consumption benefit prediction model can predict the power consumption benefit of each clock gating circuit before conversion. The power consumption benefit prediction result obtained by the prediction can reflect the power consumption change trend of the clock gating circuit after conversion and the clock gating circuit before conversion, that is, it can indicate whether the power consumption of the clock gating circuit after conversion is compared with the power consumption of the clock gating circuit before conversion. Is it an upward trend (negative power consumption benefit) or a downward trend (positive power consumption benefit) or a flat trend (zero power consumption benefit), thereby predicting whether it is necessary to convert the clock gating circuit before conversion. Avoid the situation where the clock gating circuit after conversion does not produce the positive effect of reducing power consumption, but increases the power consumption of the circuit.

[0059] Step S103: if it is determined that the power consumption benefit prediction result is a positive power consumption benefit, the clock gating circuit before conversion is converted to obtain a clock gating circuit after conversion.

[0060] The positive power consumption benefit indicates that the power consumption of the converted clock gating circuit can achieve the positive effect of reducing power consumption. Therefore, based on the power consumption benefit prediction result of the positive power consumption benefit, it can be indicated to convert the clock gating circuit before the conversion to obtain the converted clock gating circuit that can reduce the circuit power consumption.

[0061] It can be seen that the technical solution provided by the embodiment of the present invention, before converting the clock gating circuit before conversion to the clock gating circuit after conversion, uses the power consumption benefit prediction model in advance to predict the power consumption benefit of the clock gating circuit before conversion, and obtains the power consumption benefit prediction result. Since the power consumption benefit prediction model is used to predict the power consumption change trend between the clock gating circuit before conversion and the clock gating circuit after conversion. Therefore, it can be judged whether the clock gating circuit before conversion needs to be converted according to the power consumption benefit prediction result formed by the power consumption benefit prediction model; if it is determined that the power consumption benefit prediction result corresponding to the clock gating circuit before conversion is a positive power consumption benefit, that is, it indicates that the power consumption of the gated circuit after conversion can produce a positive effect (the power consumption of the clock gating circuit after conversion is reduced), then the clock gating circuit before conversion of the target is converted. Since the input data of the power consumption benefit prediction model is part of the design data in the circuit design data of the clock gating circuit before conversion (that is, the target circuit design data), the calculation amount of obtaining the power consumption benefit prediction result can be reduced, and the complex calculation process of calculating the power consumption of the clock gating circuit after conversion and the power consumption of the clock gating circuit before conversion can be avoided, and the calculation difficulty of obtaining the power consumption benefit prediction result can be reduced. Thus, it is possible to quickly determine whether a clock gating circuit before conversion can generate positive power consumption benefits when converted to a clock gating circuit after conversion, thereby improving the efficiency of determining the effectiveness of the conversion of the clock gating circuit.

[0062] In order to quickly obtain the power consumption benefit prediction result, in one implementation, a power consumption benefit prediction model may be established in advance based on the power consumption benefit calculation principle.

[0063] Please continue to refer to Figure 1 ,like Figure 1 As shown, the method may also include:

[0064] Step S100: establishing a power consumption benefit prediction model based on the power consumption benefit calculation principle.

[0065] The power consumption benefit calculation principle is to calculate the difference between the power consumption of the clock gating circuit before conversion and the power consumption of the clock gating circuit after conversion.

[0066] For example, the power consumption of the clock gating circuit before conversion is W1, and the power consumption of the clock gating circuit before conversion converted to the clock gating circuit after conversion is W2. The power consumption benefit calculation principle can be expressed as:

[0067] G' = W1-W2;

[0068] Of course, it can also be expressed as:

[0069] G'=W2-W1.

[0070] The calculation of W1 and W2 can be expressed using the circuit design data of the clock gating circuit before conversion.

[0071] When the power consumption benefit is expressed by the formula G'=W1-W2, a positive power consumption benefit is indicated when G' is greater than 0. When the power consumption benefit is expressed by the formula G'=W2-W1, a positive power consumption benefit is indicated when G' is less than 0. That is, W2 is less than W1 for a positive power consumption benefit.

[0072] Therefore, a power consumption benefit prediction model can be established based on the power consumption benefit calculation principle.

[0073] Step S100 may include:

[0074] According to the power consumption benefit calculation principle, a power consumption change trend relationship between the power consumption of the clock gating circuit before conversion and the power consumption of the clock gating circuit after conversion is constructed to obtain an initial power consumption benefit prediction model;

[0075] Normalizing the initial power consumption benefit prediction model using power consumption trend non-influence data in the non-target circuit design data to obtain a power consumption benefit prediction model;

[0076] The non-target circuit design data refers to the design data in the circuit design data other than the target design data; and the power consumption trend-influenced data has no effect on the power consumption change trend of the clock gating circuit before conversion and the clock gating circuit after conversion; the target circuit design data has an effect on the power consumption change trend of the clock gating circuit before conversion and the clock gating circuit after conversion.

[0077] The circuit design data describes the power consumption information of each device in the clock gating circuit before the conversion. Therefore, according to the power consumption benefit calculation principle, the circuit design data of the clock gating circuit before the conversion can be used to construct the power consumption change trend relationship of the power consumption W1 of the clock gating circuit before the conversion and the power consumption W2 of the clock gating circuit after the conversion to obtain an initial power consumption benefit prediction model, whose expression is, for example, the expression of the aforementioned power consumption benefit calculation principle: G'=W1-W2.

[0078] It can be seen that in the initial power consumption benefit prediction model, it is necessary to calculate the power consumption W1 of the clock gating circuit before the conversion, the power consumption W2 of the clock gating circuit after the conversion, and then calculate the difference between the two. Therefore, the calculation amount of the initial power consumption benefit prediction model is relatively large.

[0079] In order to simplify the calculation amount of the initial power consumption benefit prediction model, the initial power consumption benefit prediction model is further normalized in the embodiment of the present invention, and the parameters in the power consumption change trend relationship that will not affect the power consumption change trend: the data with no influence on the power consumption trend are removed; thereby, those features that have little effect on the model prediction results (data with no influence on the power consumption trend) can be effectively eliminated, thereby simplifying the final power consumption benefit prediction model and improving the generalization ability and interpretability of the power consumption benefit prediction model.

[0080] In one embodiment, the power consumption trend non-influence data is: the clock signal flip rate in the circuit design data of the clock gating circuit before conversion; the target circuit design data is the turn-on level probability of the clock gating enable signal, and the number of drivers determined by the number of timing devices driven by the clock gating signal; the turn-on level probability is the proportion of the clock controlled by the clock gating enable signal to be in the on state within a certain period of time;

[0081] According to the power consumption benefit calculation principle, a power consumption change trend relationship formula of the clock gating circuit before conversion and the power consumption of the clock gating circuit after conversion is constructed to obtain an initial power consumption benefit prediction model, including:

[0082] According to the power consumption benefit calculation principle, the power consumption change trend relationship is constructed using the non-target circuit design data, the number of drivers, and the turn-on level probability to obtain an initial power consumption benefit prediction model;

[0083] The method of utilizing the power consumption trend non-influence data in the non-target circuit design data to normalize the initial power consumption benefit prediction model to obtain the power consumption benefit prediction model includes:

[0084] Using the clock signal flip rate, normalizing the initial power consumption benefit prediction model to obtain a normalized power consumption change trend relationship;

[0085] The power consumption benefit prediction model is obtained based on the normalized power consumption change trend relationship.

[0086] Since the power consumption benefit prediction model is mainly aimed at predicting the power consumption change trend between the power consumption generated by the converted clock gating circuit formed after the introduction of the clock gating unit and the power consumption generated by the clock gating circuit before the conversion without the introduction of the clock gating unit, the power consumption benefit prediction model does not directly depend on the toggle rate of the clock signal itself (i.e., the clock toggle rate T ck ), the parameters of the power-benefit prediction model are more directly reflected in the power consumption of typical devices in the process library. After removing the clock flip rate, the power-benefit prediction model itself becomes more concise and clear, which greatly reduces the amount of calculation and improves the scope of application of the power-benefit prediction model.

[0087] In the embodiment of the present invention, by analyzing the circuit design data, the design data (target circuit design data) that affects the power consumption change trend of the clock gating circuit after the conversion and the power consumption of the clock gating circuit before the conversion are determined as: the number of drives n determined by the number of timing devices driven by the clock gating enable signal E (that is, the number of drives is the number of timing devices driven by the clock gating enable signal), and the turn-on level probability P.

[0088] To illustrate the impact of target circuit design data on power consumption trends, Figure 2 and Figure 3 The design structure diagram of the circuit shown is used as an example for explanation. Figure 2 and Figure 3 The timing device shown is a flip-flop.

[0089] like Figure 2 and Figure 3 The design structure diagram of the circuit shown in the figure shows that Figure 2 The clock gating circuit shown before the conversion is converted to Figure 3 When the converted clock gating circuit is shown, a clock gating unit is added to the circuit.

[0090] If the converted clock gating circuit cannot effectively reduce the clock flip-flop rate of its fan-out (driven) trigger (for example, when the clock gating enable signal is turned on, the probability of the clock signal being in the on state is close to 1), the dynamic power consumption of its fan-out trigger will not be significantly reduced, but the power consumption of the clock gating unit due to clock flip-flop will be increased. Due to the high clock signal flip-flop rate of the clock gating unit, the increased dynamic power consumption cannot be ignored.

[0091] Please refer to Figure 4 , Figure 4 It is a schematic diagram of the relationship between the turn-on level probability and the power consumption change trend provided by an embodiment of the present invention.

[0092] like Figure 4 As shown, the horizontal axis is the turn-on level probability P of the clock gating enable signal, and the vertical axis is the power consumption change trend of the clock gating circuit before the conversion and the power consumption Power of the clock gating circuit after the conversion.

[0093] exist Figure 4 In the relationship diagram shown, there are shown relationship curves of the power consumption change trends of the turn-on level probability P and the power consumption Power under three groups of different drive numbers n.

[0094] The number of drivers n of the first group is 2, and the power consumption of the corresponding clock gating circuit before conversion is ng_2, and the power consumption of the clock gating circuit after conversion is cg_2;

[0095] The number of drivers n in the second group is 8, and the power consumption of the corresponding clock gating circuit before conversion is ng_8, and the power consumption of the clock gating circuit after conversion is cg_8;

[0096] The number n of drivers of the third group is 16, and the corresponding power consumption of the clock gating circuit before conversion is ng_16, and the power consumption of the clock gating circuit after conversion is cg_16.

[0097] based on Figure 4 From the curve shown, we can draw the following conclusions:

[0098] 1. The power consumption of the clock gating circuit before the conversion and the power consumption of the clock gating circuit after the conversion are both linearly positively correlated with the turn-on level probability P of the clock gating enable signal;

[0099] 2. When the number n of sequential devices driven by the clock gating enable signal is determined: when the probability P of the on level of the gating enable signal is greater than a specific value Pt, the power consumption of the clock gating circuit after the conversion is greater than the power consumption of the clock gating circuit before the conversion.

[0100] For example Figure 4 As shown, when n is 2, when the turn-on level probability P is greater than Pt' between 0.3-0.4, cg_2 is greater than ng_2. When n is 8, when the turn-on level probability P is greater than Pt" between 0.8-0.9, cg_4 is greater than ng_4.

[0101] That is to say, the power consumption of the clock gating circuit before the conversion and the power consumption of the clock gating circuit after the conversion are both linearly positively correlated with the turn-on level probability P; and are constrained by a specific turn-on level probability to obtain a positive power consumption benefit.

[0102] Please refer to Figure 5 , Figure 5 It is a schematic diagram of the relationship between the number of drivers and the power consumption change trend provided by an embodiment of the present invention.

[0103] like Figure 5 As shown, the horizontal axis is the number n of sequential devices driven by the clock gating enable signal, and the vertical axis is the power consumption change trend of the clock gating circuit before the conversion and the power consumption Power of the clock gating circuit after the conversion.

[0104] exist Figure 5 In the relationship diagram shown, there are shown relationship curves of the power consumption change trends of the number of drivers and the power consumption Power under two groups of different turn-on level probabilities P.

[0105] Among them, ng_0.5 and ng_0.9 correspond to the power consumption of the clock gating circuit before conversion when the turn-on level probabilities are 0.5 and 0.9 respectively; cg_0.5 and cg_0.9 correspond to the power consumption of the clock gating circuit after conversion when the turn-on level probabilities are 0.5 and 0.9 respectively.

[0106] based on Figure 5 From the curve shown, we can draw the following conclusions:

[0107] 1. The power consumption of the clock gating circuit before conversion and the power consumption of the clock gating circuit after conversion are both linearly positively correlated with the number of drivers n;

[0108] 2. When the turn-on level probability P is determined: when the number of drivers n is less than a specific value Nt, the power consumption of the clock gating circuit after the conversion is greater than the power consumption of the clock gating circuit before the conversion.

[0109] For example Figure 5 As shown, when P is 0.5, when the number of drivers n is greater than Nt' which is between 2 and 4, cg_0.9 is greater than ng_0.9. When P is 0.9, when the number of drivers n is greater than Nt' which is between 10 and 12, cg_0.9 is greater than ng_0.9.

[0110] The power consumption is linearly correlated with the number of drivers n, that is, the power consumption of the clock gating circuit before the conversion and the power consumption of the clock gating circuit after the conversion are both linearly positively correlated with the number of drivers and are constrained by a specific number of drivers Nt to obtain positive power consumption benefits.

[0111] Therefore, when establishing the power consumption benefit prediction model, the embodiment of the present invention constructs a relational expression with the power consumption benefit prediction structure based on the target circuit design data: the turn-on level probability P and the number of drivers n.

[0112] The relational expression in the established power consumption benefit prediction model is:

[0113] G = a*nb*n*Pc;

[0114] Wherein, a, b, and c are arbitrary real numbers, which can be determined according to the non-target circuit design data of the clock gating circuit before the specific conversion, or can be set by the designer based on the circuit design requirements.

[0115] In the above relational expression, n and P are input variables, and their values ​​are determined according to the circuit design data of the specific clock gating circuit before conversion. When the power consumption benefit prediction model is used to predict the power consumption benefit of each clock gating circuit before conversion, the target circuit design data of each clock gating circuit before conversion is used as input, and the power consumption benefit prediction model is used to calculate the power consumption benefit prediction result G of the clock gating circuit before conversion.

[0116] The target circuit design data is the number of drivers n, the probability of the on-level P, and the power consumption trend has no effect on the clock signal flip rate T. ck In the case of , according to the power consumption benefit calculation principle: the difference between the power consumption of the clock gating circuit before the conversion and the power consumption of the clock gating circuit after the conversion, the power consumption change trend relationship constructed can be expressed as:

[0117] G'=(n*T ck *ED ck +n*T d *EM)-(n*T ck *P*ED ck +T ck *EL ck ),

[0118] Where: T ck The clock signal toggle rate is optimized for clock gating techniques that are not performed;

[0119] T d is the average flip rate of the data signal;

[0120] ED ck The average power consumption of clock signal toggle of sequential devices driven by clock gating enable signal;

[0121] EL ck is the average power consumption of clock signal flipping of clock gating unit;

[0122] EM is the average power consumption of data input flip of one selector;

[0123] n*T ck *P*ED ck : The register clock signal flip power of the converted clock gating circuit;

[0124] T ck *EL ck : The clock signal flipping power of the clock gating unit of the clock gating circuit;

[0125] n*T ck *ED ck : The register clock signal flip power of the clock gating circuit before conversion;

[0126] n*T d *EM: Selector flip power of the clock gating circuit before conversion.

[0127] Based on the power consumption change trend relation G', the initial power consumption benefit prediction model is obtained. In order to improve the applicability of the final power consumption benefit prediction model, the initial power consumption benefit prediction model is further simplified, that is, the data T that has no influence on the power consumption trend is removed. ck , the initial power consumption benefit prediction model is normalized.

[0128] The normalized power consumption trend relationship is expressed as:

[0129] G=G' / T ck =(ED ck +T d / T ck *EM)*n-ED ck *n*P-EL ck =a*nb*n*Pc;

[0130] Among them, T d / T ck It is actually the flip rate of data relative to the clock, which can be determined based on the circuit design requirements of the clock gating circuit before conversion. ck +T d / T ck *EM is coefficient a, ED is coefficient ck is the coefficient b, EL ck is a constant c.

[0131] After normalizing G', in the normalized power consumption change trend relation G, except that n and P are variables that change based on the change of the clock gating circuit before the conversion, ED ck , T d / T ck ,EM,ED ck ,EL ck All of them are values ​​determined by non-target circuit design data in the circuit design data. For example, the above coefficients and constants are calculated based on parameters of conventional electronic devices (typical devices) in a process library used in digital circuit design.

[0132] The power consumption benefit prediction model obtained based on the normalized power consumption change trend relationship is more concise and clear, which can greatly reduce the calculation amount of the power consumption benefit prediction result and improve the application scope of the model.

[0133] The target design data is n and P in the circuit design data, so in order to obtain the target design data of each clock gating circuit before conversion, it can be determined according to the clock gating circuit before conversion. In one embodiment, the circuit design data of the clock gating circuit before conversion is the description information of the connection relationship of the logic circuit, and step S101 may include:

[0134] Generate a netlist file based on the logic circuit connection relationship description information, and extract a clock gating enable signal and a valid port of a sequential device driven by the clock gating enable signal based on the netlist file, and obtain the number of sequential devices driven by the clock gating enable signal to determine the number of drives;

[0135] And, generating a waveform file based on the logic circuit connection relationship description information, and extracting the turn-on level probability of the clock gating enable signal based on the waveform file;

[0136] The target circuit design data is obtained based on the number of drivers and the turn-on level probability,

[0137] Or, based on the circuit design requirements of the clock gating circuit before the conversion, the number of timing devices driven by the clock gating enable signal is set to determine the number of drives and the turn-on level probability of the clock gating enable signal, and the target circuit design data is obtained.

[0138] The logic circuit connection relationship description information may be information formed based on a register transfer level (RTL) code, which is circuit design data of the clock gating circuit before the conversion.

[0139] The netlist file for obtaining the number of drivers n may be a general unit library netlist file, for example, when using a design compiler (DC) for logic synthesis, the RTL code is converted into an intermediate representation: a generic technology (GTECH) netlist file, which is represented by the devices in the tool library inside the DC tool.

[0140] When obtaining the number of drivers n in the target circuit design data, the RTL code can be converted into a general cell library netlist first. The signal corresponding to the synchronous valid port of the general register device (such as the \**SEQGEN** in the GTECH netlist) in the general cell library netlist is captured as the clock gating enable signal E. For the clock gating enable signal E, if it is connected to the synchronous valid ports of n general register devices at the same time, the number of drivers of the registers driven by it is n.

[0141] Of course, in other implementations, the designer may also directly input the number of drivers according to circuit design requirements.

[0142] The waveform file is used to obtain the on-level probability P. The on-level probability of the clock enable signal refers to the proportion of the clock enable signal in a certain period of time when the clock is controlled by the clock gating enable signal to be on (the level of the controlled clock to be on can be high or low).

[0143] Therefore, the extraction of P is related to the waveform of the signal, and P can be obtained based on the waveform file.

[0144] In one implementation, the waveform file generated based on the logic circuit connection relationship description information includes:

[0145] Simulating the logic circuit connection relationship description information to obtain a first waveform file, and converting the first waveform file into a waveform file that passes the unit library netlist; converting the waveform file that passes the unit library netlist into a file that describes a signal flip rate and a level probability to generate the waveform file;

[0146] Or, a universal cell library netlist is generated based on the logic circuit connection relationship description information, and the universal cell library netlist is simulated to generate a waveform file of the universal cell library netlist; the waveform file of the cell library netlist is converted into a file describing the signal flip rate and level probability to generate the waveform file.

[0147] The first waveform file may be a Fast Signal Database (FSDB) waveform file, a Charge-Coupled Device (CCD) waveform file, or the like.

[0148] The RTL code is simulated by an EDA simulation tool to generate an RTL-based waveform file (such as the FSDB file and CCD file mentioned above), and the RTL-based waveform file is converted into a waveform file based on a general cell library netlist by an EDA waveform conversion tool, and the waveform file of the general cell library netlist is converted into a file describing the signal flip rate and level probability (such as a Switching Activity Interchange Format (SAIF)) to form a waveform file, from which the turn-on level probability P of the clock gating enable signal is extracted.

[0149] Alternatively, a waveform file of the general cell library netlist is directly generated based on the general cell library netlist simulation, and the waveform file of the general cell library netlist is converted into a file (such as a SAIF file) that describes the signal flip rate and level probability, and a waveform file is generated to extract the turn-on level probability P of the clock gating enable signal from the waveform file.

[0150] Of course, when the turn-on level probability P is obtained, it can also be directly set by the designer based on circuit design requirements.

[0151] In order to use the power consumption benefit prediction model to accurately calculate the power consumption benefit prediction result corresponding to each clock gating circuit before conversion, the power consumption benefit prediction model is initialized in advance before operating the target circuit design data to determine the coefficients of the target circuit design data in the power consumption benefit prediction model, thereby obtaining the power consumption benefit prediction model suitable for each clock gating circuit before conversion and calculating a reliable power consumption benefit prediction result.

[0152] In one implementation, the initialization of the power consumption benefit prediction model can be directly set by the designer according to the circuit design requirements. Step S102 includes:

[0153] Based on the circuit design requirements of the clock gating circuit before the conversion, coefficients and constants of the target circuit design data in the power consumption benefit prediction model are determined to complete the initialization of the power consumption benefit prediction model for the clock gating circuit before the conversion;

[0154] Based on the circuit design requirements of the clock gating circuit before the conversion, the coefficients and constants of the target circuit design data in the power consumption benefit prediction model are determined to complete the initialization of the power consumption benefit prediction model.

[0155] Based on the normalized power consumption trend relationship in the above power consumption benefit prediction model, it can be seen that when calculating the power consumption benefit prediction result based on the input target circuit design data, the power consumption trend relationship also includes the coefficient: a(ED ck +T d / T ck *EM)、b(ED ck ) and constant c(L ck ).

[0156] Furthermore, the above coefficients can be determined according to circuit design data. Since the circuit design data is designed by designers based on the design requirements of the circuit, the coefficients and constants can be set by designers based on the circuit design requirements.

[0157] For example, designers can input ED based on circuit design requirements. ck , T d / T ck , the design value of EM, and the corresponding ED ck +T d / T ck *EM coefficient a, input ED ck The design value of is taken as the coefficient b, and the input value is EL ck The design value of is taken as the constant c.

[0158] The power consumption benefit prediction model is initialized, and then the power consumption benefit prediction result of the clock gating circuit before conversion can be calculated based on the extraction and input of variables n and P.

[0159] In other implementations, the coefficients and constants may be automatically determined by an EDA tool to complete the initialization of the power consumption benefit prediction model.

[0160] Please refer to Figure 6 , Figure 6 It is another flowchart diagram of the clock gating circuit conversion method provided by an embodiment of the present invention.

[0161] like Figure 6 As shown, the method comprises the following steps:

[0162] Step S200: establishing a power consumption benefit prediction model based on the power consumption benefit calculation principle.

[0163] Step S201, obtaining target circuit design data of the clock gating circuit before conversion.

[0164] Step S202 , extracting non-target circuit design data from the circuit design data of the clock gating circuit before conversion.

[0165] Step S203 , using the non-target circuit design data to determine the coefficients and constants of the target circuit design data in the power consumption benefit prediction model, and completing the initialization of the power consumption benefit prediction model.

[0166] Since the coefficients and constants in the power consumption change trend relationship in the power consumption benefit prediction model are typical devices in the tool library used in circuit design, it is possible to obtain parameter description information of typical devices in the clock gating circuit before the conversion based on the circuit design data of the clock gating circuit before the conversion, and obtain the coefficients and constants of the target circuit design data.

[0167] The following describes a process of calculating coefficients and constants based on non-target circuit design data in the circuit design data.

[0168] For example, under typical operating voltage, temperature and process of a process library:

[0169] Typical devices (registers) have the following parameter information descriptions:

[0170] The falling edge power consumption lookup table fall_power records the falling edge power consumption of registers in different design scenarios:

[0171] Index parameter of the falling edge power consumption of the register: index_1(“1, 2.01, 4.06, 8.17, 16.47, 33.17, 66.82, 134.61”);

[0172] The falling edge power consumption value corresponding to each parameter in index parameter index_1: Values("1.87, 1.86, 1.85, 1.84, 1.86, 1.95, 2.18, 2.72").

[0173] The rising edge power consumption lookup table rise_power records the rising edge power consumption of registers in different design scenarios:

[0174] Index parameter of rising edge power consumption of register: index_1(“1, 2.01, 4.06, 8.17, 16.47, 33.17, 66.82, 134.61”);

[0175] The rising edge power consumption value corresponding to each parameter in index parameter index_1: values("1.27, 1.26, 1.26, 1.25, 1.27, 1.36, 1.59, 2.14").

[0176] The following parameter information is described for a typical device (clock gating unit (latch)):

[0177] The falling edge power consumption lookup table fall_power records the falling edge power consumption of the clock gating unit in different design scenarios:

[0178] Index parameter of falling edge power consumption of clock gating unit: index_1(“1, 2.01, 4.06, 8.17, 16.47, 33.17, 66.82, 134.61”);

[0179] The falling edge power consumption value corresponding to each parameter in index parameter index_1: Values("2.93, 2.91, 2.90, 2.89, 2.91, 3.00, 3.23, 3.76");

[0180] The rising edge power consumption lookup table rise_power records the rising edge power consumption of the clock gating unit in different design scenarios:

[0181] Index parameter of rising edge power consumption of clock gating unit: index_1(“1, 2.01, 4.06, 8.17, 16.47, 33.17, 66.82, 134.61”);

[0182] The rising edge power consumption value corresponding to each parameter in index parameter index_1: Values("0.30, 0.31, 0.31, 0.29, 0.30, 0.31, 0.33, 0.35").

[0183] The following parameter information is described for typical devices (selectors):

[0184] The falling edge power consumption lookup table fall_power of the first selector Pin (I0) records the falling edge power consumption of Pin (I0) in different design scenarios:

[0185] Index parameter of falling edge power consumption of Pin (I0): index_1 (“1, 2.22, 4.94, 11.00, 24.47, 54.42, 121.04, 269.2”);

[0186] The falling edge power consumption value corresponding to each parameter in index parameter index_1: Values("0.09, 0.09, 0.09, 0.09, 0.09, 0.09, 0.09, 0.09");

[0187] The rising edge power consumption lookup table rise_power records the rising edge power consumption of Pin (I0) in different design scenarios:

[0188] Index parameter of rising edge power consumption of Pin (I0): index_1 (“1, 2.22, 4.94, 11.00, 24.47, 54.42, 121.04, 269.2”);

[0189] The rising edge power consumption value corresponding to each parameter in index parameter index_1: Values("0.06, 0.06, 0.06, 0.06, 0.06, 0.06, 0.06, 0.06");

[0190] The falling edge power consumption lookup table fall_power of the second selector Pin (I1) records the falling edge power consumption of Pin (I1) in different design scenarios:

[0191] Index parameter of the falling edge power consumption of Pin (I1): index_1 (“1, 2.22, 4.94, 11.00, 24.47, 54.42, 121.04, 269.2”);

[0192] The falling edge power consumption value corresponding to each parameter in index parameter index_1: Values(0.21, 0.21, 0.21, 0.21, 0.21, 0.21, 0.21, 0.21");

[0193] The rising edge power consumption lookup table rise_power records the rising edge power consumption of Pin (I1) in different design scenarios:

[0194] Index parameter of rising edge power consumption of Pin(I1): index_1(“1, 2.22, 4.94, 11.00, 24.47, 54.42, 121.04, 269.2”);

[0195] The rising edge power consumption value corresponding to each parameter in index parameter index_1: Values("0.02, 0.02, 0.02, 0.02, 0.02, 0.02, 0.02, 0.02");

[0196] …

[0197] The falling edge power consumption lookup table fall_power of the S+1th selector Pin (IS) records the falling edge power consumption of Pin (IS) in different design scenarios:

[0198] Index parameter of the falling edge power consumption of Pin (IS): index_1 (“1, 2.22, 4.94, 11.00, 24.47, 54.42, 121.04, 269.2”);

[0199] The falling edge power consumption value corresponding to each parameter in index parameter index_1: Values("1.09, 1.08, 1.07, 1.08, 1.14, 1.32, 1.74, 2.73");

[0200] The rising edge power consumption lookup table rise_power records the rising edge power consumption of Pin (IS) in different design scenarios:

[0201] Index parameter of rising edge power consumption of Pin(IS): index_1(“1, 2.22, 4.94, 11.00, 24.47, 54.42, 121.04, 269.2”);

[0202] The rising edge power consumption value corresponding to each parameter in index parameter index_1: Values("0.02, 0.02, 0.01, 0.02, 0.02, 0.10, 0.24, 1.20").

[0203] The above fall_power represents the power consumption lookup table of the falling edge of the signal specified by pin; rise_power represents the power consumption lookup table of the rising edge of the signal specified by pin; the data in the index_1 array is the change time (input transition) of the signal specified by pin. The data in the values ​​array is the power consumption value corresponding to the input transition listed in index_1.

[0204] Assuming that the input transition of the clock CK in the circuit design data of the clock gating circuit before the current conversion is 66.82 and the input transition of the data signal is 121.04, by looking up the above fall_power and rise_power lookup tables, we can get:

[0205] The typical register clock power consumption is 2.18 on the rising edge and 1.59 on the falling edge. The average power consumption can be:

[0206] ED ck =(power consumption on rising edge + power consumption on falling edge) / 2=(2.18+1.59) / 2=1.885;

[0207] The typical clock gating unit has a rising edge power consumption of 3.23, a falling edge power consumption of 0.33, and an average power consumption of:

[0208] EL ck =(power consumption on rising edge + power consumption on falling edge) / 2=(3.23+0.33) / 2=1.78;

[0209] The typical selector signal I0 has a rising edge power consumption of 0.09, a falling edge power consumption of 0.06, and an average power consumption of:

[0210] EM_I0 = (power consumption on rising edge + power consumption on falling edge) / 2 = (0.09 + 0.06) / 2 = 0.075;

[0211] The typical selector signal I1 has a rising edge power consumption of 0.21, a falling edge power consumption of 0.02, and an average power consumption of:

[0212] EM_I1 = (power consumption on rising edge + power consumption on falling edge) / 2 = (0.21 + 0.02) / 2 = 0.115;

[0213] The typical selector signal S has a rising edge power consumption of 1.74, a falling edge power consumption of 0.24, and an average power consumption of:

[0214] EM_S = (power consumption on rising edge + power consumption on falling edge) / 2 = (1.74 + 0.24) / 2 = 0.99;

[0215] EM=EM_I0+EM_I1+EM_S=0.075+0.115+0.99=1.18;

[0216] Extract based on waveform and other information: T d / T ck =0.2, then the power consumption benefit prediction model after initialization is:

[0217] G=(ED ck +T d / T ck*EM)*n-ED ck *n*P-EL ck

[0218] =(1.885+0.2*1.18)*n-1.885*n*P-1.78;

[0219] =2.121*n-1.885*n*P-1.78

[0220] That is, a=2.121, b=1.885, c=1.78.

[0221] Step S204 , using the initialized power consumption benefit prediction model, based on the target circuit design data, the power consumption benefit of the clock gating circuit before conversion is predicted to obtain a power consumption benefit prediction result.

[0222] The coefficients a and b and the constant c in the initialized power consumption benefit prediction model are all known, and the power consumption benefit prediction result can be calculated based on the input target circuit design data n and P.

[0223] Step S205, determining whether the power consumption benefit prediction result is a positive power consumption benefit, if yes, executing step S206, if no, executing step S207.

[0224] In one implementation, whether the power consumption benefit prediction result is a positive power consumption benefit can be determined by judging the power consumption change trend. Step S103 includes:

[0225] If the power consumption benefit prediction result indicates that the power consumption change trend of the clock gating circuit before conversion after conversion to the clock gating circuit is: the power consumption of the clock gating circuit after conversion is reduced, then the power consumption benefit prediction result is determined to be a positive power consumption benefit, and the clock gating circuit before conversion is converted to a clock gating circuit.

[0226] The power consumption change trend indicates the power consumption change difference between the power consumption of the clock gating circuit before the conversion and the power consumption of the clock gating circuit. Therefore, when the power consumption change trend is that the power consumption of the clock gating circuit after the conversion is reduced, it means that the conversion of the clock gating circuit has a positive effect on the power consumption of the circuit. Therefore, the clock gating circuit before the conversion can be converted.

[0227] Step S206, converting the clock gating circuit before conversion to obtain a clock gating circuit after conversion.

[0228] Step S207 , determining that the power consumption benefit prediction result is a negative power consumption benefit or a zero power consumption benefit, and not converting the clock gating circuit before conversion.

[0229] If it is determined that the power consumption benefit prediction result is a negative power consumption benefit or a zero power consumption benefit, it means that the power consumption of the clock gating circuit after the conversion is increased or unchanged compared with the power consumption of the clock gating circuit before the conversion. At this time, the conversion of the clock gating circuit before the conversion is meaningless, and it will increase the power consumption of the circuit. Therefore, the clock gating circuit before the conversion is not converted to avoid an increase in circuit power consumption.

[0230] In one implementation, if it is determined that the power consumption benefit prediction result is a negative power consumption benefit or a zero power consumption benefit, then the clock gating circuit before the conversion is not converted, including:

[0231] If the power consumption benefit prediction result indicates that the power consumption change trend of the clock gating circuit before the conversion after the conversion to the clock gating circuit is: the power consumption of the clock gating circuit after the conversion increases or remains the same as the power consumption before the conversion, then the power consumption benefit prediction result is determined to be a negative power consumption benefit or a zero power consumption benefit, and the clock gating circuit before the conversion is not converted.

[0232] The power consumption trend is: the power consumption of the clock gating circuit after conversion increases, which means that the power consumption benefit is negative, that is, the clock gating circuit cannot produce a positive effect: reduce the circuit power consumption, and the clock gating circuit before conversion is not converted at this time.

[0233] The power consumption change trend is: the power consumption of the clock gating circuit after the conversion is equal to the power consumption before the conversion, which means that there is no power consumption benefit. At this time, the clock gating circuit before the conversion is also not converted.

[0234] The embodiment of the present invention also provides a clock gating circuit conversion device, please refer to Figure 7 , Figure 7 It is a structural schematic diagram of a clock gating circuit conversion device provided by an embodiment of the present invention.

[0235] like Figure 7 As shown, the device comprises:

[0236] A data acquisition module 71, used to acquire target circuit design data of the clock gating circuit before conversion, wherein the target circuit design data is part of the circuit design data of the clock gating circuit before conversion;

[0237] The power consumption benefit prediction module 72 is used to use a pre-established power consumption benefit prediction model to predict the power consumption benefit of the clock gating circuit before conversion based on the target circuit design data to obtain a power consumption benefit prediction result; wherein the power consumption benefit prediction model is used to predict the power consumption change trend between the clock gating circuit before conversion and the clock gating circuit after conversion to form a power consumption benefit prediction result;

[0238] The circuit conversion module 73 is configured to convert the clock gating circuit before conversion to obtain a clock gating circuit after conversion if it is determined that the power consumption benefit prediction result is a positive power consumption benefit.

[0239] Alternatively, if Figure 7 As shown, the device may also include:

[0240] The power consumption benefit prediction model establishment module 70 is used to establish a power consumption benefit prediction model based on the power consumption benefit calculation principle;

[0241] The power consumption benefit prediction model establishment module 70 is used to establish a power consumption benefit prediction model based on the power consumption benefit calculation principle, including:

[0242] According to the power consumption benefit calculation principle, a power consumption change trend relationship between the power consumption of the clock gating circuit before conversion and the power consumption of the clock gating circuit after conversion is constructed to obtain an initial power consumption benefit prediction model;

[0243] Normalizing the initial power consumption benefit prediction model using power consumption trend non-influence data in the non-target circuit design data to obtain a power consumption benefit prediction model;

[0244] The non-target circuit design data refers to the design data in the circuit design data other than the target design data; and the power consumption trend-influenced data has no effect on the power consumption change trend of the clock gating circuit before conversion and the clock gating circuit after conversion; the target circuit design data has an effect on the power consumption change trend of the clock gating circuit before conversion and the clock gating circuit after conversion.

[0245] Optionally, the power consumption trend unaffected data is: the clock signal flip rate in the circuit design data of the clock gating circuit before conversion; the target circuit design data is the turn-on level probability of the clock gating enable signal, and the number of drivers determined by the number of timing devices driven by the clock gating signal; the turn-on level probability is the proportion of the clock controlled by the clock gating enable signal to be in the on state within a certain period of time;

[0246] The power consumption benefit prediction model establishment module 70 is used to construct a power consumption change trend relationship between the power consumption of the clock gating circuit before conversion and the power consumption of the clock gating circuit after conversion according to the power consumption benefit calculation principle, and obtain an initial power consumption benefit prediction model, including:

[0247] According to the power consumption benefit calculation principle, the power consumption change trend relationship is constructed using the non-target circuit design data, the number of drivers, and the turn-on level probability to obtain an initial power consumption benefit prediction model;

[0248] The power consumption benefit prediction model establishment module 70 is used to use the power consumption trend non-influence data in the non-target circuit design data to normalize the initial power consumption benefit prediction model to obtain the power consumption benefit prediction model, including:

[0249] Using the clock signal flip rate, normalizing the initial power consumption benefit prediction model to obtain a normalized power consumption change trend relationship;

[0250] The power consumption benefit prediction model is obtained based on the normalized power consumption change trend relationship.

[0251] Optionally, it also includes:

[0252] The first initialization module is used to determine the coefficients and constants of the target circuit design data in the power consumption benefit prediction model based on the circuit design requirements of the clock gating circuit before the conversion, and complete the initialization of the power consumption benefit prediction model.

[0253] Optionally, it also includes:

[0254] The second initialization module is used to use the non-target circuit design data to determine the coefficients and constants included in the normalized power consumption change trend relationship in the power consumption benefit prediction model, so as to complete the initialization of the power consumption benefit prediction model.

[0255] Optionally, it also includes:

[0256] The circuit stop conversion module 74 is configured to not convert the clock gating circuit before the conversion if it is determined that the power consumption benefit prediction result is a negative power consumption benefit or a zero power consumption benefit.

[0257] It can be seen that the technical solution provided by the embodiment of the present invention, before converting the clock gating circuit before conversion to the clock gating circuit after conversion, uses the power consumption benefit prediction model in advance to predict the power consumption benefit of the clock gating circuit before conversion, and obtains the power consumption benefit prediction result. Since the power consumption benefit prediction model is used to predict the power consumption change trend between the clock gating circuit before conversion and the clock gating circuit after conversion. Therefore, it can be judged whether the clock gating circuit before conversion needs to be converted according to the power consumption benefit prediction result formed by the power consumption benefit prediction model; if it is determined that the power consumption benefit prediction result corresponding to the clock gating circuit before conversion is a positive power consumption benefit, that is, it indicates that the power consumption of the gated circuit after conversion can produce a positive effect (the power consumption of the clock gating circuit after conversion is reduced), then the clock gating circuit before conversion of the target is converted. Since the input data of the power consumption benefit prediction model is part of the design data in the circuit design data of the clock gating circuit before conversion (that is, the target circuit design data), the calculation amount of obtaining the power consumption benefit prediction result can be reduced, and the complex calculation process of calculating the power consumption of the clock gating circuit after conversion and the power consumption of the clock gating circuit before conversion can be avoided, and the calculation difficulty of obtaining the power consumption benefit prediction result can be reduced. Thus, it is possible to quickly determine whether a clock gating circuit before conversion can generate positive power consumption benefits when converted to a clock gating circuit after conversion, thereby improving the efficiency of determining the effectiveness of the conversion of the clock gating circuit.

[0258] The embodiment of the present invention also provides a simulation device, please refer to Figure 8 , Figure 8 The schematic diagram is a structural diagram of a simulation device provided by an embodiment of the present invention. A functional module using a power consumption benefit prediction model is integrated in the simulation device to implement the clock gating circuit conversion method described above.

[0259] like Figure 8 As shown, the simulation device includes:

[0260] A data analysis module 81 is used to analyze the clock gating circuit before conversion and obtain target circuit design data of the clock gating circuit before conversion, wherein the target circuit design data is part of the circuit design data of the clock gating circuit before conversion;

[0261] The power consumption benefit prediction model selection module 82 is used to select a power consumption benefit prediction model, and use the power consumption benefit prediction model to predict the power consumption benefit of the clock gating circuit before conversion based on the target circuit design data to obtain a power consumption benefit prediction result; the power consumption benefit prediction model is used to predict the power consumption change trend between the clock gating circuit before conversion and the clock gating circuit after conversion to form a power consumption benefit prediction result;

[0262] If it is determined that the power consumption benefit prediction result is a positive power consumption benefit, the clock gating circuit before conversion is converted to obtain a clock gating circuit after conversion.

[0263] The power consumption benefit prediction model selection module 82 selects to use the power consumption benefit prediction module. After calculating the power consumption benefit prediction result, it can not only avoid meaningless conversion of the clock gating circuit before the conversion, but also provide the designer with information about the increased power consumption of the clock gating circuit after the conversion, so that the designer can optimize the clock gating circuit before the conversion.

[0264] It can be seen that the technical solution provided by the embodiment of the present invention, before converting the clock gating circuit before conversion to the clock gating circuit after conversion, uses the power consumption benefit prediction model in advance to predict the power consumption benefit of the clock gating circuit before conversion, and obtains the power consumption benefit prediction result. Since the power consumption benefit prediction model is used to predict the power consumption change trend between the clock gating circuit before conversion and the clock gating circuit after conversion. Therefore, it can be judged whether the clock gating circuit before conversion needs to be converted according to the power consumption benefit prediction result formed by the power consumption benefit prediction model; if it is determined that the power consumption benefit prediction result corresponding to the clock gating circuit before conversion is a positive power consumption benefit, that is, it indicates that the power consumption of the gated circuit after conversion can produce a positive effect (the power consumption of the clock gating circuit after conversion is reduced), then the clock gating circuit before conversion of the target is converted. Since the input data of the power consumption benefit prediction model is part of the design data in the circuit design data of the clock gating circuit before conversion (that is, the target circuit design data), the calculation amount of obtaining the power consumption benefit prediction result can be reduced, and the complex calculation process of calculating the power consumption of the clock gating circuit after conversion and the power consumption of the clock gating circuit before conversion can be avoided, and the calculation difficulty of obtaining the power consumption benefit prediction result can be reduced. Thus, it is possible to quickly determine whether a clock gating circuit before conversion can generate positive power consumption benefits when converted to a clock gating circuit after conversion, thereby improving the efficiency of determining the effectiveness of the conversion of the clock gating circuit.

[0265] An embodiment of the present invention provides an electronic device, such as a terminal device, a server device, or other computer device, including a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the clock gating circuit conversion method as described in any of the aforementioned embodiments.

[0266] An embodiment of the present invention provides a storage medium, wherein the storage medium stores a program, and when the program is executed, the clock gating circuit conversion method as described in any of the above embodiments is implemented.

[0267] An embodiment of the present invention provides a computer program product, including a computer program. When the computer program is executed by a processor, the clock gating circuit conversion method as described in any one of the above embodiments is implemented.

[0268] The above describes multiple implementation schemes provided by the embodiments of the present invention. The various optional methods introduced in the implementation schemes can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present invention.

[0269] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A clock gating circuit conversion method, characterized in that: include: Acquire target circuit design data of the clock gating circuit before conversion, wherein the target circuit design data is part of the circuit design data of the clock gating circuit before conversion; Using a pre-established power consumption benefit prediction model, based on the target circuit design data, the power consumption benefit of the clock gating circuit before conversion is predicted to obtain a power consumption benefit prediction result; wherein the power consumption benefit prediction model is used to predict the power consumption change trend between the clock gating circuit before conversion and the clock gating circuit after conversion to form a power consumption benefit prediction result; If it is determined that the power consumption benefit prediction result is a positive power consumption benefit, the clock gating circuit before conversion is converted to obtain a clock gating circuit after conversion.

2. The clock gating circuit conversion method according to claim 1, characterized in that: It also includes: establishing a power consumption benefit prediction model based on the power consumption benefit calculation principle; The power consumption benefit prediction model is established based on the power consumption benefit calculation principle, including: According to the power consumption benefit calculation principle, a power consumption change trend relationship between the power consumption of the clock gating circuit before conversion and the power consumption of the clock gating circuit after conversion is constructed to obtain an initial power consumption benefit prediction model; Normalizing the initial power consumption benefit prediction model using power consumption trend non-influence data in the non-target circuit design data to obtain a power consumption benefit prediction model; The non-target circuit design data refers to the design data in the circuit design data other than the target design data; and the power consumption trend-influenced data has no effect on the power consumption change trend of the clock gating circuit before conversion and the clock gating circuit after conversion; the target circuit design data has an effect on the power consumption change trend of the clock gating circuit before conversion and the clock gating circuit after conversion.

3. The clock gating circuit conversion method according to claim 2, characterized in that: The power consumption trend unaffected data is: the clock signal flip rate in the circuit design data of the clock gating circuit before conversion; the target circuit design data is the turn-on level probability of the clock gating enable signal, and the number of drivers determined by the number of timing devices driven by the clock gating signal; The on-level probability is the proportion of the clock being in the on state controlled by the clock gating enable signal within a certain period of time; According to the power consumption benefit calculation principle, a power consumption change trend relationship formula of the clock gating circuit before conversion and the power consumption of the clock gating circuit after conversion is constructed to obtain an initial power consumption benefit prediction model, including: According to the power consumption benefit calculation principle, the power consumption change trend relationship is constructed using the non-target circuit design data, the number of drivers, and the turn-on level probability to obtain an initial power consumption benefit prediction model; The method of utilizing the power consumption trend non-influence data in the non-target circuit design data to normalize the initial power consumption benefit prediction model to obtain the power consumption benefit prediction model includes: Using the clock signal flip rate, normalizing the initial power consumption benefit prediction model to obtain a normalized power consumption change trend relationship; The power consumption benefit prediction model is obtained based on the normalized power consumption change trend relationship.

4. The clock gating circuit conversion method according to any one of claims 1 to 3, characterized in that: Before the step of using the pre-established power consumption benefit prediction model to predict the power consumption benefit of the clock gating circuit before conversion based on the target circuit design data to obtain the power consumption benefit prediction result, the step further includes: Based on the circuit design requirements of the clock gating circuit before the conversion, the coefficients and constants of the target circuit design data in the power consumption benefit prediction model are determined to complete the initialization of the power consumption benefit prediction model.

5. The clock gating circuit conversion method according to any one of claims 1 to 3, characterized in that: Before the step of using the pre-established power consumption benefit prediction model to predict the power consumption benefit of the clock gating circuit before conversion based on the target circuit design data to obtain the power consumption benefit prediction result, the step further includes: extracting non-target circuit design data from the circuit design data of the clock gating circuit before the conversion; The non-target circuit design data is used to determine the coefficients and constants included in the normalized power consumption change trend relationship in the power consumption benefit prediction model, thereby completing the initialization of the power consumption benefit prediction model.

6. The clock gating circuit conversion method according to any one of claims 1 to 3, characterized in that: Also includes: If it is determined that the power consumption benefit prediction result is a negative power consumption benefit or a zero power consumption benefit, the clock gating circuit before the conversion is not converted.

7. The clock gating circuit conversion method according to claim 6, characterized in that: If it is determined that the power consumption benefit prediction result is a positive power consumption benefit, the clock gating circuit before conversion is converted to obtain a clock gating circuit after conversion, including: If the power consumption benefit prediction result indicates that the power consumption change trend of the clock gating circuit before the conversion and the clock gating circuit after the conversion is: the power consumption of the clock gating circuit after the conversion is reduced, then the power consumption benefit prediction result is determined to be a positive power consumption benefit, and the clock gating circuit before the conversion is converted.

8. The clock gating circuit conversion method according to claim 7, characterized in that: If it is determined that the power consumption benefit prediction result is a negative power consumption benefit or a zero power consumption benefit, then the clock gating circuit before the conversion is not converted, including: If the power consumption benefit prediction result indicates that the power consumption change trend of the clock gating circuit before the conversion and the clock gating circuit after the conversion is: the power consumption of the clock gating circuit after the conversion increases or remains the same as the power consumption before the conversion, then the power consumption benefit prediction result is determined to be a negative power consumption benefit or a zero power consumption benefit, and the clock gating circuit before the conversion is not converted.

9. The clock gating circuit conversion method according to any one of claims 1 to 3, characterized in that: The circuit design data of the clock gating circuit before the conversion is the logic circuit connection relationship description information; The step of obtaining target circuit design data of the clock gating circuit before conversion includes: Generate a netlist file based on the logic circuit connection relationship description information, and extract a clock gating enable signal and a valid port of a sequential device driven by the clock gating enable signal based on the netlist file, and obtain the number of sequential devices driven by the clock gating enable signal to determine the number of drives; And, generating a waveform file based on the logic circuit connection relationship description information, and extracting the turn-on level probability of the clock gating enable signal based on the waveform file; The target circuit design data is acquired based on the number of drivers and the turn-on level probability, Or, based on the circuit design requirements of the clock gating circuit before the conversion, the number of timing devices driven by the clock gating enable signal is set to determine the number of drives and the turn-on level probability of the clock gating enable signal, and the target circuit design data is obtained.

10. The clock gating circuit conversion method according to claim 9, characterized in that: The generating of a waveform file based on the logic circuit connection relationship description information comprises: Simulating the logic circuit connection relationship description information to obtain a first waveform file, and converting the first waveform file into a waveform file that passes the unit library netlist; converting the waveform file that passes the unit library netlist into a file that describes a signal flip rate and a level probability to generate the waveform file; Or, a universal cell library netlist is generated based on the logic circuit connection relationship description information, and the universal cell library netlist is simulated to generate a waveform file of the universal cell library netlist; the waveform file of the cell library netlist is converted into a file describing the signal flip rate and level probability to generate the waveform file.

11. A clock gating circuit conversion device, characterized in that: include: A data acquisition module, used to acquire target circuit design data of the clock gating circuit before conversion, wherein the target circuit design data is part of the circuit design data of the clock gating circuit before conversion; A power consumption benefit prediction module, used to use a pre-established power consumption benefit prediction model to predict the power consumption benefit of the clock gating circuit before conversion based on the target circuit design data to obtain a power consumption benefit prediction result; wherein the power consumption benefit prediction model is used to predict the power consumption change trend between the clock gating circuit before conversion and the clock gating circuit after conversion to form a power consumption benefit prediction result; The circuit conversion module is used for converting the clock gating circuit before conversion to obtain the clock gating circuit after conversion if it is determined that the power consumption benefit prediction result is a positive power consumption benefit.

12. The clock gating circuit conversion device according to claim 11, characterized in that: Also includes: A power consumption benefit prediction model establishment module is used to establish a power consumption benefit prediction model based on the power consumption benefit calculation principle; The power consumption benefit prediction model establishment module is used to establish a power consumption benefit prediction model based on the power consumption benefit calculation principle, including: According to the power consumption benefit calculation principle, a power consumption change trend relationship between the power consumption of the clock gating circuit before conversion and the power consumption of the clock gating circuit after conversion is constructed to obtain an initial power consumption benefit prediction model; Normalizing the initial power consumption benefit prediction model using power consumption trend non-influence data in the non-target circuit design data to obtain a power consumption benefit prediction model; The non-target circuit design data is design data other than the target design data in the circuit design data; The power consumption trend has no influence on the power consumption change trend of the clock gating circuit before conversion and the clock gating circuit after conversion; the target circuit design data has an influence on the power consumption change trend of the clock gating circuit before conversion and the clock gating circuit after conversion.

13. The clock gating circuit conversion device according to claim 12, characterized in that: The power consumption trend unaffected data is: the clock signal flip rate in the circuit design data of the clock gating circuit before conversion; the target circuit design data is the turn-on level probability of the clock gating enable signal, and the number of drivers determined by the number of timing devices driven by the clock gating signal; The on-level probability is the proportion of the clock being in the on state controlled by the clock gating enable signal within a certain period of time; The power consumption benefit prediction model establishment module is used to construct the power consumption change trend relationship of the clock gating circuit before conversion and the power consumption of the clock gating circuit after conversion according to the power consumption benefit calculation principle, and obtain the initial power consumption benefit prediction model, including: According to the power consumption benefit calculation principle, the power consumption change trend relationship is constructed using the non-target circuit design data, the number of drivers, and the turn-on level probability to obtain an initial power consumption benefit prediction model; The power consumption benefit prediction model establishment module is used to use the power consumption trend non-influence data in the non-target circuit design data to normalize the initial power consumption benefit prediction model to obtain the power consumption benefit prediction model, including: Using the clock signal flip rate, normalizing the initial power consumption benefit prediction model to obtain a normalized power consumption change trend relationship; The power consumption benefit prediction model is obtained based on the normalized power consumption change trend relationship.

14. The clock gating circuit conversion device according to any one of claims 11 to 13, characterized in that: Also includes: The first initialization module is used to determine the coefficients and constants of the target circuit design data in the power consumption benefit prediction model based on the circuit design requirements of the clock gating circuit before the conversion, and complete the initialization of the power consumption benefit prediction model.

15. The clock gating circuit conversion device according to any one of claims 11 to 13, characterized in that: Also includes: A second initialization module, used for extracting non-target circuit design data from the circuit design data of the clock gating circuit before the conversion; The non-target circuit design data is used to determine the coefficients and constants included in the normalized power consumption change trend relationship in the power consumption benefit prediction model, thereby completing the initialization of the power consumption benefit prediction model.

16. The clock gating circuit conversion device according to any one of claims 11 to 13, characterized in that: Also includes: The circuit stop conversion module is used for not converting the clock gating circuit before the conversion if it is determined that the power consumption benefit prediction result is a negative power consumption benefit or a zero power consumption benefit.

17. A simulation device, characterized in that: include: A data analysis module, used for analyzing the clock gating circuit before conversion, and obtaining target circuit design data of the clock gating circuit before conversion, wherein the target circuit design data is part of the circuit design data of the clock gating circuit before conversion; A power consumption benefit prediction model selection module is used to select a power consumption benefit prediction model, and use the power consumption benefit prediction model to predict the power consumption benefit of the clock gating circuit before the conversion based on the target circuit design data to obtain a power consumption benefit prediction result; the power consumption benefit prediction model is used to predict the power consumption change trend between the clock gating circuit before the conversion and the clock gating circuit after the conversion to form a power consumption benefit prediction result; If it is determined that the power consumption benefit prediction result is a positive power consumption benefit, the clock gating circuit before conversion is converted to obtain a clock gating circuit after conversion.

18. An electronic device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the clock gating circuit conversion method according to any one of claims 1 to 11.

19. A storage medium, characterized in that: The storage medium stores a program, and when the program is executed, the clock gating circuit conversion method according to any one of claims 1 to 11 is implemented.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the clock gating circuit conversion method according to any one of claims 1 to 11 is implemented.

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