TRANSISTOR DRIVE DEVICE AND DRIVE METHOD

Description

TECHNICAL FIELD

[0001] The present invention relates, in general, to a driving device comprising a plurality of transistors having the same type of conductivity, and more particularly, transistors of the same type on a fully depleted semiconductor-on-insulator substrate. The present invention also relates to a method for driving this transistor driving device. An advantageous application of this transistor driving device relates to resistive memory circuits of the RRAM type (acronym for "Resistive Random Access Memories"). STATE OF THE ART

[0002] Resistive memories, in particular OxRAM (Oxide-Based Random Access Memories) resistive memories, are currently being developed for non-volatile applications, with the aim of replacing Flash-type memories. One of their advantages is that they can be integrated with the BEOL (Back-End Of Line) process of CMOS (Complementary Metal-Oxide-Semiconductor) technology.

[0003] Resistive memories typically comprise a multitude of memory cells arranged in a matrix. In a so-called "1T1R" configuration, each memory cell (also called a memory point) comprises a resistive memory element ("1R") associated with a selection transistor ("1T").

[0004] The resistive memory element can reversibly switch between two resistance states, which correspond to logic values ​​"0" and "1" used to encode a bit of information.

[0005] Information is written to the memory cell by switching the resistive memory element from a high resistance state (HRS) to a low resistance state (LRS). Conversely, to erase information from the memory cell, the resistive memory element is switched from the low resistance state to the high resistance state.

[0006] In some cases, more than two resistance states can be generated, allowing multiple bits of information to be stored in a single memory cell. These are called multi-level cells (MLCs).

[0007] Writing and erasing these MLC multilevel cells can be achieved by finely controlling, in an analog manner, the voltage applied to the different connections of the memory cell. These connections are known as "bitline" BL (connection to the resistive element), "sourceline" SL (connection to the source of the selection transistor), "wordline" WL (connection to the gate of the selection transistor). Other known writing and erasing solutions consist of varying the duration of the so-called SET / RESET transition operations (transition from HRS to LRS / transition from LRS to HRS, respectively), typically by adjusting the width of the applied voltage pulses. This "analog" management of writing and erasing nevertheless requires new circuits for generating or regulating analog voltages and currents and / or a significant modification of existing circuits.

[0008] Furthermore, the size of a 1T1R memory cell is primarily dictated by the substrate area occupied by the selection transistor, rather than the dimensions of the memory element, the latter being located at the metallization level (BEOL). To increase the density of resistive memories, it is therefore necessary to reduce the area occupied by the selection transistor of each memory cell. This reduction is typically achieved at the expense of the current that the selection transistor is capable of delivering. The programming window of the memory cell is therefore reduced. One solution is to apply a bias to the back of the transistor (a technique called BB for "back-biasing" in English), which allows dynamic modulation of the threshold voltage of the transistor and therefore its capacity to supply current.Forward back-bias (FBB) of the selection transistor generally reduces the threshold voltage and increases the through-current, for example during a memory cell write operation. Reverse back-bias (RBB) of the selection transistor typically limits current leakage, for example during a memory cell read operation. Different architectures implementing RBB bias have been developed. The document "Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications embedding 16MB Phase Change Memory, F. Arnaud et al, IEDM18-424 (2018)" describes a memory cell architecture based on complementary transistors on a fully depleted silicon-on-insulator (FDSOI) substrate.The implementation of BB biasing remains limited and partly ineffective in this type of architecture. Memory cells in particular exhibit inconsistent performance with this type of architecture. Document FR2975828 A1 discloses another architecture for driving NMOS and PMOS transistors requiring a ground plane interposed between the active layer and the isolation wells implanted in the substrate. In this type of architecture, the threshold voltage of the transistor remains limited. It is not possible to perform MLC programming of memory cells via this architecture.

[0009] There is therefore a need to increase the passing current while limiting current leakage, in a homogeneous manner for all the memory cells, and thus enable MLC programming and / or a reduction in the size of the memory cells.

[0010] An objective of the present invention is to meet this need, and to at least partially overcome the drawbacks mentioned above.

[0011] Other objects, features, and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY

[0012] To achieve this objective, according to a first aspect, a transistor driving device according to independent device claim 1 is provided.

[0013] Thus, unlike the known transistor architecture disclosed in the document "Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications embedding 16MB Phase Change Memory, F. Arnaud et al, IEDM18-424 (2018)", the device according to the present invention only comprises transistors having a single type of conductivity, typically an N-type conductivity. This makes it possible to increase the performance of all the transistors by applying, for example, a single first bias voltage in a FBB "forward back bias" configuration via the bias circuit. On the contrary, in the known architecture comprising complementary N-type and P-type transistors, by biasing all the transistors in FBB with a single potential, some will be accelerated and others slowed down, which limits the overall performance gain.To partially overcome this drawback, a solution proposed by the document “Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications embedding 16MB Phase Change Memory, F. Arnaud et al, IEDM18-424 (2018)” consists of using transistors and wells associated with these transistors having the same type of conductivity, according to an architecture known as “flip well”. On the contrary, in the device according to the present invention, the transistors and their associated wells have two different types of conductivity.

[0014] The device according to the present invention also makes it possible to limit current leaks from all of the transistors by applying a first bias voltage in “reverse back bias” RBB configuration via the bias circuit.

[0015] Thus, the device according to the present invention makes it possible to obtain good homogeneity of the performances of the transistors. It allows operation of the transistors in FBB or in RBB with a single architecture, depending on the first bias voltage applied. According to a particular example, for driving RRAM type memories, the device makes it possible to use only N-type selection transistors, typically NMOS transistors. The device also makes it possible to apply an FBB or RBB bias as desired, without it being necessary to take into account the presence of PMOS transistors as in the prior art.

[0016] The use of at least one second voltage-controlled box allows dynamic isolation of the first boxes from each other. The range of possible values ​​for the first BB bias voltage can thus be extended. This allows in fineto modify the threshold voltages of the transistors more strongly or more significantly. In the case of a decrease in threshold voltages, the performance of these transistors increases. The size of the transistors can thus be reduced. This also makes it possible to reduce the current leakage of the transistors in native BB, i.e. without FBB. The static consumption of the device is thus reduced.

[0017] Typically, the variation in the potential of the second well does not modify the conductivity of the transistor(s) located on the first well(s). The second well makes it possible in particular to isolate the first wells from each other and from the substrate. The variation in the potential of the second well advantageously makes it possible to double the potential range of the first well.

[0018] According to another aspect, a method of driving the transistor driving device is provided, comprising: At a first time t1: Applying a first bias voltage V1 to at least one first box of the plurality of first boxes, Applying a second bias voltage V2 to the at least one second box surrounding said at least one first box.

[0019] Said applications of the first and second voltages V1, V2 are such that there is no electrical conduction between said at least one first and second box.

[0020] At a second time t2: Applying a third bias voltage V3 to at least one first well (21) of the plurality of first wells, Applying a fourth bias voltage V4 to the at least one second well (22) surrounding said at least one first well (21), said third and fourth voltages V3, V4 being different from V1 and / or V2.

[0021] The second box thus plays the role of electrical insulation between the first boxes.

[0022] This dynamic isolation of the first wells from each other, controlled via the bias circuit, advantageously makes it possible to extend the range of possible values ​​for the first bias voltage BB. This extended range of values ​​typically makes it possible to envisage MLC programming when the transistors are selection transistors associated with resistive elements and forming with said resistive elements 1T1R memory cells. Unlike the prior art, it is possible to apply different electrical potentials to the first and second wells of the device according to the invention. The bias voltages applied to the first and second wells can vary over time. This dynamic biasing of the first and second wells makes it possible to envisage MLC multilevel programming. According to one aspect, the device makes it possible to associate an FDSOI type circuit and RRAM type memories.This improves both the programming and performance of RRAM type memories (lower consumption, access to multi-level MLC, etc.).

[0023] Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated. In particular, certain features and advantages of the piloting device may apply mutatis mutandis to the process of controlling this device, and vice versa. BRIEF DESCRIPTION OF THE FIGURES

[0024] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of embodiments thereof which are illustrated by the following accompanying drawings in which: There Figure 1schematically illustrates in cross-section a transistor control device, according to an embodiment of the present invention. The Figure 2 schematically illustrates in top view a transistor driving device, according to an embodiment of the present invention. The Figure 3 schematically illustrates in top view a transistor driving device, according to another embodiment of the present invention. The Figure 4 illustrates an electrical diagram of a memory cell, according to an embodiment of the present invention. The Figure 5 is a graph illustrating different resistance levels of the transistor (when it is on) obtained in the context of MLC programming, according to an embodiment of the present invention.

[0025] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily to the scale of practical applications. In particular, on the schematic diagrams, the thicknesses of the different layers and portions, and the dimensions of the patterns are not representative of reality. DETAILED DESCRIPTION

[0026] Before commencing a detailed review of embodiments of the invention, optional features that may optionally be used in combination or alternatively are set forth below: According to one example, the at least one second box comprises a plurality of second boxes separated from each other by the substrate, each second box being associated with, and disposed under and around, a first box of the plurality of first boxes.

[0027] In one example, the transistors are separated from each other by isolation trenches of a single type, typically shallow trenches known by the acronym STI (standing for "Shallow Trench Isolation"). This simplifies the device design, compared to a device using two types of isolation trenches, typically shallow trenches STI and deep trenches known by the acronym DTI (standing for "Deep Trench Isolation").

[0028] According to one example, the transistors are selection transistors, the device further comprising a resistive element associated with each selection transistor and forming with said selection transistor a memory cell (1T1R).

[0029] In one example, all of the plurality of transistors are MOS transistors.

[0030] According to one example, the second conductivity type is N-type. The selection transistors are thus preferably NMOS transistors.

[0031] In one example, all transistors are N-type MOS transistors, and the second bias voltage V2 is between 0V and 6V.

[0032] In an example, the first bias voltage V1 is between -6V and +6V.

[0033] According to one example, the second bias voltage V2 is greater than or equal to the first bias voltage V1.

[0034] According to an example, the first bias voltage V1 is such that V2 - 6 ≤ V1 ≤ V2.

[0035] According to one example, the transistors are selection transistors, the device further comprising a resistive element associated with each selection transistor and forming with said selection transistor a memory cell (1T1R), the method further comprising: Applying a fixed control voltage to at least some of the selection transistors, so as to select certain memory cells associated with said selection transistors, and Varying the first bias voltage V1 of certain first wells underlying said selected memory cells, according to at least three distinct bias values ​​so as to create at least three distinct levels of resistance of the selection transistor for said selected memory cells.

[0036] According to one example, the transistors are selection transistors, the device further comprising a resistive element associated with each selection transistor and forming with said selection transistor a memory cell (1T1R), the method further comprising: Setting the second bias voltage V2 of the at least one second well, Varying the first bias voltage V1 of certain first wells underlying the selection transistors, according to at least three distinct bias values ​​so as to create at least three distinct resistance levels of the selection transistor for the memory cells associated with said first wells. The bias voltage V2 typically takes a fixed value, for example 0V, 3V, 6V, for a time typically corresponding to the duration of an elementary programming operation (for example the coding of a bit). This value can then evolve towards another fixed value, for another elementary programming operation for example.

[0037] Unless incompatibility exists, it is understood that all of the above optional features may be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention.

[0038] It is specified that, in the context of the present invention, the terms "on", "overcomes", "covers", "underlying", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0039] A layer can also be composed of several sub-layers of the same material or of different materials.

[0040] A substrate, a stack, a layer, "based" on a material A, means a substrate, a stack, a layer comprising this material A only or this material A and possibly other materials, for example alloying elements and / or doping elements. Thus, a silicon-based layer means, for example, a Si, n-doped Si, p-doped Si, SiGe layer.

[0041] Several embodiments of the invention implementing successive steps of the control method are described below. Unless explicitly stated, the adjective “successive” does not necessarily imply, even if this is generally preferred, that the steps follow one another immediately, intermediate steps being able to separate them.

[0042] Furthermore, the term "step" means the carrying out of a part of the process, and can designate a set of sub-steps.

[0043] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may in particular be followed by actions linked to a different step, and other actions of the first step may be repeated subsequently. Thus, the term "step" does not necessarily mean actions that are unitary and inseparable in time and in the sequence of phases of the process.

[0044] A preferably orthonormal reference frame, comprising the x, y, z axes, is shown in the attached figures. When only one reference frame is shown on the same sheet of figures, this reference frame applies to all the figures in this sheet.

[0045] In the present patent application, the thickness of a layer is taken along a direction normal to the main extension plane of the layer. Thus, a layer typically has a thickness along z. The relative terms "on", "overcomes", "under", "underlying", "intercalated" refer to positions taken along the z direction.

[0046] The terms "vertical" and "vertically" refer to a direction along z. The terms "horizontal", "horizontally", "lateral", "laterally" refer to a direction in the xy plane. Unless explicitly stated, thickness, height and depth are measured along z.

[0047] An element located "perpendicular to" or "in line with" another element means that these two elements are both located on the same line perpendicular to a plane in which a lower or upper face of a substrate mainly extends, that is to say on the same line oriented vertically in the figures.

[0048] In the following embodiments, the driving device and the driving method are illustrated in particular for driving memory cells of the 1T1R type, typically comprising a transistor and a resistive element in series. The invention is not limited to memory cells. Any electronic device based on transistors of the same type can be implemented in the driving device and / or the driving method according to the present invention.

[0049] In the following embodiments, the first well(s) are preferably PWells. The second well(s) are preferably Deep NWells and / or NWells. The substrate is preferably P-type (Psub). The transistors are preferably NMOS. It is understood that the conductivity types may be reversed relative to each other, according to another embodiment of the present invention.

[0050] There Figure 1 illustrates an embodiment of the transistor driving device.

[0051] The transistors 20 are here typically FDSOI type MOS transistors with a back gate, also called ultra-thin body and buried oxide transistors or UTBB (for "Ultra Thin Body and BOX" in English). This type of MOS transistor is manufactured from an SOI substrate successively comprising along z a silicon substrate 10, an electrically insulating layer 11 called buried, generally an oxide layer (or BOX layer, for "buried oxide layer" in English), and a thin layer 12 of monocrystalline silicon, also called active layer. The particularity of the UTBB FDSOI transistor is that the BOX layer 11 is extremely thin, typically with a thickness e 11 of less than 30 nm, which makes it possible to apply a bias to the rear face of the transistor 20. The thickness e 12 of the thin layer 12 of monocrystalline silicon is typically less than 10 nm.

[0052] The transistors 20 have a channel 12c formed in the active layer 12, under the gate of the transistors 20. This channel 12c is configured to operate in a so-called “fully depleted” mode, in the blocked state of the transistor. The active layer 12 is typically intentionally undoped.

[0053] The transistors 20 of the device 1 all have the same type of conductivity, preferably an N-type conductivity (the majority charge carriers are electrons).

[0054] The device 1 also comprises at least one first well 21 having a conductivity type opposite to the conductivity type of the transistors 20. In this example, the well 21 is of type P. Such a P-type well can be called “PWell” according to the usual terminology. This first well 21 typically makes it possible to apply a bias V1 to the rear face of the transistor(s) 20. This bias V1 makes it possible to lower or increase the threshold voltage of the transistors 20, which can then respectively deliver more or less current. It is generally advantageous for the transistor to deliver more current in the on state, and less leakage current (in the off state).

[0055] The device 1 comprises a biasing circuit configured to apply this first biasing voltage V1 to the first well 21, via a first contact 31.

[0056] In order to increase the bias voltage range V1, the device 1 comprises a second well 22 surrounding the first well V1. The second well 22 typically extends under the first well 21, and laterally borders the first well 21. The second well 22 is configured to electrically insulate the first well 21 from the substrate 10. The second well 22 has a conductivity type opposite to the conductivity type of the first well 21. In this example, the well 22 is of type N, like the transistors 20. Such an N-type well 22 may comprise a portion extending under the first well 21 called “Deep NWell” according to the usual terminology, and a portion laterally surrounding the first well 21 called “NWell”. The Deep NWell portion of the well 22 typically makes it possible to ensure deep insulation of the first well 21, typically from the substrate 10.The NWell portion of the box 22 typically provides lateral insulation of the first box 21, typically from another adjacent first box 21. The second box 22 is typically formed by an NWell and a Deep NWell. In the following, the second box 22 is indifferently called “NWell” or “Deep NWell”, without this necessarily limiting it to one or other of the parts of said box.

[0057] A first diode 211 PN is thus formed between the first well 21 and the second well 22. A second diode 212 PN is thus formed between the substrate 10 and the second well 22.

[0058] Advantageously, a second bias voltage V2 can be applied to this second well 22 via a second contact 32 of the bias circuit. This second bias voltage V2 is typically between 0V and 6V, which makes it possible to keep the PN diode 212 in the blocking state. For a silicon-based PN diode 212, the current increases significantly above 6V (or below -6V for a reverse-biased diode), according to a typical Zener diode characteristic. The P-type substrate 10 is typically biased at 0V.

[0059] The bias voltage range V1 for keeping the PN diode 211 in the blocking state is advantageously increased by varying the second bias voltage V2. For diodes 211, 212 of substantially the same nature, the bias voltage range V1 is typically between -6V and +6V. For example, for V2 = 0V, the bias voltage V1 may be between -6V and 0V. This corresponds to an RBB bias of the NMOS transistors 20. For V2 = 3V, the bias voltage V1 may be between -3V and +3V. For V2 = 6V, the bias voltage V1 may be between 0V and +6V. This corresponds to an FBB polarization of the NMOS 20 transistors. The bias voltage range V1 allowing the NMOS 20 transistors to be biased on the rear face (BB) is thus significantly doubled by the addition of the Deep NWell 22 controlled by voltage V2.

[0060] The control of the second box 22 is preferably carried out so as to maintain the blocking state of the diodes 211, 212. According to one possibility, the bias voltages V1, V2 are applied via the bias circuit such that V1 ≤ V2.

[0061] As shown in the Figure 1, the device 1 may also comprise isolation trenches 23 on either side of the transistors 20 and the contacts 31, 32. These isolation trenches 23 are preferably shallow isolation trenches called STI (for "Shallow Trench Isolation" in English). Preferably, the device 1 comprises only STI 23 between the transistors 20 and the contacts 31, 32. In particular and advantageously, the device 1 does not require the use of other types of isolation trenches, in particular deep isolation trenches called DTI (for "Deep Trench Isolation" in English), to extend the bias voltage range V1 (BB ​​bias). The trench isolation technology is thus simplified, and the associated cost remains low compared to technologies using two depths of STI and / or DTI.

[0062] There Figure 2illustrates an embodiment in which eight first wells 21a, 21b, 21c, 21d, 21e, 21f, 21g, 21h are isolated from each other by a second well 22. The first wells 21a, 21b, 21c, 21d, 21e, 21f, 21g, 21h are preferably PWells. The second well 22 is preferably a Deep NWell. The substrate 10 is preferably of type P.

[0063] For an RRAM or OxRAM type application, each of the first eight boxes may comprise a plurality of memory cells arranged in the form of lines. Each first box comprises, for example, 8 lines.

[0064] Each first well can be biased separately from the other first wells, via a dedicated biasing circuit. Thus, a first well 21 biased so as to apply an FBB back bias to the selection transistors typically corresponds to a memory cell programming operation (writing or erasing, SET / RESET). The memory cells formed on this first well are said to be “selected”.

[0065] The memory cells formed on a first well 21 biased so as to apply an RBB back bias to the selection transistors, are typically “unselected”, or selected in read only mode.

[0066] It is thus possible to program the memory cells of the lines formed on the box 21a, in FBB configuration over an extended range of values ​​V1, V2, while maintaining the memory cells of the lines formed on the boxes 21b, 21c, 21d, 21e, 21f, 21g, 21h in RBB configuration over an extended range of values ​​V1, V2.

[0067] This allows, for example, to reduce the threshold voltage of the selection transistors (wordline connection) for writing or erasing, in FBB configuration. The threshold voltage of the selection transistors (wordline connection) for reading can also be reduced, in RBB configuration. The static consumption of the non-selected lines can also be reduced, in RBB configuration.

[0068] The extended value ranges in RBB (-6V to 0V) and FBB (0V to +6V) advantageously allow reading and writing several bits of information within a memory cell, as described in more detail below.

[0069] There Figure 3 illustrates another embodiment in which the first boxes 21, 21a, 21b, 21c, 21d, are distributed in different second boxes 22, 22a, 22b, 22c, 22d. In this example, each first box 21 is associated with a second box 22. Other configurations are conceivable, for example four first boxes 21 distributed within two second boxes 22.

[0070] The second wells 22a, 22b, 22c, 22d are separated and isolated from each other by the substrate 10. The separation distance ds between two adjacent second wells 22a, 22b is of the order of a few micrometers, for example 3 µm. This makes it possible to polarize the second wells 22 independently. The possibilities of applying different FBB and RBB polarizations are increased. Thus, for example, the first well 21a PWell is polarized at -6V and the second well 22a Deep NWell is polarized at 0V. This makes it possible to generate an RBB polarization limiting or eliminating current leaks. The memory cells associated with the well 21a are not selected. The first well 21b PWell is for example polarized at +6V and the second well 22b Deep NWell is polarized at +6V. This makes it possible to generate an FBB bias reducing the threshold voltage of the selection transistors, for write or erase operations for example.The bias voltages V2 are thus applied independently of each other via the bias circuit. The versatility of the device 1 is increased. The biases V1, V2 of the first and second wells 21, 22 can vary dynamically depending on the memory accesses for example. The application of the bias voltages V1, V2 is typically controlled by the bias circuit of the device 1. The number of RBB and / or FBB bias configurations of the different memory cells is thus increased. The extended value ranges in RBB (-6V to 0V) and in FBB (0V to +6V) also make it possible to implement easier MLC programming of the memory cells.

[0071] There Figure 4 illustrates an electrical diagram of a memory cell mounted on a first PWell box isolated from the substrate by a second Deep NWell box, according to a principle of the invention.

[0072] Advantageously, the MLC programming of the memory cells can be implemented by controlling the back bias (BB) by the bias voltage V1, the range of values ​​of which is extended by varying V2. In particular, the control of the back bias BB makes it possible to control the threshold voltage of the transistor and therefore the resistance R between the source and the drain of the transistor (1T) which acts as a current limiter, in particular in a memory SET operation. If the resistance R of the transistor is reduced, the current passing increases. This makes it possible to reinforce the SET operation.

[0073] As shown in the Figure 5, the variation of bias voltage V1 (BB) introduces a variation of the resistance R of the transistor and therefore of the resistive element of the RRAM memory. It is thus possible to access 3 or more levels of RRAM resistance each coding for distinct bits of information. In the example illustrated, for 3 values ​​of V1 included in the range of values ​​between -3V and +3V, V2 being fixed at +3V, 3 levels of resistance R1, R2, R3 are obtained. By extending the range of values ​​of V1, for example between -6V and +6V, the number of permitted resistance levels increases.

[0074] The use of a dual voltage-controlled PWell / Deep NWell well for FDSOI NMOS transistors advantageously allows the threshold voltages of these transistors to be significantly modified. The overall energy efficiency is improved. Such a dual voltage-controlled well also makes it possible to consider the implementation of MLC for memory cells based on a single type of transistor. The surface area occupied by these memory cells, each storing more than one bit of data, can thus be significantly reduced.

[0075] The invention is not limited to the embodiments previously described.

Claims

1. Transistor driving device (1) comprising: - A substrate (10) with the basis of a semiconductive material (10), having a first type of conductivity (P), - An insulating layer (11) with the basis of a dielectric material on said substrate (10), - A semiconductive material-based layer (12), called active layer, located on the insulating layer (11), - A plurality of transistors (20), each comprising a channel (12c) formed in the active layer (12) and configured to be completely depleted, - A plurality of first chambers (21, 21a, 21b, 21c, 21d, 21e, 21f, 21g, 21h) formed in the substrate (10) and having the first type of conductivity (P), each first chamber (21) being associated with and disposed under a group of transistors of the plurality of transistors (20), - At least one second chamber (22, 22a, 22b, 22c, 22d) having a second type of conductivity (N), formed in the substrate (10) under and around the first chambers (21), so as to insulate the first chambers (21) from one another and regarding the substrate (10), said at least one second chamber (22, 22a, 22b, 22c, 22d) comprising one or more first chambers (21), each only having the first type of conductivity (P), - A bias circuit, configured to apply at least one first bias voltage V1 to the first chambers (21), and at least one second bias voltage V2 to the at least one second chamber (22), All the transistors (20) of the plurality of transistors having the second type of conductivity (N), the device (1) being characterised in that the first chambers (21) are directly in contact with the insulating layer (11) and do not comprise conductivity regions which are different from the first type of conductivity (P), such that the substrate (10) does not comprise a ground plane within a first chamber (21).

2. Device (1) according to the preceding claim, wherein the at least one second chamber (22) comprises a plurality of second chambers (22a, 22b, 22c, 22d) separated from one another by the substrate (10), each second chamber (22, 22a, 22b, 22c, 22d) being associated with and disposed under and around a first chamber (21, 21a, 21b, 21c, 21d) of the plurality of first chambers.

3. Device (1) according to any one of the preceding claims, wherein the transistors (20) are separated from one another by insulating trenches (23) of one single type (STI).

4. Device (1) according to the preceding claim, wherein the insulating trenches (23) completely pass through the active layer (12) and do not completely pass through the first chambers (21) of the plurality of first chambers (21, 21a, 21b, 21c, 21d, 21e, 21f, 21g, 21h).

5. Device (1) according to any one of the preceding claims, wherein the transistors (20) are selection transistors, the device (1) further comprising a resistive element (1R) associated with each selection transistor and forming a memory cell (1T1R) with said selection transistor.

6. Device (1) according to any one of the preceding claims, wherein all the transistors (20) of the plurality of transistors are MOS transistors, and wherein the second type of conductivity is of the N type.

7. Method for driving a transistor driving device (1) according to any one of the preceding claims, comprising: At a first time t1: - Applying a first bias voltage V1 to at least one first chamber (21) of the plurality of first chambers, - Applying a second bias voltage V2 to the at least one second chamber (22) surrounding said at least one first chamber (21), Said applications of the first and second voltages V1, V2 being such that there is no electrical conduction between said at least one first and second chambers (21, 22), At a second time t2: - Applying a third bias voltage V3 to at least one first chamber (21) of the plurality of first chambers, - Applying a fourth bias voltage V4 to the at least one second chamber (22) surrounding said at least one first chamber (21), said third and fourth voltages V3, V4 being different from V1 and / or from V2.

8. Method according to the preceding claim, wherein all the transistors (20) are N-type MOS transistors, and wherein the second bias voltage V2 is between 0V and 6V.

9. Method according to any one of the two preceding claims, wherein the first bias voltage V1 is between -6V and +6V.

10. Method according to any one of the three preceding claims, wherein the second bias voltage V2 is greater than or equal to the first bias voltage V1.

11. Method according to any one of claims 7 to 10, wherein the first bias voltage V1 is such that V2 - 6 ≤ V1 ≤ V2.

12. Method according to any one of claims 7 to 11, wherein the transistors (20) are selection transistors, the device (1) further comprising a resistive element (1R) associated with each selection transistor, and forming a memory cell (1T1R) with said selection transistor, said method further comprising: - Applying a fixed control voltage to at least some of the selection transistors, so as to select certain memory cells associated with said selection transistors, and - Making the first bias voltage V1 of some first chambers (21) underlying said selected memory cells vary, according to at least three distinct bias voltages, so as to create at least three distinct levels of resistance of the selection transistor (R1, R2, R3) for said selected memory cells.

13. Method according to any one of claims 7 to 11, wherein the transistors (20) are selection transistors, the device (1) further comprising a resistive element (1R) associated with each selection transistor, and forming a memory cell (1T1R) with said selection transistor, said method further comprising: - Fixing the second bias voltage V2 of the at least one second chamber (22), - Making the first bias voltage V1 of some first chambers (21) underlying the selection transistors vary, according to at least three distinct bias values, so as to create at least three distinct levels of resistance of the selection transistor (R1, R2, R3) for the memory cells associated with said first chambers.