Method for producing a carrier substrate with a charge capture layer

Description

FIELD OF THE INVENTION

[0001] The present invention relates to a method for preparing a support substrate comprising a charge trapping layer. It also relates to a method for transferring a thin layer onto such a support substrate to form a composite substrate. These support and composite substrates find notable application in the field of integrated radiofrequency devices, i.e. electronic devices processing signals whose frequency is between approximately 3kHz and 300GHz, for example in the field of telecommunications (telephony, Wi-Fi, Bluetooth, etc.). TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] To protect against or limit the electromagnetic coupling phenomenon that can occur between an electronic device and the support substrate of a silicon-on-insulator (SOI) substrate on which this device is formed, it is known to insert a charge trapping layer between the buried dielectric layer and the SOI support, directly under the dielectric layer. This layer can consist, for example, of a 0.1 to 10 micron layer of polycrystalline silicon formed on a base substrate of monocrystalline silicon which is often chosen to be highly resistive (i.e., having a resistivity greater than 500 ohms.cm, or even greater than 1000 ohms.cm). The grain boundaries forming the polycrystal then constitute traps for charge carriers, which can come from the trapping layer itself or from the underlying substrate. In this way, the appearance of a conductive plane under the insulator is prevented.The manufacture of this type of well-known SOI substrate is for example described in documents FR2860341, FR2933233, FR2953640, US2015115480, US7268060, US6544656 or WO2020008116.

[0003] To promote the creation and avoid the recrystallization of the charge trapping layer formed on the base substrate of monocrystalline silicon, it is known to form on this base substrate, and before the formation by deposition of the trapping layer, a layer of amorphous dielectric, typically a layer of silicon dioxide. The layer of amorphous dielectric makes it possible to preserve the polycrystalline character of the trapping layer by avoiding its recrystallization when the stack is brought to temperature.

[0004] Document EP3136421 thus proposes to form a polycrystalline silicon trapping layer on a base substrate having a resistivity of 700 Ohms-cm. The base substrate is oxidized by simple cleaning or by dry oxidation. Then the trapping layer is formed in two successive deposition steps using a trichlorosilane precursor gas. The first step aims to form a seed layer at a relatively low temperature, below 1010°C, directly on the silicon oxide layer, and the second step is carried out at a temperature higher than the first. According to this document, this approach makes it possible to form the trapping layer quickly, and without excessively deforming the base substrate, which could prevent assembly by molecular adhesion of this substrate when it is intended to form a support substrate for a silicon-on-insulator substrate.

[0005] Document EP2503592 provides for the production of such a trapping layer "in situ". In this document, the trapping layer is formed on a dielectric layer of a silicon base substrate without removing the base substrate from the equipment used to form this stack. This may be a chamber of an epitaxy frame.

[0006] In this approach, the base substrate is placed in the chamber of the equipment, and an oxidizing gas is circulated in this chamber to superficially form the dielectric layer during an oxidation step carried out at a temperature of the order of 1100°C. Then, without removing the base substrate from the chamber, a carrier gas is circulated to evacuate the oxidizing gas and the temperature of the chamber and / or the substrate is brought to a relatively low deposition temperature, of the order of 900°C or less.

[0007] When the oxidizing atmosphere has been evacuated by the carrier gas and the deposition temperature has been established, the precursor gas containing silicon is introduced to gradually form, by deposition, the polycrystalline silicon layer on the dielectric layer. By sequencing the introduction of the gases into the chamber in this way, the precursor gas must not be introduced before the oxidizing gas has been evacuated and before the temperature has been well established at the target temperature of approximately 900°C or less, and the premature deposition of polycrystalline silicon which would not have the required qualities is prevented.

[0008] However, the formation of a polycrystalline silicon layer at a relatively low deposition temperature is particularly slow, of the order of 0.3 microns per minute at 900°C. It is indeed well known that the deposition rate generally increases with temperature. To improve this deposition rate, and therefore the manufacturing time of the support provided with the trapping layer, it may be envisaged, as proposed by document EP3136421, to only form a seed portion of the trapping layer at low temperature, the rest of the layer then being able to be formed at a relatively higher temperature, and therefore more quickly.

[0009] Although such an approach does indeed improve the production rate of support substrates, the formation of the seed layer remains a particularly time-consuming step. It is generally desirable to further increase the production rate, without compromising the quality of the support, of course.

[0010] More generally, we are seeking to prepare a support substrate comprising a charge trapping layer more simply, using a process that is simpler to implement and using more available materials.

[0011] FR 3 104 322 A1 discloses a method for preparing a support substrate provided with a charge trapping layer. SUBJECT OF THE INVENTION

[0012] An object of the invention is to provide a method for preparing a support substrate provided with a charge trapping layer that at least partially addresses these problems. More specifically, an object of the invention is to provide a method for preparing a support substrate provided with a charge trapping layer, the implementation time of which, at comparable quality, is reduced in comparison with the methods of the prior art. More precisely still, an object of the invention is to provide a method for preparing a support substrate provided with a charge trapping layer that does not require a seed portion formed at a relatively low temperature of approximately 1010°C or less. BRIEF DESCRIPTION OF THE INVENTION

[0013] In order to achieve this aim, the subject of the invention proposes a method for preparing a support substrate provided with a charge trapping layer. The method comprises introducing a base substrate made of monocrystalline silicon having a resistivity less than or equal to 500 ohm.cm into a chamber of a deposition equipment and, without extracting the base substrate from the chamber and while sweeping the chamber using a precursor gas, the following successive steps: forming an intrinsic silicon epitaxial layer on the base substrate by introducing a silicon-containing precursor gas into the chamber for a determined period of time; forming a dielectric layer on an exposed face of the intrinsic silicon epitaxial layer by introducing a reactive gas into the chamber during a first period of time; forming a polycrystalline silicon charge trapping layer directly on the dielectric layer by introducing a silicon-containing precursor gas into the chamber during a second period of time, subsequent to the first.

[0014] According to the invention, the time during which the dielectric layer is exposed only to the carrier gas, between the first time period and the second time period, is less than 30 seconds. According to the invention also, the step of forming the charge trapping layer is carried out at a temperature strictly between 1010°C and 1200°C.

[0015] By limiting the duration of exposure of the dielectric layer to the carrier gas alone, between the first time period and the second time period, the surface state of this layer is conditioned or maintained to make it particularly suitable for receiving a polycrystalline silicon layer of quality, identical to that obtained at a much lower temperature in an approach in accordance with the state of the art. This surprising result makes it possible to grow, at equal quality, the trapping layer with a high growth rate, and therefore to form a support substrate at an improved rate, in comparison with an approach in accordance with the state of the art.

[0016] According to other advantageous and non-limiting characteristics of the invention, taken alone or in any technically feasible combination: the carrier gas comprises, or consists of, hydrogen; the precursor gas containing silicon is chosen from the list consisting of silane, disiliane, trichlorosilane, dicholorosilane and silicon tetrachloride; the method comprises, before the step of forming the epitaxial layer of intrinsic silicon, a step of annealing the base substrate in a neutral or reducing atmosphere, at a temperature between 900°C and 1200°C, to remove a native oxide possibly present on the surface; the formation of the epitaxial layer of intrinsic silicon on the base substrate is carried out at an epitaxy temperature between 900°C and 1200°C; the step of forming the epitaxial layer of intrinsic silicon leads to the formation of a layer whose thickness is between 5 and 20 microns; the dielectric layer is made of silicon oxide and the reactive gas comprises between 0.1% and 10% of oxygen in a neutral gas such as argon;the step of forming the dielectric layer is carried out at a temperature between 900°C and 1150°C; the dielectric layer has a thickness greater than 0.5 nm; the step of forming the charge trapping layer is carried out at a temperature greater than 1050°C or 1100°C; the charge trapping layer and the dielectric layer are formed at respective temperatures identical to within 50°C; the time during which the dielectric layer is exposed only to the carrier gas is less than 20 seconds or 15 seconds; the charge trapping layer has a thickness between 0.1 and 10 microns. ; BRIEF DESCRIPTION OF THE FIGURES

[0017] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which: [ Fig. 1 ] There figure 1 represents a support substrate according to one embodiment; [ Fig. 2 ] There figure 2 represents a composite substrate which comprises a support substrate in accordance with the present invention; [ Fig. 3 ] There figure 3 illustrates the succession of the two main stages of a process in accordance with the invention. DETAILED DESCRIPTION OF THE INVENTION

[0018] In reference to the figure 1 , a support substrate 1 of one embodiment comprises a base substrate 2, an intrinsic monocrystalline silicon layer 5 disposed on and in contact with the base substrate 2, a dielectric layer 3 disposed on the intrinsic monocrystalline silicon layer 5 and a charge trapping layer 4 disposed on the dielectric layer 3 and in contact with this layer.

[0019] The support substrate 1 may take the form of a circular plate of standardized dimensions, for example 200 mm or 300 mm, or even 450 mm in diameter. However, the invention is in no way limited to these dimensions or to this form.

[0020] The base substrate 2 is made of monocrystalline silicon and has a thickness of several hundred microns. The base substrate 2 has a relatively low resistivity, less than or equal to 500 ohms.cm, or 100 ohms.cm or less. It can be a standard monocrystalline CZ substrate, whose resistivity is less than 500 ohms.cm. This approach is advantageous, in that such a substrate can be procured easily and at low cost.

[0021] The support substrate 1 also comprises a layer of intrinsic monocrystalline silicon 5, i.e. not intentionally doped and therefore particularly resistive, arranged between (and in contact with) the base substrate 2 and the dielectric layer 3. The layer of intrinsic monocrystalline silicon 5 advantageously has a resistivity greater than 2000 ohm.cm, which can even reach 20 kohm.cm or more. Its thickness can be between 0.5 and 100 microns, and preferably between 5 and 20 microns.

[0022] The dielectric layer 3, for example made of silicon oxide or silicon nitride, has a thickness greater than 0.5 nm, for example between 0.5 nm and 50 nm. This amorphous dielectric layer 3 makes it possible to form the charge trapping layer 4 in a polycrystalline form, and to avoid or limit the recrystallization of this layer, when the support substrate 1 is exposed to a high temperature, during the formation of this layer 4 or during subsequent heat treatments that the support substrate 1 is required to undergo.

[0023] The support substrate 1 also comprises a charge trapping layer 4 made of polycrystalline silicon, arranged on and directly in contact with the dielectric layer 3. The trapping layer 4 has a resistivity greater than 500 ohm.cm, preferably greater than 1 kohm.cm. As mentioned in the introduction to the present application, the trapping layer has the function of trapping the charge carriers that may be present in the support 1 and of limiting their mobility. The charge trapping layer 4 has a thickness typically between 0.1 micron and 10 microns, or even more.

[0024] The trapping layer 4, due to its non-crystalline nature, has structural defects such as dislocations, grain boundaries, amorphous zones, interstices, inclusions, pores defining grains of the layer, etc. These structural defects form traps for charges likely to circulate in the material, for example at the level of incomplete or dangling chemical bonds. This prevents conduction in the trapping layer 4 and the support substrate 1 consequently has high radiofrequency performance. This performance can be established by a characterization measurement called "second harmonic distortion" on a support thus prepared. This measurement is typically carried out at 900 MHz. Generally, the distortion measurement is sought to be less than -70 dB so that the support substrate can be considered to have high radiofrequency performance.

[0025] This characterization measurement, a detailed description of which can be found in the document entitled “White paper - RF SOI wafer characterization” of January 2015, published by Soitec and in document US2015 / 0168326, is particularly relevant because it is very representative of the performance of an integrated RF device which would be formed on a composite substrate incorporating the characterized support substrate.

[0026] The grain size of the polycrystalline silicon trapping layer 4 is advantageously between 50 nm (below which their thermal stability is no longer assured and where there is a risk of their recrystallization at temperature) and 2000 nm (beyond which the RF performance of the support substrate is affected).

[0027] In any case, and whatever the precise characteristics of the grains of the trapping layer 4, it has a high resistivity greater than 500 ohm.cm. To this end, the trapping layer 4 is not intentionally doped, that is to say, it has a charge-carrying dopant concentration of less than 2E13 atoms per cubic centimeter. It can be rich in nitrogen or carbon in order to improve its resistivity characteristic.

[0028] For the sake of completeness, the figure 2represents a composite substrate S which comprises a support substrate 1 according to the present invention. As is very clear from this figure, the composite substrate comprises, on the support substrate 1, a thin film 6 preferably made of crystalline material. For example and without limitation, the thin film 6 can be made of a semiconductor material, such as silicon, or of a piezoelectric material, such as lithium tantalate (LiTaO 3 ) or lithium niobate (LiNbO 3 ).

[0029] The composite substrate S of the figure 2can be formed in many ways from the support substrate 1, but advantageously this formation comprises a step of transferring the thin film 6 onto this support substrate. As is well known per se, this transfer is usually carried out by assembling so-called "main" faces of a donor substrate and the support substrate 1. Provision is generally made to provide at least one of these faces with a dielectric assembly layer 7, typically of silicon oxide, which can be formed by heat treatment or by deposition. The assembly preferably uses bonding by molecular adhesion.

[0030] After this assembly step, the thickness of the donor substrate is reduced in order to form the thin film 6. This reduction step can be carried out by mechanical or chemical thinning. It can also be carried out by fracture at a fragile zone previously introduced into the donor substrate, for example in accordance with the principles of Smart Cut ™ technology.

[0031] Thin film finishing steps 6, such as a polishing step, heat treatment in a reducing or neutral atmosphere or sacrificial oxidation can be chained with the thickness reduction step.

[0032] It is noted that the donor substrate may be a simple substrate, i.e. not comprising integrated devices, or alternatively the donor substrate may have been previously treated in order to produce integrated devices on its surface.

[0033] We now explain the method for preparing the support substrate 1 which was the subject of the previous section of this description.

[0034] The base substrate 2 made of monocrystalline silicon is introduced into a chamber of a deposition equipment.

[0035] This equipment may correspond to epitaxial deposition equipment. It comprises a susceptor arranged in the chamber to receive the base substrate and expose one of these faces to the atmosphere and to the gas flows circulating in the chamber. The susceptor may be mobile, and in particular have a rotational movement to angularly standardize the exposure of the free face of the base substrate 2 to the gas flow. To allow the introduction of these flows and the control of the atmosphere contained in the chamber, the latter is provided with a plurality of inlet ports, and at least one evacuation port. The chamber is also equipped with a device for heating the substrate, the gases and / or the walls of the chamber, for example lamps emitting radiation capable of heating the free surface of the base substrate.A plurality of conduits fluidically connected to the inlet ports of the chamber allows the introduction with a controlled flow rate of the gases allowing the treatment of the base substrate 2. This is in particular a reactive, oxidizing or nitriding gas, a carrier gas for example a mixture of argon and hydrogen, or hydrogen, and a precursor gas containing silicon. This precursor gas can be, for example, silane, disiliane, trichlorosilane, dicholorosilane and silicon tetrachloride. The equipment can naturally be provided with other conduits to introduce other gases into the chamber. The equipment is also provided with a control device configured to control all the parameters (flow rates of the different gases, temperature, pressure, etc.) of the preparation process implemented.

[0036] The method for preparing the support substrate according to the preceding section of the present description comprises a sequence of steps, which are carried out without removing the base substrate 2 from the chamber of the equipment. Consequently, the base substrate is not exposed to any gas or atmosphere other than those introduced or present in the chamber during the entire duration of the preparation method.

[0037] As is well known per se, the carrier gas GPo is introduced into the chamber at a determined flow rate via an inlet port to sweep it throughout the duration of the process for preparing the support substrate 1, and in particular during the two main stages of this process.

[0038] The treatment method firstly comprises, before the first step of forming the dielectric layer 3, a preliminary step of forming the intrinsic silicon epitaxial layer 5 on the base substrate 2, at an epitaxy temperature typically between 900°C and 1200°C, for a determined period of time T0. For this purpose, the carrier and precursor gases containing silicon can be circulated simultaneously in the chamber. Optionally, this preliminary step of forming the intrinsic silicon epitaxial layer 5 can be preceded by a deoxidation annealing of the base substrate in a reducing or weakly reducing atmosphere, at a temperature between 900°C and 1200°C, to remove a native oxide possibly present superficially on the base substrate 2.This annealing can be carried out while only the carrier gas circulates in the chamber, for a duration of several seconds to several minutes, depending on the chosen temperature, in order to eliminate this native oxide.

[0039] Of course, these steps of deoxidation annealing and / or formation of an epitaxial layer are carried out “in situ”, that is to say without extracting the base substrate 2 from the chamber of the equipment and without exposing the free surface of the support 1 being prepared to gases or atmospheres other than those which are introduced or present in the chamber throughout the duration of the process.

[0040] Then, in a first step, and as illustrated in the figure 3the dielectric layer 3 is formed on the exposed face of the epitaxial layer 5 by introducing into the chamber, and with a chosen flow rate, a reactive gas GR, during a first time period T1. The heating device is controlled so that the dielectric layer is formed at a temperature typically between 900°C and 1150°C, and preferably between 950°C and 1100°C. Depending on the nature of the dielectric layer that it is desired to form, silicon dioxide or silicon nitride for example, this reactive gas can be formed from an oxidizing gas or a nitriding gas. Preferably, the dielectric layer is made of silicon oxide, and in this case the reactive gas can for example comprise between 0.1% and 10% oxygen in a neutral gas such as argon. The oxidizing atmosphere of the chamber is maintained for a chosen duration (the first time period) depending on the desired thickness of the dielectric layer 3.Preferably, the dielectric layer 3 has a thickness greater than 0.5 nm.

[0041] Then, in a second step following the first, a charge trapping layer 4 of polycrystalline silicon is formed directly on the dielectric layer 3 by introducing into the chamber, and with a chosen flow rate, the precursor gas GPr containing silicon, during a second time period T2 after the first time period T1. The amorphous nature of the dielectric layer prevents the crystallization of the trapping layer which forms during this second step, which could occur if this dielectric layer were not present.

[0042] The sequence of the first and second stages is carried out in a controlled manner, in order to avoid in particular the mixing of reactive and precursor gases, which could cause unwanted chemical reactions in the chamber and prevent the deposition of a trapping layer of the desired quality. In other words, and as is very visible on the figure 3 , the first step in which the reactant gas forms the chamber atmosphere does not overlap with the second step in which the precursor gas forms the chamber atmosphere.

[0043] At the end of the first step, and during the transition period Tt which separates the end of the first time period from the beginning of the second time period, the carrier gas, which constantly sweeps the chamber throughout the preparation process, expels the reactive gas from the chamber. This transition period is also used to adjust the temperature of the chamber and / or the substrate, in the case where the temperature of the first step is different from the temperature of the second step. In a second step, and after this transition period Tt, the precursor gas is introduced into the chamber. When this gas is introduced into the chamber, the atmosphere and the temperature of this chamber are therefore perfectly adapted to the formation of a high-quality charge trapping layer 4. The carrier gas and the precursor gas circulate simultaneously in the chamber during the remainder of this second process step.

[0044] Conventionally, and as reported in the introduction to the present application, the growth of the trapping layer is carried out, at least on a seed portion in contact with the dielectric layer, at a relatively low temperature of 1010°C or less in order to obtain a layer of satisfactory quality. This quality is measured in particular by measuring second harmonic distortion. It is also measured by the stress in the charge trapping layer 4 which can tend to deform the substrate if it is too great. It is generally sought to limit this deformation (typically a curvature designated by the English term "bow" in semiconductor technology), for a substrate 300 mm in diameter, to less than 200 microns or even less than 100 microns.

[0045] However, and surprisingly, the inventors of the present application have observed that it was possible to obtain a trapping layer 4 of quality entirely similar to that of the prior art, by carrying out this second step at a relatively higher temperature, strictly greater than 1010°C, provided that the duration of the transition period Tt did not exceed 30 seconds. In other words, when the duration during which the dielectric layer 3 is exposed only to the carrier gas is less than 30 seconds, the formation of the charge trapping layer 4 can be carried out, according to the invention, at a temperature strictly between 1010°C and 1200°C, while presenting an acceptable quality of this layer, both in deformation and in second harmonic distortion measurement.

[0046] It therefore appears that by limiting the duration of exposure of the dielectric layer 3 to the carrier gas alone, between the first period of time and the second period of time, the surface state of this layer 3 is conditioned or maintained to make it particularly suitable for the direct growth of the trapping layer 4 at a temperature much higher than in the state of the art. For this purpose, it may be advantageous to limit the duration during which the dielectric layer 3 is exposed only to the carrier gas to 20 seconds or even to 15 seconds.

[0047] It is also noted that by limiting this duration, the phenomenon of dissolution of the dielectric layer 3 which can occur during the transition period is avoided or limited. This dissolution phenomenon leads to a loss of thickness of this dielectric layer, this loss being proportional to the duration of the transition period Tt raised to the power n, (Tt)^n, n being able to vary between 2 and 4 depending on the temperature, the initial thickness of the dielectric layer and the flow rate of carrier gas. When the duration of the transition period Tt is excessive, the thickness of the dielectric layer is likely to become insufficient to allow the formation of a charge trapping layer of satisfactory quality.

[0048] It is recalled that a relatively high temperature for forming the trapping layer is an important characteristic since it can then be formed much more quickly, at equivalent quality. Thus, the growth rate at 950°C is of the order of 0.8 microns per minute, of the order of 1.25 microns per minute at 1000°C and of the order of 2 microns per minute at 1100°C, which is notably higher than the 0.3 microns per minute observed at 900°C. This significantly improves the production rate of a support substrate compared to the rate obtained using the methods of the state of the art.

[0049] This is particularly the case when the trapping layer is relatively thick, greater than 2 microns.

[0050] Thus, and in order to aim for a high growth rate of the trapping layer 4, the step of forming this layer 4 is preferably carried out at a temperature strictly greater than 1010°C, 1050°C, or greater than 1100°C.

[0051] Whatever the temperature chosen during this step of forming the trapping layer 4, it is carried out for a period of time sufficient to form a target thickness of polycrystalline silicon, directly on the dielectric layer 3.

[0052] To limit the loss of thickness of the dielectric layer 2 during the transition period Tt, the treatment temperature can be lowered during this period, for example by 50°C compared to the temperature of the first time period.

[0053] Advantageously, the charge trapping layer 4 and the dielectric layer 3 are formed at respective temperatures identical to within 50°C. For example, the two steps can be sequenced as previously presented by maintaining the same temperature of 1050°C or 1100°C for the first and second steps. Since it is not necessary to raise or lower the temperature between the two steps, the duration of the transition period can be reduced more easily, below 30 seconds, for example below 20 seconds or even 15 seconds.

[0054] The dielectric layer 3 can be formed at a temperature higher, lower or equal to the formation temperature of the charge trapping layer 4.

Claims

1. A method for preparing a carrier substrate (1) provided with a charge-trapping layer (4), the method comprising placing a base substrate (2) made of monocrystalline silicon exhibiting a resistivity lower than or equal to 500 ohm.cm in a chamber of a deposition apparatus and, without removing the base substrate (2) from the chamber and while sweeping the chamber with a carrier gas, carrying out the following steps: - forming an epitaxial layer made of intrinsic silicon (5) over the base substrate (2), while adding a precursor gas containing silicon in the chamber for a determined period of time; - forming a dielectric layer (3) over the epitaxial layer made of intrinsic silicon (5) while adding a reactive gas in the chamber for a first period of time; forming a charge-trapping layer (4) made of polycrystalline silicon directly over the dielectric layer (3) while adding a precursor gas containing silicon in the chamber for a second period of time subsequent to the first one; - the duration for which - the dielectric layer (3) is exposed only to the carrier gas, between the first period of time and the second period of time, being shorter than 30 seconds and the step of forming the charge-trapping layer (4) being conducted - at a temperature strictly comprised between 1,010°C and 1,200°C.

2. The method according to the preceding claim, wherein the carrier gas comprises, or consists of, hydrogen.

3. The method according to one of the preceding claims, wherein the precursor gas containing silicon is selected from the list formed of silane, disiliane, trichlorosilane, dichlorosilane and silicon tetrachloride.

4. The method according to one of the preceding claims, comprising, before the step of forming the epitaxial layer made of intrinsic silicon (5), a step of annealing the base substrate (2) in a neutral or reducing atmosphere, at a temperature comprised between 900°C and 1,200°C, to eliminate a native oxide possibly present at the surface.

5. The method according to one of the preceding claims, wherein the formation of the epitaxial layer made of intrinsic silicon (5) over the base substrate (2) is carried out at an epitaxial temperature comprised between 900°C and 1,200°C.

6. The method according to one of the preceding claims, wherein the step of forming the epitaxial layer made of intrinsic silicon (5) leads to forming a layer (5) whose thickness is comprised between 5 and 20 microns.

7. The method according to one of the preceding claims, wherein the dielectric layer (3) is made of silicon oxide and the reactive gas comprises between 0.1% and 10% oxygen in a neutral gas such as argon.

8. The method according to one of the preceding claims, wherein the step of forming the dielectric layer (3) is conducted at a temperature comprised between 900°C and 1,150°C.

9. The method according to one of the preceding claims, wherein the dielectric layer (3) has a thickness larger than 0.5 nm.

10. The method according to one of the preceding claims, wherein the step of forming the charge-trapping layer (4) is conducted at a temperature higher than 1,050°C or than 1,100°C.

11. The method according to one of the preceding claims, wherein the charge-trapping layer (4) and the dielectric layer (3) are formed at identical respective temperatures, within a 50°C margin.

12. The method according to one of the preceding claims, wherein the duration for which the dielectric layer (3) is exposed only to the carrier gas is shorter than 20 seconds or than 15 seconds.

13. The method according to one of the preceding claims, wherein the charge-trapping layer (4) has a thickness comprised between 0.1 and 10 microns.