AUTOMATIC CONFIGURATION OF PIPELINE MODULES IN AN ELECTRONIC SYSTEM
Patent Information
- Application Number
- DE602023011746
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2022-04-11
- Filing Date
- 2023-04-11
- Publication Date
- 2026-02-11
- Estimated Expiration
- 2043-04-11
AI Technical Summary
Conventional RTL generation for SoCs with reconfigurable and parametrizable hardware components is time-consuming and requires manual configuration adjustments, leading to lengthy iteration cycles due to unmet timing and area constraints, which are only detected late in the synthesis flow.
An automated method and computing platform that generates an optimized pipeline configuration by iteratively modifying timing paths and reducing register counts while satisfying timing and area constraints, using a relaxed configuration algorithm to quickly produce a full RTL description.
Substantially reduces RTL generation time from hours to minutes, enhances predictability, and ensures timely detection of configuration issues, allowing for efficient and accurate pipeline module setup.