METHOD FOR MANUFACTURING A STORAGE DEVICE AND A STORAGE DEVICE

Description

TECHNICAL FIELD

[0001] The present invention relates to non-volatile resistive memories integrated into an interconnect network, for example of a CMOS (Complementary Metal Oxide Semiconductor) type technology. It can be applied to different types of resistive memories and in particular to oxide-based resistive memories (OxRAM), ferroelectric-based resistive memories (FeRAM), and conductive bridge resistive memories (CBRAM). STATE OF THE ART

[0002] As illustrated in the figure 1 , the 1000' memory points of non-volatile resistive memories are classically made up of three stacked elements: a lower conductive electrode 120', an active layer 150' whose properties allow a change of state in order to store information, and an upper conductive electrode 220'.

[0003] In the case of OxRAM type resistive memory, the active layer is based on a dielectric. Applying an electric field across the terminals of the lower and upper electrodes allows a conductive filament to break or form within the dielectric layer, thus switching from a high resistivity state to a low resistivity state of the dielectric layer, these two states corresponding respectively to the information "0" (or "OFF" state) and the information "1" (or "ON" state) of the memory.

[0004] The integration of such a memory point into an interconnection network is commonly based on a mesa-type structure in which the memory point is formed according to a pattern created by lithography. Connections to the electrodes are typically made via 110' and 210' wires connected to metal lines that constitute the interconnection network. Furthermore, the mesa structure thus created is then encapsulated by a stack of dielectric layers and subsequently planarized to provide electrical insulation and enable higher levels of interconnection. This interconnection network is preferably part of the layers designated as BEOL, an acronym for "Back End Of Line."

[0005] To increase the density of memory points in each memory plane, the goal is to reduce the size of the memory points and / or decrease their spacing. One of the major obstacles in this regard is the minimum size achievable to create a mesa-type structure. Specifically, the size of the memory point is currently determined by the size of the lithography pattern. However, the most advanced lithography techniques using extreme ultraviolet (EUV) immersion lithography and DRIE (Dry Reactive Ion Etching) plasma etching offer a resolution of approximately 60 nm at best for defining mesa-type structures, i.e., isolated points.The resulting memory point densities are not satisfactory and there is a need to overcome this dimensional barrier in order to create more efficient memory devices and / or devices with smaller overall dimensions.

[0006] Examples of prior art can be found in documents US2010 / 084741 A1 and US2009 / 269928 A1.

[0007] One objective of the present invention is therefore to propose a solution for improving the density of memory points within memory devices. SUMMARY

[0008] To achieve this objective, a first object of the invention relates to a memory device comprising a plurality of memory points, the device comprising a plurality of first electrodes and a plurality of second electrodes, each second electrode being at least partially located opposite a first electrode, characterized in that it further comprises an active layer extending continuously between the plurality of first electrodes and the plurality of second electrodes, and in that: each first electrode, a second electrode located at least partially opposite said first electrode, and a portion of active layer extending between said first electrode and said second electrode together form a memory point.

[0009] A second object of the invention relates to a method for manufacturing a memory device comprising a plurality of memory points, the method comprising the following steps: Form a plurality of first electrodes, form an active layer on each of the first electrodes, the active layer being continuous, Form a plurality of second electrodes on the active layer, each second electrode being at least partly opposite a first electrode, each first electrode, a second electrode being at least partly opposite said first electrode, and a portion of active layer extending between said first electrode and said second electrode together forming a memory point.

[0010] Since the active layer is common to the plurality of memory points, the memory points thus formed do not require lithography and etching steps to create the active layer, technological steps whose resolution is currently limited to 60 nm. Existing techniques, however, make it possible to form electrodes with lithography and etching steps having a resolution below 40 nm. Thus, the process according to the invention can significantly increase, typically doubling, the density of memory points within a memory device.

[0011] Furthermore, eliminating the need for engraving to form the memory dot pattern reduces edge defects caused by this manufacturing step. These defects, which are poorly controlled in the prior art, can lead to a deterioration in the memory device's performance. The process according to the invention therefore makes it possible to produce a memory device with improved performance compared to the prior art.

[0012] The fact that the active layer is continuous and shared by several memory locations eliminates the need for lithography and etching steps that could damage the active layer and ultimately lead to reduced memory device performance. During the development of the present invention, it was observed that this shared active layer does not hinder the proper functioning of each individual memory location.

[0013] Furthermore, the device according to the invention comprises a stack comprising, stacked in a so-called stacking direction, in this order: A first support layer having a top face, the first support layer comprising a plurality of first holes each extending from its top face, each first hole housing: i. A first metallic via, ii. A first electrode from the plurality of first electrodes, each first electrode surmounting a distinct first metallic via. The active layer, surmounting the top face of the first support layer, on the active layer, a second support layer comprising a plurality of second holes passing through it and each opening onto the active layer, each second hole housing: i. A second metallic via, ii. A second electrode from the plurality of second electrodes, said second electrode being disposed between the second metallic via and the active layer, and being at least partly opposite a first electrode among the plurality of first electrodes.

[0014] Similarly, in the process according to the invention, the step of forming the plurality of first electrodes comprises the following steps: Provide a first support layer, having an upper face and a lower face opposite each other, the first support layer comprising a plurality of first holes, each extending from its upper face and opening onto its lower face; Form a first electrode in each first hole of the plurality of first holes. the active layer being formed on the upper surface of the first support layer, the process further comprising a step of forming in each first hole a first metallic via, the first electrode being in contact with the first metallic via.

[0015] The process also includes the following steps: Form a second support layer on the active layer, the second support layer comprising a plurality of second holes traversing the second support layer and each opening onto the active layer, each second hole being at least partly opposite a different first electrode, Form in each second hole of the plurality of second holes a second electrode of the plurality of second electrodes and a second metallic via, the second electrode being in contact with the second metallic via.

[0016] The memory points thus formed require only the creation of holes in the first and second support layers. Existing techniques allow the formation of holes such as those formed in this advantageous embodiment of the process according to the invention with a resolution below 40 nm.

[0017] Furthermore, the first and second holes preferably each have a continuous profile along the stacking direction.

[0018] The advantages presented with reference to the process according to the second aspect of the invention apply mutatis mutandis to the device according to the first aspect of the invention. BRIEF DESCRIPTION OF THE FIGURES

[0019] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which: There figure 1 represents memory points according to prior art within an interconnected network. Figures 2A to 2M illustrate one embodiment of the process according to the invention. figure 3 illustrates an embodiment in which two memory points share an electrode and a via.

[0020] The drawings are provided as examples and are not intended to limit the scope of the invention. They are schematic representations of the principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the relative dimensions and thicknesses are not representative of reality. DETAILED DESCRIPTION

[0021] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are stated below: According to a preferred embodiment, the first holes each have a continuous profile along the stacking direction projected onto any plane including the stacking direction. According to a preferred embodiment, the second holes each have a continuous profile along the stacking direction projected onto any plane including the stacking direction.

[0022] In one example, each second electrode is in direct contact with the active layer.

[0023] According to one embodiment, at least one first electrode among the plurality of first electrodes is at least partly opposite at least two second electrodes.

[0024] According to an alternative embodiment, each of the first electrodes is located opposite a single second electrode.

[0025] In one example, the first metallic via and the first electrode contained within the same first hole are made of different materials. In another example, the second metallic via and the second electrode contained within the same first hole are made of different materials.

[0026] As an example, the first metallic via is based on one of the following materials: W, WN, Ru, Co, Ni, Cu, a combination of layers containing these materials, or an alloy of these materials. As an example, the second metallic via is based on one of the following materials: W, WN, Ru, Co, Ni, Cu, a combination of layers containing these materials, or an alloy of these materials.

[0027] For example, the first electrode is based on one of the following materials: TiN, Ti, TaN, W, WN, Ru, C, Si, Co, Ni, a combination of layers containing these materials, or an alloy of these materials. For example, the second electrode is based on one of the following materials: TiN, Ti, TaN, W, WN, Ru, C, Si, Co, Ni, a combination of layers containing these materials, or an alloy of these materials.

[0028] According to one example, the device also includes a protective layer between the active layer and the second support layer.

[0029] As an example, the active layer is based on a dielectric, for example one of the following materials: SiO x with x equal to 1 or 2, such as SiO 2 , HfO x with x equal to 1 or 2, such as HfO 2 , Al 2 O 3 , TiO 2 , Ta 2 O 5 , ZrO 2 , an alloy of these elements.

[0030] According to one example, the active layer is based on a ferroelectric material, for example one of the following: Hf x Zr 1-x O 2 with 0 <x<1, du HfO 2 dopé Si, de l'AIScN et un titano-zirconate de plomb (PZT). Dans le cas d'une couche active à base de HfO 2 dopé Si, le Si est de préférence présent dans une concentration inférieure ou égale à 10% atomique, de préférence sensiblement égale à 1% atomique.

[0031] According to one example, the active layer includes a solid electrolyte, for example, based on one of the following: silver-doped germanium sulfide and copper-doped germanium sulfide.

[0032] In an advantageous example, each first electrode is flush with the top face of the first support layer.

[0033] According to one embodiment, the device further comprises a plurality of first secondary electrodes and a plurality of second secondary electrodes, each second secondary electrode being at least partially located opposite a first secondary electrode, the device further comprising a secondary active layer extending continuously between the plurality of first secondary electrodes and the plurality of second secondary electrodes, and: each first secondary electrode, a second secondary electrode located at least partly opposite said first secondary electrode, and a portion of secondary active layer extending between said first secondary electrode and said second secondary electrode together form a secondary memory point.

[0034] According to a preferred example, each memory point is an oxide-based resistive memory (OxRam).

[0035] Two elements are understood to be isolated from each other if they are not in direct contact and are separated from each other by a medium or material having an electrical resistivity greater than 10 6 < Ω.m.

[0036] According to an advantageous embodiment, the first support layer comprises at least one first contact hole, the second support layer comprises at least one second contact hole, the first contact hole and the second contact hole being at least partially opposite each other, the method further comprising the following steps: Form in the first contact hole a first metallic via contact, Form in the second contact hole a second metallic via contact, the first metallic via contact and the second metallic via contact being in electrical conduction.

[0037] Two elements are considered to be in electrical conduction when they are in direct contact or in contact via conductive layers typically exhibiting a resistivity of less than 150 µΩ·cm. The first and second elements are preferably in direct contact via metallic contact. In one variant, the first and second elements are in contact via metallic contact via at least one metallic layer, typically a first contact electrode and / or a second contact electrode.

[0038] According to one example, the first metallic via and the first electrode located in the same first hole are formed during the same deposition step.

[0039] According to an advantageous example, the formation of the second support layer comprises a step of depositing the support layer and a step of forming the plurality of first holes in the support layer, the process further comprising, after the formation of the second support layer on the active layer, and before the formation in each second hole of the second metallic via and the second electrode, a step of processing the active layer through the second holes, the active layer processing step preferably taking place at one of the following times: Before the formation of the second support layer, After the deposition of the second support layer and before the formation of the plurality of first holes, After the formation of the plurality of first holes.

[0040] According to one example, the process further includes, after the formation of the active layer, and before the formation of the second support layer, the formation of a protective layer on an upper face of the active layer.

[0041] According to one example, the process further includes, after the formation of the second support layer on the active layer, the removal of portions of the apparent protective layer through the second holes.

[0042] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the depositing, transferring, gluing, assembling or applying a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0043] A layer can also be composed of several sub-layers of the same material or of different materials.

[0044] A substrate, layer, or device "based on" a material M is understood to be a substrate, layer, or device comprising only that material M, or that material M and possibly other materials, for example, alloying elements, impurities, or dopants. Thus, a material based on a III-N material may comprise a III-N material with added dopants.

[0045] Selective etching with respect to or etching exhibiting selectivity with respect to means an etching process configured to remove a material A or a layer A from a material B or a layer B, and exhibiting an etching speed of material A greater than the etching speed of material B. Selectivity is the ratio of the etching speed of material A to the etching speed of material B. The selectivity between A and B is denoted SA:B.

[0046] A coordinate system, preferably orthonormal, comprising the X, Y, Z axes is represented in figures 2A to 2K The Z direction can be designated as the "stacking direction".

[0047] In this patent application, the terms thickness for a layer and height for a structure or device will be preferred. Height is measured perpendicular to the horizontal XY plane. Thickness is measured in a direction normal to the principal plane of extension of the layer. Thus, a layer typically has a thickness along the Z-axis when it extends primarily along the horizontal XY plane, and a projecting element, for example, an insulation trench, has a height along the Z-axis. The relative terms "on," "under," and "below" preferentially refer to positions measured along the Z-axis.

[0048] The terms "approximately", "about", "in the order of" mean "within 10%, preferably within 5%".

[0049] An embodiment of the process according to the invention will now be described with reference to figures 2A to 2K For clarity, these figures illustrate the creation of only two memory locations. Naturally, these steps can simultaneously create numerous memory locations from the same first support layer, the same active layer, and the same second support layer.

[0050] There figure 2AThis illustrates the provision of a stack comprising, in particular, a first support layer 10. This first support layer 10 can rest, as illustrated, on any suitable support 30 for the intended applications. Typically, this is a line comprising metallic connecting elements 35a, 35b, of the "end-of-line" or "BEOL" type. This support 30 can be referred to as the lower metallic line or the lower interconnection line. The support 30 may also include other metallic layers. Furthermore, the support 30 may include transistors.

[0051] The first support layer 10 has a lower face 12 facing this support 30, as well as a upper face 11 opposite the lower face 12. As illustrated in the figure 2B , holes called first holes 15a, 15b are then formed in the first support layer 10 from its upper face 11.

[0052] Preferably, the first holes 15a, 15b penetrate the first support layer 10 through its entire thickness e 10 in the Z direction. Advantageously, each first hole 15a, 15b opens onto a metallic interconnection 35a, 35b of the lower metal line 30. It is also possible that, initially, the first holes 15a, 15b do not open onto the lower face 12 of the first support layer 10. After the formation of the memory points 1000a, 1000b, this lower face 12 can be polished or ground (for example, by chemical-mechanical polishing - CMP) to bring the first metallic vias 110a, 110b, whose formation will be described later, flush with it. Assembly with the lower metal line 30 then takes place after this polishing step.

[0053] The first holes 15a, 15b can, for example, be formed by lithography and etching. Preferably, this involves anisotropic etching such as reactive ion etching or plasma etching.

[0054] The profile of the first holes 15a, 15b is preferably continuous. In particular, the profile of the first holes 15a, 15b is continuous along a direction perpendicular to the upper face 11 of the first support layer 10 (here, the stacking direction Z). A continuous profile is understood to be one that does not exhibit an abrupt change in cross-section in the horizontal XY plane along the stacking direction Z. Such a change can, for example, be called a step-off. Such a step-off is obtained, for example, when a first layer is etched according to a certain pattern, and then a second layer is deposited on the first layer according to another pattern. In other words, each first hole 15a, 15b defines a continuous surface, this surface corresponding to the boundary formed by the first support layer 10 of said first hole 15a, 15b.In particular, by projecting the profile onto any plane perpendicular to the horizontal XY plane, this profile is continuous along the stacking direction Z. Thus, by tracing the first hole 15a, 15b from the upper face 11 to the lower face 12, a curve, preferably a straight line, is defined. This curve has no angles. This straight line can be vertical or, preferably, oblique in a plane containing Z, as illustrated in the figures. Advantageously, the surface defined by each first hole 15a, 15b in the first support layer 10 exhibits rotational symmetry about an axis parallel to the stacking direction Z.

[0055] The profile of the first holes 15a, 15b may or may not be constant along the stacking direction Z. A hole with a constant profile is one whose cross-section in the horizontal XY plane is constant along its entire height along Z. Conversely, a hole with a non-constant profile is one whose cross-section in the horizontal XY plane varies along the height of the hole.

[0056] The first holes 15a and 15b each have a maximum dimension L15 in the horizontal XY plane. In the typical case of holes that are circular when projected onto the horizontal XY plane, their maximum dimension corresponds to their diameter. If a hole does not have a constant cross-section along the stacking direction Z, then L15 is considered to be the maximum diameter (or other characteristic dimension) of that hole along the Z direction. Preferably, L15 is less than 200 nm, preferably less than 100 nm, and even more advantageously less than 50 nm. In particular, L15 can be approximately 40 nm.

[0057] According to an advantageous embodiment, at least one first contact hole 15* is also formed in the first support layer 10 from its upper face 11. The first contact hole 15* and the first holes 15a, 15b are preferably formed simultaneously, during the same etching step. Advantageously, the first contact hole 15* leads to a metallic interconnection 35* of the lower metallic line 30.

[0058] This gives us the first support layer 10 comprising a plurality of first holes 15a, 15b, and preferably at least one first contact hole 15*, which, according to an advantageous embodiment of the process according to the invention, is provided during the first step of the process.

[0059] As illustrated by the passage from the figure 2B to the figure 2E , a second step of the process consists of filling each first hole 15a, 15b with a first metallic via 110a, 110b and a first electrode 120a, 120b.

[0060] The characteristics described below for a first metallic via 110a, 110b and a first electrode 120a, 120b apply to all first metallic vias 110a, 110b and first electrodes 120a, 120b.

[0061] The first metallic via 110a, 110b is preferably in contact with a metallic interconnection 35a, 35b of the lower metallic line 30. The first electrode 120a, 120b and the first metallic via 110a, 110b are in contact.

[0062] The first electrode 120a, 120b can be multilayered.

[0063] The first electrode 120a, 120b is preferably made of a material inert to the active layer 150, meaning it does not participate in the filament formation and breakage mechanism within the active layer. In a specific case, it may promote the creation of a conductive filament within the active layer 150, which will be described later. It may be made of the same material as the first metallic via 110a, 110b, or of a different material.

[0064] According to a first example illustrated by the sequence of steps shown in figures 2B, 2C , 2D and 2E , the first holes 15a, 15b are initially completely filled by the first metallic via 110a, 110b ( figure 2C ), then a portion of this first metallic via 110a, 110b is removed, typically by engraving, from its upper face 111a, 111b ( figure 2D). The space thus left empty by this withdrawal in the first hole 15a, 15b is then at least partially, preferably entirely, filled by the first electrode 120a, 120b ( figure 2E ).

[0065] According to a second example illustrated by the sequence of steps shown in Figures 2B , 2D and 2E , the first holes 15a, 15b are initially partially filled by the first metallic via 110a, 110b ( figure 2D ), then the first electrode 120a, 120b is deposited on the first metallic via 110a, 110b ( figure 2E ).

[0066] In both cases, the assembly consisting of the first metallic via 110a, 110b and the first electrode 120a, 120b located in the same first hole 15a, 15b constitutes a first conducting assembly 100a, 100b. Just like the first holes 15a, 15b, the first conducting assemblies 100a, 100b have a continuous profile.

[0067] As illustrated on the figures 2C to 2EA first metallic contact via 110* and a first contact electrode 120* are formed in the first contact hole 15*, preferably during the same deposition and etching steps as the first metallic vias 110a, 110b and the first electrodes 120a, 120b, respectively. It is understood, however, that the first contact hole 15* may accommodate only a first metallic contact via 110* or only a first contact electrode 120*. The first metallic contact via 110*, the first contact electrode 120*, or both, as appropriate, constitutes a first conductive contact assembly 100*. The first conductive contact assembly 100* is preferably in contact with a metallic interconnection 35* of the lower metallic line 30.

[0068] The deposition of the first electrodes 120a, 120b, the first metallic vias 110a, 110b, the first metallic contact via 110* and the first contact electrode 120* can for example be done by physical vapor deposition (PVD, “Physical Vapor Deposition”) or by chemical vapor deposition (CVD, “Chemical Vapor Deposition”).

[0069] It is understood that after the formation of the first metallic vias 110a, 110b, the first contact metallic vias 110*, the first electrodes 120a, 120b, and the first contact electrodes 120* in the first holes 15a, 15b, and in the first contact holes 15*, the first support layer 10 always defines these holes 15a, 15b, 15*, even if they are filled. Thus, in the remainder of this description, a hole formed in the support layer 10 can therefore refer to an empty hole or a filled hole.

[0070] As illustrated in the figure 2FIn a third step of the process, an active layer 150 is formed on the upper face 11 of the first support layer 10 and on, and preferably in contact with, each of the first electrodes 120a, 120b. The active layer 150 thus extends over a plurality of first conducting assemblies 100a, 100b. The active layer 150 is continuous, thus there is continuity of material between the portions of the active layer 150 overlying the different first conducting assemblies 100a, 100b.

[0071] The active layer 150 can be multilayered. It is preferably single-layered.

[0072] Furthermore, at this stage of the process, the active layer 150 preferably also covers the first conductive contact assembly 100*. Indeed, depositing the active layer 150 over the entire surface of the stack (so-called "full plate" deposition) simplifies the process.

[0073] The active layer 150 is based on a material that can selectively transition from a first state exhibiting a first resistivity to a second state exhibiting a second resistivity, different from the first. Preferably, the first resistivity is greater than 2 times, preferably 10 times, and preferably 100 times, the second resistivity.

[0074] At this stage, it is possible to perform a treatment step on the active layer 150. This can be a surface treatment or a treatment throughout the entire thickness of the active layer 150. The treatment could, for example, be ion implantation aimed at modifying the layer's properties to promote the formation or rupture of the conductive filament. A heat treatment can also be carried out at this stage to relax the stresses in the active layer 150 and thus limit structural defects that may be present after deposition, or to modify the structure of the active layer 150 to promote the formation or rupture of the conductive filament. In In particular, this heat treatment can transform the active layer 150 from an amorphous state to a crystalline state, which is preferable in the case of FeRAM memory. This treatment can be performed in a wafer-scale oven.

[0075] Advantageously, a protective layer 160 is formed on the active layer 150. This protective layer 160 can, for example, be based on SiN, SiCN, carbon, or any other material offering good selectivity to etching both with respect to the second support layer 20 described above and to the active layer 150 so that it will be possible to etch the second holes 25a and 25b by stopping on this layer 160 and without damaging the active layer 150, then to remove the portions of the layer 160 exposed in the bottoms of the second holes 25a and 25b by a process allowing little or no degradation of the first electrodes 120a, 120b.

[0076] There figure 2GThis illustrates the deposition of a second support layer 20 on the active layer 150. This second support layer 20 indirectly covers at least the plurality of holes 15a, 15b, now filled by the plurality of first conductive assemblies 100a, 100b. It also advantageously covers the first contact conductive assembly 100*. If a protective layer 160 has previously been deposited on the active layer 150, the second support layer 20 also covers it, preferably in contact with it.

[0077] After the formation of the second support layer 20, a treatment step can be carried out. This may involve a heat treatment as described previously. When this heat treatment is performed at this stage of the process, the second support layer 20 protects the active layer 150 during the treatment.

[0078] As illustrated in the figure 2H, a plurality of second holes 25a, 25b is then formed in the second support layer 20, from its upper face 21. The second holes 25a, 25b each pass through the second support layer 20 over its entire thickness e 20 in the Z direction. Each second hole 25a, 25b thus opens onto the active layer 150 and is located opposite a distinct first hole 15a, 15b.

[0079] If a protective layer 160 is present between the active layer 150 and the second support layer 20, the second holes 25a, 25b also pass through the protective layer 160 through its entire thickness in the Z direction. The formation of the second holes 25a, 25b can then take place in two steps: a first etching in the second support layer 20 and a second etching in the protective layer 160. The protective layer 160 thus protects the active layer 150 during the etching of the second holes 25a, 25b in the second support layer 20. It is itself advantageously removed locally by means of a process that causes very little or no damage to the active layer 150, for example, chemical etching or RIE (Reactive Ion Etching) selectively targeting the active layer.The presence of the protective layer 160 and the formation of the second holes 25a, 25b in two successive and distinct withdrawal steps thus limit the degradation of the active layer 150. This allows the performance of the memory points obtained at the end of the process to be optimized.

[0080] As with the first holes 15a, 15b, the profile of the second holes 25a, 25b is continuous and may or may not be constant along the stacking direction Z.

[0081] The second holes 25a and 25b each have a maximum dimension L25 in the horizontal XY plane. In the typical case of holes that are circular when projected onto the horizontal XY plane, their maximum dimension corresponds to their diameter. If a hole does not have a constant cross-section along the stacking direction Z, then L15 is considered to be the maximum diameter (or other characteristic dimension) of that hole along the Z direction. Preferably, L25 is less than 200 nm, preferably less than 100 nm, and even more advantageously less than 50 nm. L25 can, in particular, be approximately 40 nm. It should be noted that the second holes 25a and 25b may have a maximum dimension L25 different from the maximum dimension L15 of the first holes.

[0082] At this stage, it is possible to perform a treatment step on the active layer 150 through the second holes 25a, 25b. More precisely, the treatment is effective on the portions of the active layer 150 visible through the second holes 25a, 25b. This can be a surface treatment or a treatment throughout the entire thickness of the active layer 150. The treatment could, for example, be ion implantation aimed at modifying the properties of the layer to promote the formation or rupture of the conductive filament. A heat treatment can also be carried out at this stage to relax the stresses in the active layer 150 and thus limit structural defects that may be present after deposition or after the etching of the holes 25a, 25b, or even modify the structure of the active layer 150 to promote the formation or rupture of the conductive filament.In particular, this heat treatment can transform the active layer 150 from an amorphous state to a crystalline state, which is preferable in the case of FeRAM memory. This treatment can be performed in a wafer-scale oven or by using a laser locally at the second holes 25a, 25b.

[0083] At this stage, it is also possible to deposit a second active layer 170 over the entire exposed surface of the stack, namely on the upper face 21 and the inner sides 23a, 23b of the support layer 20 and on the portions of the active layer 150 visible through the second holes 25a, 25b. This second active layer 170 can advantageously improve the performance of the memory point in conjunction with the first active layer 150. This layer 170 is deposited continuously over the entire plate without the need for etching (except for a portion that will be etched during the formation of the second contact hole 25* described below).

[0084] According to an advantageous embodiment, at least one second contact hole 25* is also formed in the second support layer 20 from its upper face 11, and, if they have been previously deposited, in the protective layer 160 and in the second active layer 170. Similarly, if the active layer 150 has been previously deposited up to the first conductive assembly 100*, the second contact hole 25* also passes through the active layer 150.

[0085] The second contact hole 25* is formed independently of the second holes 25a, 25b in order to etch the active layer 150 and possibly the protective layer 160 only in this second contact hole 25* the areas of the active layer 150 or the protective layer 160 apparent through the second holes 25a, 25b are then protected.

[0086] According to another advantageous embodiment, the second contact hole 25* can be formed before the second holes 25a, 25b. This avoids the risk of damaging the active layer 150 during the formation of the second contact hole 25*.

[0087] According to another advantageous embodiment, the second contact hole 25* can be formed in part during the formation of the second holes 25a, 25b. In this case, the second holes 25a, 25b and the second contact hole 25* are etched at the same time in the support layer 20 (and in the protective layer 160 if present) up to the active layer 150, then a new protective layer is placed over the second holes 25a, 25b to etch the active layer 150 only in the second contact hole 25*.

[0088] The second contact hole 25* and the first contact hole 15* are opposite each other and allow the passage of current between the lower and upper levels of the circuit.

[0089] This gives us the second support layer 20 comprising a plurality of second holes 25a, 25b, and preferably at least one second contact hole 25*, which is formed during the fourth step of the process according to the invention.

[0090] As illustrated by the figures 2I and 2J , a fifth step of the process consists of filling each second hole 25a, 25b with a second metallic via 210a, 210b and a second electrode 220a, 220b.

[0091] The characteristics described below for a second metallic via 210a, 210b and a second electrode 220a, 220b apply to all second metallic vias 210a, 210b and second electrodes 220a, 220b.

[0092] The second electrode 220a, 220b can be deposited directly onto the active layer 150, and optionally against the inner flank 23a, 23b of the second support layer 20, defining the hole 20a, 20b in which it is deposited. If a second active layer 170 has been deposited on the active layer 150 and on the inner flank 23a, 23b of the second support layer 20, the second electrode 220a, 220b will be deposited on the second active layer 170. In all cases, the second electrode 220a, 220b then defines a cavity in which the second metallic via 210a, 210b can be deposited.

[0093] Regardless of the shape chosen for the second electrode 220a, 220b, the second electrode 220a, 220b and the second metallic via 210a, 210b are in contact.

[0094] The second electrode 220a, 220b can be multilayer. It is preferably monolayer.

[0095] The second electrode 220a, 220b is preferably based on a material that promotes the creation of a conductive filament within the active layer 150. It can be based on the same material as the second metallic via 210a, 210b, or on a distinct material.

[0096] The assembly consisting of the second metallic via 210a, 210b and the second electrode 220a, 220b located in the same second hole 25a, 25b constitutes a second conductive assembly 200a, 200b. Just like the second holes 25a, 25b, the second conductive assemblies 200a, 200b have a continuous profile.

[0097] As illustrated on the figure 2JA second metallic contact via 210* and optionally a second contact electrode 220* (not shown) can be formed in the second contact hole 25*, preferably during the same deposition and etching steps as the second metallic vias 210a, 210b and the second electrodes 220a, 220b, respectively. The second metallic contact via 210*, optionally with the second contact electrode 120*, constitutes a second conductive contact assembly 200*.

[0098] The deposition of the second electrodes 220a, 220b, the second metallic vias 210a, 210b, the second metallic contact via 210* and the second contact electrode 220* can, for example, be done by physical vapor deposition (PVD, “Physical Vapor Deposition”) or by chemical vapor deposition (CVD, “Chemical Vapor Deposition”).

[0099] As illustrated in the figure 2KA layer or line 40 can be formed on the second support layer 20 and on the second conductor assemblies 200a, 200b. This is typically a line comprising metallic connecting elements 45a, 45b, of the "end of line" or "BEOL" type. This line 40 can be described as the upper metallic line or the upper interconnection line.

[0100] Each second metallic via 210a, 210b is preferably in contact with a metallic interconnection 45a, 45b of the upper metallic line 40. Furthermore, the second conductor contact assembly 200* is preferably in contact with a metallic interconnection 45* of the upper metallic line 40.

[0101] Each set consisting of a first electrode 120a, 120b and a second electrode 220a, 220b facing each other, as well as the portion of active layer 150 separating them, forms a memory point 1000a, 1000b.

[0102] Furthermore, each assembly consisting of a first conductor contact 100* and a second conductor contact 200* placed opposite each other forms a 1000* contact point or 1000* via contact. This 1000* via contact is fully electrically conductive. It thus allows the passage of current from one level of the interconnection network to the level directly above or below.

[0103] According to an embodiment illustrated in the figure 3 It is possible that several memory points 1000a, 1000b have a common conductor set, whether it is the first conductor set 100a or the second conductor set 100b. In other words, the same first metallic via 110a and the same first metallic electrode 120a, or the same second metallic via 210a and the same second metallic electrode 220a can be part of several memory points 1000a, 1000b.

[0104] In the example illustrated in figure 3Two memory points 1000a, 1000b share the same first conductor assembly 100a. This assembly extends below two separate conductor assemblies 200a, 200b. To achieve such a device, only the dimensions and positioning of the first holes 15a, 15b need to be modified compared to an embodiment in which all memory points consist of separate first conductor assemblies 100a, 100b and second conductor assemblies 200a, 200b.

[0105] The structure illustrated in the figure 3 corresponds to a so-called 1T2R structure. It is understood that it is possible to form any structure of the type 1TnR, n being an integer greater than 2, n corresponding to the number of second conducting sets located opposite the same first conducting set.

[0106] Case 1T1R corresponds to the embodiment illustrated in figure 2M .

[0107] In the case of a 1TnR structure, every second via 200a, 200b is preferably connected to an independent upper line (typically designated "bit line") allowing a particular bias to be applied to each memory point 1000a, 1000b during the reading or writing of one of the n memory points thus formed.

[0108] It is understood that the terms "lower" and "upper" are not to be interpreted restrictively, particularly with regard to the order of implementation of the process. It is entirely conceivable that the first support layer 10 may initially be deposited on an interconnection line that will act as the upper metallic line, and that the second support layer 20 may be covered by an interconnection line that will act as the lower metallic line within a BEOL-type interconnection network.

[0109] It appears, in light of the various embodiments described, that by forming vias and electrodes within the first and second holes, the invention makes it possible to increase the density of memory points within a device. In particular, the invention makes it possible to obtain higher densities of memory points than by forming them using mesa-type structures.

[0110] In addition to the higher memory point densities achieved with this invention, another drawback of mesa-structured memory points is overcome. Indeed, when creating mesa-type structures, to obtain an acceptable memory point density, structures with a height greater than their diameter (a high aspect ratio, typically greater than 1:1) and also greater than the spacing between structures are used. This raises the problem of encapsulating these memory point matrices with an insulating layer without leaving gaps. These gaps can create integration problems, for example during planarization, or even affect the reliability of the device. By integrating the vias and electrodes into the gaps formed within the continuous layers 10, 20, the encapsulation and planarization steps of the memory points are eliminated, and there is no longer a risk of unwanted gaps forming between the memory points.

[0111] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention.

Claims

1. Memory device (1) comprising a plurality of memory points (1000a, 1000b), the device (1) comprising a plurality of first electrodes (120a, 120b) and a plurality of second electrodes (220a, 220b), each second electrode (220a, 220b) being located at least partially facing a first electrode (120a, 120b), further an active layer (150) extending continuously between the plurality of first electrodes (120a, 120b) and the plurality of second electrodes (220a, 220b), and: • each first electrode (120a, 120b), • a second electrode (220a, 220b) being located at least partially facing said first electrode (120a, 120b), and • an active layer (150) portion extending between said first electrode (120a, 120b) and said second electrode (220a, 220b) together form a memory point (1000a, 1000b), the device comprising a stack comprising, stacked along a so-called stacking direction (Z), in this order: • a first support layer (10) having an upper face (11), the first support layer (10) comprising a plurality of first holes (15a, 15b) each extending from its upper face (11), each first hole (15a, 15b) housing: i. a first metal via (110a, 110b), ii. a first electrode (120a, 120b) of the plurality of first electrodes (120a, 120b), each first electrode (120a, 120b) surmounting a distinct first metal via (110a, 110b), • the active layer (150), surmounting the upper face (11) of the first support layer (10), • on the active layer (150), a second support layer (20) comprising a plurality of second holes (25a, 25b) passing through it and each opening onto the active layer (150), each second hole (25a, 25b) housing: i. a second metal via (210a, 210b), ii. a second electrode (220a, 220b) of the plurality of second electrodes (120a, 120b), said second electrode (220a, 220b) being disposed between the second metal via (210a, 210b) and the active layer (150), and being located at least partially facing a first electrode (120a, 120b) from among the plurality of first electrodes (120a, 120b).

2. Memory device (1) according to the preceding claim, wherein the first holes (15a, 15b) each have a continuous profile along the stacking direction (Z) projecting into any plane comprising the stacking direction (Z).

3. Memory device (1) according to any one of the preceding claims, wherein the second holes (25a, 25b) each have a continuous profile along the stacking direction (Z) projecting into any plane comprising the stacking direction (Z).

4. Memory device (1) according to any one of the preceding claims, wherein each second electrode (220a, 220b) is in direct contact with the active layer (150).

5. Memory device (1) according to any one of the preceding claims, wherein at least one first electrode (120a, 120b) from among the plurality of first electrodes (120a, 120b) is located at least partially facing at least two second electrodes (220a, 220b).

6. Memory device (1) according to any one of claims 1 to 4, wherein each of the first electrodes (120a, 120b) is located facing one single second electrode (220a, 220b).

7. Memory device (1) according to any one of the preceding claims, wherein the first metal via (110a, 110b) and the first electrode (120a, 120b) contained in one same first hole (15a, 15b) are with the basis of distinct materials.

8. Memory device (1) according to any one of the preceding claims, further comprising a protective layer (160) between the active layer (150) and the second support layer (20).

9. Memory device (1) according to any one of the preceding claims, wherein each first electrode (120a, 120b) is flush with the upper face (11) of the first support layer (10).

10. Memory device (1) according to any one of the preceding claims, further comprising a plurality of first secondary electrodes and a plurality of second secondary electrodes, each second secondary electrode being located at least partially facing a first secondary electrode, the device further comprising a secondary active layer extending continuously between the plurality of first secondary electrodes and the plurality of second secondary electrodes, and in which: • each first secondary electrode, • a second secondary electrode being located at least partially facing said first secondary electrode, and • a secondary active layer portion extending between said first secondary electrode and said second secondary electrode together form a secondary memory point.

11. Memory device (1) according to any one of the preceding claims, wherein each memory point (1000a, 1000b) is an oxide-based resistive memory (OxRam).

12. Method for manufacturing a memory device (1) comprising a plurality of memory points (1000a, 1000b), the method comprising the following steps: • Forming a plurality of first electrodes (120a, 120b), • Forming an active layer (150) on each of the first electrodes (120a, 120b), the active layer (150) being continuous, • Forming a plurality of second electrodes (220a, 220b) on the active layer (150), each second electrode (220a, 220b) being located at least partially facing a first electrode (120a, 120b), each first electrode (120a, 120b), a second electrode (220a, 220b) being located at least partially facing said first electrode (120a, 120b), and an active layer (150) portion extending between said first electrode (120a, 120b) and said second electrode (220a, 220b) together forming a memory point (1000a, 1000b), the step of forming the plurality of first electrodes (120a, 120b) comprising the following steps: • Providing a first support layer (10), having an upper face (11) and a lower face (12) opposite one another, the first support layer (10) comprising a plurality of first holes (15a, 15b), each extending from its upper face (11) and opening onto its lower face (12), • Forming a first electrode (120a, 120b) in each first hole (15a, 15b) of the plurality of first holes (15a, 15b), the active layer (150) being formed on the upper face (11) of the first support layer (10), the method further comprising a formation step in each first hole (15a, 15b) of a first metal via (110a, 110b), the first electrode (120a, 120b) being located in contact with the first metal via (110a, 110b), the method further comprising the following steps: • Forming a second support layer (20) on the active layer (150), the second support layer (20) comprising a plurality of second holes (25a, 25b) passing through the second support layer (20) and each opening onto the active layer (150), each second hole (25a, 25b) being located at least partially facing a different first electrode (220a, 220b), • Forming, in each second hole (25a, 25b) of the plurality of second holes (25a, 25b), a second electrode (220a, 220b) of the plurality of second electrodes (220a, 200b) and a second metal via (210a, 210b), the second electrode (220a, 220b) being located in contact with the second metal via (210a, 210b).

13. Method according to the preceding claim, wherein the formation of the second support layer (20) comprises a step of depositing the support layer (20) and a formation step of the plurality of first holes (15a, 15b) in the support layer (20), the method further comprising, before the formation in each second hole (25a, 25b) of the second metal via (210a, 210b) and of the second electrode (220a, 220b), a step of treating the active layer (150), the step of treating the active layer (150) preferably taking place at one from among the following times: • Before the formation of the second support layer (20), • After the deposition of the second support layer (20) and before the formation of the plurality of first holes (15a, 15b), • After the formation of the plurality of first holes (15a, 15b).