Two-dimensional electron gas field-effect transistor having side gates

Abstract

The invention relates to a two-dimensional electron gas field-effect transistor, referred to as TEGFET, comprising a drain (3), a source (4) and at least one channel (6) included in a heterostructure formed by a stack of at least two semiconductor layers (21, 22). The TEGFET comprises at least two side gates (5) arranged on either side of the at least one channel and each being arranged opposite one side of the at least one channel, said side of the at least one channel having a smaller dimension of said at least one channel, referred to as thickness of the at least one channel, extending along an axis (8) in which the at least two semiconductor layers are stacked and extending perpendicularly to the length of the at least one channel. The TEGFET does not include a gate positioned below or above the at least one channel with respect to an axis perpendicular to a plane, referred to as the channel plane, in which the at least one channel extends between the source and the drain, said channel plane being perpendicular to the thickness of the at least one channel.

Description

[0001] DESCRIPTION

[0002] Two-dimensional electron gas field effect transistor with side gates

[0003] Technical field

[0004] The present invention belongs to the technical field of two-dimensional electron gas field effect transistors, known as TEGFETs. The operating principle of field effect transistors is to modulate the current flowing between the source and the drain by modifying the voltage applied between the gate and the source of the transistor. In the case of TEGFETs, the modulation of the source-drain current is achieved by modulating the electron density of the two-dimensional electron gas. The two-dimensional electron gas is confined in a channel of a heterostructure.

[0005] TEGFETs exhibit high electron transport speeds, making them suitable for use in high-frequency devices. TEGFETs are also used for high-power applications, such as GaN-based devices or components.

[0006] The invention relates, in particular but not limited to, high-frequency transistors. In particular, the invention is applicable to all existing types of TEGFETs and, in particular but not limited to, type III-V and III-VN TEGFETs.

[0007] State of the prior art

[0008] In view of the aforementioned areas of application of TEGFETS, their reliability is a determining criterion.

[0009] The operation of state-of-the-art TEGFETs consists of depleting the two-dimensional electron gas across the entire width of the channel so as to modify the density and / or geometric distribution of charge carriers in the channel.

[0010] This is particularly the case for nanometer-sized transistors. This type of transistor has a channel, for example a nanowire or a nanostructure, whose channel length, located opposite the gate(s), in which the conductivity is modulated and / or controlled is typically of the order of a few hundred nanometers, generally less than 300 nm. The channel length is in this case less than, equal to or of the same order of magnitude as the mean free path of electrons in the channel, which is generally at room temperature, of the order of forty nanometers in gallium arsenide (GaAs), and for example of the order of a hundred nanometers in gallium nitride (GaN). Also, the transport of electrons in the channel in this type of transistor is ballistic and governed by quantum physics.

[0011] This type of quantum-sized transistor therefore has reduced electrical power due to the nanometric size of the channel.

[0012] Most prior art TEGFETs have an upper gate, located vertically above the channel, relative to the plane formed by the two-dimensional electron gas, which makes it possible to control the source-drain current by modulating the electron density of the two-dimensional gas by means of an electric field normal to the two-dimensional electron gas. The application of an electric field normal to the two-dimensional electron gas has the effect of generating a depletion of the two-dimensional electron gas over the entire width of the channel, by depletion or enrichment of carriers depending on the type and / or architecture of the field effect transistor, and thus modifying the conductivity of the channel.

[0013] State-of-the-art TEGFETs have several drawbacks including, but not limited to, gate leakage currents, interface defects, and gate fragility.

[0014] Gate leakage currents are key indicators of device health. They can reveal future degradation. Improving reliability requires controlling leakage current, which is also the source of electronic noise, generation-recombination, and 1 / frequency (f) noise.

[0015] Interface defects are defined as defects at the semiconductor-gate interface and / or defects at the dielectric-gate interface when a dielectric has been deposited to reduce leakage current. These defects contribute to trapping effects processes such as transconductance frequency dispersion, DC drain characteristic collapse, gate-drain transients, and microwave power limitation.

[0016] The fragility of the gate comes, on the one hand, from the fragility of the oxide or crystal between the gate and the gas and, on the other hand, from the fact that the gate is deposited on the surface of the semiconductor without being diffused. The fact that it is simply deposited makes it very sensitive to any electrostatic shock. The present invention aims to overcome, at least in part, the disadvantages of the state-of-the-art devices.

[0017] An aim of the invention is, furthermore, to propose a TEGFET:

[0018] - to overcome the disadvantages of state-of-the-art devices, and / or

[0019] - whose current-voltage characteristics are reliable and reproducible, and / or

[0020] - having a saturation curve in which the drain-source current IDS is almost constant and / or does not depend or depends little on the drain-source voltage VDS, and / or

[0021] - in which the current IDS varies significantly or significantly, for a given voltage DS, when the gate bias voltage VGS varies, so that it is possible to drive the TEGFET by varying the voltage GS, and / or

[0022] - having little or no grid leakage current, and / or

[0023] - presenting reliable and reproducible characteristics over a temperature range between 300 and 1.5 Kelvins, and / or

[0024] - being insensitive or only slightly sensitive to the local environment and to interference, such as, for example, electromagnetic radiation or ionizing radiation, and / or

[0025] - usable for high power applications.

[0026] Presentation of the invention

[0027] For this purpose, a two-dimensional electron gas field effect transistor, called TEGFET, is proposed. Said TEGFET comprises a drain, a source and at least one channel included in a heterostructure formed by a stack of at least two semiconductor layers, preferably at least two distinct layers or layers of different composition. The at least one channel connects, along its largest dimension, called the length of the at least one channel, the source and the drain.

[0028] Said TEGFET comprises at least two lateral gates arranged on either side of the at least one channel and each arranged opposite one side of the at least one channel, said sides of the at least one channel comprising, or extending along, a smaller dimension of said at least one channel, called the thickness of the at least one channel, the thickness extending along an axis along which the at least two semiconductor layers are stacked and extending perpendicular to the length of the at least one channel. Preferably, the TEGFET does not comprise a gate positioned below or above the at least one channel relative to an axis perpendicular to a plane, called the channel plane, along which the at least one channel extends between the source and the drain, said channel plane being perpendicular to the thickness of the at least one channel and / or being perpendicular to the stacking axis of the at least two semiconductor layers and / or being parallel to the length of the at least one channel.

[0029] Preferably, "side of the at least one channel" is understood to mean a face or a surface or an interface. Preferably, the side of the at least one channel extends or comprises the thickness and the length of the at least one channel.

[0030] Preferably, at least one of the side grids faces a side of the at least one channel which is opposite the side facing which at least one other of the side grids faces.

[0031] Preferably, the source and the drain are included in or belong to the same layer of the TEGFET. Preferably, the layer comprising the drain and the source further comprises the at least one channel.

[0032] Preferably, the conductivity of the at least one channel and / or the electron density of the two-dimensional gas is modulated and / or controlled, preferably only, by the at least two side gates.

[0033] Preferably, the at least two side gates are arranged to modulate and / or control the conductivity of the at least one channel and / or the electron density of the two-dimensional gas.

[0034] Preferably, the TEGFET does not include a gate positioned below or above the channel to modulate and / or control the conductivity of the at least one channel and / or the electron density of the two-dimensional gas.

[0035] Preferably, the two-dimensional electron gas is comprised and confined in the at least one channel. Preferably, the channel plane is parallel to the plane along which the two-dimensional gas extends.

[0036] Preferably, the two-dimensional electron gas extends between an interface, extending along a plane parallel to the stacking axis, preferably perpendicular to the channel plane, between the source and the stack of the at least two semiconductor layers and an interface, extending along a plane parallel to the stacking axis, preferably perpendicular to the channel plane, between the drain and the stack of the at least two semiconductor layers. Preferably, the two-dimensional electron gas does not extend into the source or the drain.

[0037] Preferably, the channel extends to the source and the drain. Preferably, the length of the at least one channel corresponds to the largest dimension of the at least one channel and / or to the largest distance separating two ends, preferably opposite, of the at least one channel.

[0038] Channel plane can be understood to mean a plane perpendicular to the thickness of at least one channel.

[0039] Preferably, the thickness of the at least one channel has a dimension smaller than the length and width of the at least one channel. The thickness of the at least one channel can be defined as the smallest dimension of the at least one channel and / or as the smallest distance separating two, preferably opposite, faces of the at least one channel.

[0040] The TEGFET may comprise an even number of side gates. The TEGFET may comprise more than two side gates. The TEGFET may comprise a succession of adjacent side gates, extending along the axis connecting the source to the drain, arranged on either side of the at least one channel. Two adjacent side gates of the succession of side gates may be separated by a trench or a recess. The side gates, of the succession of side gates, may be aligned, two by two, along an axis perpendicular to the axis connecting the source to the drain and perpendicular to the stacking axis.

[0041] Preferably, the at least one channel comprises two opposite sides, more preferably two parallel sides.

[0042] Preferably, the at least one channel has a width extending along an axis connecting the two sides of the at least one channel.

[0043] Preferably, the width of the at least one channel extends along an axis included in the channel plane and / or along an axis which is perpendicular to the axis connecting the drain to the source and / or along an axis perpendicular to the length of the at least one channel and / or along an axis perpendicular to the thickness of the at least one channel.

[0044] Preferably, the width of the at least one channel has a dimension less than the length of the at least one channel.

[0045] Preferably, the TEGFET comprises two side gates distinct from each other. More preferably, each of the two side gates is independent, in particular from the other of the two side gates. More preferably, the two side gates have no common portion. Preferably, the two side gates are symmetrical. Preferably, the two side gates are symmetrical with respect to the at least one channel.

[0046] Preferably, the two side gates are made of or comprise or consist of a semiconductor material. Preferably, the semiconductor material comprises metal atoms, preferably diffused metal atoms. Preferably, the semiconductor material, or the portion or part of the semiconductor material, comprising the diffused metal atoms constitutes an ohmic contact.

[0047] Preferably, the two side grids and the channel are physically and / or spatially distinct elements or components or structures or layers or materials.

[0048] Preferably, the two lateral grids are arranged, laterally, on either side of the at least one channel relative to the axis connecting the source and the drain.

[0049] Preferably, the two side grids extend mainly along a plane along which the at least one channel mainly extends.

[0050] The TEGFET can comprise a single channel.

[0051] Preferably, the TEGFET may comprise two channels, more preferably three channels, more preferably four channels and more preferably five channels. Preferably, the channel planes of the TEGFET channels are parallel to each other. Preferably, the channels of the TEGFET form a stack along the stacking axis of the at least two semiconductor layers.

[0052] Preferably, the face of one of the two lateral grids located on the side of the at least one channel is parallel to the face of the other of the two lateral grids located on the side of the at least one channel.

[0053] Preferably, the width of the face of each of the side grids located on the side of the at least one channel corresponds to or is equal to or, preferably, is greater than, the thickness of the at least one channel.

[0054] The length of the face, located on the side of the at least one channel, of each of the side grids can be defined as the largest dimension of said face and / or as the largest distance separating two ends, preferably opposite, of said face.

[0055] Preferably, the width of the face, located on the side of the at least one channel, of each of the side grids has a dimension smaller than the length of said face. The width of the face, located on the side of the at least one channel, of each of the side grids can be defined as the smallest dimension of said face and / or as the smallest distance separating two ends, preferably opposite, of said face.

[0056] Preferably, none of the side gates, among the at least two side gates, is in contact with, nor has a common portion or common interface with the drain and the source.

[0057] A larger dimension of the at least two side grates may extend primarily perpendicular or parallel to the axis connecting the grate and the drain.

[0058] Preferably, the conductivity of the at least one channel is modulated and / or controlled over a portion or part of the at least one channel. Preferably, the conductivity of the at least one channel is modulated and / or controlled over a slice of the at least one channel. More preferably, the slice of the at least one channel in which the conductivity is modulated and / or controlled corresponds to a portion or part of the at least one channel extending over only a portion of the width and / or over the entire length and / or over the entire thickness of the at least one channel.

[0059] Preferably, the slice of the at least one channel in which the conductivity of the at least one channel is modulated and / or controlled corresponds to a portion or part of the at least one channel extending over a part or portion of the length of the at least one channel. By "a part of the length of the at least one channel" can be understood a distance, along the axis connecting the source and the drain or along the axis of the length of the at least one channel, less than or equal to the length of the at least one channel. More preferably, the distance or dimension, along the axis connecting the source and the drain, of the slice of the at least one channel in which the conductivity of the channel is modulated and / or controlled is equal to the length of the face of a lateral gate, among the at least two lateral gates, located on the side of the at least one channel or to the length of the face of each of the lateral gates located on the side of the at least one channel.

[0060] The portion or part of the at least one channel in which the conductivity is modulated and / or controlled can be defined as the portion or part of the TEGFET making it possible to control, in a controlled manner, the blocking and / or circulation, preferably controlled, of carriers between the drain and the source.

[0061] The width of the at least one channel may vary along the axis connecting the source to the drain. Preferably, the term lateral or laterally defines or designates a position or location relative to the axis connecting the drain to the source.

[0062] Preferably, the term "lateral axis" may be understood to mean an axis which is included in the channel plane and which is perpendicular to the axis connecting the source and the drain and which is perpendicular to the thickness of the at least one channel.

[0063] Preferably, the at least two lateral gates extend, along the stacking axis of the at least two semiconductor layers or along an axis perpendicular to the channel plane, on either side of each channel, among the at least one channel. Preferably, the at least two lateral gates extend, along the stacking axis of the at least two semiconductor layers or along an axis perpendicular to the channel plane, from an external surface of the TEGFET towards the at least one channel. Preferably, the at least two lateral gates extend, along the stacking axis of the at least two semiconductor layers and along the direction connecting the external upper surface of the at least two lateral gates to the at least one channel, beyond each channel, among the at least one channel.

[0064] Preferably, none of the side grids are in contact with or have a common portion or common interface with the at least one channel.

[0065] Preferably, the TEGFET is arranged, more preferably the at least two lateral gates are arranged to modulate and / or modify and / or vary the potential in the at least one channel along an axis, called lateral, included in the channel plane and perpendicular to the axis connecting the source and the drain. Preferably, the TEGFET is arranged to, more preferably the at least two lateral gates are arranged to modulate and / or modify and / or vary the potential in the at least one channel along the lateral axis by polarizing the at least two lateral gates relative to the source.

[0066] Preferably, the modulation and / or modification and / or lateral variation of the potential in the at least one channel has the effect of modifying, preferably over one or more portions or parts of the width of the at least one channel, the potential and / or of creating a potential gradient laterally in the at least one channel.

[0067] Preferably, the modulation and / or modification and / or lateral variation of the potential in the at least one channel has the effect of modulating or modifying or varying in the at least one channel, along the lateral axis, the electron density of the two-dimensional gas and / or the drain-source current density and / or the saturation current.

[0068] Preferably, as for state-of-the-art FETs, the TEGFET according to the invention is arranged so that the potential in the at least one channel varies along the axis of the channel.

[0069] Furthermore, preferably, according to the invention, the TEGFET, preferably the at least two side gates, are arranged so that the potential is maximum at the center of the at least one channel, when the two gates are at the same potential relative to the source. Preferably, according to the invention, the TEGFET, preferably the at least two side gates, are arranged so that the potential is zero on one or on each of the two sides of the at least one channel, when one or both gates are at the same potential as the source.

[0070] Preferably, the TEGFET comprises a dielectric disposed between each of the side gates, among the at least two side gates, and the at least one channel or separating each of the side gates from the at least one channel.

[0071] Preferably, dielectric is understood to mean a body or medium having dielectric properties. The effect of the dielectric is to insulate the side gates of the at least one channel.

[0072] More preferably, the absence of contact or common part or common interface between the at least one lateral grid and the at least one channel, more preferably the dielectric arranged between each of the two lateral grids and the at least one channel, contributes to and / or has the effect of and / or makes it possible to modulate and / or modify and / or vary the potential in the at least one channel along the lateral axis.

[0073] Preferably, the TEGFET comprises an interface between the at least one channel and the dielectric which is opposite or facing or successive or consecutive, preferably directly consecutive, to an interface between the dielectric and one, several or, preferably each, of the side gates among the at least two side gates.

[0074] Preferably, the interface between the at least one channel and the dielectric and, respectively, the interface between the at least one channel and a side gate considered among the at least two side gates is a wall or a face or a side or a surface of the at least one channel and, respectively, a wall or a face or a side or a surface of the side gate considered. The interface between the at least one channel and the dielectric and, respectively, the interface between the at least one channel and a side gate considered among the at least two side gates may be a common wall or a common face or a common side or a common surface between the at least one channel and the dielectric and, respectively, between the at least one channel and the side gate considered.

[0075] Preferably, the dielectric is arranged in the form of a trench or recess.

[0076] Preferably, the dielectric is formed by a recess.

[0077] Preferably, the recess constitutes a volume extending between a side grid considered among the at least two side grids and the at least one channel.

[0078] Preferably, the recess is delimited laterally, along an axis parallel to the width of the at least one channel, by a face or surface of the at least one channel located opposite or facing the face of a lateral grid considered among the at least two lateral grids and the face, located on the side of the at least one channel, of the lateral grid considered. In this case, preferably, the interface between the at least one channel and the dielectric is formed by the face of the at least one channel opposite the face of the lateral grid considered. More preferably, in this case, the interface between the dielectric and the lateral grid considered is formed by the face, located on the side of the at least one channel, of the lateral grid considered.

[0079] Preferably, the recess comprises or contains a gas.

[0080] In other words, the dielectric can be a gas.

[0081] The gas contained or included in the recess may be air.

[0082] Preferably, the recess does not comprise or is not made of or does not contain solid material.

[0083] Preferably, the at least two side gates, more preferably each of the side gates, comprises and / or is made of and / or is formed of and / or is composed of one or more semiconductor materials or a layer of one or more semiconductor materials.

[0084] Preferably, the at least two lateral gates, more preferably each of the lateral gates, comprises and / or is made up of and / or is formed of and / or is composed of semiconductor materials or a stack of layers of semiconductor material. Preferably, the semiconductor material(s) making up the at least two lateral gates comprises metal atoms diffused into the semiconductor material(s), preferably comprises metal atoms having diffused into the semiconductor material(s).

[0085] Preferably, the drain, the source and the at least two side gates each comprise a metal layer forming a separate electrical contact. Preferably, the metal layer of the drain, the metal layer of the source and the metal layer of the at least two side gates are respectively located on an outer upper surface of the drain, the source and the at least two side gates. Preferably, the metal layers and the outer upper surfaces of the drain, the source and the at least two side gates constitute, at least in part, preferably only in part, an outer upper surface of the TEG-FET.

[0086] Preferably, the metal layer has a thickness of 10 to 500 nm. Preferably, the metal layer comprises and / or is composed of a eutectic. Preferably, the eutectic comprises and / or is composed of gold, germanium and nickel.

[0087] Preferably, the TEGFET according to the invention is arranged and / or capable of modulating and / or modifying and / or varying the potential of the at least one channel along the lateral axis. Preferably, the TEGFET according to the invention is arranged and / or capable of modulating and / or modifying and / or varying the electron density of the two-dimensional gas and / or the current density of the two-dimensional electron gas along the lateral axis, more preferably over a portion, preferably only over a portion, of the width of the at least one channel. Preferably, the TEGFET according to the invention is not arranged or capable of applying a constant potential over the entire width of the at least one channel. Preferably, the TEGFET according to the invention is not arranged or capable of varying the electron density of the two-dimensional gas and / or the current density, uniformly, over the entire width of the at least one channel.

[0088] Preferably, the at least two lateral gates, more preferably each of the lateral gates, is arranged to modulate and / or modify and / or vary the potential of the at least one channel along the lateral axis. Preferably, the at least two lateral gates, more preferably each of the lateral gates, are arranged and / or capable of modulating and / or modifying and / or varying the electron density of the two-dimensional electron gas, preferably non-uniformly, across the width of the at least one channel. Preferably, the TEGFET according to the invention is not arranged or capable of applying a constant potential across the entire width of the at least one channel. Preferably, the at least two lateral gates, more preferably each of the lateral gates, is not arranged or capable of generating a depletion of the two-dimensional electron gas and / or the current density, uniformly, across the entire width of the at least one channel.

[0089] Preferably, the TEGFET according to the invention, preferably the two side gates, more preferably the arrangement of the two side gates, is not arranged and / or is not capable of transforming the two-dimensional electron gas into a one-dimensional electron gas.

[0090] Preferably, and unlike the state-of-the-art nanometric-sized FET in which the operation consists of depleting the channel of its electrons, uniformly over the entire width of the channel, to modulate the conductivity of the channel, the TEGFET according to the invention does not generate a depletion of the two-dimensional electron gas, uniformly, over the entire width of the at least one channel, but instead generates a non-uniform modulation of the electron density and of the current over the entire width of the at least one channel.

[0091] For this purpose, preferably:

[0092] - a ratio between the width of the at least one channel and the mean free path of the electrons in the at least one channel, and / or

[0093] - a ratio between a length of the slice of the at least one channel, located opposite the at least two lateral grids, in which the conductivity is modulated and / or controlled, and the mean free path of the electrons in the at least one channel, and / or

[0094] - a ratio between a length, preferably a minimum length if the length varies, of the at least two lateral grids and the mean free path of the electrons in the at least one channel, is greater than 10, preferably 25, more preferably 50, preferably 60, more preferably 70, more preferably 80, even more preferably 90 and particularly advantageously 100. Preferably, the term “length of the at least two lateral grids” is understood to mean the dimension of the at least two lateral grids in a direction parallel to the length of the at least one channel.

[0095] Also, the width of the at least one channel and / or the length of the edge of the at least one channel, located opposite the at least two lateral gates, in which the conductivity is modulated and / or controlled, and / or the length of the at least two lateral gates is preferably greater than 0.5 pm, more preferably than 1.25 pm, preferably than 2.5 pm, more preferably than 3 pm, more preferably than 3.5 pm, even more preferably than 4 pm, particularly advantageously than 4.5 pm and most preferably than 5 pm.

[0096] Thus, and unlike the state-of-the-art nanometric-sized FET, the transport of electrons in the at least one channel of the TEGFET according to the invention is of the diffusive type, that is to say that the electrons undergo inelastic shocks and their displacement is controlled by the mean free path of the electrons. However, the inventors have observed that the at least one micrometric-sized channel according to the invention makes it possible to implement TEGFETs. Furthermore, and surprisingly, the TEGFETs according to the invention have characteristics equivalent to or even superior to the state-of-the-art nanometric-sized TEGFETs (which operate with ballistic transport of electrons in the channel).

[0097] Preferably:

[0098] - the ratio between the width of the at least one channel and the mean free path of the electrons in the at least one channel, and / or

[0099] - the ratio between the length of the slice of the at least one channel, located opposite the at least two lateral grids, in which the conductivity is modulated and / or controlled, and the mean free path of the electrons in the at least one channel, and / or

[0100] - the ratio between the length of the at least two lateral gates and the mean free path of the electrons in the at least one channel, has the effect that the potential and / or the conductivity of the electron gas varies, in a non-uniform manner, according to the width of the at least one channel. Thus, according to the invention, an equipotential is observed on the sides of the at least one channel, that is to say on the lateral edges of the at least one channel, in which the drain-source current is zero, or almost zero. It is also observed that the drain-source current flows mainly in the central part or portion of the at least one channel. In addition, the width of the at least one channel, on the scale of at least one micrometer, according to the invention, also has the effect of increasing the electrical power of the TEGFET.

[0101] Preferably, one of the side grids may be electrically connected to the source.

[0102] Preferably, electrically connecting one of the side grids to the source allows the side grid connected to the source to have the same potential as that of the source.

[0103] According to the invention, there is also provided a method for modulating the conductivity of at least one channel of a two-dimensional electron gas field effect transistor, called TEGFET. The method comprises the step of applying a potential difference between a source and a drain of the TEGFET. The method further comprises the step of applying:

[0104] - the same potential difference between at least one side gate of the TEGFET, for example a first side gate, among at least two side gates arranged laterally on either side of the at least one channel of the TEGFET, and the source of the TEGFET, and / or

[0105] - the same potential on one or each of the side gates and on the source of the TEGFET, and / or

[0106] - a potential difference between at least one of the side gates of the TEGFET, for example a second or second side gate, arranged laterally on either side of the at least one channel of the TEGFET, or between each of the side gates of the TEGFET, and the source of the TEGFET.

[0107] The at least one channel connects, along a greater dimension of the at least one channel, called the length of the at least one channel, the source and the drain of the TEGFET.

[0108] The TEGFET does not include a gate positioned below or above the at least one channel relative to an axis perpendicular to a plane, called the channel plane, along which the at least one channel extends between the source and the drain. The channel plane is perpendicular to a smaller dimension of the at least one channel, called the thickness of the at least one channel, extending:

[0109] - along an axis along which at least two semiconductor layers are stacked forming a heterostructure in which at least one channel is included, and

[0110] - perpendicular to the length of the at least one channel.

[0111] The step of applying the same potential or a potential difference between the at least two side grids and the source and / or applying the same potential or a potential difference between at least one side grid and at least one other side grid may consist of modulating and / or modifying and / or varying the potential of at least one side grid relative to the potential of the source and / or the potential of at least one side grid relative to the potential of at least one other side grid.

[0112] Preferably, the method for modulating the conductivity of at least one channel of a TEGFET does not comprise a step of modulating and / or modifying and / or varying the potential in the at least one channel and / or the electron density of the two-dimensional gas and / or the current density, uniformly, across the entire width of the at least one channel.

[0113] Preferably, the method of modulating the conductivity of at least one channel of a TEGFET does not comprise a step of applying a constant potential across the entire width of the at least one channel.

[0114] Preferably, the method for modulating the conductivity of at least one channel comprises the step of modulating and / or modifying and / or varying the potential and / or the conductivity in the at least one channel along an axis, called lateral, included in the channel plane and perpendicular to the axis connecting the source and the drain, by applying the same potential difference between at least one of the lateral grids and the source and / or by applying the same potential to one or each of the lateral grids and to the source and / or by applying a potential difference between at least one of the lateral grids, or between each of the lateral grids, and the source.

[0115] The step of modulating and / or modifying and / or varying, along the lateral axis, the electrostatic potential in the at least one channel may further comprise the step of modulating and / or modifying and / or varying the potential of the at least two lateral grids relative to the potential of the source and / or the potential of at least one lateral grid relative to the potential of at least one other lateral grid. The step of modulating and / or modifying and / or varying the potential of the at least two lateral grids relative to the potential of the source and / or the potential of at least one lateral grid relative to the potential of at least one other lateral grid may cause or have the effect of modulating and / or modifying and / or varying the electrostatic potential in the at least one channel along the lateral axis.

[0116] Preferably, the step of modulating and / or modifying and / or varying, spatially along the lateral axis, the electrostatic potential in the at least one channel, has the effect of modulating and / or modifying and / or varying the drain-source current and / or the saturation current of the TEGFET.

[0117] The method for modulating the conductivity of at least one channel may comprise the step of modulating and / or modifying and / or varying the potential in the at least one channel and / or the conductivity of the two-dimensional electron gas, non-uniformly, along the width of the at least one channel, preferably over only a portion of a width of the at least one channel, and / or the width of the at least one channel extends along an axis perpendicular to the length of the at least one channel and perpendicular to the thickness of the at least one channel, by applying the same potential difference between at least one lateral grid and the source and / or by applying the same potential to one or each of the lateral grids and to the source and / or by applying a potential difference between at least one of the lateral grids, or between each of the lateral grids, and the source.

[0118] The step of modulating and / or modifying and / or varying the electron density of the two-dimensional gas over only a portion of a width of the at least one channel may further comprise the step of modulating and / or modifying and / or varying the potential of the at least two side gates relative to the potential of the source and / or the potential of at least one side gate relative to the potential of at least one other side gate.

[0119] The step of modulating and / or modifying and / or varying the potential of the at least two side gates relative to the potential of the source and / or the potential of at least one side gate relative to the potential of at least one other side gate may cause or have the effect of modulating and / or modifying and / or varying the electron density of the two-dimensional gas over only a portion of the width of the at least one channel. Preferably, the method of modulating the conductivity of at least one channel does not comprise a step of transforming the two-dimensional electron gas into a one-dimensional electron gas.

[0120] The method for modulating the conductivity of a channel of a TEGFET according to the invention is preferably implemented by the TEGFET according to the invention. Preferably, the TEGFET according to the invention is particularly suitable, more preferably specially designed, for implementing the method according to the invention. Preferably, the method according to the invention is particularly suitable, more preferably specially designed, for being implemented by the TEGFET according to the invention. Thus, any characteristic of the method for modulating the conductivity of a channel of a TEGFET according to the invention can be integrated into the TEGFET according to the invention and vice versa.

[0121] According to the invention, there is also provided a method of manufacturing a TEGFET, preferably the TEGFET according to the invention. The manufacturing method comprises a single annealing step to form, simultaneously in a single step, separate ohmic contacts between:

[0122] - a first layer of metal, intended to form an electrical contact, and a drain of the TEGFET, and

[0123] - a second layer of metal, intended to form an electrical contact, and a source of the TEGFET, and

[0124] - a third layer of metal, intended to form an electrical contact, and at least two lateral gates of the TEGFET, arranged laterally on either side of at least one channel of the TEGFET.

[0125] Preferably, the first, second and third metal layers are upper external layers. Preferably, the first, second and third metal layers are arranged on an upper layer of a stack of at least two layers of semiconductor materials, forming a heterostructure in which the at least one channel is included, intended to form the drain, the source and the at least two lateral gates.

[0126] Preferably, the single annealing step of the method according to the invention further consists in forming, simultaneously in the same step, the drain, the source and the at least two lateral gates by diffusion of metal atoms, preferably along a stacking axis of the at least two layers of semiconductor materials:

[0127] - of the first layer of metal in the stack of at least two layers of semiconductor materials, and

[0128] - the second layer of metal in the stack of at least two layers of semiconductor materials, and

[0129] - of the third layer of metal, in the stack of at least two layers of semiconductor materials.

[0130] The annealing step can be defined as a single step consisting of forming, simultaneously and in a single step, the ohmic contacts.

[0131] Preferably, the first, second and third metal layers are separate and independent layers.

[0132] Preferably, the metal atoms of the metal layers diffuse within the stack of at least two layers of semiconductor materials forming the drain, the source and, in particular, the at least two lateral gates by a distance greater than 50 nm, preferably 100 nm, more preferably 150 nm, more preferably 200 nm, more preferably 250 nm and / or by a distance less than 400 nm, more preferably 350 nm and more preferably 300 nm. Preferably, the metal atoms of the metal layers diffuse from an upper external surface of the drain, the source and, in particular, each of the at least two lateral gates and along a stacking axis of the at least two semiconductor layers.

[0133] Preferably, the metal atoms of the metal layers diffuse, from the upper external surface of the drain, of the source and, in particular of the at least two lateral gates, inside the stack of at least two layers of semiconductor materials by a distance at least equal to or greater than a distance separating:

[0134] - the upper external surface of the upper layer of the stack of at least two semiconductor layers, and

[0135] - the canal.

[0136] Preferably, the distance separating the upper external surface of the upper layer of the stack of at least two semiconductor layers and the channel is parallel to the stack axis and / or perpendicular to a plane, called the channel plane, along which the at least one channel extends between the source and the drain. The TEGFET according to the invention is preferably implemented by the manufacturing method according to the invention. Preferably, the manufacturing method according to the invention is particularly suitable, more preferably specially designed, for implementing the TEGFET according to the invention. Thus, any characteristic of the manufacturing method according to the invention can be integrated into the TEGFET according to the invention and vice versa.

[0137] Description of figures

[0138] Other advantages and particularities of the invention will appear on reading the detailed description of implementations and embodiments which are in no way limiting, and the following appended drawings:

[0139] [Fig. 1] FIGURE 1a) is a schematic representation in oblique view of a state-of-the-art TEGFET and FIGURE 1b) is a schematic representation in top view of a state-of-the-art TEGFET,

[0140] [Fig. 2] FIGURE 2a) is a schematic representation in oblique view of an embodiment of a TEGFET according to the invention and FIGURE 2b) is a schematic representation in top view of the embodiment of the TEGFET according to the invention illustrated in FIGURE 2a),

[0141] [Fig. 3] FIGURES 3a) and 3b) are schematic side view representations of two embodiments of a TEGFET according to the invention,

[0142] [Fig. 4] FIGURE 4 is a schematic side view representation of an embodiment of a multi-channel TEGFET according to the invention,

[0143] [Fig. 5] FIGURE 5 is a top view schematic representation of one embodiment of a TEGFET in which a side gate is electrically connected to the source,

[0144] [Fig. 6] FIGURE 6a) is a schematic representation in channel bias view of a state-of-the-art TEGFET in the absence of top gate bias, FIGURE 6b) is a schematic representation in channel bias view of a state-of-the-art TEGFET in the presence of top gate bias and FIGURE 6c) is a graph illustrating the evolution of the drain-source potential in the channel along the lateral axis of a state-of-the-art TEGFET in the presence of top gate bias,

[0145] [Fig. 7] FIGURE 7 FIGURE 7a) is a schematic representation in bias view of the channel of a TEGFET according to the invention in the absence of polarization of the lateral gate(s), FIGURE 7b) is a schematic representation in bias view of the channel of a TEGFET according to the invention in the presence of a polarization of the lateral gate(s) and FIGURE 7c) is a graph illustrating the evolution of the drain-source potential in the channel along the lateral axis of a TEGFET according to the invention in the presence of a polarization of the upper gate(s),

[0146] [Fig. 8] FIGURES 8a) and 8b) are schematic representations in oblique view of a TEGFET according to the invention, respectively, before the annealing step and after the annealing step, [Fig. 9] FIGURES 9a) and 9b) are schematic representations in top view of a TEGFET according to the invention having two different channel geometries,

[0147] [Fig. 10] FIGURE 10a) is a graph illustrating the evolution of the drain-source current as a function of the drain-source voltage for different gate-source voltages at a temperature of 300 K of the TEGFET illustrated in FIGURE 9a), FIGURE 10b) is a graph illustrating the evolution of the potential in the channel along the lateral axis at the end of the channel located on the source side as a function of the drain-source voltage for a temperature of 300 K of the TEGFET illustrated in FIGURE 9b) and FIGURE 10c) is a graph illustrating the evolution of the potential in the channel along the lateral axis at the end of the channel located on the drain side as a function of the drain-source voltage for a temperature of 300 K of the TEGFET illustrated in FIGURE 9b),

[0148] [Fig. 11] FIGURE 11 is a graph illustrating the evolution of the drain-source current as a function of the drain-source voltage for different gate-source voltages at a temperature of 300 K of the TEGFET illustrated in FIGURE 9b) comprising a doped layer 5, located at a distance of 2 nm from the GaAS / GaAlAs interface of the TEGFET, comprising Berylium atoms, having an acceptor role, at a density of 4.10' 10 .cnr 2 ,

[0149] [Fig.12] FIGURE 12 is a graph illustrating the evolution of the drain-source current as a function of the drain-source voltage for different gate-source voltages at a temperature of 1.5 K of the TEGFET illustrated in FIGURE 9b) comprising a doped layer 5, located at a distance of 2.5 nm from the GaAS / GaAlAs interface of the TEGFET, comprising Berylium atoms, having an acceptor role, at a density of 8.10' 10 .cnr 2 .

[0150] Description of the embodiments

[0151] The embodiments described below being in no way limiting, it will be possible in particular to consider variants of the invention comprising only a selection of the described characteristics, isolated from the other described characteristics (even if this selection is isolated within a sentence comprising these other characteristics), if this selection of characteristics is sufficient to confer a technical advantage or to differentiate the invention compared to the state of the prior art. This selection comprises at least one characteristic, preferably functional without structural details, or with only a part of the structural details if this part only is sufficient to confer a technical advantage or to differentiate the invention compared to the state of the prior art.

[0152] Referring to Figure 1, a conventional TEGFET of the state of the art is illustrated. This TEGFET comprises a stack of at least two semiconductor layers 21, 22, a drain 3, a source 4, a channel 6 and an upper external metal gate 50 formed from a metal layer.

[0153] Many prior art TEGFETs include a gate made of a metal deposited on the semiconductor layer 21 (commonly referred to as a Schottky gate) without diffusion from the upper outer metal gate 50 to the layer 21 and channel 6. Other prior art TEGFETs include a dielectric to electrically isolate the upper outer metal gate 50 from the layer 21 and channel 6.

[0154] With reference to Figures 2 and 3, an embodiment of the TEGFET 1 according to the invention is presented. The TEGFET 1 according to the embodiment comprises a drain 3, a source 4 and at least one channel 6, a single channel 6 in the embodiment presented, included in a heterostructure formed by a stack of at least two layers 21, 22 of semiconductor. The channel 6 connects, along its length denoted L, which is its largest dimension, the source 4 and the drain 3.

[0155] The TEGFET 1 comprises at least two lateral gates 5 each arranged on an opposite side of the at least one channel 6. According to the embodiment presented, the TEGFET 1 comprises two lateral gates 5 arranged on either side of the channel 6. Each of the lateral gates 5 faces a different lateral side 7, 71, 72 of the channel 6 among two lateral sides 7, 71, 72 of the channel 6. The side 7, 71, 72 of the channel 6 comprises the thickness, denoted e, of the channel 6 which is the smallest dimension of the channel 6. The thickness e of the channel 6 extends along a stacking axis 8 of the at least two semiconductor layers 21, 22 and extends perpendicular to the length L of the channel 6. The side 7, 71, 72 of the channel 6 also comprises the length L of the channel 6. The side 7, 71, 72 of channel 6 is a surface or interface that extends along the length L of channel 6 and along the thickness e of channel 6.

[0156] The TEGFET 1 does not comprise a lower gate positioned below or an upper gate 50 positioned above the channel 6 relative to an axis 8 perpendicular to the channel plane along which the channel 6 extends. The channel plane is perpendicular to the thickness e of the channel 6. Furthermore, the stacking axis 8 is perpendicular to the channel plane. In other words, the TEGFET 1 according to the invention does not comprise a lower gate positioned below the channel 6 along the stacking axis 8 or an upper gate 50 positioned above the channel 6 along the stacking axis 8. The absence of an upper gate makes it possible to avoid all of the problems encountered with the transistors of the prior art such as, among others, gate leakage currents, interface defects and gate fragility.

[0157] According to the embodiment, the TEGFET 1 comprises a stack made for example of a GaAs substrate, a GaAlAs layer with a thickness of between 5 nm and 50 nm, a GaAs layer 22 with a thickness of between 10 and 100 nm, which constitutes the channel, and a GaAlAs layer 21 with a thickness of between 50 nm and 300 nm. In this configuration, the channel 6 is located in the GaAs layer at the interface between the layers 21 and 22.

[0158] The lateral grids 5 according to the invention associated with the absence of an upper grid 50 or lower grid make it possible to modulate and / or modify and / or vary the potential in the channel 6 along the lateral axis 10. The lateral axis 10 is included in the channel plane and is perpendicular to the axis connecting the source 4 and the drain 3. The lateral axis 10 is also perpendicular to the stacking axis 8.

[0159] Unlike the TEGFETs of the state of the art which comprise an upper gate 50 or lower and which, as illustrated in figures 6a), b) and c), therefore modify the electron density of the two-dimensional electron gas over the entire width, denoted I, of the channel 6; the particular arrangement of the TEGFET 1 according to the invention makes it possible, as illustrated in figures 7a), b) and c), to modify and modulate the potential in the channel 6 only along the lateral axis 10. Thus, according to the invention, the drain-source saturation current is controlled by the modification of the current density in the channel 6 whereas in the TEGFETs with upper gates 50 or lower it is controlled by the uniform modification over the entire lateral axis 10 of the electron density of the two-dimensional electron gas.

[0160] According to the invention, a method for modulating the conductivity of channel 6 of the TEGFET 1 according to the invention is also described. The method comprises the step of applying a potential difference between the source 4 and the drain 3. The method also comprises the step of applying:

[0161] - the same potential difference between each of the side grids 5 and the source 4, or

[0162] - the same potential on one of the side grids 5 and on the source 4 and a potential difference between another of the side grids 5 and the source 4, or

[0163] - a potential difference between each of the side grids 5 and the source 4.

[0164] The potential, identical or different, applied between one or each of the side grids 5 and the source 4 can be zero or different from zero.

[0165] The step of applying the same potential or potential difference between the at least one lateral grid 5 and the source 4 and / or applying the same potential or potential difference between at least one lateral grid 5 and another lateral grid 5 has the effect of varying the potential in the channel 6 along the lateral axis 10.

[0166] The absence of an upper gate 50 or lower gate in the TEGFET according to the invention implies that the method of modulating the conductivity of the channel 6 does not include a step consisting of uniformly varying the density of the two-dimensional electron gas over the entire width I of the channel 6.

[0167] The two side gates 5 are composed of a semiconductor material. The two side gates 5 comprise metal atoms diffused in the semiconductor material. According to the embodiment presented, the two side gates 5 are composed of a stack of a layer 22 of GaAs with a thickness of between 10 and 100 nm and a layer 21 of GaAlAs with a thickness of between 50 and 300 nm. The stack of GaAs / GaAlAs layers of the side gates 5 comprises diffused metal atoms. Each of the side gates 5 extends along the stacking axis 8 from the outer upper metal layer 9, 91 beyond the channel 6 in the direction connecting the outer upper metal layer 9, 91 to the channel 6.

[0168] The diffused metal atoms extend into the stack of layers 21, 22 over a distance of between 100 and 300 nm from the outer upper metal layer 9 in the direction connecting the outer upper metal layer 9, 91 to the channel 6.

[0169] Also, unlike the upper or lower external metal gate 50 of the state-of-the-art TEGFETs, the lateral gates 5 according to the invention are made of a semiconductor material comprising diffused metal atoms. Furthermore, the lateral gates 5 according to the invention are not external layers but extend into the structure of the TEGFET 1 along the stacking axis 8. This has the advantage of improving the mechanical strength of the gates. Furthermore, this also has the advantage of considerably increasing the applied potential before damaging the gates. Finally, this also makes it possible to extend the applied potential beyond the width I of the channel(s) 6 and thus to obtain an optimal and homogeneous electrical effect over the entire width I of the electron gas.

[0170] The drain 3 and the source 4 extend along the stack axis 8 from, respectively, the outer upper metal layer 9, 92 and the outer upper metal layer 9, 93 beyond the channel 6 in the direction connecting the outer upper metal layer 9, 92 to the channel 6 and connecting the outer upper metal layer 9, 93 to the channel 6. The diffused metal atoms extend into the stack of layers 21, 22 over a distance of between 100 and 300 nm from, respectively, the outer upper metal layer 9, 92 and the outer upper metal layer 9, 93 beyond the channel 6 in the direction connecting the outer upper metal layer 9, 92 to the channel 6 and connecting the outer upper metal layer 9, 93 to the channel 6.

[0171] The outer upper metal layer 9, 91, 92, 93 and the diffused metal atoms are a eutectic which includes gold, germanium and nickel.

[0172] According to the invention, none of the side gates 5 is in contact with or has a common part or common interface with the channel 6. Furthermore, the TEGFET 1 comprises a dielectric 11 disposed between each of the side gates 5 and the channel 6. The dielectric 11 is preferably arranged in the form of a recess 11. More preferably, the dielectric 11 contained in the recess 11 is a gas. According to the non-limiting embodiment presented, the gas is air. The gas may be nitrogen or other gases having dielectric properties.

[0173] Each of these characteristics, i.e. (i) the absence of contact or common part or common interface between the side gates 5 and the channel 6, (ii) the presence of a dielectric disposed between each of the side gates 5 and (iii) the arrangement of the dielectric in the form of a recess, contributes, individually, to increasing the breakdown voltage, reducing the leakage current and improving the characteristics of the TEGFET 1.

[0174] Figures 3a) and 3b) show, as non-limiting examples, two possible configurations of the TEGFET 1 according to the invention. The two-dimensional electron gas can be confined at the level:

[0175] - a heterojunction, illustrated in Figure 3a), or

[0176] - of a quantum well, illustrated in figure 3b).

[0177] In the case of a heterojunction, channel 6 is located at the interface between two layers 21, 22 of different semiconductors. In this case, the semiconductors constituting layers 21, 22 have a different forbidden band width, called gap, but belong to the same group. Channel 6 is therefore located in a semiconductor layer, here layer 22, in which the electrons of the two-dimensional gas are confined and attached to the interface of the heterojunction.

[0178] In the case of a quantum well, channel 6 is located in layer 24 of a small gap semiconductor, for example a gap less than 1 electronvolt (eV), deposited between two layers 23, 25 of the same large gap semiconductor, for example a gap greater than 1 eV.

[0179] The channel plane is parallel to the plane along which the interface of the heterojunction or of the layer 24 of the small gap semiconductor extends in the case of the quantum well.

[0180] In Figure 4 is shown a configuration in which the TEGFET 1 comprises several channels 6. According to the embodiment shown, the TEGFET 1 comprises 3 channels 6. The channels are superimposed along the stacking axis 8. The channel planes of each of the channels 6 are parallel to each other. This configuration is made possible by the use of the lateral gates 5 according to the invention. This configuration has the effect of allowing the increase in current density.

[0181] In Figure 5 is shown a configuration in which one of the side gates of the TEGFET 1 is electrically connected to the source 4. In this configuration, one of the side gates 5 and the source 4 are physically connected by the stack of layers 21, 22 and by the upper external metal layer 9, 91, 93. The source 4 and the side gate 5 connected to the source 4 are therefore at the same potential. In addition, the diffused metal atoms extend into the part of the stack of layers 21, 22 connecting the side gate 5 connected to the source 4 and the source 4.

[0182] With reference to Figure 8, a method for manufacturing a TEGFET 1 according to the invention is also described. The manufacturing method comprises a single annealing step to form, simultaneously in a single step, all of the ohmic contacts of the TEGFET 1. These are the ohmic contacts between:

[0183] - the upper external metal layer 9, 92 of the drain 3, and

[0184] - the upper outer metal layer 9, 93 of source 4, and

[0185] - the upper external metal layer 9, 91 of each of the grids 5.

[0186] Each of the upper external metal layers 9, 91, 92, 93 is intended to form an electrical contact by which the TEGFET 1 will be connected to an external power supply.

[0187] Prior to the annealing step, the method may comprise the deposition, for example by evaporation, of the metal layers 9, 91, 92, 93 on the upper external surface respectively of the drain 3, the source 4 and the side grids 5.

[0188] The annealing temperature is between 300 and 450 °C. The duration of the annealing step is between 10 seconds and 3 minutes.

[0189] The annealing step induces diffusion or has the effect of diffusing the metal atoms from each of the upper external metal layers 9, 91, 92, 93 into the semiconductor layer 21. Preferably, the annealing time and temperature are chosen so that the metal atoms diffuse from each of the metal layers 9, 91, 92, 93 into the semiconductor layers 21, 22. The annealing step has the effect of forming an ohmic contact between the upper external metal layers 9, 91, 92, 93 and the drain 3, the source 4 and, in particular, the side gates 5.

[0190] In state-of-the-art TEGFETs, diffusion of metal atoms from the upper outer metal layer 50 forming the upper or lower outer metal gate 50 is prohibited to avoid short-circuiting, and / or to avoid lowering the breakdown voltage and / or to limit leakage currents. For this purpose, it is necessary to deposit the upper outer metal layer 50 forming the upper or lower outer metal gate 50 after having carried out the annealing step to form the ohmic contact between the upper outer metal layer 9, 92 of the drain 3 and the upper outer metal layer 9, 93 of the source 4. Thus, the method for manufacturing the TEGFET 1 according to the invention comprises fewer steps and therefore offers a saving of time and energy.

[0191] In Figures 10, 11 and 12 are presented the performances and characteristics of two different channel geometries 6 of the TEGFET 1 according to the invention as illustrated in Figure 9. In the first geometry illustrated in Figure 9a), called TEGFETa) 1, the channel 6 has a length of 730 pm between the source 4 and the drain 3 and a thickness of 10 pm between the sides 7, 71 and 7, 72 of the channel 6. In the second geometry illustrated in Figure 9b), called TEGFETb) 1, the channel 6 has a length of 30 pm between the source 4 and the drain 3 and a thickness of 10 pm between the sides 7, 71 and 7, 72 of the channel 6. The width and / or the length of the channel 6 are only limited by the manufacturing process and the equipment used to manufacture the TEGFET 1. A length and / or width of the channel 6 may be several millimeters if the manufacturing process allows it.

[0192] Figure 10a) shows the evolution of the drain-source current, denoted IDS, as a function of the drain-source voltage, denoted VDS, for different gate-source voltages, denoted VGS, at a temperature of 300 K for the TEGFETb) 1. The potential difference is applied between one of the two lateral gates 5 and the source 4. In particular, one of the lateral gates 5 is grounded and the other is polarized. It should be noted that even when GS is equal to zero, a saturation of IDS is still observed. When GS is equal to zero, the lateral gates 5 are at the same potential as the source 4 which is connected to ground according to the embodiment. In addition, for a negative polarization of the lateral gates 5, that is to say for VGS less than zero, IDS decreases and when VGS is positive IDS increases. Thus, this configuration makes it possible to find the classic characteristics of a TEGFET.

[0193] In Figure 10b) is represented the evolution of the potential in channel 6 along the lateral axis 10 at the end of channel 6 located on the side of source 4, noted VYS, as a function of VDS for a temperature of 300 K for TEGFETb) 1. In Figure 10c) is represented the evolution of the potential in channel 6 along the lateral axis 10 at the end of channel 6 located on the side of drain 3, noted VYD, as a function of DS for a temperature of 300 K for TEGFETb) 1. The carrier density of the two-dimensional electron gas is in this case 2.4.10 11 .cnr 2 at 300 K and 1.10 n .cm' 2 at 1.5 K.

[0194] It should be noted that when GS is equal to 0 neither YS nor VYD is equal to 0 which indicates that even in this case the charges can accumulate along each of the sides 7, 71 and 7, 72 of the channel 6. However, VYS and VYD do not tend towards 0 if the lateral grids 5 are maintained at the same potential at floating potential, which demonstrates that the lateral grids 5 strongly modify the potential along the lateral axis 10 and along the length L of the channel 6 and this even if VGS is equal to 0.

[0195] It is also noted that these results confirm the direct and consequent effect of VGS on the potential in channel 6 along the lateral axis 10 and on the potential in channel 6 along the axis along the length L of channel 6.

[0196] Figure 11 shows the evolution of the drain-source current, noted IDS, as a function of the drain-source voltage, noted VDS, for different gate-source voltages, noted VGS, at a temperature of 300 K for the TEGFETb) 2 comprising a doped layer 5 comprising Berylium atoms, having an acceptor role, at a density of 4.10 10 .cnr 2 . The doped layer 5 is located at a distance of 2 nm from the GaAS / GaAlAs interface. The carrier density of the two-dimensional electron gas is in this case 2.7.10 11 .cnr 2 at 300 K and 1.25. 1G 11 . cm -2 at 1.5 K. This demonstrates that the geometry of TEGFET 1 does not influence the characteristics, in particular the IDS evolution as a function of VDS, of TEGFET 1 according to the invention. The saturation IDS current as well as the stability of IDS remain unchanged regardless of the geometry of TEGFET 1.

[0197] Figure 12 shows the evolution of the drain-source current, noted IDS, as a function of the drain-source voltage, noted VDS, for different gate-source voltages, noted VGS, at a temperature of 1.5 K for the TEGFETb) 2 comprising a doped layer 5 comprising Berylium atoms, having an acceptor role, at a density of 8.10 10 .cnr 2 . The doped layer 5 is located at a distance of 2.5 nm from the GaAS / GaAIAs interface. The insert in Figure 12 illustrates the evolution of the drain-source current, noted IDS, during a continuous variation, i.e. without interruption of the variation of the voltage, of the voltage VGS between -0.5 Volts and +0.5 Volts then between +0.5 Volts and -0.5 Volts at a temperature of 1.5 K, with a carrier density of the two-dimensional electron gas of 6.10 10 .cnr 2 , and at a temperature of 300 K, with a two-dimensional electron gas carrier density of 1.6.10 11 .cm -2 .

[0198] It is also noted that at 1.5 K, the quality of the IDS evolution as a function of VDS is maintained compared to 300 K presented in Figures 10 and 11. This demonstrates that even for a low carrier density, 8.10 10 .cnr 2 , the TEGFET 1 has low noise and is therefore suitable for low temperature applications.

[0199] Of course, the invention is not limited to the examples which have just been described and numerous adjustments can be made to these examples without departing from the scope of the invention.

[0200] In addition, the various features, forms, variations and embodiments of the invention may be combined with each other in various combinations to the extent that they are not incompatible or mutually exclusive.

Claims

DEMANDS 1. Two-dimensional electron gas field-effect transistor (1), referred to as TEGFET, said TEGFET comprises a drain (3), a source (4) and at least one channel (6) contained in a heterostructure formed by a stack of at least two semiconductor layers (21, 22); the at least one channel connects, along its longest dimension, referred to as the length (L) of the at least one channel, the source and the drain; said TEGFET: - comprises at least two lateral grids (5) arranged on either side of at least one channel and each arranged opposite one side (7, 71, 72) of at least one channel, said sides of at least one channel comprising a smaller dimension of said at least one channel, referred to as the thickness (e) of at least one channel, extending along an axis (8) along which the at least two semiconductor layers are stacked and extending perpendicularly to the length of at least one channel, and - does not include a grid positioned below or above at least one channel with respect to an axis perpendicular to a plane, called the channel plane, along which the at least one channel extends between the source and the drain, said channel plane being perpendicular to the thickness of the at least one channel, said TEGFET being characterized in that: - a width of at least one channel, and / or - a length of a slice of at least one channel, located opposite at least two lateral grids, in which the conductivity is modulated and / or controlled, and / or - a length of at least two lateral grids, the length of at least two lateral grids being the dimension of at least two lateral grids along a direction parallel to the length of at least one channel, is greater than or equal to 500 nanometers.

2. TEGFET according to claim 1, wherein none of the lateral grids (5) among the at least two lateral grids is in contact with or has a common part or common interface with the at least one channel (6).

3. TEGFET according to the preceding claim 1 or 2, wherein the at least two lateral grids (5) are arranged to modulate and / or modify and / or vary the potential in the at least one channel (6) along an axis (10), referred to as lateral, included in the channel plane and perpendicular to the axis connecting the source and the drain.

4. TEGFET according to any one of the preceding claims, comprising a dielectric (11) disposed between each of the lateral grids (5), among the at least two lateral grids, and at least one channel (6).

5. TEGFET according to the preceding claim, in which the dielectric (11) is arranged in the form of a recess (11).

6. TEGFET according to the preceding claim, wherein the recess (11) comprises a gas.

7. TEGFET according to any one of the preceding claims, wherein the at least two side grids (5) are composed of a semiconductor material.

8. TEGFET according to the preceding claim, wherein the semiconductor material composing the at least two side grids (5) comprises metal atoms diffused in the semiconductor material.

9. TEGFET according to any one of the preceding claims, wherein one of the side grids (5) is electrically connected to the source (4).

10. A method for modulating the conductivity of at least one channel (6) of a two-dimensional electron gas field-effect transistor (1), referred to as a TEGFET, said method comprising the steps of: - apply a potential difference between a source (4) and a drain (3) of the TEGFET, - apply : • the same potential difference between at least one of the lateral grids (5) of the TEGFET, among at least two lateral grids arranged laterally on either side of at least one channel of the TEGFET, and the source of the TEGFET, and / or • the same potential on one or both of the side grids and on the TEGFET source, and / or • a potential difference between at least one of the TEGFET's side grids and the TEGFET's source - modulate and / or modify and / or vary the electron density of the two-dimensional electron gas and / or modulate the current, non-uniformly, over a width of at least one channel; the at least one channel connects, along a larger dimension of the at least one channel, called the length (L) of the at least one channel, the source and the drain of the TEGFET and the TEGFET does not include a grid positioned below or above the at least one channel with respect to an axis perpendicular to a plane, called the channel plane, along which the at least one channel extends between the source and the drain, said channel plane being perpendicular to a smaller dimension of the at least one channel, called the thickness (e) of the at least one channel, extending along an axis (8) along which at least two layers (21, 22) of semiconductor are stacked, forming a heterostructure in which comprises at least one channel and extending perpendicularly to the length of at least one channel; each of at least two side grids is arranged opposite one side (7, 71, 72) of at least one channel, said sides of at least one channel comprise the thickness (e) of at least one channel; the width of the channel and / or a length of a slice of at least one channel, located opposite at least two side grids, in which the conductivity is modulated and / or controlled, and / or a length of at least two side grids is greater than or equal to 500 nm.

11. Method according to claim 10, comprising the step of modulating and / or modifying and / or varying the potential and / or conductivity in at least one channel (6) along an axis (10), referred to as lateral, included in the plane of the channel and perpendicular to the axis connecting the source and the drain, by applying the same potential difference between at least one of the lateral grids (5) and the source (4) and / or by applying the same potential on one or each of the lateral grids and on the source and / or by applying a potential difference between at least one of the lateral grids, or between each of the lateral grids, and the source.

12. A method according to claim 10 or 11, comprising the step of modulating and / or modifying and / or varying the potential in at least one channel (6) and / or the conductivity of the two-dimensional electron gas, in a non-uniform manner, along a width (I) of at least one channel, the width of at least one channel extending along an axis perpendicular to the length (L) of at least one channel and perpendicular to the thickness (e) of at least one channel, by applying the same potential difference between at least one of the side grids (5) and the source (4) and / or by applying the same potential on one or each of the side grids and on the source and / or by applying a potential difference between at least one of the side grids, or between each of the side grids, and the source.

13. A method for manufacturing a two-dimensional electron gas field-effect transistor (1), referred to as a TEGFET, said manufacturing method comprises a single annealing step to form, simultaneously in a single step, distinct ohmic contacts between: - a first layer of metal (9, 92), intended to form an electrical contact, and a drain (3) of the TEGFET, and - a second layer of metal (9, 93), intended to form an electrical contact, and a source (4) of the TEGFET, and - a third layer of metal (9, 91), intended to form an electrical contact, and at least two lateral grids (5) of the TEGFET, arranged laterally on either side of at least one channel of the TEGFET and arranged, each, opposite one side (7, 71, 72) of the at least one channel, said sides of the at least one channel comprising a smaller dimension of said at least one channel, called thickness (e) of the at least one channel, extending along an axis (8) along which the at least two semiconductor layers are stacked and extending perpendicularly to a length of the at least one channel; an annealing time and temperature are chosen such that the metal atoms diffuse from each of the metal layers (9, 91, 92, 93) into the semiconductor layers (21, 22).

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